* [Intel-gfx] [PATCH] drm/i915/gt: Clear compress metadata for Xe_HP platforms
@ 2022-02-28 21:21 Ramalingam C
2022-02-28 21:28 ` Ramalingam C
` (2 more replies)
0 siblings, 3 replies; 4+ messages in thread
From: Ramalingam C @ 2022-02-28 21:21 UTC (permalink / raw)
To: intel-gfx, dri-devel
From: Ayaz A Siddiqui <ayaz.siddiqui@intel.com>
Xe-HP and latest devices support Flat CCS which reserved a portion of
the device memory to store compression metadata, during the clearing of
device memory buffer object we also need to clear the associated
CCS buffer.
Flat CCS memory can not be directly accessed by S/W.
Address of CCS buffer associated main BO is automatically calculated
by device itself. KMD/UMD can only access this buffer indirectly using
XY_CTRL_SURF_COPY_BLT cmd via the address of device memory buffer.
v2: Fixed issues with platform naming [Lucas]
v3: Rebased [Ram]
Used the round_up funcs [Bob]
v4: Fixed ccs blk calculation [Ram]
Added Kdoc on flat-ccs.
v5: GENMASK is used [Matt]
mocs fix [Matt]
Comments Fix [Matt]
Flush address programming [Ram]
Signed-off-by: Ayaz A Siddiqui <ayaz.siddiqui@intel.com>
Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
---
drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 15 ++
drivers/gpu/drm/i915/gt/intel_migrate.c | 146 ++++++++++++++++++-
2 files changed, 157 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
index f8253012d166..237c1baccc64 100644
--- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
+++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
@@ -203,6 +203,21 @@
#define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
#define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2)
+#define XY_CTRL_SURF_INSTR_SIZE 5
+#define MI_FLUSH_DW_SIZE 3
+#define XY_CTRL_SURF_COPY_BLT ((2 << 29) | (0x48 << 22) | 3)
+#define SRC_ACCESS_TYPE_SHIFT 21
+#define DST_ACCESS_TYPE_SHIFT 20
+#define CCS_SIZE_MASK GENMASK(17, 8)
+#define XY_CTRL_SURF_MOCS_MASK GENMASK(31, 25)
+#define NUM_CCS_BYTES_PER_BLOCK 256
+#define NUM_BYTES_PER_CCS_BYTE 256
+#define NUM_CCS_BLKS_PER_XFER 1024
+#define INDIRECT_ACCESS 0
+#define DIRECT_ACCESS 1
+#define MI_FLUSH_LLC BIT(9)
+#define MI_FLUSH_CCS BIT(16)
+
#define COLOR_BLT_CMD (2 << 29 | 0x40 << 22 | (5 - 2))
#define XY_COLOR_BLT_CMD (2 << 29 | 0x50 << 22)
#define SRC_COPY_BLT_CMD (2 << 29 | 0x43 << 22)
diff --git a/drivers/gpu/drm/i915/gt/intel_migrate.c b/drivers/gpu/drm/i915/gt/intel_migrate.c
index 20444d6ceb3c..26ee6ae0e1bb 100644
--- a/drivers/gpu/drm/i915/gt/intel_migrate.c
+++ b/drivers/gpu/drm/i915/gt/intel_migrate.c
@@ -16,6 +16,8 @@ struct insert_pte_data {
};
#define CHUNK_SZ SZ_8M /* ~1ms at 8GiB/s preemption delay */
+#define GET_CCS_BYTES(i915, size) (HAS_FLAT_CCS(i915) ? \
+ DIV_ROUND_UP(size, NUM_BYTES_PER_CCS_BYTE) : 0)
static bool engine_supports_migration(struct intel_engine_cs *engine)
{
@@ -467,6 +469,113 @@ static bool wa_1209644611_applies(int ver, u32 size)
return height % 4 == 3 && height <= 8;
}
+/**
+ * DOC: Flat-CCS - Memory compression for Local memory
+ *
+ * On Xe-HP and later devices, we use dedicated compression control state (CCS)
+ * stored in local memory for each surface, to support the 3D and media
+ * compression formats.
+ *
+ * The memory required for the CCS of the entire local memory is 1/256 of the
+ * local memory size. So before the kernel boot, the required memory is reserved
+ * for the CCS data and a secure register will be programmed with the CCS base
+ * address.
+ *
+ * Flat CCS data needs to be cleared when a lmem object is allocated.
+ * And CCS data can be copied in and out of CCS region through
+ * XY_CTRL_SURF_COPY_BLT. CPU can't access the CCS data directly.
+ *
+ * When we exhaust the lmem, if the object's placements support smem, then we can
+ * directly decompress the compressed lmem object into smem and start using it
+ * from smem itself.
+ *
+ * But when we need to swapout the compressed lmem object into a smem region
+ * though objects' placement doesn't support smem, then we copy the lmem content
+ * as it is into smem region along with ccs data (using XY_CTRL_SURF_COPY_BLT).
+ * When the object is referred, lmem content will be swaped in along with
+ * restoration of the CCS data (using XY_CTRL_SURF_COPY_BLT) at corresponding
+ * location.
+ */
+
+static inline u32 *i915_flush_dw(u32 *cmd, u64 dst, u32 flags)
+{
+ /* Address needs to be QWORD aligned */
+ GEM_BUG_ON(!IS_ALIGNED(dst, 8));
+
+ *cmd++ = MI_FLUSH_DW | flags;
+ *cmd++ = lower_32_bits(dst);
+ *cmd++ = upper_32_bits(dst);
+
+ return cmd;
+}
+
+static u32 calc_ctrl_surf_instr_size(struct drm_i915_private *i915, int size)
+{
+ u32 num_cmds, num_blks, total_size;
+
+ if (!GET_CCS_BYTES(i915, size))
+ return 0;
+
+ /*
+ * XY_CTRL_SURF_COPY_BLT transfers CCS in 256 byte
+ * blocks. one XY_CTRL_SURF_COPY_BLT command can
+ * transfer upto 1024 blocks.
+ */
+ num_blks = DIV_ROUND_UP(GET_CCS_BYTES(i915, size),
+ NUM_CCS_BYTES_PER_BLOCK);
+ num_cmds = DIV_ROUND_UP(num_blks, NUM_CCS_BLKS_PER_XFER);
+ total_size = (XY_CTRL_SURF_INSTR_SIZE) * num_cmds;
+
+ /*
+ * Adding a flush before and after XY_CTRL_SURF_COPY_BLT
+ */
+ total_size += 2 * MI_FLUSH_DW_SIZE;
+
+ return total_size;
+}
+
+static u32 *_i915_ctrl_surf_copy_blt(u32 *cmd, u64 src_addr, u64 dst_addr,
+ u8 src_mem_access, u8 dst_mem_access,
+ int src_mocs, int dst_mocs,
+ u16 ccs_blocks)
+{
+ int blks_left = ccs_blocks, blks_per_copy;
+
+ /*
+ * The XY_CTRL_SURF_COPY_BLT instruction is used to copy the CCS
+ * data in and out of the CCS region.
+ *
+ * We can copy at most 1024 blocks of 256 bytes using one
+ * XY_CTRL_SURF_COPY_BLT instruction.
+ *
+ * In case we need to copy more than 1024 blocks, we need to add
+ * another instruction to the same batch buffer.
+ *
+ * 1024 blocks of 256 bytes of CCS represent a total 256KB of CCS.
+ *
+ * 256 KB of CCS represents 256 * 256 KB = 64 MB of LMEM.
+ */
+ do {
+ blks_per_copy = blks_left >= NUM_CCS_BLKS_PER_XFER ?
+ NUM_CCS_BLKS_PER_XFER : blks_left;
+ *cmd++ = ((XY_CTRL_SURF_COPY_BLT) |
+ (src_mem_access << SRC_ACCESS_TYPE_SHIFT) |
+ (dst_mem_access << DST_ACCESS_TYPE_SHIFT) |
+ FIELD_PREP(CCS_SIZE_MASK, blks_per_copy - 1));
+ *cmd++ = lower_32_bits(src_addr);
+ *cmd++ = ((upper_32_bits(src_addr) & 0xFFFF) |
+ FIELD_PREP(XY_CTRL_SURF_MOCS_MASK, src_mocs));
+ *cmd++ = lower_32_bits(dst_addr);
+ *cmd++ = ((upper_32_bits(dst_addr) & 0xFFFF) |
+ FIELD_PREP(XY_CTRL_SURF_MOCS_MASK, dst_mocs));
+ src_addr += SZ_64M;
+ dst_addr += SZ_64M;
+ blks_left -= blks_per_copy;
+ } while (blks_left > 0);
+
+ return cmd;
+}
+
static int emit_copy(struct i915_request *rq,
u32 dst_offset, u32 src_offset, int size)
{
@@ -614,16 +723,24 @@ intel_context_migrate_copy(struct intel_context *ce,
return err;
}
-static int emit_clear(struct i915_request *rq, u64 offset, int size, u32 value)
+static int emit_clear(struct i915_request *rq, u64 offset, int size,
+ u32 value, bool is_lmem)
{
- const int ver = GRAPHICS_VER(rq->engine->i915);
+ struct drm_i915_private *i915 = rq->engine->i915;
+ const int ver = GRAPHICS_VER(i915);
+ u32 num_ccs_blks, ccs_ring_size;
+ int mocs = rq->engine->gt->mocs.uc_index << 1;
u32 *cs;
GEM_BUG_ON(size >> PAGE_SHIFT > S16_MAX);
offset += (u64)rq->engine->instance << 32;
- cs = intel_ring_begin(rq, ver >= 8 ? 8 : 6);
+ /* Clear CCS only when value is 0 */
+ ccs_ring_size = (is_lmem && !value) ?
+ calc_ctrl_surf_instr_size(i915, size) : 0;
+
+ cs = intel_ring_begin(rq, round_up(ver >= 8 ? 8 + ccs_ring_size : 6, 2));
if (IS_ERR(cs))
return PTR_ERR(cs);
@@ -646,6 +763,27 @@ static int emit_clear(struct i915_request *rq, u64 offset, int size, u32 value)
*cs++ = value;
}
+ if (is_lmem && HAS_FLAT_CCS(i915) && !value) {
+ num_ccs_blks = DIV_ROUND_UP(GET_CCS_BYTES(i915, size),
+ NUM_CCS_BYTES_PER_BLOCK);
+
+ /*
+ * Flat CCS surface can only be accessed via
+ * XY_CTRL_SURF_COPY_BLT CMD and using indirect
+ * mapping of associated LMEM.
+ * We can clear ccs surface by writing all 0s,
+ * so we will flush the previously cleared buffer
+ * and use it as a source.
+ */
+ cs = i915_flush_dw(cs, offset, MI_FLUSH_LLC | MI_FLUSH_CCS);
+ cs = _i915_ctrl_surf_copy_blt(cs, offset, offset,
+ DIRECT_ACCESS, INDIRECT_ACCESS,
+ mocs, mocs, num_ccs_blks);
+ cs = i915_flush_dw(cs, offset, MI_FLUSH_LLC | MI_FLUSH_CCS);
+
+ if (ccs_ring_size & 1)
+ *cs++ = MI_NOOP;
+ }
intel_ring_advance(rq, cs);
return 0;
}
@@ -711,7 +849,7 @@ intel_context_migrate_clear(struct intel_context *ce,
if (err)
goto out_rq;
- err = emit_clear(rq, offset, len, value);
+ err = emit_clear(rq, offset, len, value, is_lmem);
/* Arbitration is re-enabled between requests. */
out_rq:
--
2.20.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/gt: Clear compress metadata for Xe_HP platforms
2022-02-28 21:21 [Intel-gfx] [PATCH] drm/i915/gt: Clear compress metadata for Xe_HP platforms Ramalingam C
@ 2022-02-28 21:28 ` Ramalingam C
2022-03-01 1:42 ` [Intel-gfx] ✓ Fi.CI.BAT: success for " Patchwork
2022-03-01 12:19 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2 siblings, 0 replies; 4+ messages in thread
From: Ramalingam C @ 2022-02-28 21:28 UTC (permalink / raw)
To: intel-gfx, dri-devel
Matt,
This is the continuation of review happened at
https://patchwork.freedesktop.org/patch/475177/?series=100419&rev=1
On 2022-03-01 at 02:51:39 +0530, Ramalingam C wrote:
> From: Ayaz A Siddiqui <ayaz.siddiqui@intel.com>
>
> Xe-HP and latest devices support Flat CCS which reserved a portion of
> the device memory to store compression metadata, during the clearing of
> device memory buffer object we also need to clear the associated
> CCS buffer.
>
> Flat CCS memory can not be directly accessed by S/W.
> Address of CCS buffer associated main BO is automatically calculated
> by device itself. KMD/UMD can only access this buffer indirectly using
> XY_CTRL_SURF_COPY_BLT cmd via the address of device memory buffer.
>
> v2: Fixed issues with platform naming [Lucas]
> v3: Rebased [Ram]
> Used the round_up funcs [Bob]
> v4: Fixed ccs blk calculation [Ram]
> Added Kdoc on flat-ccs.
> v5: GENMASK is used [Matt]
> mocs fix [Matt]
> Comments Fix [Matt]
> Flush address programming [Ram]
>
> Signed-off-by: Ayaz A Siddiqui <ayaz.siddiqui@intel.com>
> Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 15 ++
> drivers/gpu/drm/i915/gt/intel_migrate.c | 146 ++++++++++++++++++-
> 2 files changed, 157 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
> index f8253012d166..237c1baccc64 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
> @@ -203,6 +203,21 @@
> #define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
> #define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2)
>
> +#define XY_CTRL_SURF_INSTR_SIZE 5
> +#define MI_FLUSH_DW_SIZE 3
> +#define XY_CTRL_SURF_COPY_BLT ((2 << 29) | (0x48 << 22) | 3)
> +#define SRC_ACCESS_TYPE_SHIFT 21
> +#define DST_ACCESS_TYPE_SHIFT 20
> +#define CCS_SIZE_MASK GENMASK(17, 8)
> +#define XY_CTRL_SURF_MOCS_MASK GENMASK(31, 25)
> +#define NUM_CCS_BYTES_PER_BLOCK 256
> +#define NUM_BYTES_PER_CCS_BYTE 256
> +#define NUM_CCS_BLKS_PER_XFER 1024
> +#define INDIRECT_ACCESS 0
> +#define DIRECT_ACCESS 1
> +#define MI_FLUSH_LLC BIT(9)
> +#define MI_FLUSH_CCS BIT(16)
> +
> #define COLOR_BLT_CMD (2 << 29 | 0x40 << 22 | (5 - 2))
> #define XY_COLOR_BLT_CMD (2 << 29 | 0x50 << 22)
> #define SRC_COPY_BLT_CMD (2 << 29 | 0x43 << 22)
> diff --git a/drivers/gpu/drm/i915/gt/intel_migrate.c b/drivers/gpu/drm/i915/gt/intel_migrate.c
> index 20444d6ceb3c..26ee6ae0e1bb 100644
> --- a/drivers/gpu/drm/i915/gt/intel_migrate.c
> +++ b/drivers/gpu/drm/i915/gt/intel_migrate.c
> @@ -16,6 +16,8 @@ struct insert_pte_data {
> };
>
> #define CHUNK_SZ SZ_8M /* ~1ms at 8GiB/s preemption delay */
> +#define GET_CCS_BYTES(i915, size) (HAS_FLAT_CCS(i915) ? \
> + DIV_ROUND_UP(size, NUM_BYTES_PER_CCS_BYTE) : 0)
>
> static bool engine_supports_migration(struct intel_engine_cs *engine)
> {
> @@ -467,6 +469,113 @@ static bool wa_1209644611_applies(int ver, u32 size)
> return height % 4 == 3 && height <= 8;
> }
>
> +/**
> + * DOC: Flat-CCS - Memory compression for Local memory
> + *
> + * On Xe-HP and later devices, we use dedicated compression control state (CCS)
> + * stored in local memory for each surface, to support the 3D and media
> + * compression formats.
> + *
> + * The memory required for the CCS of the entire local memory is 1/256 of the
> + * local memory size. So before the kernel boot, the required memory is reserved
> + * for the CCS data and a secure register will be programmed with the CCS base
> + * address.
> + *
> + * Flat CCS data needs to be cleared when a lmem object is allocated.
> + * And CCS data can be copied in and out of CCS region through
> + * XY_CTRL_SURF_COPY_BLT. CPU can't access the CCS data directly.
> + *
> + * When we exhaust the lmem, if the object's placements support smem, then we can
> + * directly decompress the compressed lmem object into smem and start using it
> + * from smem itself.
> + *
> + * But when we need to swapout the compressed lmem object into a smem region
> + * though objects' placement doesn't support smem, then we copy the lmem content
> + * as it is into smem region along with ccs data (using XY_CTRL_SURF_COPY_BLT).
> + * When the object is referred, lmem content will be swaped in along with
> + * restoration of the CCS data (using XY_CTRL_SURF_COPY_BLT) at corresponding
> + * location.
> + */
> +
> +static inline u32 *i915_flush_dw(u32 *cmd, u64 dst, u32 flags)
> +{
> + /* Address needs to be QWORD aligned */
> + GEM_BUG_ON(!IS_ALIGNED(dst, 8));
> +
> + *cmd++ = MI_FLUSH_DW | flags;
> + *cmd++ = lower_32_bits(dst);
> + *cmd++ = upper_32_bits(dst);
> +
> + return cmd;
> +}
> +
> +static u32 calc_ctrl_surf_instr_size(struct drm_i915_private *i915, int size)
> +{
> + u32 num_cmds, num_blks, total_size;
> +
> + if (!GET_CCS_BYTES(i915, size))
> + return 0;
> +
> + /*
> + * XY_CTRL_SURF_COPY_BLT transfers CCS in 256 byte
> + * blocks. one XY_CTRL_SURF_COPY_BLT command can
> + * transfer upto 1024 blocks.
> + */
> + num_blks = DIV_ROUND_UP(GET_CCS_BYTES(i915, size),
> + NUM_CCS_BYTES_PER_BLOCK);
> + num_cmds = DIV_ROUND_UP(num_blks, NUM_CCS_BLKS_PER_XFER);
> + total_size = (XY_CTRL_SURF_INSTR_SIZE) * num_cmds;
> +
> + /*
> + * Adding a flush before and after XY_CTRL_SURF_COPY_BLT
> + */
i couldn't find any Bspec reference for this. But make the data to be
flushed we are adding before and after.
> + total_size += 2 * MI_FLUSH_DW_SIZE;
> +
> + return total_size;
> +}
> +
> +static u32 *_i915_ctrl_surf_copy_blt(u32 *cmd, u64 src_addr, u64 dst_addr,
> + u8 src_mem_access, u8 dst_mem_access,
> + int src_mocs, int dst_mocs,
> + u16 ccs_blocks)
> +{
> + int blks_left = ccs_blocks, blks_per_copy;
> +
> + /*
> + * The XY_CTRL_SURF_COPY_BLT instruction is used to copy the CCS
> + * data in and out of the CCS region.
> + *
> + * We can copy at most 1024 blocks of 256 bytes using one
> + * XY_CTRL_SURF_COPY_BLT instruction.
> + *
> + * In case we need to copy more than 1024 blocks, we need to add
> + * another instruction to the same batch buffer.
> + *
> + * 1024 blocks of 256 bytes of CCS represent a total 256KB of CCS.
> + *
> + * 256 KB of CCS represents 256 * 256 KB = 64 MB of LMEM.
> + */
> + do {
> + blks_per_copy = blks_left >= NUM_CCS_BLKS_PER_XFER ?
> + NUM_CCS_BLKS_PER_XFER : blks_left;
> + *cmd++ = ((XY_CTRL_SURF_COPY_BLT) |
> + (src_mem_access << SRC_ACCESS_TYPE_SHIFT) |
> + (dst_mem_access << DST_ACCESS_TYPE_SHIFT) |
> + FIELD_PREP(CCS_SIZE_MASK, blks_per_copy - 1));
> + *cmd++ = lower_32_bits(src_addr);
> + *cmd++ = ((upper_32_bits(src_addr) & 0xFFFF) |
> + FIELD_PREP(XY_CTRL_SURF_MOCS_MASK, src_mocs));
> + *cmd++ = lower_32_bits(dst_addr);
> + *cmd++ = ((upper_32_bits(dst_addr) & 0xFFFF) |
> + FIELD_PREP(XY_CTRL_SURF_MOCS_MASK, dst_mocs));
> + src_addr += SZ_64M;
> + dst_addr += SZ_64M;
> + blks_left -= blks_per_copy;
> + } while (blks_left > 0);
> +
> + return cmd;
> +}
> +
> static int emit_copy(struct i915_request *rq,
> u32 dst_offset, u32 src_offset, int size)
> {
> @@ -614,16 +723,24 @@ intel_context_migrate_copy(struct intel_context *ce,
> return err;
> }
>
> -static int emit_clear(struct i915_request *rq, u64 offset, int size, u32 value)
> +static int emit_clear(struct i915_request *rq, u64 offset, int size,
> + u32 value, bool is_lmem)
> {
> - const int ver = GRAPHICS_VER(rq->engine->i915);
> + struct drm_i915_private *i915 = rq->engine->i915;
> + const int ver = GRAPHICS_VER(i915);
> + u32 num_ccs_blks, ccs_ring_size;
> + int mocs = rq->engine->gt->mocs.uc_index << 1;
You mentioned it might be better to be rename uc_index. But this
variable is used named after the dg1's usage for uc mocs setting..
But for dg2 and xehpsdv this is used for pointing to uc_coherent_gomem.
So i leaving the variable name as it is for this patch.
Ram
> u32 *cs;
>
> GEM_BUG_ON(size >> PAGE_SHIFT > S16_MAX);
>
> offset += (u64)rq->engine->instance << 32;
>
> - cs = intel_ring_begin(rq, ver >= 8 ? 8 : 6);
> + /* Clear CCS only when value is 0 */
> + ccs_ring_size = (is_lmem && !value) ?
> + calc_ctrl_surf_instr_size(i915, size) : 0;
> +
> + cs = intel_ring_begin(rq, round_up(ver >= 8 ? 8 + ccs_ring_size : 6, 2));
> if (IS_ERR(cs))
> return PTR_ERR(cs);
>
> @@ -646,6 +763,27 @@ static int emit_clear(struct i915_request *rq, u64 offset, int size, u32 value)
> *cs++ = value;
> }
>
> + if (is_lmem && HAS_FLAT_CCS(i915) && !value) {
> + num_ccs_blks = DIV_ROUND_UP(GET_CCS_BYTES(i915, size),
> + NUM_CCS_BYTES_PER_BLOCK);
> +
> + /*
> + * Flat CCS surface can only be accessed via
> + * XY_CTRL_SURF_COPY_BLT CMD and using indirect
> + * mapping of associated LMEM.
> + * We can clear ccs surface by writing all 0s,
> + * so we will flush the previously cleared buffer
> + * and use it as a source.
> + */
> + cs = i915_flush_dw(cs, offset, MI_FLUSH_LLC | MI_FLUSH_CCS);
> + cs = _i915_ctrl_surf_copy_blt(cs, offset, offset,
> + DIRECT_ACCESS, INDIRECT_ACCESS,
> + mocs, mocs, num_ccs_blks);
> + cs = i915_flush_dw(cs, offset, MI_FLUSH_LLC | MI_FLUSH_CCS);
> +
> + if (ccs_ring_size & 1)
> + *cs++ = MI_NOOP;
> + }
> intel_ring_advance(rq, cs);
> return 0;
> }
> @@ -711,7 +849,7 @@ intel_context_migrate_clear(struct intel_context *ce,
> if (err)
> goto out_rq;
>
> - err = emit_clear(rq, offset, len, value);
> + err = emit_clear(rq, offset, len, value, is_lmem);
>
> /* Arbitration is re-enabled between requests. */
> out_rq:
> --
> 2.20.1
>
^ permalink raw reply [flat|nested] 4+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gt: Clear compress metadata for Xe_HP platforms
2022-02-28 21:21 [Intel-gfx] [PATCH] drm/i915/gt: Clear compress metadata for Xe_HP platforms Ramalingam C
2022-02-28 21:28 ` Ramalingam C
@ 2022-03-01 1:42 ` Patchwork
2022-03-01 12:19 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2 siblings, 0 replies; 4+ messages in thread
From: Patchwork @ 2022-03-01 1:42 UTC (permalink / raw)
To: Ramalingam C; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 6405 bytes --]
== Series Details ==
Series: drm/i915/gt: Clear compress metadata for Xe_HP platforms
URL : https://patchwork.freedesktop.org/series/100856/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11300 -> Patchwork_22442
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22442/index.html
Participating hosts (46 -> 40)
------------------------------
Additional (1): bat-jsl-2
Missing (7): shard-tglu shard-rkl fi-bsw-cyan bat-dg2-9 bat-rpls-2 shard-dg1 fi-bdw-samus
Known issues
------------
Here are the changes found in Patchwork_22442 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@amdgpu/amd_cs_nop@fork-compute0:
- fi-blb-e6850: NOTRUN -> [SKIP][1] ([fdo#109271]) +17 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22442/fi-blb-e6850/igt@amdgpu/amd_cs_nop@fork-compute0.html
* igt@i915_pm_rps@basic-api:
- bat-dg1-5: [PASS][2] -> [FAIL][3] ([i915#4032])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11300/bat-dg1-5/igt@i915_pm_rps@basic-api.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22442/bat-dg1-5/igt@i915_pm_rps@basic-api.html
* igt@kms_force_connector_basic@force-connector-state:
- bat-adlp-4: [PASS][4] -> [DMESG-WARN][5] ([i915#3576])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11300/bat-adlp-4/igt@kms_force_connector_basic@force-connector-state.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22442/bat-adlp-4/igt@kms_force_connector_basic@force-connector-state.html
#### Possible fixes ####
* igt@i915_selftest@live@gt_heartbeat:
- fi-glk-dsi: [DMESG-FAIL][6] ([i915#541]) -> [PASS][7]
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11300/fi-glk-dsi/igt@i915_selftest@live@gt_heartbeat.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22442/fi-glk-dsi/igt@i915_selftest@live@gt_heartbeat.html
* igt@i915_selftest@live@requests:
- fi-blb-e6850: [DMESG-FAIL][8] ([i915#5026]) -> [PASS][9]
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11300/fi-blb-e6850/igt@i915_selftest@live@requests.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22442/fi-blb-e6850/igt@i915_selftest@live@requests.html
* igt@kms_flip@basic-flip-vs-modeset@a-edp1:
- bat-adlp-4: [DMESG-WARN][10] ([i915#3576]) -> [PASS][11] +1 similar issue
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11300/bat-adlp-4/igt@kms_flip@basic-flip-vs-modeset@a-edp1.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22442/bat-adlp-4/igt@kms_flip@basic-flip-vs-modeset@a-edp1.html
* igt@kms_force_connector_basic@force-connector-state:
- fi-cfl-8109u: [DMESG-WARN][12] ([i915#165]) -> [PASS][13] +1 similar issue
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11300/fi-cfl-8109u/igt@kms_force_connector_basic@force-connector-state.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22442/fi-cfl-8109u/igt@kms_force_connector_basic@force-connector-state.html
* igt@kms_force_connector_basic@prune-stale-modes:
- fi-cfl-8109u: [DMESG-WARN][14] ([i915#165] / [i915#295]) -> [PASS][15] +1 similar issue
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11300/fi-cfl-8109u/igt@kms_force_connector_basic@prune-stale-modes.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22442/fi-cfl-8109u/igt@kms_force_connector_basic@prune-stale-modes.html
#### Warnings ####
* igt@kms_frontbuffer_tracking@basic:
- fi-cfl-8109u: [DMESG-WARN][16] ([i915#165] / [i915#295]) -> [DMESG-FAIL][17] ([i915#295])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11300/fi-cfl-8109u/igt@kms_frontbuffer_tracking@basic.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22442/fi-cfl-8109u/igt@kms_frontbuffer_tracking@basic.html
* igt@kms_pipe_crc_basic@read-crc-pipe-b:
- fi-cfl-8109u: [DMESG-WARN][18] ([i915#165] / [i915#295]) -> [DMESG-WARN][19] ([i915#295]) +10 similar issues
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11300/fi-cfl-8109u/igt@kms_pipe_crc_basic@read-crc-pipe-b.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22442/fi-cfl-8109u/igt@kms_pipe_crc_basic@read-crc-pipe-b.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#165]: https://gitlab.freedesktop.org/drm/intel/issues/165
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#295]: https://gitlab.freedesktop.org/drm/intel/issues/295
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#3576]: https://gitlab.freedesktop.org/drm/intel/issues/3576
[i915#4032]: https://gitlab.freedesktop.org/drm/intel/issues/4032
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#5026]: https://gitlab.freedesktop.org/drm/intel/issues/5026
[i915#5068]: https://gitlab.freedesktop.org/drm/intel/issues/5068
[i915#5127]: https://gitlab.freedesktop.org/drm/intel/issues/5127
[i915#5153]: https://gitlab.freedesktop.org/drm/intel/issues/5153
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#541]: https://gitlab.freedesktop.org/drm/intel/issues/541
Build changes
-------------
* Linux: CI_DRM_11300 -> Patchwork_22442
CI-20190529: 20190529
CI_DRM_11300: 10eb9bc8729d3da3fe8f53c8e5b70b8a9a52b6e0 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6361: 2372a4beb6a33c5f0799a4a8ccbb93794f52dbca @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_22442: b2d4ef97bcd8bf53b4ceb406631fce6f78013363 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
b2d4ef97bcd8 drm/i915/gt: Clear compress metadata for Xe_HP platforms
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22442/index.html
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^ permalink raw reply [flat|nested] 4+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/gt: Clear compress metadata for Xe_HP platforms
2022-02-28 21:21 [Intel-gfx] [PATCH] drm/i915/gt: Clear compress metadata for Xe_HP platforms Ramalingam C
2022-02-28 21:28 ` Ramalingam C
2022-03-01 1:42 ` [Intel-gfx] ✓ Fi.CI.BAT: success for " Patchwork
@ 2022-03-01 12:19 ` Patchwork
2 siblings, 0 replies; 4+ messages in thread
From: Patchwork @ 2022-03-01 12:19 UTC (permalink / raw)
To: Ramalingam C; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 30280 bytes --]
== Series Details ==
Series: drm/i915/gt: Clear compress metadata for Xe_HP platforms
URL : https://patchwork.freedesktop.org/series/100856/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11300_full -> Patchwork_22442_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_22442_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_22442_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (13 -> 13)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_22442_full:
### IGT changes ###
#### Possible regressions ####
* igt@gem_exec_suspend@basic-s0@smem:
- shard-iclb: [PASS][1] -> [SKIP][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11300/shard-iclb3/igt@gem_exec_suspend@basic-s0@smem.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22442/shard-iclb5/igt@gem_exec_suspend@basic-s0@smem.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-d-hdmi-a-3-planes-downscale}:
- {shard-dg1}: NOTRUN -> [SKIP][3] +8 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22442/shard-dg1-18/igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-d-hdmi-a-3-planes-downscale.html
* {igt@kms_plane_scaling@planes-scaling-unity-scaling}:
- {shard-rkl}: NOTRUN -> [SKIP][4] +6 similar issues
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22442/shard-rkl-1/igt@kms_plane_scaling@planes-scaling-unity-scaling.html
* {igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-b-edp-1-scaler-with-clipping-clamping}:
- shard-iclb: [PASS][5] -> [INCOMPLETE][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11300/shard-iclb4/igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-b-edp-1-scaler-with-clipping-clamping.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22442/shard-iclb2/igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-b-edp-1-scaler-with-clipping-clamping.html
New tests
---------
New tests have been introduced between CI_DRM_11300_full and Patchwork_22442_full:
### New IGT tests (1) ###
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-75@pipe-d-edp-1-planes-upscale-downscale:
- Statuses : 1 pass(s)
- Exec time: [1.28] s
Known issues
------------
Here are the changes found in Patchwork_22442_full that come from known issues:
### CI changes ###
#### Issues hit ####
* boot:
- shard-glk: ([PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25], [PASS][26], [PASS][27], [PASS][28], [PASS][29], [PASS][30], [PASS][31]) -> ([PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49], [PASS][50], [PASS][51], [PASS][52], [PASS][53], [FAIL][54], [PASS][55], [PASS][56]) ([i915#4392])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11300/shard-glk9/boot.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11300/shard-glk9/boot.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11300/shard-glk9/boot.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11300/shard-glk8/boot.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11300/shard-glk8/boot.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11300/shard-glk8/boot.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11300/shard-glk7/boot.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11300/shard-glk7/boot.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11300/shard-glk7/boot.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11300/shard-glk6/boot.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11300/shard-glk6/boot.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11300/shard-glk6/boot.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11300/shard-glk5/boot.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11300/shard-glk5/boot.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11300/shard-glk5/boot.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11300/shard-glk3/boot.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11300/shard-glk3/boot.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11300/shard-glk3/boot.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11300/shard-glk2/boot.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11300/shard-glk2/boot.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11300/shard-glk2/boot.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11300/shard-glk2/boot.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11300/shard-glk1/boot.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11300/shard-glk1/boot.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11300/shard-glk1/boot.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22442/shard-glk9/boot.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22442/shard-glk8/boot.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22442/shard-glk8/boot.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22442/shard-glk8/boot.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22442/shard-glk7/boot.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22442/shard-glk7/boot.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22442/shard-glk7/boot.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22442/shard-glk6/boot.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22442/shard-glk6/boot.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22442/shard-glk5/boot.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22442/shard-glk5/boot.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22442/shard-glk5/boot.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22442/shard-glk3/boot.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22442/shard-glk3/boot.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22442/shard-glk3/boot.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22442/shard-glk2/boot.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22442/shard-glk2/boot.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22442/shard-glk2/boot.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22442/shard-glk1/boot.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22442/shard-glk1/boot.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22442/shard-glk1/boot.html
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22442/shard-glk1/boot.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22442/shard-glk1/boot.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22442/shard-glk9/boot.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22442/shard-glk9/boot.html
### IGT changes ###
#### Issues hit ####
* igt@gem_eio@in-flight-contexts-1us:
- shard-iclb: [PASS][57] -> [TIMEOUT][58] ([i915#3070])
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11300/shard-iclb4/igt@gem_eio@in-flight-contexts-1us.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22442/shard-iclb2/igt@gem_eio@in-flight-contexts-1us.html
* igt@gem_exec_balancer@parallel-bb-first:
- shard-tglb: NOTRUN -> [DMESG-WARN][59] ([i915#5076])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22442/shard-tglb5/igt@gem_exec_balancer@parallel-bb-first.html
* igt@gem_exec_balancer@parallel-keep-submit-fence:
- shard-kbl: NOTRUN -> [DMESG-WARN][60] ([i915#5076])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22442/shard-kbl1/igt@gem_exec_balancer@parallel-keep-submit-fence.html
* igt@gem_exec_capture@pi@vcs0:
- shard-skl: NOTRUN -> [INCOMPLETE][61] ([i915#4547])
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22442/shard-skl4/igt@gem_exec_capture@pi@vcs0.html
* igt@gem_exec_fair@basic-deadline:
- shard-tglb: [PASS][62] -> [FAIL][63] ([i915#2846])
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11300/shard-tglb6/igt@gem_exec_fair@basic-deadline.html
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22442/shard-tglb2/igt@gem_exec_fair@basic-deadline.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-glk: [PASS][64] -> [FAIL][65] ([i915#2842])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11300/shard-glk5/igt@gem_exec_fair@basic-none-share@rcs0.html
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22442/shard-glk3/igt@gem_exec_fair@basic-none-share@rcs0.html
* igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-kbl: [PASS][66] -> [FAIL][67] ([i915#2842])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11300/shard-kbl3/igt@gem_exec_fair@basic-none-solo@rcs0.html
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22442/shard-kbl4/igt@gem_exec_fair@basic-none-solo@rcs0.html
* igt@gem_exec_fair@basic-pace@vcs1:
- shard-iclb: NOTRUN -> [FAIL][68] ([i915#2842])
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22442/shard-iclb4/igt@gem_exec_fair@basic-pace@vcs1.html
* igt@gem_huc_copy@huc-copy:
- shard-skl: NOTRUN -> [SKIP][69] ([fdo#109271] / [i915#2190])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22442/shard-skl6/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@parallel-random-verify:
- shard-tglb: NOTRUN -> [SKIP][70] ([i915#4613])
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22442/shard-tglb7/igt@gem_lmem_swapping@parallel-random-verify.html
- shard-apl: NOTRUN -> [SKIP][71] ([fdo#109271] / [i915#4613])
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22442/shard-apl2/igt@gem_lmem_swapping@parallel-random-verify.html
* igt@gem_pxp@create-regular-context-2:
- shard-tglb: NOTRUN -> [SKIP][72] ([i915#4270])
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22442/shard-tglb5/igt@gem_pxp@create-regular-context-2.html
* igt@gem_softpin@noreloc-s3:
- shard-kbl: [PASS][73] -> [DMESG-WARN][74] ([i915#180]) +1 similar issue
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11300/shard-kbl3/igt@gem_softpin@noreloc-s3.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22442/shard-kbl4/igt@gem_softpin@noreloc-s3.html
* igt@gem_userptr_blits@coherency-sync:
- shard-tglb: NOTRUN -> [SKIP][75] ([fdo#110542])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22442/shard-tglb7/igt@gem_userptr_blits@coherency-sync.html
* igt@gem_userptr_blits@huge-split:
- shard-tglb: [PASS][76] -> [FAIL][77] ([i915#3376])
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11300/shard-tglb3/igt@gem_userptr_blits@huge-split.html
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22442/shard-tglb3/igt@gem_userptr_blits@huge-split.html
* igt@gem_userptr_blits@unsync-unmap-after-close:
- shard-tglb: NOTRUN -> [SKIP][78] ([i915#3297])
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22442/shard-tglb7/igt@gem_userptr_blits@unsync-unmap-after-close.html
* igt@gen9_exec_parse@allowed-all:
- shard-glk: [PASS][79] -> [DMESG-WARN][80] ([i915#1436] / [i915#716])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11300/shard-glk2/igt@gen9_exec_parse@allowed-all.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22442/shard-glk1/igt@gen9_exec_parse@allowed-all.html
* igt@gen9_exec_parse@allowed-single:
- shard-skl: [PASS][81] -> [DMESG-WARN][82] ([i915#1436] / [i915#716])
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11300/shard-skl6/igt@gen9_exec_parse@allowed-single.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22442/shard-skl4/igt@gen9_exec_parse@allowed-single.html
* igt@gen9_exec_parse@shadow-peek:
- shard-tglb: NOTRUN -> [SKIP][83] ([i915#2527] / [i915#2856]) +2 similar issues
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22442/shard-tglb5/igt@gen9_exec_parse@shadow-peek.html
* igt@i915_pm_dc@dc6-psr:
- shard-tglb: NOTRUN -> [FAIL][84] ([i915#454])
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22442/shard-tglb7/igt@i915_pm_dc@dc6-psr.html
* igt@i915_pm_dc@dc9-dpms:
- shard-iclb: [PASS][85] -> [SKIP][86] ([i915#4281])
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11300/shard-iclb7/igt@i915_pm_dc@dc9-dpms.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22442/shard-iclb3/igt@i915_pm_dc@dc9-dpms.html
* igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-dp:
- shard-kbl: NOTRUN -> [SKIP][87] ([fdo#109271] / [i915#1937])
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22442/shard-kbl6/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-dp.html
* igt@i915_pm_rc6_residency@rc6-fence:
- shard-tglb: [PASS][88] -> [WARN][89] ([i915#2681] / [i915#2684])
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11300/shard-tglb2/igt@i915_pm_rc6_residency@rc6-fence.html
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22442/shard-tglb5/igt@i915_pm_rc6_residency@rc6-fence.html
* igt@i915_pm_rpm@modeset-pc8-residency-stress:
- shard-apl: NOTRUN -> [SKIP][90] ([fdo#109271]) +89 similar issues
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22442/shard-apl1/igt@i915_pm_rpm@modeset-pc8-residency-stress.html
* igt@i915_suspend@fence-restore-tiled2untiled:
- shard-apl: [PASS][91] -> [DMESG-WARN][92] ([i915#180]) +3 similar issues
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11300/shard-apl7/igt@i915_suspend@fence-restore-tiled2untiled.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22442/shard-apl1/igt@i915_suspend@fence-restore-tiled2untiled.html
* igt@kms_async_flips@crc:
- shard-tglb: [PASS][93] -> [FAIL][94] ([i915#4272])
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11300/shard-tglb6/igt@kms_async_flips@crc.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22442/shard-tglb2/igt@kms_async_flips@crc.html
* igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip:
- shard-apl: NOTRUN -> [SKIP][95] ([fdo#109271] / [i915#3777]) +2 similar issues
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22442/shard-apl1/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html
* igt@kms_big_fb@y-tiled-8bpp-rotate-90:
- shard-tglb: NOTRUN -> [SKIP][96] ([fdo#111614])
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22442/shard-tglb7/igt@kms_big_fb@y-tiled-8bpp-rotate-90.html
* igt@kms_big_fb@yf-tiled-64bpp-rotate-0:
- shard-tglb: NOTRUN -> [SKIP][97] ([fdo#111615]) +2 similar issues
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22442/shard-tglb5/igt@kms_big_fb@yf-tiled-64bpp-rotate-0.html
* igt@kms_ccs@pipe-a-bad-aux-stride-y_tiled_gen12_mc_ccs:
- shard-skl: NOTRUN -> [SKIP][98] ([fdo#109271] / [i915#3886])
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22442/shard-skl6/igt@kms_ccs@pipe-a-bad-aux-stride-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_mc_ccs:
- shard-apl: NOTRUN -> [SKIP][99] ([fdo#109271] / [i915#3886]) +2 similar issues
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22442/shard-apl1/igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-a-random-ccs-data-y_tiled_ccs:
- shard-tglb: NOTRUN -> [SKIP][100] ([i915#3689]) +2 similar issues
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22442/shard-tglb5/igt@kms_ccs@pipe-a-random-ccs-data-y_tiled_ccs.html
* igt@kms_ccs@pipe-b-crc-primary-basic-y_tiled_gen12_rc_ccs_cc:
- shard-kbl: NOTRUN -> [SKIP][101] ([fdo#109271] / [i915#3886]) +2 similar issues
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22442/shard-kbl1/igt@kms_ccs@pipe-b-crc-primary-basic-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-c-missing-ccs-buffer-yf_tiled_ccs:
- shard-tglb: NOTRUN -> [SKIP][102] ([fdo#111615] / [i915#3689]) +2 similar issues
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22442/shard-tglb7/igt@kms_ccs@pipe-c-missing-ccs-buffer-yf_tiled_ccs.html
* igt@kms_chamelium@hdmi-crc-multiple:
- shard-skl: NOTRUN -> [SKIP][103] ([fdo#109271] / [fdo#111827]) +4 similar issues
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22442/shard-skl6/igt@kms_chamelium@hdmi-crc-multiple.html
* igt@kms_chamelium@vga-hpd-enable-disable-mode:
- shard-kbl: NOTRUN -> [SKIP][104] ([fdo#109271] / [fdo#111827]) +1 similar issue
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22442/shard-kbl6/igt@kms_chamelium@vga-hpd-enable-disable-mode.html
* igt@kms_color_chamelium@pipe-b-ctm-0-5:
- shard-apl: NOTRUN -> [SKIP][105] ([fdo#109271] / [fdo#111827]) +8 similar issues
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22442/shard-apl1/igt@kms_color_chamelium@pipe-b-ctm-0-5.html
* igt@kms_color_chamelium@pipe-d-ctm-max:
- shard-tglb: NOTRUN -> [SKIP][106] ([fdo#109284] / [fdo#111827]) +2 similar issues
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22442/shard-tglb7/igt@kms_color_chamelium@pipe-d-ctm-max.html
* igt@kms_content_protection@dp-mst-lic-type-0:
- shard-tglb: NOTRUN -> [SKIP][107] ([i915#3116] / [i915#3299])
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22442/shard-tglb7/igt@kms_content_protection@dp-mst-lic-type-0.html
* igt@kms_content_protection@lic:
- shard-apl: NOTRUN -> [TIMEOUT][108] ([i915#1319])
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22442/shard-apl4/igt@kms_content_protection@lic.html
* igt@kms_cursor_crc@pipe-b-cursor-max-size-sliding:
- shard-tglb: NOTRUN -> [SKIP][109] ([i915#3359])
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22442/shard-tglb7/igt@kms_cursor_crc@pipe-b-cursor-max-size-sliding.html
* igt@kms_cursor_crc@pipe-c-cursor-32x32-onscreen:
- shard-tglb: NOTRUN -> [SKIP][110] ([i915#3319])
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22442/shard-tglb7/igt@kms_cursor_crc@pipe-c-cursor-32x32-onscreen.html
* igt@kms_cursor_crc@pipe-d-cursor-256x256-rapid-movement:
- shard-kbl: NOTRUN -> [SKIP][111] ([fdo#109271]) +38 similar issues
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22442/shard-kbl6/igt@kms_cursor_crc@pipe-d-cursor-256x256-rapid-movement.html
* igt@kms_cursor_crc@pipe-d-cursor-512x170-offscreen:
- shard-tglb: NOTRUN -> [SKIP][112] ([fdo#109279] / [i915#3359]) +3 similar issues
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22442/shard-tglb7/igt@kms_cursor_crc@pipe-d-cursor-512x170-offscreen.html
* igt@kms_cursor_legacy@cursora-vs-flipb-atomic:
- shard-tglb: NOTRUN -> [SKIP][113] ([fdo#109274] / [fdo#111825]) +4 similar issues
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22442/shard-tglb5/igt@kms_cursor_legacy@cursora-vs-flipb-atomic.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-iclb: [PASS][114] -> [FAIL][115] ([i915#2346])
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11300/shard-iclb6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22442/shard-iclb7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_cursor_legacy@pipe-d-single-bo:
- shard-kbl: NOTRUN -> [SKIP][116] ([fdo#109271] / [i915#533])
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22442/shard-kbl6/igt@kms_cursor_legacy@pipe-d-single-bo.html
* igt@kms_cursor_legacy@short-flip-before-cursor-toggle:
- shard-skl: [PASS][117] -> [FAIL][118] ([i915#2346])
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11300/shard-skl8/igt@kms_cursor_legacy@short-flip-before-cursor-toggle.html
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22442/shard-skl4/igt@kms_cursor_legacy@short-flip-before-cursor-toggle.html
* igt@kms_dp_tiled_display@basic-test-pattern-with-chamelium:
- shard-tglb: NOTRUN -> [SKIP][119] ([i915#3528])
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22442/shard-tglb7/igt@kms_dp_tiled_display@basic-test-pattern-with-chamelium.html
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ab-hdmi-a1-hdmi-a2:
- shard-glk: [PASS][120] -> [FAIL][121] ([i915#79])
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11300/shard-glk6/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ab-hdmi-a1-hdmi-a2.html
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22442/shard-glk9/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ab-hdmi-a1-hdmi-a2.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-blt:
- shard-tglb: NOTRUN -> [SKIP][122] ([fdo#109280] / [fdo#111825]) +7 similar issues
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22442/shard-tglb5/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-farfromfence-mmap-gtt:
- shard-skl: NOTRUN -> [SKIP][123] ([fdo#109271]) +37 similar issues
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22442/shard-skl6/igt@kms_frontbuffer_tracking@fbcpsr-farfromfence-mmap-gtt.html
* igt@kms_invalid_mode@clock-too-high:
- shard-tglb: NOTRUN -> [SKIP][124] ([i915#4278])
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22442/shard-tglb7/igt@kms_invalid_mode@clock-too-high.html
* igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
- shard-tglb: NOTRUN -> [SKIP][125] ([i915#1839])
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22442/shard-tglb7/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
* igt@kms_pipe_b_c_ivb@from-pipe-c-to-b-with-3-lanes:
- shard-tglb: NOTRUN -> [SKIP][126] ([fdo#109289]) +1 similar issue
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22442/shard-tglb7/igt@kms_pipe_b_c_ivb@from-pipe-c-to-b-with-3-lanes.html
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-d-frame-sequence:
- shard-apl: NOTRUN -> [SKIP][127] ([fdo#109271] / [i915#533])
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22442/shard-apl1/igt@kms_pipe_crc_basic@nonblocking-crc-pipe-d-frame-sequence.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-d:
- shard-skl: NOTRUN -> [SKIP][128] ([fdo#109271] / [i915#533])
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22442/shard-skl6/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-d.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-7efc:
- shard-apl: NOTRUN -> [FAIL][129] ([fdo#108145] / [i915#265]) +1 similar issue
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22442/shard-apl4/igt@kms_plane_alpha_blend@pipe-a-alpha-7efc.html
* igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max:
- shard-skl: NOTRUN -> [FAIL][130] ([fdo#108145] / [i915#265])
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22442/shard-skl6/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max.html
* igt@kms_plane_lowres@pipe-b-tiling-yf:
- shard-tglb: NOTRUN -> [SKIP][131] ([fdo#111615] / [fdo#112054])
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22442/shard-tglb5/igt@kms_plane_lowres@pipe-b-tiling-yf.html
* igt@kms_plane_lowres@pipe-c-tiling-none:
- shard-tglb: NOTRUN -> [SKIP][132] ([i915#3536]) +1 similar issue
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22442/shard-tglb5/igt@kms_plane_lowres@pipe-c-tiling-none.html
* igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area:
- shard-skl: NOTRUN -> [SKIP][133] ([fdo#109271] / [i915#658])
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22442/shard-skl6/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area.html
* igt@kms_psr2_su@page_flip-xrgb8888:
- shard-kbl: NOTRUN -> [SKIP][134] ([fdo#109271] / [i915#658])
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22442/shard-kbl1/igt@kms_psr2_su@page_flip-xrgb8888.html
* igt@kms_psr@psr2_sprite_mmap_gtt:
- shard-tglb: NOTRUN -> [FAIL][135] ([i915#132] / [i915#3467])
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22442/shard-tglb5/igt@kms_psr@psr2_sprite_mmap_gtt.html
* igt@kms_psr@psr2_sprite_plane_move:
- shard-iclb: [PASS][136] -> [SKIP][137] ([fdo#109441]) +2 similar issues
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11300/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22442/shard-iclb3/igt@kms_psr@psr2_sprite_plane_move.html
* igt@kms_writeback@writeback-invalid-parameters:
- shard-apl: NOTRUN -> [SKIP][138] ([fdo#109271] / [i915#2437])
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22442/shard-apl4/igt@kms_writeback@writeback-invalid-parameters.html
* igt@nouveau_crc@pipe-b-source-outp-complete:
- shard-tglb: NOTRUN -> [SKIP][139] ([i915#2530]) +1 similar issue
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22442/shard-tglb7/igt@nouveau_crc@pipe-b-source-outp-complete.html
* igt@prime_nv_api@i915_nv_double_import:
- shard-tglb: NOTRUN -> [SKIP][140] ([fdo#109291]) +1 similar issue
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22442/shard-tglb7/igt@prime_nv_api@i915_nv_double_import.html
* igt@sysfs_clients@recycle:
- shard-skl: NOTRUN -> [SKIP][141] ([fdo#109271] / [i915#2994])
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22442/shard-skl6/igt@sysfs_clients@recycle.html
#### Possible fixes ####
* igt@feature_discovery@psr2:
- {shard-rkl}: ([SKIP][142], [SKIP][143]) ([i915#658]) -> [PASS][144]
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11300/shard-rkl-4/igt@feature_discovery@psr2.html
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11300/shard-rkl-5/igt@feature_discovery@psr2.html
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22442/shard-rkl-6/igt@feature_discovery@psr2.html
* igt@gem_eio@unwedge-stress:
- shard-iclb: [TIMEOUT][145] ([i915#2481] / [i915#3070]) -> [PASS][146]
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11300/shard-iclb6/igt@gem_eio@unwedge-stress.html
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22442/shard-iclb4/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_capture@pi@rcs0:
- {shard-rkl}: [INCOMPLETE][147] ([i915#3371]) -> [PASS][148]
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11300/shard-rkl-1/igt@gem_exec_capture@pi@rcs0.html
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22442/shard-rkl-4/igt@gem_exec_capture@pi@rcs0.html
* igt@gem_exec_endless@dispatch@vecs0:
- {shard-tglu}: [INCOMPLETE][149] ([i915#3778]) -> [PASS][150]
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11300/shard-tglu-5/igt@gem_exec_endless@dispatch@vecs0.html
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22442/shard-tglu-2/igt@gem_exec_endless@dispatch@vecs0.html
* igt@gem_exec_fair@basic-none@vcs0:
- shard-apl: [FAIL][151] ([i915#2842]) -> [PASS][152]
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11300/shard-apl6/igt@gem_exec_fair@basic-none@vcs0.html
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22442/shard-apl8/igt@gem_exec_fair@basic-none@vcs0.html
* igt@gem_exec_fair@basic-pace@vcs0:
- shard-iclb: [FAIL][153] ([i915#2842]) -> [PASS][154]
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11300/shard-iclb6/igt@gem_exec_fair@basic-pace@vcs0.html
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22442/shard-iclb4/igt@gem_exec_fair@basic-pace@vcs0.html
* igt@gem_exec_fair@basic-pace@vcs1:
- shard-kbl: [FAIL][155] ([i915#2842]) -> [PASS][156] +1 similar issue
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11300/shard-kbl7/igt@gem_exec_fair@basic-pace@vcs1.html
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22442/shard-kbl4/igt@gem_exec_fair@basic-pace@vcs1.html
* igt@i915_pm_backlight@bad-brightness:
- {shard-rkl}: [SKIP][157] ([i915#3012]) -> [PASS][158] +1 similar issue
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11300/shard-rkl-5/igt@i915_pm_backlight@bad-brightness.html
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22442/shard-rkl-6/igt@i915_pm_backlight@bad-brightness.html
* igt@i915_pm_rpm@basic-rte:
- {shard-rkl}: [SKIP][159] ([fdo#109308]) -> [PASS][160] +1 similar issue
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22442/index.html
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end of thread, other threads:[~2022-03-01 12:19 UTC | newest]
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-- links below jump to the message on this page --
2022-02-28 21:21 [Intel-gfx] [PATCH] drm/i915/gt: Clear compress metadata for Xe_HP platforms Ramalingam C
2022-02-28 21:28 ` Ramalingam C
2022-03-01 1:42 ` [Intel-gfx] ✓ Fi.CI.BAT: success for " Patchwork
2022-03-01 12:19 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
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