* [Intel-gfx] [PATCH] drm/i915/dg2: Add preemption changes for Wa_14015141709
@ 2022-03-03 22:42 Matt Roper
2022-03-04 1:30 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
` (5 more replies)
0 siblings, 6 replies; 9+ messages in thread
From: Matt Roper @ 2022-03-03 22:42 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
From: Akeem G Abodunrin <akeem.g.abodunrin@intel.com>
Starting with DG2, preemption can no longer be controlled using userspace
on a per-context basis. Instead, the hardware only allows us to enable or
disable preemption in a global, system-wide basis. Also, we lose the
ability to specify the preemption granularity (such as batch-level vs
command-level vs object-level).
As a result of this - for debugging purposes, this patch adds debugfs
interface to configure (disable/enable) preemption globally.
Jira: VLK-27831
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
Cc: John Harrison <john.c.harrison@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: Akeem G Abodunrin <akeem.g.abodunrin@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 3 ++
drivers/gpu/drm/i915/gt/intel_workarounds.c | 2 +-
drivers/gpu/drm/i915/i915_debugfs.c | 50 +++++++++++++++++++++
drivers/gpu/drm/i915/i915_drv.h | 3 ++
4 files changed, 57 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 19cd34f24263..21ede1887b9f 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -468,6 +468,9 @@
#define VF_PREEMPTION _MMIO(0x83a4)
#define PREEMPTION_VERTEX_COUNT REG_GENMASK(15, 0)
+#define GEN12_VFG_PREEMPTION_CHICKEN _MMIO(0x83b4)
+#define GEN12_VFG_PREEMPT_CHICKEN_DISABLE REG_BIT(8)
+
#define GEN8_RC6_CTX_INFO _MMIO(0x8504)
#define GEN12_SQCM _MMIO(0x8724)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index c014b40d2e9f..18dc82f29776 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -2310,7 +2310,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
FF_DOP_CLOCK_GATE_DISABLE);
}
- if (IS_GRAPHICS_VER(i915, 9, 12)) {
+ if (HAS_PERCTX_PREEMPT_CTRL(i915)) {
/* FtrPerCtxtPreemptionGranularityControl:skl,bxt,kbl,cfl,cnl,icl,tgl */
wa_masked_en(wal,
GEN7_FF_SLICE_CS_CHICKEN1,
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 747fe9f41e1f..40e6e17e2950 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -571,6 +571,55 @@ static int i915_wa_registers(struct seq_file *m, void *unused)
return 0;
}
+static void i915_global_preemption_config(struct drm_i915_private *i915,
+ u32 val)
+{
+ const u32 bit = GEN12_VFG_PREEMPT_CHICKEN_DISABLE;
+
+ if (val)
+ intel_uncore_write(&i915->uncore, GEN12_VFG_PREEMPTION_CHICKEN,
+ _MASKED_BIT_DISABLE(bit));
+ else
+ intel_uncore_write(&i915->uncore, GEN12_VFG_PREEMPTION_CHICKEN,
+ _MASKED_BIT_ENABLE(bit));
+}
+
+static int i915_global_preempt_support_get(void *data, u64 *val)
+{
+ struct drm_i915_private *i915 = data;
+ intel_wakeref_t wakeref;
+ u32 curr_status = 0;
+
+ if (HAS_PERCTX_PREEMPT_CTRL(i915) || GRAPHICS_VER(i915) < 11)
+ return -EINVAL;
+
+ with_intel_runtime_pm(&i915->runtime_pm, wakeref)
+ curr_status = intel_uncore_read(&i915->uncore,
+ GEN12_VFG_PREEMPTION_CHICKEN);
+ *val = (curr_status & GEN12_VFG_PREEMPT_CHICKEN_DISABLE) ? 0 : 1;
+
+ return 0;
+}
+
+static int i915_global_preempt_support_set(void *data, u64 val)
+{
+ struct drm_i915_private *i915 = data;
+ intel_wakeref_t wakeref;
+
+ if (HAS_PERCTX_PREEMPT_CTRL(i915) || GRAPHICS_VER(i915) < 11)
+ return -EINVAL;
+
+ with_intel_runtime_pm(&i915->runtime_pm, wakeref)
+ i915_global_preemption_config(i915, val);
+
+ return 0;
+}
+
+DEFINE_SIMPLE_ATTRIBUTE(i915_global_preempt_support_fops,
+ i915_global_preempt_support_get,
+ i915_global_preempt_support_set,
+ "%lld\n");
+
static int i915_wedged_get(void *data, u64 *val)
{
struct drm_i915_private *i915 = data;
@@ -765,6 +814,7 @@ static const struct i915_debugfs_files {
const struct file_operations *fops;
} i915_debugfs_files[] = {
{"i915_perf_noa_delay", &i915_perf_noa_delay_fops},
+ {"i915_global_preempt_support", &i915_global_preempt_support_fops},
{"i915_wedged", &i915_wedged_fops},
{"i915_gem_drop_caches", &i915_drop_caches_fops},
#if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 457bc1993d19..8c3f69c87d36 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1407,6 +1407,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define HAS_GUC_DEPRIVILEGE(dev_priv) \
(INTEL_INFO(dev_priv)->has_guc_deprivilege)
+#define HAS_PERCTX_PREEMPT_CTRL(i915) \
+ ((GRAPHICS_VER(i915) >= 9) && GRAPHICS_VER_FULL(i915) < IP_VER(12, 55))
+
static inline bool run_as_guest(void)
{
return !hypervisor_is_type(X86_HYPER_NATIVE);
--
2.34.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/dg2: Add preemption changes for Wa_14015141709
2022-03-03 22:42 [Intel-gfx] [PATCH] drm/i915/dg2: Add preemption changes for Wa_14015141709 Matt Roper
@ 2022-03-04 1:30 ` Patchwork
2022-03-04 1:31 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
` (4 subsequent siblings)
5 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2022-03-04 1:30 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/dg2: Add preemption changes for Wa_14015141709
URL : https://patchwork.freedesktop.org/series/101023/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
1deb35fff8c4 drm/i915/dg2: Add preemption changes for Wa_14015141709
-:127: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible side-effects?
#127: FILE: drivers/gpu/drm/i915/i915_drv.h:1410:
+#define HAS_PERCTX_PREEMPT_CTRL(i915) \
+ ((GRAPHICS_VER(i915) >= 9) && GRAPHICS_VER_FULL(i915) < IP_VER(12, 55))
total: 0 errors, 0 warnings, 1 checks, 88 lines checked
^ permalink raw reply [flat|nested] 9+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/dg2: Add preemption changes for Wa_14015141709
2022-03-03 22:42 [Intel-gfx] [PATCH] drm/i915/dg2: Add preemption changes for Wa_14015141709 Matt Roper
2022-03-04 1:30 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
@ 2022-03-04 1:31 ` Patchwork
2022-03-04 2:05 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
` (3 subsequent siblings)
5 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2022-03-04 1:31 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/dg2: Add preemption changes for Wa_14015141709
URL : https://patchwork.freedesktop.org/series/101023/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 9+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/dg2: Add preemption changes for Wa_14015141709
2022-03-03 22:42 [Intel-gfx] [PATCH] drm/i915/dg2: Add preemption changes for Wa_14015141709 Matt Roper
2022-03-04 1:30 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
2022-03-04 1:31 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2022-03-04 2:05 ` Patchwork
2022-03-04 10:13 ` [Intel-gfx] [PATCH] " Jani Nikula
` (2 subsequent siblings)
5 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2022-03-04 2:05 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 5996 bytes --]
== Series Details ==
Series: drm/i915/dg2: Add preemption changes for Wa_14015141709
URL : https://patchwork.freedesktop.org/series/101023/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11322 -> Patchwork_22483
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22483/index.html
Participating hosts (45 -> 42)
------------------------------
Missing (3): fi-bsw-cyan fi-icl-u2 fi-bdw-samus
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_22483:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live@workarounds:
- {bat-adlp-6}: [PASS][1] -> [DMESG-WARN][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11322/bat-adlp-6/igt@i915_selftest@live@workarounds.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22483/bat-adlp-6/igt@i915_selftest@live@workarounds.html
Known issues
------------
Here are the changes found in Patchwork_22483 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_selftest@live@requests:
- fi-blb-e6850: [PASS][3] -> [DMESG-FAIL][4] ([i915#5026])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11322/fi-blb-e6850/igt@i915_selftest@live@requests.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22483/fi-blb-e6850/igt@i915_selftest@live@requests.html
* igt@kms_psr@primary_page_flip:
- fi-skl-6600u: [PASS][5] -> [FAIL][6] ([i915#4547])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11322/fi-skl-6600u/igt@kms_psr@primary_page_flip.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22483/fi-skl-6600u/igt@kms_psr@primary_page_flip.html
* igt@runner@aborted:
- fi-skl-6600u: NOTRUN -> [FAIL][7] ([i915#4312])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22483/fi-skl-6600u/igt@runner@aborted.html
- fi-blb-e6850: NOTRUN -> [FAIL][8] ([fdo#109271] / [i915#2403] / [i915#2426] / [i915#4312])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22483/fi-blb-e6850/igt@runner@aborted.html
#### Possible fixes ####
* igt@i915_selftest@live@guc_multi_lrc:
- {bat-rpls-2}: [DMESG-WARN][9] ([i915#4391]) -> [PASS][10] +2 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11322/bat-rpls-2/igt@i915_selftest@live@guc_multi_lrc.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22483/bat-rpls-2/igt@i915_selftest@live@guc_multi_lrc.html
* igt@i915_selftest@live@hugepages:
- {bat-rpls-2}: [DMESG-WARN][11] -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11322/bat-rpls-2/igt@i915_selftest@live@hugepages.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22483/bat-rpls-2/igt@i915_selftest@live@hugepages.html
* igt@i915_selftest@live@perf:
- {fi-tgl-dsi}: [DMESG-WARN][13] ([i915#2867]) -> [PASS][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11322/fi-tgl-dsi/igt@i915_selftest@live@perf.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22483/fi-tgl-dsi/igt@i915_selftest@live@perf.html
* igt@i915_selftest@live@requests:
- {bat-rpls-2}: [DMESG-FAIL][15] ([i915#5087]) -> [PASS][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11322/bat-rpls-2/igt@i915_selftest@live@requests.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22483/bat-rpls-2/igt@i915_selftest@live@requests.html
* igt@kms_busy@basic@flip:
- {bat-adlp-6}: [DMESG-WARN][17] ([i915#3576]) -> [PASS][18]
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11322/bat-adlp-6/igt@kms_busy@basic@flip.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22483/bat-adlp-6/igt@kms_busy@basic@flip.html
#### Warnings ####
* igt@i915_selftest@live@hangcheck:
- fi-hsw-4770: [INCOMPLETE][19] ([i915#3303]) -> [INCOMPLETE][20] ([i915#4785])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11322/fi-hsw-4770/igt@i915_selftest@live@hangcheck.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22483/fi-hsw-4770/igt@i915_selftest@live@hangcheck.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#2403]: https://gitlab.freedesktop.org/drm/intel/issues/2403
[i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426
[i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867
[i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
[i915#3576]: https://gitlab.freedesktop.org/drm/intel/issues/3576
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4391]: https://gitlab.freedesktop.org/drm/intel/issues/4391
[i915#4547]: https://gitlab.freedesktop.org/drm/intel/issues/4547
[i915#4785]: https://gitlab.freedesktop.org/drm/intel/issues/4785
[i915#5026]: https://gitlab.freedesktop.org/drm/intel/issues/5026
[i915#5087]: https://gitlab.freedesktop.org/drm/intel/issues/5087
Build changes
-------------
* Linux: CI_DRM_11322 -> Patchwork_22483
CI-20190529: 20190529
CI_DRM_11322: 7328c1d5b59036c9eee129e43b07b417e6c127e1 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6362: 698695136f8ade2391f2d8f45300eae2df02e947 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_22483: 1deb35fff8c4e44e5dae6f00dd908368a4a8e210 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
1deb35fff8c4 drm/i915/dg2: Add preemption changes for Wa_14015141709
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22483/index.html
[-- Attachment #2: Type: text/html, Size: 6932 bytes --]
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/dg2: Add preemption changes for Wa_14015141709
2022-03-03 22:42 [Intel-gfx] [PATCH] drm/i915/dg2: Add preemption changes for Wa_14015141709 Matt Roper
` (2 preceding siblings ...)
2022-03-04 2:05 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2022-03-04 10:13 ` Jani Nikula
2022-03-04 22:54 ` Matt Roper
2022-03-04 11:35 ` Tvrtko Ursulin
2022-03-04 15:26 ` [Intel-gfx] ✓ Fi.CI.IGT: success for " Patchwork
5 siblings, 1 reply; 9+ messages in thread
From: Jani Nikula @ 2022-03-04 10:13 UTC (permalink / raw)
To: Matt Roper, intel-gfx; +Cc: dri-devel
On Thu, 03 Mar 2022, Matt Roper <matthew.d.roper@intel.com> wrote:
> From: Akeem G Abodunrin <akeem.g.abodunrin@intel.com>
>
> Starting with DG2, preemption can no longer be controlled using userspace
> on a per-context basis. Instead, the hardware only allows us to enable or
> disable preemption in a global, system-wide basis. Also, we lose the
> ability to specify the preemption granularity (such as batch-level vs
> command-level vs object-level).
>
> As a result of this - for debugging purposes, this patch adds debugfs
> interface to configure (disable/enable) preemption globally.
>
> Jira: VLK-27831
Please remove internal Jira references.
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
> Cc: John Harrison <john.c.harrison@intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Signed-off-by: Akeem G Abodunrin <akeem.g.abodunrin@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_gt_regs.h | 3 ++
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 2 +-
> drivers/gpu/drm/i915/i915_debugfs.c | 50 +++++++++++++++++++++
> drivers/gpu/drm/i915/i915_drv.h | 3 ++
> 4 files changed, 57 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> index 19cd34f24263..21ede1887b9f 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> @@ -468,6 +468,9 @@
> #define VF_PREEMPTION _MMIO(0x83a4)
> #define PREEMPTION_VERTEX_COUNT REG_GENMASK(15, 0)
>
> +#define GEN12_VFG_PREEMPTION_CHICKEN _MMIO(0x83b4)
> +#define GEN12_VFG_PREEMPT_CHICKEN_DISABLE REG_BIT(8)
> +
> #define GEN8_RC6_CTX_INFO _MMIO(0x8504)
>
> #define GEN12_SQCM _MMIO(0x8724)
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index c014b40d2e9f..18dc82f29776 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -2310,7 +2310,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> FF_DOP_CLOCK_GATE_DISABLE);
> }
>
> - if (IS_GRAPHICS_VER(i915, 9, 12)) {
> + if (HAS_PERCTX_PREEMPT_CTRL(i915)) {
Adding HAS_PERCTX_PREEMPT_CTRL(i915) and using it is a separate change
from the debugfs. Please split it up.
> /* FtrPerCtxtPreemptionGranularityControl:skl,bxt,kbl,cfl,cnl,icl,tgl */
> wa_masked_en(wal,
> GEN7_FF_SLICE_CS_CHICKEN1,
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 747fe9f41e1f..40e6e17e2950 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -571,6 +571,55 @@ static int i915_wa_registers(struct seq_file *m, void *unused)
> return 0;
> }
>
> +static void i915_global_preemption_config(struct drm_i915_private *i915,
> + u32 val)
> +{
> + const u32 bit = GEN12_VFG_PREEMPT_CHICKEN_DISABLE;
We rarely use const for locals, and usually only if the function is big.
I'd probably use:
u32 tmp = val ?
_MASKED_BIT_DISABLE(GEN12_VFG_PREEMPT_CHICKEN_DISABLE) :
_MASKED_BIT_ENABLE(GEN12_VFG_PREEMPT_CHICKEN_DISABLE);
To have just one intel_uncore_write().
> +
> + if (val)
> + intel_uncore_write(&i915->uncore, GEN12_VFG_PREEMPTION_CHICKEN,
> + _MASKED_BIT_DISABLE(bit));
> + else
> + intel_uncore_write(&i915->uncore, GEN12_VFG_PREEMPTION_CHICKEN,
> + _MASKED_BIT_ENABLE(bit));
We really shouldn't be adding new direct low-level register access in
i915_debugfs.c.
Please define an interface for this and add the functionality to a
suitable place, and then call the functions from here.
> +}
> +
> +static int i915_global_preempt_support_get(void *data, u64 *val)
> +{
> + struct drm_i915_private *i915 = data;
> + intel_wakeref_t wakeref;
> + u32 curr_status = 0;
> +
> + if (HAS_PERCTX_PREEMPT_CTRL(i915) || GRAPHICS_VER(i915) < 11)
> + return -EINVAL;
> +
> + with_intel_runtime_pm(&i915->runtime_pm, wakeref)
> + curr_status = intel_uncore_read(&i915->uncore,
> + GEN12_VFG_PREEMPTION_CHICKEN);
> + *val = (curr_status & GEN12_VFG_PREEMPT_CHICKEN_DISABLE) ? 0 : 1;
> +
> + return 0;
> +}
> +
> +static int i915_global_preempt_support_set(void *data, u64 val)
> +{
> + struct drm_i915_private *i915 = data;
> + intel_wakeref_t wakeref;
> +
> + if (HAS_PERCTX_PREEMPT_CTRL(i915) || GRAPHICS_VER(i915) < 11)
> + return -EINVAL;
> +
> + with_intel_runtime_pm(&i915->runtime_pm, wakeref)
> + i915_global_preemption_config(i915, val);
> +
> + return 0;
> +}
> +
> +DEFINE_SIMPLE_ATTRIBUTE(i915_global_preempt_support_fops,
> + i915_global_preempt_support_get,
> + i915_global_preempt_support_set,
> + "%lld\n");
DEFINE_DEBUGFS_ATTRIBUTE.
> +
> static int i915_wedged_get(void *data, u64 *val)
> {
> struct drm_i915_private *i915 = data;
> @@ -765,6 +814,7 @@ static const struct i915_debugfs_files {
> const struct file_operations *fops;
> } i915_debugfs_files[] = {
> {"i915_perf_noa_delay", &i915_perf_noa_delay_fops},
> + {"i915_global_preempt_support", &i915_global_preempt_support_fops},
> {"i915_wedged", &i915_wedged_fops},
> {"i915_gem_drop_caches", &i915_drop_caches_fops},
> #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 457bc1993d19..8c3f69c87d36 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1407,6 +1407,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> #define HAS_GUC_DEPRIVILEGE(dev_priv) \
> (INTEL_INFO(dev_priv)->has_guc_deprivilege)
>
> +#define HAS_PERCTX_PREEMPT_CTRL(i915) \
> + ((GRAPHICS_VER(i915) >= 9) && GRAPHICS_VER_FULL(i915) < IP_VER(12, 55))
> +
> static inline bool run_as_guest(void)
> {
> return !hypervisor_is_type(X86_HYPER_NATIVE);
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/dg2: Add preemption changes for Wa_14015141709
2022-03-03 22:42 [Intel-gfx] [PATCH] drm/i915/dg2: Add preemption changes for Wa_14015141709 Matt Roper
` (3 preceding siblings ...)
2022-03-04 10:13 ` [Intel-gfx] [PATCH] " Jani Nikula
@ 2022-03-04 11:35 ` Tvrtko Ursulin
2022-03-04 15:26 ` [Intel-gfx] ✓ Fi.CI.IGT: success for " Patchwork
5 siblings, 0 replies; 9+ messages in thread
From: Tvrtko Ursulin @ 2022-03-04 11:35 UTC (permalink / raw)
To: Matt Roper, intel-gfx; +Cc: dri-devel
On 03/03/2022 22:42, Matt Roper wrote:
> From: Akeem G Abodunrin <akeem.g.abodunrin@intel.com>
>
> Starting with DG2, preemption can no longer be controlled using userspace
> on a per-context basis. Instead, the hardware only allows us to enable or
> disable preemption in a global, system-wide basis. Also, we lose the
> ability to specify the preemption granularity (such as batch-level vs
> command-level vs object-level).
>
> As a result of this - for debugging purposes, this patch adds debugfs
> interface to configure (disable/enable) preemption globally.
>
> Jira: VLK-27831
>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
> Cc: John Harrison <john.c.harrison@intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Signed-off-by: Akeem G Abodunrin <akeem.g.abodunrin@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_gt_regs.h | 3 ++
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 2 +-
> drivers/gpu/drm/i915/i915_debugfs.c | 50 +++++++++++++++++++++
> drivers/gpu/drm/i915/i915_drv.h | 3 ++
> 4 files changed, 57 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> index 19cd34f24263..21ede1887b9f 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> @@ -468,6 +468,9 @@
> #define VF_PREEMPTION _MMIO(0x83a4)
> #define PREEMPTION_VERTEX_COUNT REG_GENMASK(15, 0)
>
> +#define GEN12_VFG_PREEMPTION_CHICKEN _MMIO(0x83b4)
> +#define GEN12_VFG_PREEMPT_CHICKEN_DISABLE REG_BIT(8)
> +
> #define GEN8_RC6_CTX_INFO _MMIO(0x8504)
>
> #define GEN12_SQCM _MMIO(0x8724)
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index c014b40d2e9f..18dc82f29776 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -2310,7 +2310,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> FF_DOP_CLOCK_GATE_DISABLE);
> }
>
> - if (IS_GRAPHICS_VER(i915, 9, 12)) {
> + if (HAS_PERCTX_PREEMPT_CTRL(i915)) {
> /* FtrPerCtxtPreemptionGranularityControl:skl,bxt,kbl,cfl,cnl,icl,tgl */
> wa_masked_en(wal,
> GEN7_FF_SLICE_CS_CHICKEN1,
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 747fe9f41e1f..40e6e17e2950 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -571,6 +571,55 @@ static int i915_wa_registers(struct seq_file *m, void *unused)
> return 0;
> }
>
> +static void i915_global_preemption_config(struct drm_i915_private *i915,
> + u32 val)
> +{
> + const u32 bit = GEN12_VFG_PREEMPT_CHICKEN_DISABLE;
> +
> + if (val)
> + intel_uncore_write(&i915->uncore, GEN12_VFG_PREEMPTION_CHICKEN,
> + _MASKED_BIT_DISABLE(bit));
> + else
> + intel_uncore_write(&i915->uncore, GEN12_VFG_PREEMPTION_CHICKEN,
> + _MASKED_BIT_ENABLE(bit));
In addition to what Jani suggested some other questions:
Does this setting survive GT reset?
Would intel_reg read/write work?
Can we not add the debugfs file to start with if register is n/a for a platform?
> +}
> +
> +static int i915_global_preempt_support_get(void *data, u64 *val)
> +{
> + struct drm_i915_private *i915 = data;
> + intel_wakeref_t wakeref;
> + u32 curr_status = 0;
> +
> + if (HAS_PERCTX_PREEMPT_CTRL(i915) || GRAPHICS_VER(i915) < 11)
> + return -EINVAL;
What is the purpose of the "< 11" condition here? Because HAS_PERCTX_PREEMPT_CTRL is defined as starting on Gen9? Is the 11 arbitrary then or has some deeper meaning?
Regards,
Tvrtko
> +
> + with_intel_runtime_pm(&i915->runtime_pm, wakeref)
> + curr_status = intel_uncore_read(&i915->uncore,
> + GEN12_VFG_PREEMPTION_CHICKEN);
> + *val = (curr_status & GEN12_VFG_PREEMPT_CHICKEN_DISABLE) ? 0 : 1;
> +
> + return 0;
> +}
> +
> +static int i915_global_preempt_support_set(void *data, u64 val)
> +{
> + struct drm_i915_private *i915 = data;
> + intel_wakeref_t wakeref;
> +
> + if (HAS_PERCTX_PREEMPT_CTRL(i915) || GRAPHICS_VER(i915) < 11)
> + return -EINVAL;
> +
> + with_intel_runtime_pm(&i915->runtime_pm, wakeref)
> + i915_global_preemption_config(i915, val);
> +
> + return 0;
> +}
> +
> +DEFINE_SIMPLE_ATTRIBUTE(i915_global_preempt_support_fops,
> + i915_global_preempt_support_get,
> + i915_global_preempt_support_set,
> + "%lld\n");
> +
> static int i915_wedged_get(void *data, u64 *val)
> {
> struct drm_i915_private *i915 = data;
> @@ -765,6 +814,7 @@ static const struct i915_debugfs_files {
> const struct file_operations *fops;
> } i915_debugfs_files[] = {
> {"i915_perf_noa_delay", &i915_perf_noa_delay_fops},
> + {"i915_global_preempt_support", &i915_global_preempt_support_fops},
> {"i915_wedged", &i915_wedged_fops},
> {"i915_gem_drop_caches", &i915_drop_caches_fops},
> #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 457bc1993d19..8c3f69c87d36 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1407,6 +1407,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> #define HAS_GUC_DEPRIVILEGE(dev_priv) \
> (INTEL_INFO(dev_priv)->has_guc_deprivilege)
>
> +#define HAS_PERCTX_PREEMPT_CTRL(i915) \
> + ((GRAPHICS_VER(i915) >= 9) && GRAPHICS_VER_FULL(i915) < IP_VER(12, 55))
> +
> static inline bool run_as_guest(void)
> {
> return !hypervisor_is_type(X86_HYPER_NATIVE);
^ permalink raw reply [flat|nested] 9+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/dg2: Add preemption changes for Wa_14015141709
2022-03-03 22:42 [Intel-gfx] [PATCH] drm/i915/dg2: Add preemption changes for Wa_14015141709 Matt Roper
` (4 preceding siblings ...)
2022-03-04 11:35 ` Tvrtko Ursulin
@ 2022-03-04 15:26 ` Patchwork
5 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2022-03-04 15:26 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 30279 bytes --]
== Series Details ==
Series: drm/i915/dg2: Add preemption changes for Wa_14015141709
URL : https://patchwork.freedesktop.org/series/101023/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11322_full -> Patchwork_22483_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (13 -> 13)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_22483_full:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-a-edp-1-planes-upscale-downscale}:
- {shard-rkl}: NOTRUN -> [SKIP][1] +1 similar issue
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22483/shard-rkl-6/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-a-edp-1-planes-upscale-downscale.html
* igt@prime_mmap_coherency@ioctl-errors:
- {shard-dg1}: NOTRUN -> [SKIP][2] +2 similar issues
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22483/shard-dg1-15/igt@prime_mmap_coherency@ioctl-errors.html
Known issues
------------
Here are the changes found in Patchwork_22483_full that come from known issues:
### CI changes ###
#### Possible fixes ####
* boot:
- shard-apl: ([PASS][3], [FAIL][4], [PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25], [PASS][26], [PASS][27]) ([i915#4386]) -> ([PASS][28], [PASS][29], [PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49], [PASS][50], [PASS][51], [PASS][52])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11322/shard-apl1/boot.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11322/shard-apl1/boot.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11322/shard-apl1/boot.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11322/shard-apl1/boot.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11322/shard-apl2/boot.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11322/shard-apl2/boot.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11322/shard-apl2/boot.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11322/shard-apl2/boot.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11322/shard-apl2/boot.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11322/shard-apl3/boot.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11322/shard-apl3/boot.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11322/shard-apl3/boot.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11322/shard-apl4/boot.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11322/shard-apl4/boot.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11322/shard-apl4/boot.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11322/shard-apl6/boot.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11322/shard-apl6/boot.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11322/shard-apl6/boot.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11322/shard-apl6/boot.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11322/shard-apl7/boot.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11322/shard-apl7/boot.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11322/shard-apl7/boot.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11322/shard-apl8/boot.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11322/shard-apl8/boot.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11322/shard-apl8/boot.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22483/shard-apl1/boot.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22483/shard-apl1/boot.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22483/shard-apl1/boot.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22483/shard-apl2/boot.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22483/shard-apl2/boot.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22483/shard-apl2/boot.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22483/shard-apl3/boot.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22483/shard-apl3/boot.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22483/shard-apl3/boot.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22483/shard-apl3/boot.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22483/shard-apl4/boot.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22483/shard-apl4/boot.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22483/shard-apl4/boot.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22483/shard-apl6/boot.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22483/shard-apl6/boot.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22483/shard-apl6/boot.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22483/shard-apl6/boot.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22483/shard-apl6/boot.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22483/shard-apl6/boot.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22483/shard-apl7/boot.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22483/shard-apl7/boot.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22483/shard-apl7/boot.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22483/shard-apl7/boot.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22483/shard-apl8/boot.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22483/shard-apl8/boot.html
- {shard-rkl}: ([PASS][53], [PASS][54], [PASS][55], [PASS][56], [FAIL][57], [PASS][58], [PASS][59], [PASS][60], [PASS][61], [PASS][62], [PASS][63], [PASS][64], [PASS][65], [PASS][66], [PASS][67], [PASS][68], [PASS][69], [PASS][70], [PASS][71]) ([i915#5131]) -> ([PASS][72], [PASS][73], [PASS][74], [PASS][75], [PASS][76], [PASS][77], [PASS][78], [PASS][79], [PASS][80], [PASS][81], [PASS][82], [PASS][83], [PASS][84], [PASS][85], [PASS][86], [PASS][87], [PASS][88], [PASS][89], [PASS][90], [PASS][91])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11322/shard-rkl-6/boot.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11322/shard-rkl-6/boot.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11322/shard-rkl-6/boot.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11322/shard-rkl-6/boot.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11322/shard-rkl-5/boot.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11322/shard-rkl-5/boot.html
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11322/shard-rkl-5/boot.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11322/shard-rkl-5/boot.html
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11322/shard-rkl-5/boot.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11322/shard-rkl-5/boot.html
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11322/shard-rkl-2/boot.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11322/shard-rkl-2/boot.html
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11322/shard-rkl-2/boot.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11322/shard-rkl-2/boot.html
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11322/shard-rkl-2/boot.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11322/shard-rkl-2/boot.html
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11322/shard-rkl-1/boot.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11322/shard-rkl-1/boot.html
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11322/shard-rkl-1/boot.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22483/shard-rkl-6/boot.html
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22483/shard-rkl-6/boot.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22483/shard-rkl-6/boot.html
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22483/shard-rkl-5/boot.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22483/shard-rkl-5/boot.html
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22483/shard-rkl-5/boot.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22483/shard-rkl-4/boot.html
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22483/shard-rkl-4/boot.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22483/shard-rkl-2/boot.html
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22483/shard-rkl-2/boot.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22483/shard-rkl-2/boot.html
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22483/shard-rkl-2/boot.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22483/shard-rkl-2/boot.html
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22483/shard-rkl-2/boot.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22483/shard-rkl-1/boot.html
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22483/shard-rkl-1/boot.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22483/shard-rkl-1/boot.html
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22483/shard-rkl-1/boot.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22483/shard-rkl-1/boot.html
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22483/shard-rkl-1/boot.html
### IGT changes ###
#### Issues hit ####
* igt@gem_create@create-massive:
- shard-apl: NOTRUN -> [DMESG-WARN][92] ([i915#4991])
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22483/shard-apl6/igt@gem_create@create-massive.html
* igt@gem_exec_balancer@parallel:
- shard-iclb: NOTRUN -> [SKIP][93] ([i915#4525])
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22483/shard-iclb3/igt@gem_exec_balancer@parallel.html
- shard-tglb: NOTRUN -> [DMESG-WARN][94] ([i915#5076])
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22483/shard-tglb3/igt@gem_exec_balancer@parallel.html
* igt@gem_exec_fair@basic-none@rcs0:
- shard-kbl: [PASS][95] -> [FAIL][96] ([i915#2842]) +1 similar issue
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11322/shard-kbl4/igt@gem_exec_fair@basic-none@rcs0.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22483/shard-kbl6/igt@gem_exec_fair@basic-none@rcs0.html
* igt@gem_huc_copy@huc-copy:
- shard-tglb: [PASS][97] -> [SKIP][98] ([i915#2190])
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11322/shard-tglb2/igt@gem_huc_copy@huc-copy.html
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22483/shard-tglb6/igt@gem_huc_copy@huc-copy.html
* igt@gem_render_copy@linear-to-vebox-y-tiled:
- shard-apl: NOTRUN -> [SKIP][99] ([fdo#109271]) +135 similar issues
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22483/shard-apl2/igt@gem_render_copy@linear-to-vebox-y-tiled.html
* igt@kms_big_fb@linear-32bpp-rotate-0:
- shard-glk: [PASS][100] -> [DMESG-WARN][101] ([i915#118]) +1 similar issue
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11322/shard-glk6/igt@kms_big_fb@linear-32bpp-rotate-0.html
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22483/shard-glk8/igt@kms_big_fb@linear-32bpp-rotate-0.html
* igt@kms_big_fb@linear-64bpp-rotate-270:
- shard-iclb: NOTRUN -> [SKIP][102] ([fdo#110725] / [fdo#111614])
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22483/shard-iclb3/igt@kms_big_fb@linear-64bpp-rotate-270.html
- shard-tglb: NOTRUN -> [SKIP][103] ([fdo#111614])
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22483/shard-tglb3/igt@kms_big_fb@linear-64bpp-rotate-270.html
* igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip:
- shard-apl: NOTRUN -> [SKIP][104] ([fdo#109271] / [i915#3777])
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22483/shard-apl6/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html
* igt@kms_ccs@pipe-b-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc:
- shard-apl: NOTRUN -> [SKIP][105] ([fdo#109271] / [i915#3886]) +8 similar issues
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22483/shard-apl6/igt@kms_ccs@pipe-b-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-d-bad-aux-stride-y_tiled_ccs:
- shard-tglb: NOTRUN -> [SKIP][106] ([i915#3689]) +1 similar issue
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22483/shard-tglb7/igt@kms_ccs@pipe-d-bad-aux-stride-y_tiled_ccs.html
* igt@kms_ccs@pipe-d-crc-primary-basic-y_tiled_ccs:
- shard-iclb: NOTRUN -> [SKIP][107] ([fdo#109278]) +1 similar issue
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22483/shard-iclb3/igt@kms_ccs@pipe-d-crc-primary-basic-y_tiled_ccs.html
* igt@kms_chamelium@dp-crc-fast:
- shard-iclb: NOTRUN -> [SKIP][108] ([fdo#109284] / [fdo#111827])
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22483/shard-iclb3/igt@kms_chamelium@dp-crc-fast.html
- shard-tglb: NOTRUN -> [SKIP][109] ([fdo#109284] / [fdo#111827])
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22483/shard-tglb3/igt@kms_chamelium@dp-crc-fast.html
* igt@kms_chamelium@vga-hpd-enable-disable-mode:
- shard-apl: NOTRUN -> [SKIP][110] ([fdo#109271] / [fdo#111827]) +12 similar issues
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22483/shard-apl6/igt@kms_chamelium@vga-hpd-enable-disable-mode.html
* igt@kms_content_protection@lic:
- shard-apl: NOTRUN -> [TIMEOUT][111] ([i915#1319])
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22483/shard-apl8/igt@kms_content_protection@lic.html
* igt@kms_cursor_crc@pipe-b-cursor-256x256-onscreen:
- shard-iclb: [PASS][112] -> [DMESG-WARN][113] ([i915#4391])
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11322/shard-iclb7/igt@kms_cursor_crc@pipe-b-cursor-256x256-onscreen.html
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22483/shard-iclb7/igt@kms_cursor_crc@pipe-b-cursor-256x256-onscreen.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-iclb: [PASS][114] -> [FAIL][115] ([i915#2346])
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11322/shard-iclb2/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22483/shard-iclb7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-hdmi-a1-hdmi-a2:
- shard-glk: [PASS][116] -> [FAIL][117] ([i915#79])
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11322/shard-glk3/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-hdmi-a1-hdmi-a2.html
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22483/shard-glk6/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-hdmi-a1-hdmi-a2.html
* igt@kms_flip@flip-vs-suspend-interruptible@c-dp1:
- shard-kbl: [PASS][118] -> [INCOMPLETE][119] ([i915#636])
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11322/shard-kbl7/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22483/shard-kbl3/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-cpu:
- shard-iclb: NOTRUN -> [SKIP][120] ([fdo#109280])
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22483/shard-iclb3/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-cpu.html
* igt@kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-move:
- shard-tglb: NOTRUN -> [SKIP][121] ([fdo#109280] / [fdo#111825]) +1 similar issue
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22483/shard-tglb7/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-move.html
* igt@kms_pipe_b_c_ivb@from-pipe-c-to-b-with-3-lanes:
- shard-tglb: NOTRUN -> [SKIP][122] ([fdo#109289])
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22483/shard-tglb1/igt@kms_pipe_b_c_ivb@from-pipe-c-to-b-with-3-lanes.html
* igt@kms_pipe_crc_basic@read-crc-pipe-d-frame-sequence:
- shard-apl: NOTRUN -> [SKIP][123] ([fdo#109271] / [i915#533]) +1 similar issue
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22483/shard-apl2/igt@kms_pipe_crc_basic@read-crc-pipe-d-frame-sequence.html
* igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes:
- shard-apl: [PASS][124] -> [DMESG-WARN][125] ([i915#180]) +7 similar issues
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11322/shard-apl6/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes.html
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22483/shard-apl6/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes.html
* igt@kms_psr2_su@page_flip-p010:
- shard-apl: NOTRUN -> [SKIP][126] ([fdo#109271] / [i915#658])
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22483/shard-apl2/igt@kms_psr2_su@page_flip-p010.html
* igt@kms_psr@psr2_cursor_plane_onoff:
- shard-iclb: [PASS][127] -> [SKIP][128] ([fdo#109441])
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11322/shard-iclb2/igt@kms_psr@psr2_cursor_plane_onoff.html
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22483/shard-iclb8/igt@kms_psr@psr2_cursor_plane_onoff.html
* igt@kms_sysfs_edid_timing:
- shard-apl: NOTRUN -> [FAIL][129] ([IGT#2])
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22483/shard-apl1/igt@kms_sysfs_edid_timing.html
* igt@kms_writeback@writeback-invalid-parameters:
- shard-apl: NOTRUN -> [SKIP][130] ([fdo#109271] / [i915#2437]) +1 similar issue
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22483/shard-apl8/igt@kms_writeback@writeback-invalid-parameters.html
* igt@nouveau_crc@pipe-c-source-outp-complete:
- shard-tglb: NOTRUN -> [SKIP][131] ([i915#2530])
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22483/shard-tglb1/igt@nouveau_crc@pipe-c-source-outp-complete.html
* igt@sysfs_clients@fair-7:
- shard-apl: NOTRUN -> [SKIP][132] ([fdo#109271] / [i915#2994]) +2 similar issues
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22483/shard-apl1/igt@sysfs_clients@fair-7.html
#### Possible fixes ####
* igt@gem_ctx_persistence@engines-hostile@rcs0:
- {shard-rkl}: [FAIL][133] ([i915#2410]) -> ([PASS][134], [PASS][135])
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11322/shard-rkl-2/igt@gem_ctx_persistence@engines-hostile@rcs0.html
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22483/shard-rkl-6/igt@gem_ctx_persistence@engines-hostile@rcs0.html
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22483/shard-rkl-4/igt@gem_ctx_persistence@engines-hostile@rcs0.html
* igt@gem_eio@unwedge-stress:
- shard-iclb: [TIMEOUT][136] ([i915#2481] / [i915#3070]) -> [PASS][137]
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11322/shard-iclb4/igt@gem_eio@unwedge-stress.html
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22483/shard-iclb2/igt@gem_eio@unwedge-stress.html
- {shard-rkl}: [TIMEOUT][138] ([i915#3063]) -> [PASS][139]
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11322/shard-rkl-1/igt@gem_eio@unwedge-stress.html
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22483/shard-rkl-1/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_fair@basic-none@vcs0:
- shard-apl: [FAIL][140] ([i915#2842]) -> [PASS][141]
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11322/shard-apl7/igt@gem_exec_fair@basic-none@vcs0.html
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22483/shard-apl1/igt@gem_exec_fair@basic-none@vcs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- {shard-tglu}: [FAIL][142] ([i915#2842]) -> [PASS][143]
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11322/shard-tglu-1/igt@gem_exec_fair@basic-pace-share@rcs0.html
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22483/shard-tglu-5/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_fair@basic-pace@vecs0:
- shard-kbl: [FAIL][144] ([i915#2842]) -> [PASS][145]
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11322/shard-kbl4/igt@gem_exec_fair@basic-pace@vecs0.html
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22483/shard-kbl7/igt@gem_exec_fair@basic-pace@vecs0.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-iclb: [FAIL][146] ([i915#2849]) -> [PASS][147]
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11322/shard-iclb5/igt@gem_exec_fair@basic-throttle@rcs0.html
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22483/shard-iclb3/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@gem_lmem_swapping@smem-oom@lmem0:
- {shard-dg1}: [DMESG-WARN][148] ([i915#4936]) -> [PASS][149]
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11322/shard-dg1-15/igt@gem_lmem_swapping@smem-oom@lmem0.html
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22483/shard-dg1-12/igt@gem_lmem_swapping@smem-oom@lmem0.html
* igt@gem_mmap_offset@clear:
- {shard-rkl}: [INCOMPLETE][150] -> [PASS][151]
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11322/shard-rkl-5/igt@gem_mmap_offset@clear.html
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22483/shard-rkl-2/igt@gem_mmap_offset@clear.html
* igt@gem_workarounds@suspend-resume-fd:
- shard-snb: [TIMEOUT][152] -> [PASS][153]
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11322/shard-snb6/igt@gem_workarounds@suspend-resume-fd.html
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22483/shard-snb2/igt@gem_workarounds@suspend-resume-fd.html
* igt@i915_pm_backlight@fade_with_suspend:
- {shard-rkl}: [SKIP][154] ([i915#3012]) -> [PASS][155] +1 similar issue
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11322/shard-rkl-5/igt@i915_pm_backlight@fade_with_suspend.html
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22483/shard-rkl-6/igt@i915_pm_backlight@fade_with_suspend.html
* igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a:
- {shard-tglu}: [FAIL][156] ([i915#3825]) -> [PASS][157]
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11322/shard-tglu-3/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a.html
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22483/shard-tglu-1/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a.html
* igt@i915_pm_rpm@gem-mmap-type@uc:
- {shard-rkl}: [SKIP][158] ([fdo#109308]) -> [PASS][159] +4 similar issues
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11322/shard-rkl-2/igt@i915_pm_rpm@gem-mmap-type@uc.html
[159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22483/shard-rkl-6/igt@i915_pm_rpm@gem-mmap-type@uc.html
* igt@kms_3d:
- {shard-dg1}: [SKIP][160] -> [PASS][161] +18 similar issues
[160]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11322/shard-dg1-18/igt@kms_3d.html
[161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22483/shard-dg1-13/igt@kms_3d.html
* igt@kms_big_fb@linear-16bpp-rotate-0:
- {shard-tglu}: [DMESG-WARN][162] ([i915#402]) -> [PASS][163] +1 similar issue
[162]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11322/shard-tglu-5/igt@kms_big_fb@linear-16bpp-rotate-0.html
[163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22483/shard-tglu-1/igt@kms_big_fb@linear-16bpp-rotate-0.html
* igt@kms_big_fb@linear-32bpp-rotate-180:
- shard-glk: [DMESG-WARN][164] ([i915#118]) -> [PASS][165] +1 similar issue
[164]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11322/shard-glk1/igt@kms_big_fb@linear-32bpp-rotate-180.html
[165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22483/shard-glk8/igt@kms_big_fb@linear-32bpp-rotate-180.html
* igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0:
- {shard-dg1}: [FAIL][166] -> [PASS][167] +2 similar issues
[166]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11322/shard-dg1-18/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0.html
[167]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22483/shard-dg1-13/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0.html
* igt@kms_ccs@pipe-a-crc-primary-basic-y_tiled_gen12_rc_ccs:
- {shard-rkl}: [SKIP][168] ([i915#1845] / [i915#4098]) -> [PASS][169] +1 similar issue
[168]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11322/shard-rkl-2/igt@kms_ccs@pipe-a-crc-primary-basic-y_tiled_gen12_rc_ccs.html
[169]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22483/shard-rkl-6/igt@kms_ccs@pipe-a-crc-primary-basic-y_tiled_gen12_rc_ccs.html
* igt@kms_color@pipe-a-ctm-0-5:
- {shard-rkl}: [SKIP][170] ([i915#1149] / [i915#1849]) -> [PASS][171] +2 similar issues
[170]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11322/shard-rkl-5/igt@kms_color@pipe-a-ctm-0-5.html
[171]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22483/shard-rkl-6/igt@kms_color@pipe-a-ctm-0-5.html
* igt@kms_color@pipe-b-ctm-blue-to-red:
- {shard-rkl}: [SKIP][172] ([i915#1149] / [i915#1849] / [i915#4070]) -> [PASS][173]
[172]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11322/shard-rkl-2/igt@kms_color@pipe-b-ctm-blue-to-red.html
[173]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22483/shard-rkl-6/igt@kms_color@pipe-b-ctm-blue-to-red.html
* igt@kms_cursor_crc@pipe-a-cursor-256x85-sliding:
- {shard-rkl}: [SKIP][174] ([fdo#112022] / [i915#4070]) -> [PASS][175] +1 similar issue
[174]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11322/shard-rkl-2/igt@kms_cursor_crc@pipe-a-cursor-256x85-sliding.html
[175]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22483/shard-rkl-6/igt@kms_cursor_crc@pipe-a-cursor-256x85-sliding.html
* igt@kms_cursor_crc@pipe-b-cursor-128x42-random:
- {shard-rkl}: [SKIP][176] ([fdo#112022]) -> [PASS][177] +3 similar issues
[176]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11322/shard-rkl-5/igt@kms_cursor_crc@pipe-b-cursor-128x42-random.html
[177]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22483/shard-rkl-6/igt@kms_cursor_crc@pipe-b-cursor-128x42-random.html
* igt@kms_cursor_edge_walk@pipe-a-64x64-top-edge:
- {shard-rkl}: [SKIP][178] ([i915#1849] / [i915#4070]) -> [PASS][179] +1 similar issue
[178]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11322/shard-rkl-2/igt@kms_cursor_edge_walk@pipe-a-64x64-top-edge.html
[179]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22483/shard-rkl-6/igt@kms_cursor_edge_walk@pipe-a-64x64-top-edge.html
* igt@kms_cursor_legacy@cursora-vs-flipa-toggle:
- {shard-rkl}: [SKIP][180] ([fdo#111825]) -> [PASS][181]
[180]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11322/shard-rkl-5/igt@kms_cursor_legacy@cursora-vs-flipa-toggle.html
[181]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22483/shard-rkl-6/igt@kms_cursor_legacy@cursora-vs-flipa-toggle.html
* igt@kms_cursor_legacy@pipe-c-torture-bo:
- {shard-rkl}: [SKIP][182] ([i915#4070]) -> [PASS][183]
[182]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11322/shard-rkl-6/igt@kms_cursor_legacy@pipe-c-torture-bo.html
[183]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22483/shard-rkl-5/igt@kms_cursor_legacy@pipe-c-torture-bo.html
* igt@kms_draw_crc@draw-method-xrgb2101010-render-untiled:
- {shard-rkl}: [SKIP][184] ([fdo#111314]) -> [PASS][185] +5 similar issues
[184]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11322/shard-rkl-5/igt@kms_draw_crc@draw-method-xrgb2101010-render-untiled.html
[185]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22483/shard-rkl-6/igt@kms_draw_crc@draw-method-xrgb2101010-render-untiled.html
* igt@kms_flip@2x-plain-flip-fb-recreate@bc-hdmi-a1-hdmi-a2:
- shard-glk: [FAIL][186] ([i915#2122]) -> [PASS][187]
[186]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11322/shard-glk6/igt@kms_flip@2x-plain-flip-fb-recreate@bc-hdmi-a1-hdmi-a2.html
[187]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22483/shard-glk8/igt@kms_flip@2x-plain-flip-fb-recreate@bc-hdmi-a1-hdmi-a2.html
* igt@kms_flip@flip-vs-suspend-interruptible@b-vga1:
- shard-snb: [DMESG-WARN][188] -> [PASS][189]
[188]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11322/shard-snb4/igt@kms_flip@flip-vs-suspend-interruptible@b-vga1.html
[189]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22483/shard-snb5/igt@kms_flip@flip-vs-suspend-interruptible@b-vga1.html
* igt@kms_flip@flip-vs-suspend-interruptible@c-dp1:
- shard-apl: [DMESG-WARN][190] ([i915#180]) -> [PASS][191] +3 similar issues
[190]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11322/
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22483/index.html
[-- Attachment #2: Type: text/html, Size: 32829 bytes --]
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/dg2: Add preemption changes for Wa_14015141709
2022-03-04 10:13 ` [Intel-gfx] [PATCH] " Jani Nikula
@ 2022-03-04 22:54 ` Matt Roper
2022-03-08 10:33 ` Jani Nikula
0 siblings, 1 reply; 9+ messages in thread
From: Matt Roper @ 2022-03-04 22:54 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx, dri-devel
On Fri, Mar 04, 2022 at 12:13:12PM +0200, Jani Nikula wrote:
> On Thu, 03 Mar 2022, Matt Roper <matthew.d.roper@intel.com> wrote:
> > From: Akeem G Abodunrin <akeem.g.abodunrin@intel.com>
> >
> > Starting with DG2, preemption can no longer be controlled using userspace
> > on a per-context basis. Instead, the hardware only allows us to enable or
> > disable preemption in a global, system-wide basis. Also, we lose the
> > ability to specify the preemption granularity (such as batch-level vs
> > command-level vs object-level).
> >
> > As a result of this - for debugging purposes, this patch adds debugfs
> > interface to configure (disable/enable) preemption globally.
> >
> > Jira: VLK-27831
>
> Please remove internal Jira references.
>
> > Cc: Matt Roper <matthew.d.roper@intel.com>
> > Cc: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
> > Cc: John Harrison <john.c.harrison@intel.com>
> > Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> > Signed-off-by: Akeem G Abodunrin <akeem.g.abodunrin@intel.com>
> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > ---
> > drivers/gpu/drm/i915/gt/intel_gt_regs.h | 3 ++
> > drivers/gpu/drm/i915/gt/intel_workarounds.c | 2 +-
> > drivers/gpu/drm/i915/i915_debugfs.c | 50 +++++++++++++++++++++
> > drivers/gpu/drm/i915/i915_drv.h | 3 ++
> > 4 files changed, 57 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> > index 19cd34f24263..21ede1887b9f 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> > +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> > @@ -468,6 +468,9 @@
> > #define VF_PREEMPTION _MMIO(0x83a4)
> > #define PREEMPTION_VERTEX_COUNT REG_GENMASK(15, 0)
> >
> > +#define GEN12_VFG_PREEMPTION_CHICKEN _MMIO(0x83b4)
> > +#define GEN12_VFG_PREEMPT_CHICKEN_DISABLE REG_BIT(8)
> > +
> > #define GEN8_RC6_CTX_INFO _MMIO(0x8504)
> >
> > #define GEN12_SQCM _MMIO(0x8724)
> > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > index c014b40d2e9f..18dc82f29776 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > @@ -2310,7 +2310,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> > FF_DOP_CLOCK_GATE_DISABLE);
> > }
> >
> > - if (IS_GRAPHICS_VER(i915, 9, 12)) {
> > + if (HAS_PERCTX_PREEMPT_CTRL(i915)) {
>
> Adding HAS_PERCTX_PREEMPT_CTRL(i915) and using it is a separate change
> from the debugfs. Please split it up.
>
> > /* FtrPerCtxtPreemptionGranularityControl:skl,bxt,kbl,cfl,cnl,icl,tgl */
> > wa_masked_en(wal,
> > GEN7_FF_SLICE_CS_CHICKEN1,
> > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> > index 747fe9f41e1f..40e6e17e2950 100644
> > --- a/drivers/gpu/drm/i915/i915_debugfs.c
> > +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> > @@ -571,6 +571,55 @@ static int i915_wa_registers(struct seq_file *m, void *unused)
> > return 0;
> > }
> >
> > +static void i915_global_preemption_config(struct drm_i915_private *i915,
> > + u32 val)
> > +{
> > + const u32 bit = GEN12_VFG_PREEMPT_CHICKEN_DISABLE;
>
> We rarely use const for locals, and usually only if the function is big.
>
> I'd probably use:
>
> u32 tmp = val ?
> _MASKED_BIT_DISABLE(GEN12_VFG_PREEMPT_CHICKEN_DISABLE) :
> _MASKED_BIT_ENABLE(GEN12_VFG_PREEMPT_CHICKEN_DISABLE);
>
> To have just one intel_uncore_write().
>
> > +
> > + if (val)
> > + intel_uncore_write(&i915->uncore, GEN12_VFG_PREEMPTION_CHICKEN,
> > + _MASKED_BIT_DISABLE(bit));
> > + else
> > + intel_uncore_write(&i915->uncore, GEN12_VFG_PREEMPTION_CHICKEN,
> > + _MASKED_BIT_ENABLE(bit));
>
> We really shouldn't be adding new direct low-level register access in
> i915_debugfs.c.
>
> Please define an interface for this and add the functionality to a
> suitable place, and then call the functions from here.
>
> > +}
> > +
> > +static int i915_global_preempt_support_get(void *data, u64 *val)
> > +{
> > + struct drm_i915_private *i915 = data;
> > + intel_wakeref_t wakeref;
> > + u32 curr_status = 0;
> > +
> > + if (HAS_PERCTX_PREEMPT_CTRL(i915) || GRAPHICS_VER(i915) < 11)
> > + return -EINVAL;
> > +
> > + with_intel_runtime_pm(&i915->runtime_pm, wakeref)
> > + curr_status = intel_uncore_read(&i915->uncore,
> > + GEN12_VFG_PREEMPTION_CHICKEN);
> > + *val = (curr_status & GEN12_VFG_PREEMPT_CHICKEN_DISABLE) ? 0 : 1;
> > +
> > + return 0;
> > +}
> > +
> > +static int i915_global_preempt_support_set(void *data, u64 val)
> > +{
> > + struct drm_i915_private *i915 = data;
> > + intel_wakeref_t wakeref;
> > +
> > + if (HAS_PERCTX_PREEMPT_CTRL(i915) || GRAPHICS_VER(i915) < 11)
> > + return -EINVAL;
> > +
> > + with_intel_runtime_pm(&i915->runtime_pm, wakeref)
> > + i915_global_preemption_config(i915, val);
> > +
> > + return 0;
> > +}
> > +
> > +DEFINE_SIMPLE_ATTRIBUTE(i915_global_preempt_support_fops,
> > + i915_global_preempt_support_get,
> > + i915_global_preempt_support_set,
> > + "%lld\n");
>
> DEFINE_DEBUGFS_ATTRIBUTE.
If I'm understanding the history correctly, I think
DEFINE_DEBUGFS_ATTRIBUTE is only supposed to be used if you're also
using debugfs_create_file_unsafe() for registration; if you're still
using debugfs_create_file(), then DEFINE_SIMPLE_ATTRIBUTE is preferred
to avoid the extra overhead of redundant protection.
Arguably we should shift over to debugfs_create_file_unsafe() +
DEFINE_DEBUGFS_ATTRIBUTE, but that's probably something we should do
driver-wide in a separate series since we're not doing that for any of
our debugfs today.
One other change we should make here is to move this into the GT debugfs
area, rather than having it at the i915 level. I'll make that change in
the next version.
Matt
>
> > +
> > static int i915_wedged_get(void *data, u64 *val)
> > {
> > struct drm_i915_private *i915 = data;
> > @@ -765,6 +814,7 @@ static const struct i915_debugfs_files {
> > const struct file_operations *fops;
> > } i915_debugfs_files[] = {
> > {"i915_perf_noa_delay", &i915_perf_noa_delay_fops},
> > + {"i915_global_preempt_support", &i915_global_preempt_support_fops},
> > {"i915_wedged", &i915_wedged_fops},
> > {"i915_gem_drop_caches", &i915_drop_caches_fops},
> > #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index 457bc1993d19..8c3f69c87d36 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -1407,6 +1407,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> > #define HAS_GUC_DEPRIVILEGE(dev_priv) \
> > (INTEL_INFO(dev_priv)->has_guc_deprivilege)
> >
> > +#define HAS_PERCTX_PREEMPT_CTRL(i915) \
> > + ((GRAPHICS_VER(i915) >= 9) && GRAPHICS_VER_FULL(i915) < IP_VER(12, 55))
> > +
> > static inline bool run_as_guest(void)
> > {
> > return !hypervisor_is_type(X86_HYPER_NATIVE);
>
> --
> Jani Nikula, Intel Open Source Graphics Center
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/dg2: Add preemption changes for Wa_14015141709
2022-03-04 22:54 ` Matt Roper
@ 2022-03-08 10:33 ` Jani Nikula
0 siblings, 0 replies; 9+ messages in thread
From: Jani Nikula @ 2022-03-08 10:33 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx, dri-devel
On Fri, 04 Mar 2022, Matt Roper <matthew.d.roper@intel.com> wrote:
> On Fri, Mar 04, 2022 at 12:13:12PM +0200, Jani Nikula wrote:
>> On Thu, 03 Mar 2022, Matt Roper <matthew.d.roper@intel.com> wrote:
>> > From: Akeem G Abodunrin <akeem.g.abodunrin@intel.com>
>> >
>> > Starting with DG2, preemption can no longer be controlled using userspace
>> > on a per-context basis. Instead, the hardware only allows us to enable or
>> > disable preemption in a global, system-wide basis. Also, we lose the
>> > ability to specify the preemption granularity (such as batch-level vs
>> > command-level vs object-level).
>> >
>> > As a result of this - for debugging purposes, this patch adds debugfs
>> > interface to configure (disable/enable) preemption globally.
>> >
>> > Jira: VLK-27831
>>
>> Please remove internal Jira references.
>>
>> > Cc: Matt Roper <matthew.d.roper@intel.com>
>> > Cc: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
>> > Cc: John Harrison <john.c.harrison@intel.com>
>> > Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
>> > Signed-off-by: Akeem G Abodunrin <akeem.g.abodunrin@intel.com>
>> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
>> > ---
>> > drivers/gpu/drm/i915/gt/intel_gt_regs.h | 3 ++
>> > drivers/gpu/drm/i915/gt/intel_workarounds.c | 2 +-
>> > drivers/gpu/drm/i915/i915_debugfs.c | 50 +++++++++++++++++++++
>> > drivers/gpu/drm/i915/i915_drv.h | 3 ++
>> > 4 files changed, 57 insertions(+), 1 deletion(-)
>> >
>> > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
>> > index 19cd34f24263..21ede1887b9f 100644
>> > --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
>> > +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
>> > @@ -468,6 +468,9 @@
>> > #define VF_PREEMPTION _MMIO(0x83a4)
>> > #define PREEMPTION_VERTEX_COUNT REG_GENMASK(15, 0)
>> >
>> > +#define GEN12_VFG_PREEMPTION_CHICKEN _MMIO(0x83b4)
>> > +#define GEN12_VFG_PREEMPT_CHICKEN_DISABLE REG_BIT(8)
>> > +
>> > #define GEN8_RC6_CTX_INFO _MMIO(0x8504)
>> >
>> > #define GEN12_SQCM _MMIO(0x8724)
>> > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> > index c014b40d2e9f..18dc82f29776 100644
>> > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> > @@ -2310,7 +2310,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>> > FF_DOP_CLOCK_GATE_DISABLE);
>> > }
>> >
>> > - if (IS_GRAPHICS_VER(i915, 9, 12)) {
>> > + if (HAS_PERCTX_PREEMPT_CTRL(i915)) {
>>
>> Adding HAS_PERCTX_PREEMPT_CTRL(i915) and using it is a separate change
>> from the debugfs. Please split it up.
>>
>> > /* FtrPerCtxtPreemptionGranularityControl:skl,bxt,kbl,cfl,cnl,icl,tgl */
>> > wa_masked_en(wal,
>> > GEN7_FF_SLICE_CS_CHICKEN1,
>> > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
>> > index 747fe9f41e1f..40e6e17e2950 100644
>> > --- a/drivers/gpu/drm/i915/i915_debugfs.c
>> > +++ b/drivers/gpu/drm/i915/i915_debugfs.c
>> > @@ -571,6 +571,55 @@ static int i915_wa_registers(struct seq_file *m, void *unused)
>> > return 0;
>> > }
>> >
>> > +static void i915_global_preemption_config(struct drm_i915_private *i915,
>> > + u32 val)
>> > +{
>> > + const u32 bit = GEN12_VFG_PREEMPT_CHICKEN_DISABLE;
>>
>> We rarely use const for locals, and usually only if the function is big.
>>
>> I'd probably use:
>>
>> u32 tmp = val ?
>> _MASKED_BIT_DISABLE(GEN12_VFG_PREEMPT_CHICKEN_DISABLE) :
>> _MASKED_BIT_ENABLE(GEN12_VFG_PREEMPT_CHICKEN_DISABLE);
>>
>> To have just one intel_uncore_write().
>>
>> > +
>> > + if (val)
>> > + intel_uncore_write(&i915->uncore, GEN12_VFG_PREEMPTION_CHICKEN,
>> > + _MASKED_BIT_DISABLE(bit));
>> > + else
>> > + intel_uncore_write(&i915->uncore, GEN12_VFG_PREEMPTION_CHICKEN,
>> > + _MASKED_BIT_ENABLE(bit));
>>
>> We really shouldn't be adding new direct low-level register access in
>> i915_debugfs.c.
>>
>> Please define an interface for this and add the functionality to a
>> suitable place, and then call the functions from here.
>>
>> > +}
>> > +
>> > +static int i915_global_preempt_support_get(void *data, u64 *val)
>> > +{
>> > + struct drm_i915_private *i915 = data;
>> > + intel_wakeref_t wakeref;
>> > + u32 curr_status = 0;
>> > +
>> > + if (HAS_PERCTX_PREEMPT_CTRL(i915) || GRAPHICS_VER(i915) < 11)
>> > + return -EINVAL;
>> > +
>> > + with_intel_runtime_pm(&i915->runtime_pm, wakeref)
>> > + curr_status = intel_uncore_read(&i915->uncore,
>> > + GEN12_VFG_PREEMPTION_CHICKEN);
>> > + *val = (curr_status & GEN12_VFG_PREEMPT_CHICKEN_DISABLE) ? 0 : 1;
>> > +
>> > + return 0;
>> > +}
>> > +
>> > +static int i915_global_preempt_support_set(void *data, u64 val)
>> > +{
>> > + struct drm_i915_private *i915 = data;
>> > + intel_wakeref_t wakeref;
>> > +
>> > + if (HAS_PERCTX_PREEMPT_CTRL(i915) || GRAPHICS_VER(i915) < 11)
>> > + return -EINVAL;
>> > +
>> > + with_intel_runtime_pm(&i915->runtime_pm, wakeref)
>> > + i915_global_preemption_config(i915, val);
>> > +
>> > + return 0;
>> > +}
>> > +
>> > +DEFINE_SIMPLE_ATTRIBUTE(i915_global_preempt_support_fops,
>> > + i915_global_preempt_support_get,
>> > + i915_global_preempt_support_set,
>> > + "%lld\n");
>>
>> DEFINE_DEBUGFS_ATTRIBUTE.
>
> If I'm understanding the history correctly, I think
> DEFINE_DEBUGFS_ATTRIBUTE is only supposed to be used if you're also
> using debugfs_create_file_unsafe() for registration; if you're still
> using debugfs_create_file(), then DEFINE_SIMPLE_ATTRIBUTE is preferred
> to avoid the extra overhead of redundant protection.
>
> Arguably we should shift over to debugfs_create_file_unsafe() +
> DEFINE_DEBUGFS_ATTRIBUTE, but that's probably something we should do
> driver-wide in a separate series since we're not doing that for any of
> our debugfs today.
I'll take your word for it, did not have the time to dig into it.
Thanks,
Jani.
>
> One other change we should make here is to move this into the GT debugfs
> area, rather than having it at the i915 level. I'll make that change in
> the next version.
>
>
> Matt
>
>>
>> > +
>> > static int i915_wedged_get(void *data, u64 *val)
>> > {
>> > struct drm_i915_private *i915 = data;
>> > @@ -765,6 +814,7 @@ static const struct i915_debugfs_files {
>> > const struct file_operations *fops;
>> > } i915_debugfs_files[] = {
>> > {"i915_perf_noa_delay", &i915_perf_noa_delay_fops},
>> > + {"i915_global_preempt_support", &i915_global_preempt_support_fops},
>> > {"i915_wedged", &i915_wedged_fops},
>> > {"i915_gem_drop_caches", &i915_drop_caches_fops},
>> > #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
>> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>> > index 457bc1993d19..8c3f69c87d36 100644
>> > --- a/drivers/gpu/drm/i915/i915_drv.h
>> > +++ b/drivers/gpu/drm/i915/i915_drv.h
>> > @@ -1407,6 +1407,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>> > #define HAS_GUC_DEPRIVILEGE(dev_priv) \
>> > (INTEL_INFO(dev_priv)->has_guc_deprivilege)
>> >
>> > +#define HAS_PERCTX_PREEMPT_CTRL(i915) \
>> > + ((GRAPHICS_VER(i915) >= 9) && GRAPHICS_VER_FULL(i915) < IP_VER(12, 55))
>> > +
>> > static inline bool run_as_guest(void)
>> > {
>> > return !hypervisor_is_type(X86_HYPER_NATIVE);
>>
>> --
>> Jani Nikula, Intel Open Source Graphics Center
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 9+ messages in thread
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2022-03-03 22:42 [Intel-gfx] [PATCH] drm/i915/dg2: Add preemption changes for Wa_14015141709 Matt Roper
2022-03-04 1:30 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
2022-03-04 1:31 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-03-04 2:05 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-03-04 10:13 ` [Intel-gfx] [PATCH] " Jani Nikula
2022-03-04 22:54 ` Matt Roper
2022-03-08 10:33 ` Jani Nikula
2022-03-04 11:35 ` Tvrtko Ursulin
2022-03-04 15:26 ` [Intel-gfx] ✓ Fi.CI.IGT: success for " Patchwork
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