From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH v2 2/8] drm/i915: Remove redundant/wrong comments
Date: Tue, 8 Mar 2022 01:39:34 +0200 [thread overview]
Message-ID: <20220307233940.4161-3-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <20220307233940.4161-1-ville.syrjala@linux.intel.com>
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Remove the comment specifying the exact formulat for calculating
the DPLL frequency from the *_find_best_dpll() functions. Each
platform variant has its own way to calculate these and we have
the code already to do that. These comments are entirely redundant
and often even wrong so just get rid of them.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_dpll.c | 15 +++++----------
1 file changed, 5 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
index b3fd94538c44..f4e5290b86a4 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -425,8 +425,7 @@ i9xx_select_p2_div(const struct intel_limit *limit,
/*
* Returns a set of divisors for the desired target clock with the given
- * refclk, or FALSE. The returned values represent the clock equation:
- * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
+ * refclk, or FALSE.
*
* Target and reference clocks are specified in kHz.
*
@@ -484,8 +483,7 @@ i9xx_find_best_dpll(const struct intel_limit *limit,
/*
* Returns a set of divisors for the desired target clock with the given
- * refclk, or FALSE. The returned values represent the clock equation:
- * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
+ * refclk, or FALSE.
*
* Target and reference clocks are specified in kHz.
*
@@ -541,8 +539,7 @@ pnv_find_best_dpll(const struct intel_limit *limit,
/*
* Returns a set of divisors for the desired target clock with the given
- * refclk, or FALSE. The returned values represent the clock equation:
- * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
+ * refclk, or FALSE.
*
* Target and reference clocks are specified in kHz.
*
@@ -641,8 +638,7 @@ static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
/*
* Returns a set of divisors for the desired target clock with the given
- * refclk, or FALSE. The returned values represent the clock equation:
- * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
+ * refclk, or FALSE.
*/
static bool
vlv_find_best_dpll(const struct intel_limit *limit,
@@ -700,8 +696,7 @@ vlv_find_best_dpll(const struct intel_limit *limit,
/*
* Returns a set of divisors for the desired target clock with the given
- * refclk, or FALSE. The returned values represent the clock equation:
- * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
+ * refclk, or FALSE.
*/
static bool
chv_find_best_dpll(const struct intel_limit *limit,
--
2.34.1
next prev parent reply other threads:[~2022-03-07 23:39 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-03-07 23:39 [Intel-gfx] [PATCH v2 0/8] drm/i915: Clean up some dpll stuff Ville Syrjala
2022-03-07 23:39 ` [Intel-gfx] [PATCH v2 1/8] drm/i915: Store the /5 target clock in struct dpll on vlv/chv Ville Syrjala
2022-03-09 9:53 ` Jani Nikula
2022-03-09 21:43 ` [Intel-gfx] [PATCH v3 " Ville Syrjala
2022-03-07 23:39 ` Ville Syrjala [this message]
2022-03-09 9:50 ` [Intel-gfx] [PATCH v2 2/8] drm/i915: Remove redundant/wrong comments Jani Nikula
2022-03-07 23:39 ` [Intel-gfx] [PATCH v2 3/8] drm/i915: Clean up bxt/glk PLL registers Ville Syrjala
2022-03-09 9:22 ` Jani Nikula
2022-03-07 23:39 ` [Intel-gfx] [PATCH v2 4/8] drm/i915: Store the m2 divider as a whole in bxt_clk_div Ville Syrjala
2022-03-09 9:27 ` Jani Nikula
2022-03-07 23:39 ` [Intel-gfx] [PATCH v2 5/8] drm/i915: Replace bxt_clk_div with struct dpll Ville Syrjala
2022-03-07 23:39 ` [Intel-gfx] [PATCH v2 6/8] drm/i915: Replace hand rolled bxt vco calculation with chv_calc_dpll_params() Ville Syrjala
2022-03-09 9:46 ` Jani Nikula
2022-03-07 23:39 ` [Intel-gfx] [PATCH v2 7/8] drm/i915: Populate bxt/glk DPLL clock limits a bit more Ville Syrjala
2022-03-09 9:30 ` Jani Nikula
2022-03-07 23:39 ` [Intel-gfx] [PATCH v2 8/8] drm/i915: Remove struct dp_link_dpll Ville Syrjala
2022-03-09 9:34 ` Jani Nikula
2022-03-07 23:50 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Clean up some dpll stuff (rev3) Patchwork
2022-03-08 13:31 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2022-03-09 2:48 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Clean up some dpll stuff (rev4) Patchwork
2022-03-09 3:22 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2022-03-09 18:23 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Clean up some dpll stuff (rev5) Patchwork
2022-03-09 18:59 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2022-03-09 22:02 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Clean up some dpll stuff (rev6) Patchwork
2022-03-09 22:35 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-03-10 7:29 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
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