* [Intel-gfx] [PATCH 0/8] Patches for selftest_lrc
@ 2022-03-09 5:17 Ramalingam C
2022-03-09 5:17 ` [Intel-gfx] [PATCH 1/8] drm/i915/selftests: Exercise relative mmio paths to non-privileged registers Ramalingam C
` (9 more replies)
0 siblings, 10 replies; 11+ messages in thread
From: Ramalingam C @ 2022-03-09 5:17 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: lucas.demarchi
Patches that fix and enhance the selftest_lrc
Akeem G Abodunrin (1):
drm/i915/xehpsdv/dg1/tgl: Fix issue with LRI relative addressing
Chris Wilson (7):
drm/i915/selftests: Exercise relative mmio paths to non-privileged
registers
drm/i915/selftests: Exercise cross-process context isolation
drm/i915/selftests: Flush the submission for lrc_isolation
drm/i915/gt: Explicitly clear BB_OFFSET for new contexts
drm/i915/selftests: Check for incomplete LRI from the context image
drm/i915/selftest: Clear the output buffers before GPU writes
drm/i915/selftest: Always cancel semaphore on error
drivers/gpu/drm/i915/gt/intel_engine_regs.h | 1 +
drivers/gpu/drm/i915/gt/intel_lrc.c | 17 +
drivers/gpu/drm/i915/gt/selftest_lrc.c | 499 +++++++++++++++++---
3 files changed, 452 insertions(+), 65 deletions(-)
--
2.20.1
^ permalink raw reply [flat|nested] 11+ messages in thread
* [Intel-gfx] [PATCH 1/8] drm/i915/selftests: Exercise relative mmio paths to non-privileged registers
2022-03-09 5:17 [Intel-gfx] [PATCH 0/8] Patches for selftest_lrc Ramalingam C
@ 2022-03-09 5:17 ` Ramalingam C
2022-03-09 5:17 ` [Intel-gfx] [PATCH 2/8] drm/i915/selftests: Exercise cross-process context isolation Ramalingam C
` (8 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Ramalingam C @ 2022-03-09 5:17 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: lucas.demarchi, Chris Wilson
From: Chris Wilson <chris@chris-wilson.co.uk>
Verify that context isolation is also preserved when accessing
context-local registers with relative-mmio commands.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
---
drivers/gpu/drm/i915/gt/selftest_lrc.c | 88 ++++++++++++++++++++------
1 file changed, 67 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c
index 21c29d315cc0..073c9795f42f 100644
--- a/drivers/gpu/drm/i915/gt/selftest_lrc.c
+++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c
@@ -912,7 +912,9 @@ create_user_vma(struct i915_address_space *vm, unsigned long size)
}
static struct i915_vma *
-store_context(struct intel_context *ce, struct i915_vma *scratch)
+store_context(struct intel_context *ce,
+ struct i915_vma *scratch,
+ bool relative)
{
struct i915_vma *batch;
u32 dw, x, *cs, *hw;
@@ -941,6 +943,9 @@ store_context(struct intel_context *ce, struct i915_vma *scratch)
hw += LRC_STATE_OFFSET / sizeof(*hw);
do {
u32 len = hw[dw] & 0x7f;
+ u32 cmd = MI_STORE_REGISTER_MEM_GEN8;
+ u32 offset = 0;
+ u32 mask = ~0;
if (hw[dw] == 0) {
dw++;
@@ -952,11 +957,19 @@ store_context(struct intel_context *ce, struct i915_vma *scratch)
continue;
}
+ if (hw[dw] & MI_LRI_LRM_CS_MMIO) {
+ mask = 0xfff;
+ if (relative)
+ cmd |= MI_LRI_LRM_CS_MMIO;
+ else
+ offset = ce->engine->mmio_base;
+ }
+
dw++;
len = (len + 1) / 2;
while (len--) {
- *cs++ = MI_STORE_REGISTER_MEM_GEN8;
- *cs++ = hw[dw];
+ *cs++ = cmd;
+ *cs++ = (hw[dw] & mask) + offset;
*cs++ = lower_32_bits(scratch->node.start + x);
*cs++ = upper_32_bits(scratch->node.start + x);
@@ -995,6 +1008,7 @@ static struct i915_request *
record_registers(struct intel_context *ce,
struct i915_vma *before,
struct i915_vma *after,
+ bool relative,
u32 *sema)
{
struct i915_vma *b_before, *b_after;
@@ -1002,11 +1016,11 @@ record_registers(struct intel_context *ce,
u32 *cs;
int err;
- b_before = store_context(ce, before);
+ b_before = store_context(ce, before, relative);
if (IS_ERR(b_before))
return ERR_CAST(b_before);
- b_after = store_context(ce, after);
+ b_after = store_context(ce, after, relative);
if (IS_ERR(b_after)) {
rq = ERR_CAST(b_after);
goto err_before;
@@ -1076,7 +1090,8 @@ record_registers(struct intel_context *ce,
goto err_after;
}
-static struct i915_vma *load_context(struct intel_context *ce, u32 poison)
+static struct i915_vma *
+load_context(struct intel_context *ce, u32 poison, bool relative)
{
struct i915_vma *batch;
u32 dw, *cs, *hw;
@@ -1103,7 +1118,10 @@ static struct i915_vma *load_context(struct intel_context *ce, u32 poison)
hw = defaults;
hw += LRC_STATE_OFFSET / sizeof(*hw);
do {
+ u32 cmd = MI_INSTR(0x22, 0);
u32 len = hw[dw] & 0x7f;
+ u32 offset = 0;
+ u32 mask = ~0;
if (hw[dw] == 0) {
dw++;
@@ -1115,11 +1133,19 @@ static struct i915_vma *load_context(struct intel_context *ce, u32 poison)
continue;
}
+ if (hw[dw] & MI_LRI_LRM_CS_MMIO) {
+ mask = 0xfff;
+ if (relative)
+ cmd |= MI_LRI_LRM_CS_MMIO;
+ else
+ offset = ce->engine->mmio_base;
+ }
+
dw++;
+ *cs++ = cmd | len;
len = (len + 1) / 2;
- *cs++ = MI_LOAD_REGISTER_IMM(len);
while (len--) {
- *cs++ = hw[dw];
+ *cs++ = (hw[dw] & mask) + offset;
*cs++ = poison;
dw += 2;
}
@@ -1136,14 +1162,18 @@ static struct i915_vma *load_context(struct intel_context *ce, u32 poison)
return batch;
}
-static int poison_registers(struct intel_context *ce, u32 poison, u32 *sema)
+static int
+poison_registers(struct intel_context *ce,
+ u32 poison,
+ bool relative,
+ u32 *sema)
{
struct i915_request *rq;
struct i915_vma *batch;
u32 *cs;
int err;
- batch = load_context(ce, poison);
+ batch = load_context(ce, poison, relative);
if (IS_ERR(batch))
return PTR_ERR(batch);
@@ -1193,7 +1223,7 @@ static int compare_isolation(struct intel_engine_cs *engine,
struct i915_vma *ref[2],
struct i915_vma *result[2],
struct intel_context *ce,
- u32 poison)
+ u32 poison, bool relative)
{
u32 x, dw, *hw, *lrc;
u32 *A[2], *B[2];
@@ -1244,6 +1274,7 @@ static int compare_isolation(struct intel_engine_cs *engine,
hw += LRC_STATE_OFFSET / sizeof(*hw);
do {
u32 len = hw[dw] & 0x7f;
+ bool is_relative = relative;
if (hw[dw] == 0) {
dw++;
@@ -1255,6 +1286,9 @@ static int compare_isolation(struct intel_engine_cs *engine,
continue;
}
+ if (!(hw[dw] & MI_LRI_LRM_CS_MMIO))
+ is_relative = false;
+
dw++;
len = (len + 1) / 2;
while (len--) {
@@ -1266,9 +1300,10 @@ static int compare_isolation(struct intel_engine_cs *engine,
break;
default:
- pr_err("%s[%d]: Mismatch for register %4x, default %08x, reference %08x, result (%08x, %08x), poison %08x, context %08x\n",
- engine->name, dw,
- hw[dw], hw[dw + 1],
+ pr_err("%s[%d]: Mismatch for register %4x [using relative? %s], default %08x, reference %08x, result (%08x, %08x), poison %08x, context %08x\n",
+ engine->name, dw, hw[dw],
+ is_relative ? "Yes" : "No",
+ hw[dw + 1],
A[0][x], B[0][x], B[1][x],
poison, lrc[dw + 1]);
err = -EINVAL;
@@ -1294,7 +1329,8 @@ static int compare_isolation(struct intel_engine_cs *engine,
return err;
}
-static int __lrc_isolation(struct intel_engine_cs *engine, u32 poison)
+static int
+__lrc_isolation(struct intel_engine_cs *engine, u32 poison, bool relative)
{
u32 *sema = memset32(engine->status_page.addr + 1000, 0, 1);
struct i915_vma *ref[2], *result[2];
@@ -1324,7 +1360,7 @@ static int __lrc_isolation(struct intel_engine_cs *engine, u32 poison)
goto err_ref0;
}
- rq = record_registers(A, ref[0], ref[1], sema);
+ rq = record_registers(A, ref[0], ref[1], relative, sema);
if (IS_ERR(rq)) {
err = PTR_ERR(rq);
goto err_ref1;
@@ -1352,13 +1388,13 @@ static int __lrc_isolation(struct intel_engine_cs *engine, u32 poison)
goto err_result0;
}
- rq = record_registers(A, result[0], result[1], sema);
+ rq = record_registers(A, result[0], result[1], relative, sema);
if (IS_ERR(rq)) {
err = PTR_ERR(rq);
goto err_result1;
}
- err = poison_registers(B, poison, sema);
+ err = poison_registers(B, poison, relative, sema);
if (err) {
WRITE_ONCE(*sema, -1);
i915_request_put(rq);
@@ -1372,7 +1408,7 @@ static int __lrc_isolation(struct intel_engine_cs *engine, u32 poison)
}
i915_request_put(rq);
- err = compare_isolation(engine, ref, result, A, poison);
+ err = compare_isolation(engine, ref, result, A, poison, relative);
err_result1:
i915_vma_put(result[1]);
@@ -1434,13 +1470,23 @@ static int live_lrc_isolation(void *arg)
for (i = 0; i < ARRAY_SIZE(poison); i++) {
int result;
- result = __lrc_isolation(engine, poison[i]);
+ result = __lrc_isolation(engine, poison[i], false);
if (result && !err)
err = result;
- result = __lrc_isolation(engine, ~poison[i]);
+ result = __lrc_isolation(engine, ~poison[i], false);
if (result && !err)
err = result;
+
+ if (intel_engine_has_relative_mmio(engine)) {
+ result = __lrc_isolation(engine, poison[i], true);
+ if (result && !err)
+ err = result;
+
+ result = __lrc_isolation(engine, ~poison[i], true);
+ if (result && !err)
+ err = result;
+ }
}
intel_engine_pm_put(engine);
if (igt_flush_test(gt->i915)) {
--
2.20.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [Intel-gfx] [PATCH 2/8] drm/i915/selftests: Exercise cross-process context isolation
2022-03-09 5:17 [Intel-gfx] [PATCH 0/8] Patches for selftest_lrc Ramalingam C
2022-03-09 5:17 ` [Intel-gfx] [PATCH 1/8] drm/i915/selftests: Exercise relative mmio paths to non-privileged registers Ramalingam C
@ 2022-03-09 5:17 ` Ramalingam C
2022-03-09 5:17 ` [Intel-gfx] [PATCH 3/8] drm/i915/selftests: Flush the submission for lrc_isolation Ramalingam C
` (7 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Ramalingam C @ 2022-03-09 5:17 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: lucas.demarchi, Chris Wilson
From: Chris Wilson <chris@chris-wilson.co.uk>
Verify that one context running on engine A cannot manipulate another
client's context concurrently running on engine B using unprivileged
access.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
---
drivers/gpu/drm/i915/gt/selftest_lrc.c | 275 +++++++++++++++++++++----
1 file changed, 238 insertions(+), 37 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c
index 073c9795f42f..998e561694be 100644
--- a/drivers/gpu/drm/i915/gt/selftest_lrc.c
+++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c
@@ -913,6 +913,7 @@ create_user_vma(struct i915_address_space *vm, unsigned long size)
static struct i915_vma *
store_context(struct intel_context *ce,
+ struct intel_engine_cs *engine,
struct i915_vma *scratch,
bool relative)
{
@@ -930,7 +931,7 @@ store_context(struct intel_context *ce,
return ERR_CAST(cs);
}
- defaults = shmem_pin_map(ce->engine->default_state);
+ defaults = shmem_pin_map(engine->default_state);
if (!defaults) {
i915_gem_object_unpin_map(batch->obj);
i915_vma_put(batch);
@@ -962,7 +963,7 @@ store_context(struct intel_context *ce,
if (relative)
cmd |= MI_LRI_LRM_CS_MMIO;
else
- offset = ce->engine->mmio_base;
+ offset = engine->mmio_base;
}
dw++;
@@ -981,7 +982,7 @@ store_context(struct intel_context *ce,
*cs++ = MI_BATCH_BUFFER_END;
- shmem_unpin_map(ce->engine->default_state, defaults);
+ shmem_unpin_map(engine->default_state, defaults);
i915_gem_object_flush_map(batch->obj);
i915_gem_object_unpin_map(batch->obj);
@@ -1004,23 +1005,48 @@ static int move_to_active(struct i915_request *rq,
return err;
}
+struct hwsp_semaphore {
+ u32 ggtt;
+ u32 *va;
+};
+
+static struct hwsp_semaphore hwsp_semaphore(struct intel_engine_cs *engine)
+{
+ struct hwsp_semaphore s;
+
+ s.va = memset32(engine->status_page.addr + 1000, 0, 1);
+ s.ggtt = (i915_ggtt_offset(engine->status_page.vma) +
+ offset_in_page(s.va));
+
+ return s;
+}
+
+static u32 *emit_noops(u32 *cs, int count)
+{
+ while (count--)
+ *cs++ = MI_NOOP;
+
+ return cs;
+}
+
static struct i915_request *
record_registers(struct intel_context *ce,
+ struct intel_engine_cs *engine,
struct i915_vma *before,
struct i915_vma *after,
bool relative,
- u32 *sema)
+ const struct hwsp_semaphore *sema)
{
struct i915_vma *b_before, *b_after;
struct i915_request *rq;
u32 *cs;
int err;
- b_before = store_context(ce, before, relative);
+ b_before = store_context(ce, engine, before, relative);
if (IS_ERR(b_before))
return ERR_CAST(b_before);
- b_after = store_context(ce, after, relative);
+ b_after = store_context(ce, engine, after, relative);
if (IS_ERR(b_after)) {
rq = ERR_CAST(b_after);
goto err_before;
@@ -1046,7 +1072,7 @@ record_registers(struct intel_context *ce,
if (err)
goto err_rq;
- cs = intel_ring_begin(rq, 14);
+ cs = intel_ring_begin(rq, 18);
if (IS_ERR(cs)) {
err = PTR_ERR(cs);
goto err_rq;
@@ -1057,16 +1083,28 @@ record_registers(struct intel_context *ce,
*cs++ = lower_32_bits(b_before->node.start);
*cs++ = upper_32_bits(b_before->node.start);
- *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
- *cs++ = MI_SEMAPHORE_WAIT |
- MI_SEMAPHORE_GLOBAL_GTT |
- MI_SEMAPHORE_POLL |
- MI_SEMAPHORE_SAD_NEQ_SDD;
- *cs++ = 0;
- *cs++ = i915_ggtt_offset(ce->engine->status_page.vma) +
- offset_in_page(sema);
- *cs++ = 0;
- *cs++ = MI_NOOP;
+ if (sema) {
+ WRITE_ONCE(*sema->va, -1);
+
+ /* Signal the poisoner */
+ *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
+ *cs++ = sema->ggtt;
+ *cs++ = 0;
+ *cs++ = 0;
+
+ /* Then wait for the poison to settle */
+ *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
+ *cs++ = MI_SEMAPHORE_WAIT |
+ MI_SEMAPHORE_GLOBAL_GTT |
+ MI_SEMAPHORE_POLL |
+ MI_SEMAPHORE_SAD_NEQ_SDD;
+ *cs++ = 0;
+ *cs++ = sema->ggtt;
+ *cs++ = 0;
+ *cs++ = MI_NOOP;
+ } else {
+ cs = emit_noops(cs, 10);
+ }
*cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
*cs++ = MI_BATCH_BUFFER_START_GEN8 | BIT(8);
@@ -1075,7 +1113,6 @@ record_registers(struct intel_context *ce,
intel_ring_advance(rq, cs);
- WRITE_ONCE(*sema, 0);
i915_request_get(rq);
i915_request_add(rq);
err_after:
@@ -1091,7 +1128,9 @@ record_registers(struct intel_context *ce,
}
static struct i915_vma *
-load_context(struct intel_context *ce, u32 poison, bool relative)
+load_context(struct intel_context *ce,
+ struct intel_engine_cs *engine,
+ u32 poison, bool relative)
{
struct i915_vma *batch;
u32 dw, *cs, *hw;
@@ -1107,7 +1146,7 @@ load_context(struct intel_context *ce, u32 poison, bool relative)
return ERR_CAST(cs);
}
- defaults = shmem_pin_map(ce->engine->default_state);
+ defaults = shmem_pin_map(engine->default_state);
if (!defaults) {
i915_gem_object_unpin_map(batch->obj);
i915_vma_put(batch);
@@ -1138,7 +1177,7 @@ load_context(struct intel_context *ce, u32 poison, bool relative)
if (relative)
cmd |= MI_LRI_LRM_CS_MMIO;
else
- offset = ce->engine->mmio_base;
+ offset = engine->mmio_base;
}
dw++;
@@ -1154,7 +1193,7 @@ load_context(struct intel_context *ce, u32 poison, bool relative)
*cs++ = MI_BATCH_BUFFER_END;
- shmem_unpin_map(ce->engine->default_state, defaults);
+ shmem_unpin_map(engine->default_state, defaults);
i915_gem_object_flush_map(batch->obj);
i915_gem_object_unpin_map(batch->obj);
@@ -1164,16 +1203,17 @@ load_context(struct intel_context *ce, u32 poison, bool relative)
static int
poison_registers(struct intel_context *ce,
+ struct intel_engine_cs *engine,
u32 poison,
bool relative,
- u32 *sema)
+ const struct hwsp_semaphore *sema)
{
struct i915_request *rq;
struct i915_vma *batch;
u32 *cs;
int err;
- batch = load_context(ce, poison, relative);
+ batch = load_context(ce, engine, poison, relative);
if (IS_ERR(batch))
return PTR_ERR(batch);
@@ -1187,20 +1227,29 @@ poison_registers(struct intel_context *ce,
if (err)
goto err_rq;
- cs = intel_ring_begin(rq, 8);
+ cs = intel_ring_begin(rq, 14);
if (IS_ERR(cs)) {
err = PTR_ERR(cs);
goto err_rq;
}
+ *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
+ *cs++ = MI_SEMAPHORE_WAIT |
+ MI_SEMAPHORE_GLOBAL_GTT |
+ MI_SEMAPHORE_POLL |
+ MI_SEMAPHORE_SAD_EQ_SDD;
+ *cs++ = 0;
+ *cs++ = sema->ggtt;
+ *cs++ = 0;
+ *cs++ = MI_NOOP;
+
*cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
*cs++ = MI_BATCH_BUFFER_START_GEN8 | BIT(8);
*cs++ = lower_32_bits(batch->node.start);
*cs++ = upper_32_bits(batch->node.start);
*cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
- *cs++ = i915_ggtt_offset(ce->engine->status_page.vma) +
- offset_in_page(sema);
+ *cs++ = sema->ggtt;
*cs++ = 0;
*cs++ = 1;
@@ -1262,7 +1311,7 @@ static int compare_isolation(struct intel_engine_cs *engine,
}
lrc += LRC_STATE_OFFSET / sizeof(*hw);
- defaults = shmem_pin_map(ce->engine->default_state);
+ defaults = shmem_pin_map(engine->default_state);
if (!defaults) {
err = -ENOMEM;
goto err_lrc;
@@ -1315,7 +1364,7 @@ static int compare_isolation(struct intel_engine_cs *engine,
} while (dw < PAGE_SIZE / sizeof(u32) &&
(hw[dw] & ~BIT(0)) != MI_BATCH_BUFFER_END);
- shmem_unpin_map(ce->engine->default_state, defaults);
+ shmem_unpin_map(engine->default_state, defaults);
err_lrc:
i915_gem_object_unpin_map(ce->state->obj);
err_B1:
@@ -1332,7 +1381,7 @@ static int compare_isolation(struct intel_engine_cs *engine,
static int
__lrc_isolation(struct intel_engine_cs *engine, u32 poison, bool relative)
{
- u32 *sema = memset32(engine->status_page.addr + 1000, 0, 1);
+ struct hwsp_semaphore sema = hwsp_semaphore(engine);
struct i915_vma *ref[2], *result[2];
struct intel_context *A, *B;
struct i915_request *rq;
@@ -1360,15 +1409,12 @@ __lrc_isolation(struct intel_engine_cs *engine, u32 poison, bool relative)
goto err_ref0;
}
- rq = record_registers(A, ref[0], ref[1], relative, sema);
+ rq = record_registers(A, engine, ref[0], ref[1], relative, NULL);
if (IS_ERR(rq)) {
err = PTR_ERR(rq);
goto err_ref1;
}
- WRITE_ONCE(*sema, 1);
- wmb();
-
if (i915_request_wait(rq, 0, HZ / 2) < 0) {
i915_request_put(rq);
err = -ETIME;
@@ -1388,15 +1434,15 @@ __lrc_isolation(struct intel_engine_cs *engine, u32 poison, bool relative)
goto err_result0;
}
- rq = record_registers(A, result[0], result[1], relative, sema);
+ rq = record_registers(A, engine, result[0], result[1], relative, &sema);
if (IS_ERR(rq)) {
err = PTR_ERR(rq);
goto err_result1;
}
- err = poison_registers(B, poison, relative, sema);
+ err = poison_registers(B, engine, poison, relative, &sema);
if (err) {
- WRITE_ONCE(*sema, -1);
+ WRITE_ONCE(*sema.va, -1);
i915_request_put(rq);
goto err_result1;
}
@@ -1498,6 +1544,160 @@ static int live_lrc_isolation(void *arg)
return err;
}
+static int __lrc_cross(struct intel_engine_cs *a,
+ struct intel_engine_cs *b,
+ u32 poison)
+{
+ struct hwsp_semaphore sema = hwsp_semaphore(a);
+ struct i915_vma *ref[2], *result[2];
+ struct intel_context *A, *B;
+ struct i915_request *rq;
+ int err;
+
+ GEM_BUG_ON(a->gt->ggtt != b->gt->ggtt);
+
+ pr_debug("Context on %s, poisoning from %s with %08x\n",
+ a->name, b->name, poison);
+
+ A = intel_context_create(a);
+ if (IS_ERR(A))
+ return PTR_ERR(A);
+
+ B = intel_context_create(b);
+ if (IS_ERR(B)) {
+ err = PTR_ERR(B);
+ goto err_A;
+ }
+
+ ref[0] = create_user_vma(A->vm, SZ_64K);
+ if (IS_ERR(ref[0])) {
+ err = PTR_ERR(ref[0]);
+ goto err_B;
+ }
+
+ ref[1] = create_user_vma(A->vm, SZ_64K);
+ if (IS_ERR(ref[1])) {
+ err = PTR_ERR(ref[1]);
+ goto err_ref0;
+ }
+
+ rq = record_registers(A, a, ref[0], ref[1], false, NULL);
+ if (IS_ERR(rq)) {
+ err = PTR_ERR(rq);
+ goto err_ref1;
+ }
+
+ if (i915_request_wait(rq, 0, HZ / 2) < 0) {
+ i915_request_put(rq);
+ err = -ETIME;
+ goto err_ref1;
+ }
+ i915_request_put(rq);
+
+ result[0] = create_user_vma(A->vm, SZ_64K);
+ if (IS_ERR(result[0])) {
+ err = PTR_ERR(result[0]);
+ goto err_ref1;
+ }
+
+ result[1] = create_user_vma(A->vm, SZ_64K);
+ if (IS_ERR(result[1])) {
+ err = PTR_ERR(result[1]);
+ goto err_result0;
+ }
+
+ rq = record_registers(A, a, result[0], result[1], false, &sema);
+ if (IS_ERR(rq)) {
+ err = PTR_ERR(rq);
+ goto err_result1;
+ }
+
+ err = poison_registers(B, a, poison, false, &sema);
+ if (err) {
+ WRITE_ONCE(*sema.va, -1);
+ i915_request_put(rq);
+ goto err_result1;
+ }
+
+ if (i915_request_wait(rq, 0, HZ / 2) < 0) {
+ i915_request_put(rq);
+ err = -ETIME;
+ goto err_result1;
+ }
+ i915_request_put(rq);
+
+ err = compare_isolation(a, ref, result, A, poison, false);
+
+err_result1:
+ i915_vma_put(result[1]);
+err_result0:
+ i915_vma_put(result[0]);
+err_ref1:
+ i915_vma_put(ref[1]);
+err_ref0:
+ i915_vma_put(ref[0]);
+err_B:
+ intel_context_put(B);
+err_A:
+ intel_context_put(A);
+ return err;
+}
+
+static int live_lrc_cross(void *arg)
+{
+ struct intel_gt *gt = arg;
+ struct intel_engine_cs *a, *b;
+ enum intel_engine_id a_id, b_id;
+ const u32 poison[] = {
+ STACK_MAGIC,
+ 0x3a3a3a3a,
+ 0x5c5c5c5c,
+ 0xffffffff,
+ 0xffff0000,
+ };
+ int err = 0;
+ int i;
+
+ /*
+ * Our goal is to try and tamper with another client's context
+ * running concurrently. The HW's goal is to stop us.
+ */
+
+ for_each_engine(a, gt, a_id) {
+ if (!IS_ENABLED(CONFIG_DRM_I915_SELFTEST_BROKEN) &&
+ skip_isolation(a))
+ continue;
+
+ intel_engine_pm_get(a);
+ for_each_engine(b, gt, b_id) {
+ if (a == b)
+ continue;
+
+ intel_engine_pm_get(b);
+ for (i = 0; i < ARRAY_SIZE(poison); i++) {
+ int result;
+
+ result = __lrc_cross(a, b, poison[i]);
+ if (result && !err)
+ err = result;
+
+ result = __lrc_cross(a, b, ~poison[i]);
+ if (result && !err)
+ err = result;
+ }
+ intel_engine_pm_put(b);
+ }
+ intel_engine_pm_put(a);
+
+ if (igt_flush_test(gt->i915)) {
+ err = -EIO;
+ break;
+ }
+ }
+
+ return err;
+}
+
static int indirect_ctx_submit_req(struct intel_context *ce)
{
struct i915_request *rq;
@@ -1888,6 +2088,7 @@ int intel_lrc_live_selftests(struct drm_i915_private *i915)
SUBTEST(live_lrc_isolation),
SUBTEST(live_lrc_timestamp),
SUBTEST(live_lrc_garbage),
+ SUBTEST(live_lrc_cross),
SUBTEST(live_pphwsp_runtime),
SUBTEST(live_lrc_indirect_ctx_bb),
};
--
2.20.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [Intel-gfx] [PATCH 3/8] drm/i915/selftests: Flush the submission for lrc_isolation
2022-03-09 5:17 [Intel-gfx] [PATCH 0/8] Patches for selftest_lrc Ramalingam C
2022-03-09 5:17 ` [Intel-gfx] [PATCH 1/8] drm/i915/selftests: Exercise relative mmio paths to non-privileged registers Ramalingam C
2022-03-09 5:17 ` [Intel-gfx] [PATCH 2/8] drm/i915/selftests: Exercise cross-process context isolation Ramalingam C
@ 2022-03-09 5:17 ` Ramalingam C
2022-03-09 5:17 ` [Intel-gfx] [PATCH 4/8] drm/i915/gt: Explicitly clear BB_OFFSET for new contexts Ramalingam C
` (6 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Ramalingam C @ 2022-03-09 5:17 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: lucas.demarchi, Chris Wilson
From: Chris Wilson <chris@chris-wilson.co.uk>
The lrc_isolation test uses two contexts in order to read from one
context while poisoning from a second. The test verifies that the
writes of the second context do not leak into the first context. This is
done by first recording the register state from context A, forcing a
preemption to context B, and only then switching back to context A to
re-read the register state to see if anything changed. The sequence is
important (and internally controlled by semaphores), but it does require
that context A is submitted *before* context B, as context B has higher
priority to force the preemption.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
---
drivers/gpu/drm/i915/gt/selftest_lrc.c | 17 ++++++++++++++++-
1 file changed, 16 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c
index 998e561694be..b064e824053f 100644
--- a/drivers/gpu/drm/i915/gt/selftest_lrc.c
+++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c
@@ -1416,8 +1416,10 @@ __lrc_isolation(struct intel_engine_cs *engine, u32 poison, bool relative)
}
if (i915_request_wait(rq, 0, HZ / 2) < 0) {
+ pr_err("%s(%s): wait for reference results timed out\n",
+ __func__, engine->name);
i915_request_put(rq);
- err = -ETIME;
+ err = -EIO;
goto err_ref1;
}
i915_request_put(rq);
@@ -1440,6 +1442,17 @@ __lrc_isolation(struct intel_engine_cs *engine, u32 poison, bool relative)
goto err_result1;
}
+ /* Wait until we record the register state before allowing preemption */
+ if (wait_for_submit(engine, rq, HZ / 5)) {
+ pr_err("%s(%s): wait for submission timed out\n",
+ __func__, engine->name);
+ i915_request_put(rq);
+ err = -EIO;
+ goto err_result1;
+ }
+ while (READ_ONCE(*sema.va) && !signal_pending(current))
+ usleep_range(100, 500);
+
err = poison_registers(B, engine, poison, relative, &sema);
if (err) {
WRITE_ONCE(*sema.va, -1);
@@ -1448,6 +1461,8 @@ __lrc_isolation(struct intel_engine_cs *engine, u32 poison, bool relative)
}
if (i915_request_wait(rq, 0, HZ / 2) < 0) {
+ pr_err("%s(%s): wait for results timed out\n",
+ __func__, engine->name);
i915_request_put(rq);
err = -ETIME;
goto err_result1;
--
2.20.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [Intel-gfx] [PATCH 4/8] drm/i915/gt: Explicitly clear BB_OFFSET for new contexts
2022-03-09 5:17 [Intel-gfx] [PATCH 0/8] Patches for selftest_lrc Ramalingam C
` (2 preceding siblings ...)
2022-03-09 5:17 ` [Intel-gfx] [PATCH 3/8] drm/i915/selftests: Flush the submission for lrc_isolation Ramalingam C
@ 2022-03-09 5:17 ` Ramalingam C
2022-03-09 5:17 ` [Intel-gfx] [PATCH 5/8] drm/i915/selftests: Check for incomplete LRI from the context image Ramalingam C
` (5 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Ramalingam C @ 2022-03-09 5:17 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: lucas.demarchi, Chris Wilson
From: Chris Wilson <chris@chris-wilson.co.uk>
Even though the initial protocontext we load onto HW has the register
cleared, by the time we save it into the default image, BB_OFFSET has
had the enable bit set. Reclear BB_OFFSET for each new context.
Testcase: igt/i915_selftests/gt_lrc
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
---
drivers/gpu/drm/i915/gt/intel_engine_regs.h | 1 +
drivers/gpu/drm/i915/gt/intel_lrc.c | 17 +++++++++++++++++
drivers/gpu/drm/i915/gt/selftest_lrc.c | 5 +++++
3 files changed, 23 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_regs.h b/drivers/gpu/drm/i915/gt/intel_engine_regs.h
index 0bf8b45c9319..d6da3bbf66f8 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_regs.h
@@ -109,6 +109,7 @@
#define RING_SBBSTATE(base) _MMIO((base) + 0x118) /* hsw+ */
#define RING_SBBADDR_UDW(base) _MMIO((base) + 0x11c) /* gen8+ */
#define RING_BBADDR(base) _MMIO((base) + 0x140)
+#define RING_BB_OFFSET(base) _MMIO((base) + 0x158)
#define RING_BBADDR_UDW(base) _MMIO((base) + 0x168) /* gen8+ */
#define CCID(base) _MMIO((base) + 0x180)
#define CCID_EN BIT(0)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 07bef7128fdb..f673bae97a03 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -662,6 +662,18 @@ static int lrc_ring_mi_mode(const struct intel_engine_cs *engine)
return -1;
}
+static int lrc_ring_bb_offset(const struct intel_engine_cs *engine)
+{
+ if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50))
+ return 0x80;
+ else if (GRAPHICS_VER(engine->i915) >= 12)
+ return 0x70;
+ else if (GRAPHICS_VER(engine->i915) >= 9)
+ return 0x64;
+ else
+ return -1;
+}
+
static int lrc_ring_gpr0(const struct intel_engine_cs *engine)
{
if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50))
@@ -768,6 +780,7 @@ static void init_common_regs(u32 * const regs,
bool inhibit)
{
u32 ctl;
+ int loc;
ctl = _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH);
ctl |= _MASKED_BIT_DISABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT);
@@ -779,6 +792,10 @@ static void init_common_regs(u32 * const regs,
regs[CTX_CONTEXT_CONTROL] = ctl;
regs[CTX_TIMESTAMP] = ce->runtime.last;
+
+ loc = lrc_ring_bb_offset(engine);
+ if (loc != -1)
+ regs[loc + 1] = 0;
}
static void init_wa_bb_regs(u32 * const regs,
diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c
index b064e824053f..2149b2c92793 100644
--- a/drivers/gpu/drm/i915/gt/selftest_lrc.c
+++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c
@@ -323,6 +323,11 @@ static int live_lrc_fixed(void *arg)
lrc_ring_cmd_buf_cctl(engine),
"RING_CMD_BUF_CCTL"
},
+ {
+ i915_mmio_reg_offset(RING_BB_OFFSET(engine->mmio_base)),
+ lrc_ring_bb_offset(engine),
+ "RING_BB_OFFSET"
+ },
{ },
}, *t;
u32 *hw;
--
2.20.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [Intel-gfx] [PATCH 5/8] drm/i915/selftests: Check for incomplete LRI from the context image
2022-03-09 5:17 [Intel-gfx] [PATCH 0/8] Patches for selftest_lrc Ramalingam C
` (3 preceding siblings ...)
2022-03-09 5:17 ` [Intel-gfx] [PATCH 4/8] drm/i915/gt: Explicitly clear BB_OFFSET for new contexts Ramalingam C
@ 2022-03-09 5:17 ` Ramalingam C
2022-03-09 5:17 ` [Intel-gfx] [PATCH 6/8] drm/i915/selftest: Clear the output buffers before GPU writes Ramalingam C
` (4 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Ramalingam C @ 2022-03-09 5:17 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: lucas.demarchi, Chris Wilson
From: Chris Wilson <chris@chris-wilson.co.uk>
In order to keep the context image parser simple, we assume that all
commands follow a similar format. A few, especially not MI commands on
the render engines, have fixed lengths not encoded in a length field.
This caused us to incorrectly skip over 3D state commands, and start
interpretting context data as instructions. Eventually, as Daniele
discovered, this would lead us to find addition LRI as part of the data
and mistakenly add invalid LRI commands to the context probes.
Stop parsing after we see the first !MI command, as we know we will have
seen all the context registers by that point. (Mostly true for all gen
so far, though the render context does have LRI after the first page that
we have been ignoring so far. It would be useful to extract those as well
so that we have the full list of user accesisble registers.)
Similarly, emit a warning if we do try to emit an invalid zero-length
LRI.
Reported-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
---
drivers/gpu/drm/i915/gt/selftest_lrc.c | 63 ++++++++++++++++++++++----
1 file changed, 55 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c
index 2149b2c92793..6717ecaed178 100644
--- a/drivers/gpu/drm/i915/gt/selftest_lrc.c
+++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c
@@ -27,6 +27,9 @@
#define NUM_GPR 16
#define NUM_GPR_DW (NUM_GPR * 2) /* each GPR is 2 dwords */
+#define LRI_HEADER MI_INSTR(0x22, 0)
+#define LRI_LENGTH_MASK GENMASK(7, 0)
+
static struct i915_vma *create_scratch(struct intel_gt *gt)
{
return __vm_create_scratch_for_read_pinned(>->ggtt->vm, PAGE_SIZE);
@@ -180,7 +183,7 @@ static int live_lrc_layout(void *arg)
continue;
}
- if ((lri & GENMASK(31, 23)) != MI_INSTR(0x22, 0)) {
+ if ((lri & GENMASK(31, 23)) != LRI_HEADER) {
pr_err("%s: Expected LRI command at dword %d, found %08x\n",
engine->name, dw, lri);
err = -EINVAL;
@@ -948,21 +951,43 @@ store_context(struct intel_context *ce,
hw = defaults;
hw += LRC_STATE_OFFSET / sizeof(*hw);
do {
- u32 len = hw[dw] & 0x7f;
+ u32 len = hw[dw] & LRI_LENGTH_MASK;
u32 cmd = MI_STORE_REGISTER_MEM_GEN8;
u32 offset = 0;
u32 mask = ~0;
+ /*
+ * Keep it simple, skip parsing complex commands
+ *
+ * At present, there are no more MI_LOAD_REGISTER_IMM
+ * commands after the first 3D state command. Rather
+ * than include a table (see i915_cmd_parser.c) of all
+ * the possible commands and their instruction lengths
+ * (or mask for variable length instructions), assume
+ * we have gathered the complete list of registers and
+ * bail out.
+ */
+ if ((hw[dw] >> INSTR_CLIENT_SHIFT) != INSTR_MI_CLIENT)
+ break;
+
if (hw[dw] == 0) {
dw++;
continue;
}
- if ((hw[dw] & GENMASK(31, 23)) != MI_INSTR(0x22, 0)) {
+ if ((hw[dw] & GENMASK(31, 23)) != LRI_HEADER) {
+ /* Assume all other MI commands match LRI length mask */
dw += len + 2;
continue;
}
+ if (!len) {
+ pr_err("%s: invalid LRI found in context image\n",
+ engine->name);
+ igt_hexdump(defaults, PAGE_SIZE);
+ break;
+ }
+
if (hw[dw] & MI_LRI_LRM_CS_MMIO) {
mask = 0xfff;
if (relative)
@@ -1162,21 +1187,32 @@ load_context(struct intel_context *ce,
hw = defaults;
hw += LRC_STATE_OFFSET / sizeof(*hw);
do {
- u32 cmd = MI_INSTR(0x22, 0);
- u32 len = hw[dw] & 0x7f;
+ u32 len = hw[dw] & LRI_LENGTH_MASK;
+ u32 cmd = LRI_HEADER;
u32 offset = 0;
u32 mask = ~0;
+ /* For simplicity, break parsing at the first complex command */
+ if ((hw[dw] >> INSTR_CLIENT_SHIFT) != INSTR_MI_CLIENT)
+ break;
+
if (hw[dw] == 0) {
dw++;
continue;
}
- if ((hw[dw] & GENMASK(31, 23)) != MI_INSTR(0x22, 0)) {
+ if ((hw[dw] & GENMASK(31, 23)) != LRI_HEADER) {
dw += len + 2;
continue;
}
+ if (!len) {
+ pr_err("%s: invalid LRI found in context image\n",
+ engine->name);
+ igt_hexdump(defaults, PAGE_SIZE);
+ break;
+ }
+
if (hw[dw] & MI_LRI_LRM_CS_MMIO) {
mask = 0xfff;
if (relative)
@@ -1327,19 +1363,30 @@ static int compare_isolation(struct intel_engine_cs *engine,
hw = defaults;
hw += LRC_STATE_OFFSET / sizeof(*hw);
do {
- u32 len = hw[dw] & 0x7f;
+ u32 len = hw[dw] & LRI_LENGTH_MASK;
bool is_relative = relative;
+ /* For simplicity, break parsing at the first complex command */
+ if ((hw[dw] >> INSTR_CLIENT_SHIFT) != INSTR_MI_CLIENT)
+ break;
+
if (hw[dw] == 0) {
dw++;
continue;
}
- if ((hw[dw] & GENMASK(31, 23)) != MI_INSTR(0x22, 0)) {
+ if ((hw[dw] & GENMASK(31, 23)) != LRI_HEADER) {
dw += len + 2;
continue;
}
+ if (!len) {
+ pr_err("%s: invalid LRI found in context image\n",
+ engine->name);
+ igt_hexdump(defaults, PAGE_SIZE);
+ break;
+ }
+
if (!(hw[dw] & MI_LRI_LRM_CS_MMIO))
is_relative = false;
--
2.20.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [Intel-gfx] [PATCH 6/8] drm/i915/selftest: Clear the output buffers before GPU writes
2022-03-09 5:17 [Intel-gfx] [PATCH 0/8] Patches for selftest_lrc Ramalingam C
` (4 preceding siblings ...)
2022-03-09 5:17 ` [Intel-gfx] [PATCH 5/8] drm/i915/selftests: Check for incomplete LRI from the context image Ramalingam C
@ 2022-03-09 5:17 ` Ramalingam C
2022-03-09 5:17 ` [Intel-gfx] [PATCH 7/8] drm/i915/selftest: Always cancel semaphore on error Ramalingam C
` (3 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Ramalingam C @ 2022-03-09 5:17 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: lucas.demarchi, Chris Wilson, CQ Tang
From: Chris Wilson <chris@chris-wilson.co.uk>
When testing whether we can get the GPU to leak information about
non-privileged state, we first need to ensure that the output buffer is
set to a known value as the HW may opt to skip the write into memory for
a non-privileged read of a sensitive register. We chose POISON_INUSE (0x5a)
so that is both non-zero and distinct from the poison values used during
the test.
Reported-by: CQ Tang <cq.tang@intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
---
drivers/gpu/drm/i915/gt/selftest_lrc.c | 32 ++++++++++++++++++++++----
1 file changed, 28 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c
index 6717ecaed178..d8face764ee4 100644
--- a/drivers/gpu/drm/i915/gt/selftest_lrc.c
+++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c
@@ -1430,6 +1430,30 @@ static int compare_isolation(struct intel_engine_cs *engine,
return err;
}
+static struct i915_vma *
+create_result_vma(struct i915_address_space *vm, unsigned long sz)
+{
+ struct i915_vma *vma;
+ void *ptr;
+
+ vma = create_user_vma(vm, sz);
+ if (IS_ERR(vma))
+ return vma;
+
+ /* Set the results to a known value distinct from the poison */
+ ptr = i915_gem_object_pin_map(vma->obj, I915_MAP_WC);
+ if (IS_ERR(ptr)) {
+ i915_vma_put(vma);
+ return ERR_CAST(ptr);
+ }
+
+ memset(ptr, POISON_INUSE, vma->size);
+ i915_gem_object_flush_map(vma->obj);
+ i915_gem_object_unpin_map(vma->obj);
+
+ return vma;
+}
+
static int
__lrc_isolation(struct intel_engine_cs *engine, u32 poison, bool relative)
{
@@ -1449,13 +1473,13 @@ __lrc_isolation(struct intel_engine_cs *engine, u32 poison, bool relative)
goto err_A;
}
- ref[0] = create_user_vma(A->vm, SZ_64K);
+ ref[0] = create_result_vma(A->vm, SZ_64K);
if (IS_ERR(ref[0])) {
err = PTR_ERR(ref[0]);
goto err_B;
}
- ref[1] = create_user_vma(A->vm, SZ_64K);
+ ref[1] = create_result_vma(A->vm, SZ_64K);
if (IS_ERR(ref[1])) {
err = PTR_ERR(ref[1]);
goto err_ref0;
@@ -1476,13 +1500,13 @@ __lrc_isolation(struct intel_engine_cs *engine, u32 poison, bool relative)
}
i915_request_put(rq);
- result[0] = create_user_vma(A->vm, SZ_64K);
+ result[0] = create_result_vma(A->vm, SZ_64K);
if (IS_ERR(result[0])) {
err = PTR_ERR(result[0]);
goto err_ref1;
}
- result[1] = create_user_vma(A->vm, SZ_64K);
+ result[1] = create_result_vma(A->vm, SZ_64K);
if (IS_ERR(result[1])) {
err = PTR_ERR(result[1]);
goto err_result0;
--
2.20.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [Intel-gfx] [PATCH 7/8] drm/i915/selftest: Always cancel semaphore on error
2022-03-09 5:17 [Intel-gfx] [PATCH 0/8] Patches for selftest_lrc Ramalingam C
` (5 preceding siblings ...)
2022-03-09 5:17 ` [Intel-gfx] [PATCH 6/8] drm/i915/selftest: Clear the output buffers before GPU writes Ramalingam C
@ 2022-03-09 5:17 ` Ramalingam C
2022-03-09 5:17 ` [Intel-gfx] [PATCH 8/8] drm/i915/xehpsdv/dg1/tgl: Fix issue with LRI relative addressing Ramalingam C
` (2 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Ramalingam C @ 2022-03-09 5:17 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: lucas.demarchi, Chris Wilson, CQ Tang
From: Chris Wilson <chris@chris-wilson.co.uk>
Ensure that we always signal the semaphore when timing out, so that if it
happens to be stuck waiting for the semaphore we will quickly recover
without having to wait for a reset.
Reported-by: CQ Tang <cq.tang@intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
---
drivers/gpu/drm/i915/gt/selftest_lrc.c | 15 ++++++---------
1 file changed, 6 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c
index d8face764ee4..63fd508fea49 100644
--- a/drivers/gpu/drm/i915/gt/selftest_lrc.c
+++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c
@@ -1530,20 +1530,17 @@ __lrc_isolation(struct intel_engine_cs *engine, u32 poison, bool relative)
usleep_range(100, 500);
err = poison_registers(B, engine, poison, relative, &sema);
- if (err) {
- WRITE_ONCE(*sema.va, -1);
- i915_request_put(rq);
- goto err_result1;
- }
-
- if (i915_request_wait(rq, 0, HZ / 2) < 0) {
+ if (err == 0 && i915_request_wait(rq, 0, HZ / 2) < 0) {
pr_err("%s(%s): wait for results timed out\n",
__func__, engine->name);
- i915_request_put(rq);
err = -ETIME;
- goto err_result1;
}
+
+ /* Always cancel the semaphore wait, just in case the GPU gets stuck */
+ WRITE_ONCE(*sema.va, -1);
i915_request_put(rq);
+ if (err)
+ goto err_result1;
err = compare_isolation(engine, ref, result, A, poison, relative);
--
2.20.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [Intel-gfx] [PATCH 8/8] drm/i915/xehpsdv/dg1/tgl: Fix issue with LRI relative addressing
2022-03-09 5:17 [Intel-gfx] [PATCH 0/8] Patches for selftest_lrc Ramalingam C
` (6 preceding siblings ...)
2022-03-09 5:17 ` [Intel-gfx] [PATCH 7/8] drm/i915/selftest: Always cancel semaphore on error Ramalingam C
@ 2022-03-09 5:17 ` Ramalingam C
2022-03-09 5:35 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Patches for selftest_lrc Patchwork
2022-03-09 6:06 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
9 siblings, 0 replies; 11+ messages in thread
From: Ramalingam C @ 2022-03-09 5:17 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: Kumar, lucas.demarchi, Valsan
From: Akeem G Abodunrin <akeem.g.abodunrin@intel.com>
When bit 19 of MI_LOAD_REGISTER_IMM instruction opcode is set on devices
of tgl+, HW does not care about certain register address offsets, but
instead check the following for valid address ranges on specific engines:
RCS && CCS: BITS(0 - 10)
BCS: BITS(0 - 11)
VECS && VCS: BITS(0 - 13)
Also, tgl+ now support relative addressing for BCS engine - So, this
patch fixes issue with live_gt_lrc selftest that is failing where there is
mismatch between LRC register layout generated during init and HW
default register offsets.
Bspec: 45728
Cc: Kumar Valsan, Prathap <prathap.kumar.valsan@intel.com>
Signed-off-by: Akeem G Abodunrin <akeem.g.abodunrin@intel.com>
Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
---
drivers/gpu/drm/i915/gt/selftest_lrc.c | 36 +++++++++++++++++++++++++-
1 file changed, 35 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c
index 63fd508fea49..5b2a205ab372 100644
--- a/drivers/gpu/drm/i915/gt/selftest_lrc.c
+++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c
@@ -131,6 +131,27 @@ static int context_flush(struct intel_context *ce, long timeout)
return err;
}
+static int get_lri_mask(struct intel_engine_cs *engine, u32 lri)
+{
+ if ((lri & MI_LRI_LRM_CS_MMIO) == 0)
+ return ~0u;
+
+ if (GRAPHICS_VER(engine->i915) < 12)
+ return 0xfff;
+
+ switch (engine->class) {
+ default:
+ case RENDER_CLASS:
+ case COMPUTE_CLASS:
+ return 0x07ff;
+ case COPY_ENGINE_CLASS:
+ return 0x0fff;
+ case VIDEO_DECODE_CLASS:
+ case VIDEO_ENHANCEMENT_CLASS:
+ return 0x3fff;
+ }
+}
+
static int live_lrc_layout(void *arg)
{
struct intel_gt *gt = arg;
@@ -170,6 +191,7 @@ static int live_lrc_layout(void *arg)
dw = 0;
do {
u32 lri = READ_ONCE(hw[dw]);
+ u32 lri_mask;
if (lri == 0) {
dw++;
@@ -197,6 +219,18 @@ static int live_lrc_layout(void *arg)
break;
}
+ /*
+ * When bit 19 of MI_LOAD_REGISTER_IMM instruction
+ * opcode is set on Gen12+ devices, HW does not
+ * care about certain register address offsets, and
+ * instead check the following for valid address
+ * ranges on specific engines:
+ * RCS && CCS: BITS(0 - 10)
+ * BCS: BITS(0 - 11)
+ * VECS && VCS: BITS(0 - 13)
+ */
+ lri_mask = get_lri_mask(engine, lri);
+
lri &= 0x7f;
lri++;
dw++;
@@ -204,7 +238,7 @@ static int live_lrc_layout(void *arg)
while (lri) {
u32 offset = READ_ONCE(hw[dw]);
- if (offset != lrc[dw]) {
+ if ((offset ^ lrc[dw]) & lri_mask) {
pr_err("%s: Different registers found at dword %d, expected %x, found %x\n",
engine->name, dw, offset, lrc[dw]);
err = -EINVAL;
--
2.20.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Patches for selftest_lrc
2022-03-09 5:17 [Intel-gfx] [PATCH 0/8] Patches for selftest_lrc Ramalingam C
` (7 preceding siblings ...)
2022-03-09 5:17 ` [Intel-gfx] [PATCH 8/8] drm/i915/xehpsdv/dg1/tgl: Fix issue with LRI relative addressing Ramalingam C
@ 2022-03-09 5:35 ` Patchwork
2022-03-09 6:06 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
9 siblings, 0 replies; 11+ messages in thread
From: Patchwork @ 2022-03-09 5:35 UTC (permalink / raw)
To: Ramalingam C; +Cc: intel-gfx
== Series Details ==
Series: Patches for selftest_lrc
URL : https://patchwork.freedesktop.org/series/101188/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:28:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:28:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:28:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:33:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:33:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:51:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:51:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:51:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:57:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:57:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_reset.c:1390:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block
+drivers/gpu/drm/i915/gvt/mmio.c:298:23: warning: memcpy with byte count of 279040
+drivers/gpu/drm/i915/i915_perf.c:1448:15: warning: memset with byte count of 16777216
+drivers/gpu/drm/i915/i915_perf.c:1502:15: warning: memset with byte count of 16777216
+./include/linux/find.h:40:31: warning: shift count is negative (-24)
+./include/linux/find.h:40:31: warning: shift count is negative (-24)
+./include/linux/find.h:40:31: warning: shift count is negative (-24)
+./include/linux/find.h:40:31: warning: shift count is negative (-24)
+./include/linux/find.h:40:31: warning: shift count is negative (-262080)
+./include/linux/find.h:40:31: warning: shift count is negative (-262080)
+./include/linux/find.h:40:31: warning: shift count is negative (-448)
+./include/linux/find.h:40:31: warning: shift count is negative (-448)
+./include/linux/spinlock.h:404:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:404:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:404:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:404:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:404:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:404:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:404:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:404:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:404:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:404:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block
^ permalink raw reply [flat|nested] 11+ messages in thread
* [Intel-gfx] ✗ Fi.CI.BAT: failure for Patches for selftest_lrc
2022-03-09 5:17 [Intel-gfx] [PATCH 0/8] Patches for selftest_lrc Ramalingam C
` (8 preceding siblings ...)
2022-03-09 5:35 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Patches for selftest_lrc Patchwork
@ 2022-03-09 6:06 ` Patchwork
9 siblings, 0 replies; 11+ messages in thread
From: Patchwork @ 2022-03-09 6:06 UTC (permalink / raw)
To: Ramalingam C; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 21425 bytes --]
== Series Details ==
Series: Patches for selftest_lrc
URL : https://patchwork.freedesktop.org/series/101188/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11338 -> Patchwork_22520
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_22520 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_22520, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22520/index.html
Participating hosts (48 -> 42)
------------------------------
Additional (1): bat-dg1-6
Missing (7): fi-kbl-soraka shard-tglu fi-tgl-1115g4 fi-bsw-cyan fi-ctg-p8600 shard-rkl shard-dg1
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_22520:
### IGT changes ###
#### Possible regressions ####
* igt@i915_selftest@live@gt_lrc:
- fi-cfl-guc: [PASS][1] -> [DMESG-FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11338/fi-cfl-guc/igt@i915_selftest@live@gt_lrc.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22520/fi-cfl-guc/igt@i915_selftest@live@gt_lrc.html
- fi-rkl-guc: [PASS][3] -> [DMESG-FAIL][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11338/fi-rkl-guc/igt@i915_selftest@live@gt_lrc.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22520/fi-rkl-guc/igt@i915_selftest@live@gt_lrc.html
- fi-bsw-nick: [PASS][5] -> [DMESG-FAIL][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11338/fi-bsw-nick/igt@i915_selftest@live@gt_lrc.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22520/fi-bsw-nick/igt@i915_selftest@live@gt_lrc.html
- fi-cfl-8109u: [PASS][7] -> [DMESG-FAIL][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11338/fi-cfl-8109u/igt@i915_selftest@live@gt_lrc.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22520/fi-cfl-8109u/igt@i915_selftest@live@gt_lrc.html
- fi-bdw-5557u: NOTRUN -> [DMESG-FAIL][9]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22520/fi-bdw-5557u/igt@i915_selftest@live@gt_lrc.html
- fi-skl-6700k2: [PASS][10] -> [DMESG-FAIL][11]
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11338/fi-skl-6700k2/igt@i915_selftest@live@gt_lrc.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22520/fi-skl-6700k2/igt@i915_selftest@live@gt_lrc.html
- fi-bxt-dsi: [PASS][12] -> [DMESG-FAIL][13]
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11338/fi-bxt-dsi/igt@i915_selftest@live@gt_lrc.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22520/fi-bxt-dsi/igt@i915_selftest@live@gt_lrc.html
- bat-dg1-5: [PASS][14] -> [DMESG-FAIL][15]
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11338/bat-dg1-5/igt@i915_selftest@live@gt_lrc.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22520/bat-dg1-5/igt@i915_selftest@live@gt_lrc.html
- fi-bsw-n3050: [PASS][16] -> [DMESG-FAIL][17]
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11338/fi-bsw-n3050/igt@i915_selftest@live@gt_lrc.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22520/fi-bsw-n3050/igt@i915_selftest@live@gt_lrc.html
- fi-bsw-kefka: [PASS][18] -> [DMESG-FAIL][19]
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11338/fi-bsw-kefka/igt@i915_selftest@live@gt_lrc.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22520/fi-bsw-kefka/igt@i915_selftest@live@gt_lrc.html
- fi-kbl-x1275: [PASS][20] -> [DMESG-FAIL][21]
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11338/fi-kbl-x1275/igt@i915_selftest@live@gt_lrc.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22520/fi-kbl-x1275/igt@i915_selftest@live@gt_lrc.html
- fi-glk-dsi: [PASS][22] -> [DMESG-FAIL][23]
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11338/fi-glk-dsi/igt@i915_selftest@live@gt_lrc.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22520/fi-glk-dsi/igt@i915_selftest@live@gt_lrc.html
- bat-dg1-6: NOTRUN -> [DMESG-FAIL][24]
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22520/bat-dg1-6/igt@i915_selftest@live@gt_lrc.html
- fi-glk-j4005: [PASS][25] -> [DMESG-FAIL][26]
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11338/fi-glk-j4005/igt@i915_selftest@live@gt_lrc.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22520/fi-glk-j4005/igt@i915_selftest@live@gt_lrc.html
- fi-kbl-8809g: [PASS][27] -> [DMESG-FAIL][28]
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11338/fi-kbl-8809g/igt@i915_selftest@live@gt_lrc.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22520/fi-kbl-8809g/igt@i915_selftest@live@gt_lrc.html
- fi-kbl-7500u: [PASS][29] -> [DMESG-FAIL][30]
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11338/fi-kbl-7500u/igt@i915_selftest@live@gt_lrc.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22520/fi-kbl-7500u/igt@i915_selftest@live@gt_lrc.html
- fi-skl-guc: [PASS][31] -> [DMESG-FAIL][32]
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11338/fi-skl-guc/igt@i915_selftest@live@gt_lrc.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22520/fi-skl-guc/igt@i915_selftest@live@gt_lrc.html
- fi-kbl-7567u: [PASS][33] -> [DMESG-FAIL][34]
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11338/fi-kbl-7567u/igt@i915_selftest@live@gt_lrc.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22520/fi-kbl-7567u/igt@i915_selftest@live@gt_lrc.html
- fi-icl-u2: [PASS][35] -> [DMESG-FAIL][36]
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11338/fi-icl-u2/igt@i915_selftest@live@gt_lrc.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22520/fi-icl-u2/igt@i915_selftest@live@gt_lrc.html
- fi-cfl-8700k: [PASS][37] -> [DMESG-FAIL][38]
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11338/fi-cfl-8700k/igt@i915_selftest@live@gt_lrc.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22520/fi-cfl-8700k/igt@i915_selftest@live@gt_lrc.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live@gt_lrc:
- {bat-jsl-2}: NOTRUN -> [DMESG-FAIL][39]
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22520/bat-jsl-2/igt@i915_selftest@live@gt_lrc.html
- {bat-rpls-2}: [PASS][40] -> [DMESG-FAIL][41]
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11338/bat-rpls-2/igt@i915_selftest@live@gt_lrc.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22520/bat-rpls-2/igt@i915_selftest@live@gt_lrc.html
- {fi-ehl-2}: [PASS][42] -> [DMESG-FAIL][43]
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11338/fi-ehl-2/igt@i915_selftest@live@gt_lrc.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22520/fi-ehl-2/igt@i915_selftest@live@gt_lrc.html
- {fi-jsl-1}: [PASS][44] -> [DMESG-FAIL][45]
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11338/fi-jsl-1/igt@i915_selftest@live@gt_lrc.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22520/fi-jsl-1/igt@i915_selftest@live@gt_lrc.html
- {bat-jsl-1}: [PASS][46] -> [DMESG-FAIL][47]
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11338/bat-jsl-1/igt@i915_selftest@live@gt_lrc.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22520/bat-jsl-1/igt@i915_selftest@live@gt_lrc.html
- {bat-dg2-9}: [INCOMPLETE][48] ([i915#5270]) -> [INCOMPLETE][49]
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11338/bat-dg2-9/igt@i915_selftest@live@gt_lrc.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22520/bat-dg2-9/igt@i915_selftest@live@gt_lrc.html
- {bat-adlp-6}: [PASS][50] -> [DMESG-FAIL][51]
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11338/bat-adlp-6/igt@i915_selftest@live@gt_lrc.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22520/bat-adlp-6/igt@i915_selftest@live@gt_lrc.html
Known issues
------------
Here are the changes found in Patchwork_22520 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_gttfill@basic:
- bat-dg1-6: NOTRUN -> [SKIP][52] ([i915#4086])
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22520/bat-dg1-6/igt@gem_exec_gttfill@basic.html
* igt@gem_huc_copy@huc-copy:
- fi-skl-6600u: NOTRUN -> [SKIP][53] ([fdo#109271] / [i915#2190])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22520/fi-skl-6600u/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@verify-random:
- fi-skl-6600u: NOTRUN -> [SKIP][54] ([fdo#109271] / [i915#4613]) +3 similar issues
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22520/fi-skl-6600u/igt@gem_lmem_swapping@verify-random.html
* igt@gem_mmap@basic:
- bat-dg1-6: NOTRUN -> [SKIP][55] ([i915#4083])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22520/bat-dg1-6/igt@gem_mmap@basic.html
* igt@gem_tiled_blits@basic:
- bat-dg1-6: NOTRUN -> [SKIP][56] ([i915#4077]) +2 similar issues
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22520/bat-dg1-6/igt@gem_tiled_blits@basic.html
* igt@gem_tiled_pread_basic:
- bat-dg1-6: NOTRUN -> [SKIP][57] ([i915#4079]) +1 similar issue
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22520/bat-dg1-6/igt@gem_tiled_pread_basic.html
* igt@i915_pm_backlight@basic-brightness:
- bat-dg1-6: NOTRUN -> [SKIP][58] ([i915#1155])
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22520/bat-dg1-6/igt@i915_pm_backlight@basic-brightness.html
* igt@i915_pm_rps@basic-api:
- bat-dg1-6: NOTRUN -> [FAIL][59] ([i915#4032])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22520/bat-dg1-6/igt@i915_pm_rps@basic-api.html
* igt@i915_selftest@live@hangcheck:
- fi-bdw-5557u: NOTRUN -> [INCOMPLETE][60] ([i915#3921])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22520/fi-bdw-5557u/igt@i915_selftest@live@hangcheck.html
* igt@kms_addfb_basic@addfb25-x-tiled-legacy:
- bat-dg1-6: NOTRUN -> [SKIP][61] ([i915#4212]) +7 similar issues
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22520/bat-dg1-6/igt@kms_addfb_basic@addfb25-x-tiled-legacy.html
* igt@kms_addfb_basic@basic-y-tiled-legacy:
- bat-dg1-6: NOTRUN -> [SKIP][62] ([i915#4215])
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22520/bat-dg1-6/igt@kms_addfb_basic@basic-y-tiled-legacy.html
* igt@kms_chamelium@hdmi-edid-read:
- bat-dg1-6: NOTRUN -> [SKIP][63] ([fdo#111827]) +8 similar issues
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22520/bat-dg1-6/igt@kms_chamelium@hdmi-edid-read.html
* igt@kms_chamelium@vga-edid-read:
- fi-skl-6600u: NOTRUN -> [SKIP][64] ([fdo#109271] / [fdo#111827]) +8 similar issues
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22520/fi-skl-6600u/igt@kms_chamelium@vga-edid-read.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- bat-dg1-6: NOTRUN -> [SKIP][65] ([i915#4103] / [i915#4213]) +1 similar issue
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22520/bat-dg1-6/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- fi-skl-6600u: NOTRUN -> [SKIP][66] ([fdo#109271]) +2 similar issues
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22520/fi-skl-6600u/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
* igt@kms_force_connector_basic@force-load-detect:
- bat-dg1-6: NOTRUN -> [SKIP][67] ([fdo#109285])
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22520/bat-dg1-6/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-skl-6600u: NOTRUN -> [SKIP][68] ([fdo#109271] / [i915#533])
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22520/fi-skl-6600u/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
* igt@kms_psr@cursor_plane_move:
- bat-dg1-6: NOTRUN -> [SKIP][69] ([i915#1072] / [i915#4078]) +3 similar issues
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22520/bat-dg1-6/igt@kms_psr@cursor_plane_move.html
* igt@kms_psr@primary_page_flip:
- fi-skl-6600u: NOTRUN -> [FAIL][70] ([i915#4547])
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22520/fi-skl-6600u/igt@kms_psr@primary_page_flip.html
* igt@prime_vgem@basic-fence-flip:
- bat-dg1-6: NOTRUN -> [SKIP][71] ([i915#3708]) +3 similar issues
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22520/bat-dg1-6/igt@prime_vgem@basic-fence-flip.html
* igt@prime_vgem@basic-gtt:
- bat-dg1-6: NOTRUN -> [SKIP][72] ([i915#3708] / [i915#4077]) +1 similar issue
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22520/bat-dg1-6/igt@prime_vgem@basic-gtt.html
* igt@prime_vgem@basic-userptr:
- bat-dg1-6: NOTRUN -> [SKIP][73] ([i915#3708] / [i915#4873])
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22520/bat-dg1-6/igt@prime_vgem@basic-userptr.html
* igt@runner@aborted:
- fi-cfl-8109u: NOTRUN -> [FAIL][74] ([i915#4312] / [i915#5257])
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22520/fi-cfl-8109u/igt@runner@aborted.html
- fi-icl-u2: NOTRUN -> [FAIL][75] ([i915#4312])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22520/fi-icl-u2/igt@runner@aborted.html
- fi-glk-dsi: NOTRUN -> [FAIL][76] ([i915#4312] / [i915#5257] / [k.org#202321])
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22520/fi-glk-dsi/igt@runner@aborted.html
- fi-kbl-7500u: NOTRUN -> [FAIL][77] ([i915#1436] / [i915#4312] / [i915#5257])
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22520/fi-kbl-7500u/igt@runner@aborted.html
- fi-bxt-dsi: NOTRUN -> [FAIL][78] ([i915#4312] / [i915#5257])
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22520/fi-bxt-dsi/igt@runner@aborted.html
- bat-dg1-6: NOTRUN -> [FAIL][79] ([i915#4312] / [i915#5257])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22520/bat-dg1-6/igt@runner@aborted.html
- fi-cfl-guc: NOTRUN -> [FAIL][80] ([i915#4312] / [i915#5257])
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22520/fi-cfl-guc/igt@runner@aborted.html
- fi-glk-j4005: NOTRUN -> [FAIL][81] ([i915#4312] / [i915#5257] / [k.org#202321])
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22520/fi-glk-j4005/igt@runner@aborted.html
- fi-kbl-7567u: NOTRUN -> [FAIL][82] ([i915#1436] / [i915#4312] / [i915#5257])
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22520/fi-kbl-7567u/igt@runner@aborted.html
- fi-skl-guc: NOTRUN -> [FAIL][83] ([i915#1436] / [i915#4312] / [i915#5257])
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22520/fi-skl-guc/igt@runner@aborted.html
- fi-skl-6700k2: NOTRUN -> [FAIL][84] ([i915#1436] / [i915#4312] / [i915#5257])
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22520/fi-skl-6700k2/igt@runner@aborted.html
- fi-kbl-x1275: NOTRUN -> [FAIL][85] ([i915#1436] / [i915#4312] / [i915#5257])
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22520/fi-kbl-x1275/igt@runner@aborted.html
- fi-cfl-8700k: NOTRUN -> [FAIL][86] ([i915#4312] / [i915#5257])
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22520/fi-cfl-8700k/igt@runner@aborted.html
- bat-dg1-5: NOTRUN -> [FAIL][87] ([i915#4312] / [i915#5257])
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22520/bat-dg1-5/igt@runner@aborted.html
- fi-kbl-8809g: NOTRUN -> [FAIL][88] ([i915#1436] / [i915#4312] / [i915#5257])
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22520/fi-kbl-8809g/igt@runner@aborted.html
- fi-rkl-guc: NOTRUN -> [FAIL][89] ([i915#4312])
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22520/fi-rkl-guc/igt@runner@aborted.html
#### Possible fixes ####
* igt@i915_selftest@live@workarounds:
- fi-bdw-5557u: [INCOMPLETE][90] ([i915#5170]) -> [PASS][91]
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11338/fi-bdw-5557u/igt@i915_selftest@live@workarounds.html
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22520/fi-bdw-5557u/igt@i915_selftest@live@workarounds.html
* igt@kms_flip@basic-flip-vs-modeset@a-edp1:
- {bat-adlp-6}: [DMESG-WARN][92] ([i915#3576]) -> [PASS][93]
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11338/bat-adlp-6/igt@kms_flip@basic-flip-vs-modeset@a-edp1.html
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22520/bat-adlp-6/igt@kms_flip@basic-flip-vs-modeset@a-edp1.html
#### Warnings ####
* igt@runner@aborted:
- fi-skl-6600u: [FAIL][94] ([i915#2722] / [i915#4312]) -> [FAIL][95] ([i915#4312] / [i915#5257])
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11338/fi-skl-6600u/igt@runner@aborted.html
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22520/fi-skl-6600u/igt@runner@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2373]: https://gitlab.freedesktop.org/drm/intel/issues/2373
[i915#2722]: https://gitlab.freedesktop.org/drm/intel/issues/2722
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#3576]: https://gitlab.freedesktop.org/drm/intel/issues/3576
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921
[i915#4032]: https://gitlab.freedesktop.org/drm/intel/issues/4032
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4086]: https://gitlab.freedesktop.org/drm/intel/issues/4086
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
[i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4547]: https://gitlab.freedesktop.org/drm/intel/issues/4547
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4873]: https://gitlab.freedesktop.org/drm/intel/issues/4873
[i915#5127]: https://gitlab.freedesktop.org/drm/intel/issues/5127
[i915#5170]: https://gitlab.freedesktop.org/drm/intel/issues/5170
[i915#5257]: https://gitlab.freedesktop.org/drm/intel/issues/5257
[i915#5270]: https://gitlab.freedesktop.org/drm/intel/issues/5270
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#750]: https://gitlab.freedesktop.org/drm/intel/issues/750
[k.org#202321]: https://bugzilla.kernel.org/show_bug.cgi?id=202321
Build changes
-------------
* Linux: CI_DRM_11338 -> Patchwork_22520
CI-20190529: 20190529
CI_DRM_11338: 10d23ef3d24468332f37689a99d707e57c4d9a3f @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6368: 60e5ffca027b38398c279fba0f5a1b7517aa6061 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_22520: f1c7cca293ae0eae52bb60911d478b358b64f0ff @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
f1c7cca293ae drm/i915/xehpsdv/dg1/tgl: Fix issue with LRI relative addressing
0bea204989fd drm/i915/selftest: Always cancel semaphore on error
9471cfa10d10 drm/i915/selftest: Clear the output buffers before GPU writes
f1e142a333b9 drm/i915/selftests: Check for incomplete LRI from the context image
51273c7f1609 drm/i915/gt: Explicitly clear BB_OFFSET for new contexts
77f682a3ce02 drm/i915/selftests: Flush the submission for lrc_isolation
ecc4a703ba82 drm/i915/selftests: Exercise cross-process context isolation
4b27420f08b0 drm/i915/selftests: Exercise relative mmio paths to non-privileged registers
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22520/index.html
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Thread overview: 11+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2022-03-09 5:17 [Intel-gfx] [PATCH 0/8] Patches for selftest_lrc Ramalingam C
2022-03-09 5:17 ` [Intel-gfx] [PATCH 1/8] drm/i915/selftests: Exercise relative mmio paths to non-privileged registers Ramalingam C
2022-03-09 5:17 ` [Intel-gfx] [PATCH 2/8] drm/i915/selftests: Exercise cross-process context isolation Ramalingam C
2022-03-09 5:17 ` [Intel-gfx] [PATCH 3/8] drm/i915/selftests: Flush the submission for lrc_isolation Ramalingam C
2022-03-09 5:17 ` [Intel-gfx] [PATCH 4/8] drm/i915/gt: Explicitly clear BB_OFFSET for new contexts Ramalingam C
2022-03-09 5:17 ` [Intel-gfx] [PATCH 5/8] drm/i915/selftests: Check for incomplete LRI from the context image Ramalingam C
2022-03-09 5:17 ` [Intel-gfx] [PATCH 6/8] drm/i915/selftest: Clear the output buffers before GPU writes Ramalingam C
2022-03-09 5:17 ` [Intel-gfx] [PATCH 7/8] drm/i915/selftest: Always cancel semaphore on error Ramalingam C
2022-03-09 5:17 ` [Intel-gfx] [PATCH 8/8] drm/i915/xehpsdv/dg1/tgl: Fix issue with LRI relative addressing Ramalingam C
2022-03-09 5:35 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Patches for selftest_lrc Patchwork
2022-03-09 6:06 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
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