[Intel-gfx] [PATCH 00/13] drm/i915: Start reordering modeset clock calculations

[Ville Syrjala <ville.syrjala@linux.intel.com>]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Start reordering when we do the clock/dpll calculations
during the atomic check. The eventual goals are:
- back feed the actually calculated clock into the crtc state
  so that stuff that depends on it (eg. watermarks) will be
  calculated based on the actual hardware state we're going to use
  rather than the semi-fictional state we started with
- fix the fastset/fastboot stuff to actually require exact
  clock matches. Avoids the current mess where the user asks
  to slightly change the refresh rate (eg. to match video frame
  rate) but the kernel decides to ignore it and do a fastset instead.

Ville Syrjälä (13):
  drm/i915: Make .get_dplls() return int
  drm/i915: Pass dev_priv to intel_shared_dpll_init()
  drm/i915: Remove pointless dpll_funcs checks
  drm/i915: Adjust .crtc_compute_clock() calling convention
  drm/i915: Move stuff into intel_dpll_crtc_compute_clock()
  drm/i915: Move the dpll_hw_state clearing to
    intel_dpll_crtc_compute_clock()
  drm/i915: Clear the dpll_hw_state when disabling a pipe
  drm/i915: Split out dg2_crtc_compute_clock()
  drm/i915: Add crtc .crtc_get_shared_dpll()
  drm/i915: Split shared dpll .get_dplls() into compute and get phases
  drm/i915: Do .crtc_compute_clock() earlier
  drm/i915: Clean up DPLL related debugs
  drm/i915: Reassign DPLLs only for crtcs going throug .compute_config()

 drivers/gpu/drm/i915/display/intel_display.c  |  33 +-
 drivers/gpu/drm/i915/display/intel_dpll.c     | 249 ++++----
 drivers/gpu/drm/i915/display/intel_dpll.h     |   6 +-
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 531 +++++++++++-------
 drivers/gpu/drm/i915/display/intel_dpll_mgr.h |  12 +-
 5 files changed, 491 insertions(+), 340 deletions(-)

-- 
2.34.1