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From: Jani Nikula <jani.nikula@linux.intel.com>
To: Ville Syrjala <ville.syrjala@linux.intel.com>,
	intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 09/13] drm/i915: Add crtc .crtc_get_shared_dpll()
Date: Mon, 28 Mar 2022 14:10:41 +0300	[thread overview]
Message-ID: <87ee2mfi32.fsf@intel.com> (raw)
In-Reply-To: <20220325123205.22140-10-ville.syrjala@linux.intel.com>

On Fri, 25 Mar 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Start splitting the .compute_crtc_clock() into two parts; one
> part does the computation, the second part does the shared dpll
> assignment. I want to move the actual computation part much earlier
> into the compute_config() phase.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c |  4 ++
>  drivers/gpu/drm/i915/display/intel_dpll.c    | 54 +++++++++++++++++++-
>  drivers/gpu/drm/i915/display/intel_dpll.h    |  2 +
>  3 files changed, 59 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 7c68bc07c925..1b7bc764498c 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -5003,6 +5003,10 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state,
>  		ret = intel_dpll_crtc_compute_clock(state, crtc);
>  		if (ret)
>  			return ret;
> +
> +		ret = intel_dpll_crtc_get_shared_dpll(state, crtc);
> +		if (ret)
> +			return ret;
>  	}
>  
>  	/*
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
> index bc59efe18e89..2ee7255f3c36 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll.c
> @@ -20,6 +20,8 @@
>  struct intel_dpll_funcs {
>  	int (*crtc_compute_clock)(struct intel_atomic_state *state,
>  				  struct intel_crtc *crtc);
> +	int (*crtc_get_shared_dpll)(struct intel_atomic_state *state,
> +				    struct intel_crtc *crtc);
>  };
>  
>  struct intel_limit {
> @@ -930,6 +932,12 @@ static void i8xx_compute_dpll(struct intel_crtc_state *crtc_state,
>  
>  static int hsw_crtc_compute_clock(struct intel_atomic_state *state,
>  				  struct intel_crtc *crtc)
> +{
> +	return 0;
> +}
> +
> +static int hsw_crtc_get_shared_dpll(struct intel_atomic_state *state,
> +				    struct intel_crtc *crtc)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
>  	struct intel_crtc_state *crtc_state =
> @@ -964,6 +972,12 @@ static int dg2_crtc_compute_clock(struct intel_atomic_state *state,
>  	return intel_mpllb_calc_state(crtc_state, encoder);
>  }
>  
> +static int dg2_crtc_get_shared_dpll(struct intel_atomic_state *state,
> +				    struct intel_crtc *crtc)
> +{
> +	return 0;
> +}
> +

This seems superfluous at this time because
intel_dpll_crtc_get_shared_dpll() checks for NULL
.crtc_get_shared_dpll() and does exactly that.

Not a biggie.

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


>  static bool ilk_needs_fb_cb_tune(const struct dpll *dpll, int factor)
>  {
>  	return dpll->m < factor * dpll->n;
> @@ -1087,7 +1101,6 @@ static int ilk_crtc_compute_clock(struct intel_atomic_state *state,
>  		intel_atomic_get_new_crtc_state(state, crtc);
>  	const struct intel_limit *limit;
>  	int refclk = 120000;
> -	int ret;
>  
>  	/* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
>  	if (!crtc_state->has_pch_encoder)
> @@ -1127,6 +1140,21 @@ static int ilk_crtc_compute_clock(struct intel_atomic_state *state,
>  	ilk_compute_dpll(crtc_state, &crtc_state->dpll,
>  			 &crtc_state->dpll);
>  
> +	return 0;
> +}
> +
> +static int ilk_crtc_get_shared_dpll(struct intel_atomic_state *state,
> +				    struct intel_crtc *crtc)
> +{
> +	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> +	struct intel_crtc_state *crtc_state =
> +		intel_atomic_get_new_crtc_state(state, crtc);
> +	int ret;
> +
> +	/* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
> +	if (!crtc_state->has_pch_encoder)
> +		return 0;
> +
>  	ret = intel_reserve_shared_dplls(state, crtc, NULL);
>  	if (ret) {
>  		drm_dbg_kms(&dev_priv->drm,
> @@ -1372,14 +1400,17 @@ static int i8xx_crtc_compute_clock(struct intel_atomic_state *state,
>  
>  static const struct intel_dpll_funcs dg2_dpll_funcs = {
>  	.crtc_compute_clock = dg2_crtc_compute_clock,
> +	.crtc_get_shared_dpll = dg2_crtc_get_shared_dpll,
>  };
>  
>  static const struct intel_dpll_funcs hsw_dpll_funcs = {
>  	.crtc_compute_clock = hsw_crtc_compute_clock,
> +	.crtc_get_shared_dpll = hsw_crtc_get_shared_dpll,
>  };
>  
>  static const struct intel_dpll_funcs ilk_dpll_funcs = {
>  	.crtc_compute_clock = ilk_crtc_compute_clock,
> +	.crtc_get_shared_dpll = ilk_crtc_get_shared_dpll,
>  };
>  
>  static const struct intel_dpll_funcs chv_dpll_funcs = {
> @@ -1427,6 +1458,27 @@ int intel_dpll_crtc_compute_clock(struct intel_atomic_state *state,
>  	return i915->dpll_funcs->crtc_compute_clock(state, crtc);
>  }
>  
> +int intel_dpll_crtc_get_shared_dpll(struct intel_atomic_state *state,
> +				    struct intel_crtc *crtc)
> +{
> +	struct drm_i915_private *i915 = to_i915(state->base.dev);
> +	struct intel_crtc_state *crtc_state =
> +		intel_atomic_get_new_crtc_state(state, crtc);
> +
> +	drm_WARN_ON(&i915->drm, !intel_crtc_needs_modeset(crtc_state));
> +
> +	if (drm_WARN_ON(&i915->drm, crtc_state->shared_dpll))
> +		return 0;
> +
> +	if (!crtc_state->hw.enable)
> +		return 0;
> +
> +	if (!i915->dpll_funcs->crtc_get_shared_dpll)
> +		return 0;
> +
> +	return i915->dpll_funcs->crtc_get_shared_dpll(state, crtc);
> +}
> +
>  void
>  intel_dpll_init_clock_hook(struct drm_i915_private *dev_priv)
>  {
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll.h b/drivers/gpu/drm/i915/display/intel_dpll.h
> index e9731b2dd01c..bbc30542f29f 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll.h
> +++ b/drivers/gpu/drm/i915/display/intel_dpll.h
> @@ -18,6 +18,8 @@ enum pipe;
>  void intel_dpll_init_clock_hook(struct drm_i915_private *dev_priv);
>  int intel_dpll_crtc_compute_clock(struct intel_atomic_state *state,
>  				  struct intel_crtc *crtc);
> +int intel_dpll_crtc_get_shared_dpll(struct intel_atomic_state *state,
> +				    struct intel_crtc *crtc);
>  int vlv_calc_dpll_params(int refclk, struct dpll *clock);
>  int pnv_calc_dpll_params(int refclk, struct dpll *clock);
>  int i9xx_calc_dpll_params(int refclk, struct dpll *clock);

-- 
Jani Nikula, Intel Open Source Graphics Center

  reply	other threads:[~2022-03-28 11:10 UTC|newest]

Thread overview: 44+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-03-25 12:31 [Intel-gfx] [PATCH 00/13] drm/i915: Start reordering modeset clock calculations Ville Syrjala
2022-03-25 12:31 ` [Intel-gfx] [PATCH 01/13] drm/i915: Make .get_dplls() return int Ville Syrjala
2022-03-28 10:57   ` Jani Nikula
2022-03-25 12:31 ` [Intel-gfx] [PATCH 02/13] drm/i915: Pass dev_priv to intel_shared_dpll_init() Ville Syrjala
2022-03-28 10:57   ` Jani Nikula
2022-03-25 12:31 ` [Intel-gfx] [PATCH 03/13] drm/i915: Remove pointless dpll_funcs checks Ville Syrjala
2022-03-28 10:59   ` Jani Nikula
2022-03-25 12:31 ` [Intel-gfx] [PATCH 04/13] drm/i915: Adjust .crtc_compute_clock() calling convention Ville Syrjala
2022-03-28 11:01   ` Jani Nikula
2022-03-25 12:31 ` [Intel-gfx] [PATCH 05/13] drm/i915: Move stuff into intel_dpll_crtc_compute_clock() Ville Syrjala
2022-03-28 11:02   ` Jani Nikula
2022-03-25 12:31 ` [Intel-gfx] [PATCH 06/13] drm/i915: Move the dpll_hw_state clearing to intel_dpll_crtc_compute_clock() Ville Syrjala
2022-03-28 11:05   ` Jani Nikula
2022-03-25 12:31 ` [Intel-gfx] [PATCH 07/13] drm/i915: Clear the dpll_hw_state when disabling a pipe Ville Syrjala
2022-03-28 11:06   ` Jani Nikula
2022-03-25 12:32 ` [Intel-gfx] [PATCH 08/13] drm/i915: Split out dg2_crtc_compute_clock() Ville Syrjala
2022-03-28 11:07   ` Jani Nikula
2022-03-25 12:32 ` [Intel-gfx] [PATCH 09/13] drm/i915: Add crtc .crtc_get_shared_dpll() Ville Syrjala
2022-03-28 11:10   ` Jani Nikula [this message]
2022-03-25 12:32 ` [Intel-gfx] [PATCH 10/13] drm/i915: Split shared dpll .get_dplls() into compute and get phases Ville Syrjala
2022-03-28 11:18   ` Jani Nikula
2022-03-25 12:32 ` [Intel-gfx] [PATCH 11/13] drm/i915: Do .crtc_compute_clock() earlier Ville Syrjala
2022-03-25 12:32 ` [Intel-gfx] [PATCH 12/13] drm/i915: Clean up DPLL related debugs Ville Syrjala
2022-03-28 11:14   ` Jani Nikula
2022-03-25 12:32 ` [Intel-gfx] [PATCH 13/13] drm/i915: Reassign DPLLs only for crtcs going throug .compute_config() Ville Syrjala
2022-03-25 14:19 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Start reordering modeset clock calculations Patchwork
2022-03-25 14:20 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-03-25 14:24 ` [Intel-gfx] ✗ Fi.CI.DOCS: " Patchwork
2022-03-25 14:41 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2022-03-29 13:18 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Start reordering modeset clock calculations (rev2) Patchwork
2022-03-29 13:19 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-03-29 13:23 ` [Intel-gfx] ✗ Fi.CI.DOCS: " Patchwork
2022-03-29 13:59 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2022-03-30  1:29 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Start reordering modeset clock calculations (rev3) Patchwork
2022-03-30  1:31 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-03-30  1:35 ` [Intel-gfx] ✗ Fi.CI.DOCS: " Patchwork
2022-03-30  2:09 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-03-30  3:37 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2022-04-14  2:10 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Start reordering modeset clock calculations (rev4) Patchwork
2022-04-14  2:10 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-04-14  2:33 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2022-04-21 16:59 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Start reordering modeset clock calculations (rev5) Patchwork
2022-04-21 17:28 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-04-21 21:51 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork

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