From: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
To: intel-gfx@lists.freedesktop.org, daniele.ceraolospurio@intel.com,
john.c.harrison@intel.com
Subject: [Intel-gfx] [PATCH 0/6] Enable WAs related to DG2
Date: Fri, 15 Apr 2022 15:40:19 -0700 [thread overview]
Message-ID: <20220415224025.3693037-1-umesh.nerlige.ramappa@intel.com> (raw)
Enable work arounds related to DG2.
Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
Signed-off-by: Tilak Tangudu <tilak.tangudu@intel.com>
Signed-off-by: Matthew Brost <matthew.brost@intel.com>
John Harrison (2):
drm/i915/guc: Enable GuC based workarounds for DG2
drm/i915/dg2: Enable Wa_22012727170/Wa_22012727685
Matthew Brost (1):
drm/i915/dg2: Enable Wa_14014475959 - RCS / CCS context exit
Tilak Tangudu (1):
drm/i915: Add Wa_22011802037 force cs halt
Umesh Nerlige Ramappa (1):
drm/i915/guc: Enable Wa_22011802037 for gen12 GuC based platforms
Vinay Belgaumkar (1):
drm/i915/guc: Apply Wa_16011777198
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 41 +++++++++
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 9 ++
drivers/gpu/drm/i915/gt/intel_engine_regs.h | 1 +
drivers/gpu/drm/i915/gt/intel_engine_types.h | 8 ++
drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 7 ++
drivers/gpu/drm/i915/gt/intel_gt_pm.c | 9 +-
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 18 ++++
drivers/gpu/drm/i915/gt/intel_reset.c | 5 +-
drivers/gpu/drm/i915/gt/uc/intel_guc.c | 35 ++++++++
drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 8 +-
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 89 ++++++++++++++++++-
11 files changed, 222 insertions(+), 8 deletions(-)
--
2.35.1
next reply other threads:[~2022-04-15 22:40 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-04-15 22:40 Umesh Nerlige Ramappa [this message]
2022-04-15 22:40 ` [Intel-gfx] [PATCH 1/6] drm/i915: Add Wa_22011802037 force cs halt Umesh Nerlige Ramappa
2022-04-15 22:40 ` [Intel-gfx] [PATCH 2/6] drm/i915/guc: Enable Wa_22011802037 for gen12 GuC based platforms Umesh Nerlige Ramappa
2022-04-19 0:57 ` Ceraolo Spurio, Daniele
2022-04-15 22:40 ` [Intel-gfx] [PATCH 3/6] drm/i915/guc: Enable GuC based workarounds for DG2 Umesh Nerlige Ramappa
2022-04-18 22:37 ` Ceraolo Spurio, Daniele
2022-04-15 22:40 ` [Intel-gfx] [PATCH 4/6] drm/i915/guc: Apply Wa_16011777198 Umesh Nerlige Ramappa
2022-04-15 22:40 ` [Intel-gfx] [PATCH 5/6] drm/i915/dg2: Enable Wa_14014475959 - RCS / CCS context exit Umesh Nerlige Ramappa
2022-04-15 22:40 ` [Intel-gfx] [PATCH 6/6] drm/i915/dg2: Enable Wa_22012727170/Wa_22012727685 Umesh Nerlige Ramappa
2022-04-15 23:55 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Enable WAs related to DG2 Patchwork
2022-04-15 23:56 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-04-16 0:19 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-04-16 2:12 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20220415224025.3693037-1-umesh.nerlige.ramappa@intel.com \
--to=umesh.nerlige.ramappa@intel.com \
--cc=daniele.ceraolospurio@intel.com \
--cc=intel-gfx@lists.freedesktop.org \
--cc=john.c.harrison@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox