* [Intel-gfx] [PATCH 1/1] drm/i915/guc: Convert ct buffer to iosys_map
2022-03-22 8:44 [Intel-gfx] [PATCH 0/1] drm/i915/guc: Refactor CT access to use iosys_map Mullati Siva
@ 2022-03-22 8:44 ` Mullati Siva
2022-04-02 4:13 ` Lucas De Marchi
0 siblings, 1 reply; 14+ messages in thread
From: Mullati Siva @ 2022-03-22 8:44 UTC (permalink / raw)
To: intel-gfx, siva.mullati; +Cc: lucas.demarchi
From: Siva Mullati <siva.mullati@intel.com>
Convert CT commands and descriptors to use iosys_map rather
than plain pointer and save it in the intel_guc_ct_buffer struct.
This will help with ct_write and ct_read for cmd send and receive
after the initialization by abstracting the IO vs system memory.
Signed-off-by: Siva Mullati <siva.mullati@intel.com>
---
drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 200 +++++++++++++---------
drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h | 9 +-
2 files changed, 127 insertions(+), 82 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
index f01325cd1b62..1c21ced44106 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
@@ -44,6 +44,11 @@ static inline struct drm_device *ct_to_drm(struct intel_guc_ct *ct)
#define CT_PROBE_ERROR(_ct, _fmt, ...) \
i915_probe_error(ct_to_i915(ct), "CT: " _fmt, ##__VA_ARGS__)
+#define ct_desc_read(desc_map_, field_) \
+ iosys_map_rd_field(desc_map_, 0, struct guc_ct_buffer_desc, field_)
+#define ct_desc_write(desc_map_, field_, val_) \
+ iosys_map_wr_field(desc_map_, 0, struct guc_ct_buffer_desc, field_, val_)
+
/**
* DOC: CTB Blob
*
@@ -76,6 +81,11 @@ static inline struct drm_device *ct_to_drm(struct intel_guc_ct *ct)
#define CTB_G2H_BUFFER_SIZE (4 * CTB_H2G_BUFFER_SIZE)
#define G2H_ROOM_BUFFER_SIZE (CTB_G2H_BUFFER_SIZE / 4)
+#define CTB_SEND_DESC_OFFSET (0X0000)
+#define CTB_RECV_DESC_OFFSET (CTB_DESC_SIZE)
+#define CTB_SEND_CMDS_OFFSET (2 * CTB_DESC_SIZE)
+#define CTB_RECV_CMDS_OFFSET (2 * CTB_DESC_SIZE + CTB_H2G_BUFFER_SIZE)
+
struct ct_request {
struct list_head link;
u32 fence;
@@ -113,9 +123,9 @@ void intel_guc_ct_init_early(struct intel_guc_ct *ct)
init_waitqueue_head(&ct->wq);
}
-static void guc_ct_buffer_desc_init(struct guc_ct_buffer_desc *desc)
+static void guc_ct_buffer_desc_init(struct iosys_map *desc)
{
- memset(desc, 0, sizeof(*desc));
+ iosys_map_memset(desc, 0, 0, sizeof(struct guc_ct_buffer_desc));
}
static void guc_ct_buffer_reset(struct intel_guc_ct_buffer *ctb)
@@ -128,17 +138,18 @@ static void guc_ct_buffer_reset(struct intel_guc_ct_buffer *ctb)
space = CIRC_SPACE(ctb->tail, ctb->head, ctb->size) - ctb->resv_space;
atomic_set(&ctb->space, space);
- guc_ct_buffer_desc_init(ctb->desc);
+ guc_ct_buffer_desc_init(&ctb->desc_map);
}
static void guc_ct_buffer_init(struct intel_guc_ct_buffer *ctb,
- struct guc_ct_buffer_desc *desc,
- u32 *cmds, u32 size_in_bytes, u32 resv_space)
+ struct iosys_map *desc,
+ struct iosys_map *cmds,
+ u32 size_in_bytes, u32 resv_space)
{
GEM_BUG_ON(size_in_bytes % 4);
- ctb->desc = desc;
- ctb->cmds = cmds;
+ ctb->desc_map = *desc;
+ ctb->cmds_map = *cmds;
ctb->size = size_in_bytes / 4;
ctb->resv_space = resv_space / 4;
@@ -218,12 +229,13 @@ static int ct_register_buffer(struct intel_guc_ct *ct, bool send,
int intel_guc_ct_init(struct intel_guc_ct *ct)
{
struct intel_guc *guc = ct_to_guc(ct);
- struct guc_ct_buffer_desc *desc;
+ struct iosys_map blob_map;
+ struct iosys_map desc_map;
+ struct iosys_map cmds_map;
u32 blob_size;
u32 cmds_size;
u32 resv_space;
void *blob;
- u32 *cmds;
int err;
err = i915_inject_probe_error(guc_to_gt(guc)->i915, -ENXIO);
@@ -242,27 +254,35 @@ int intel_guc_ct_init(struct intel_guc_ct *ct)
CT_DEBUG(ct, "base=%#x size=%u\n", intel_guc_ggtt_offset(guc, ct->vma), blob_size);
- /* store pointers to desc and cmds for send ctb */
- desc = blob;
- cmds = blob + 2 * CTB_DESC_SIZE;
+ if (i915_gem_object_is_lmem(ct->vma->obj))
+ iosys_map_set_vaddr_iomem(&blob_map,
+ (void __iomem *)blob);
+ else
+ iosys_map_set_vaddr(&blob_map, blob);
+
+ /* store sysmap to desc_map and cmds_map for send ctb */
+ desc_map = IOSYS_MAP_INIT_OFFSET(&blob_map, CTB_SEND_DESC_OFFSET);
+ cmds_map = IOSYS_MAP_INIT_OFFSET(&blob_map, CTB_SEND_CMDS_OFFSET);
cmds_size = CTB_H2G_BUFFER_SIZE;
resv_space = 0;
- CT_DEBUG(ct, "%s desc %#tx cmds %#tx size %u/%u\n", "send",
- ptrdiff(desc, blob), ptrdiff(cmds, blob), cmds_size,
- resv_space);
+ CT_DEBUG(ct, "%s desc %#x cmds %#x size %u/%u\n", "send",
+ (u32)CTB_SEND_DESC_OFFSET, (u32)CTB_SEND_CMDS_OFFSET,
+ cmds_size, resv_space);
- guc_ct_buffer_init(&ct->ctbs.send, desc, cmds, cmds_size, resv_space);
+ guc_ct_buffer_init(&ct->ctbs.send,
+ &desc_map, &cmds_map, cmds_size, resv_space);
- /* store pointers to desc and cmds for recv ctb */
- desc = blob + CTB_DESC_SIZE;
- cmds = blob + 2 * CTB_DESC_SIZE + CTB_H2G_BUFFER_SIZE;
+ /* store sysmap to desc_map and cmds_map for recv ctb */
+ desc_map = IOSYS_MAP_INIT_OFFSET(&blob_map, CTB_RECV_DESC_OFFSET);
+ cmds_map = IOSYS_MAP_INIT_OFFSET(&blob_map, CTB_RECV_CMDS_OFFSET);
cmds_size = CTB_G2H_BUFFER_SIZE;
resv_space = G2H_ROOM_BUFFER_SIZE;
- CT_DEBUG(ct, "%s desc %#tx cmds %#tx size %u/%u\n", "recv",
- ptrdiff(desc, blob), ptrdiff(cmds, blob), cmds_size,
- resv_space);
+ CT_DEBUG(ct, "%s desc %#x cmds %#x size %u/%u\n", "recv",
+ (u32)CTB_RECV_DESC_OFFSET, (u32)CTB_RECV_CMDS_OFFSET,
+ cmds_size, resv_space);
- guc_ct_buffer_init(&ct->ctbs.recv, desc, cmds, cmds_size, resv_space);
+ guc_ct_buffer_init(&ct->ctbs.recv,
+ &desc_map, &cmds_map, cmds_size, resv_space);
return 0;
}
@@ -279,6 +299,10 @@ void intel_guc_ct_fini(struct intel_guc_ct *ct)
tasklet_kill(&ct->receive_tasklet);
i915_vma_unpin_and_release(&ct->vma, I915_VMA_RELEASE_MAP);
+ iosys_map_clear(&ct->ctbs.send.desc_map);
+ iosys_map_clear(&ct->ctbs.send.cmds_map);
+ iosys_map_clear(&ct->ctbs.recv.desc_map);
+ iosys_map_clear(&ct->ctbs.recv.cmds_map);
memset(ct, 0, sizeof(*ct));
}
@@ -291,8 +315,8 @@ void intel_guc_ct_fini(struct intel_guc_ct *ct)
int intel_guc_ct_enable(struct intel_guc_ct *ct)
{
struct intel_guc *guc = ct_to_guc(ct);
+ struct iosys_map blob_map;
u32 base, desc, cmds, size;
- void *blob;
int err;
GEM_BUG_ON(ct->enabled);
@@ -302,9 +326,14 @@ int intel_guc_ct_enable(struct intel_guc_ct *ct)
GEM_BUG_ON(!i915_gem_object_has_pinned_pages(ct->vma->obj));
base = intel_guc_ggtt_offset(guc, ct->vma);
+ if (i915_gem_object_is_lmem(ct->vma->obj))
+ iosys_map_set_vaddr_iomem(&blob_map, (void __iomem *)
+ __px_vaddr(ct->vma->obj));
+ else
+ iosys_map_set_vaddr(&blob_map, __px_vaddr(ct->vma->obj));
+
/* blob should start with send descriptor */
- blob = __px_vaddr(ct->vma->obj);
- GEM_BUG_ON(blob != ct->ctbs.send.desc);
+ GEM_BUG_ON(!iosys_map_is_equal(&blob_map, &ct->ctbs.send.desc_map));
/* (re)initialize descriptors */
guc_ct_buffer_reset(&ct->ctbs.send);
@@ -314,15 +343,15 @@ int intel_guc_ct_enable(struct intel_guc_ct *ct)
* Register both CT buffers starting with RECV buffer.
* Descriptors are in first half of the blob.
*/
- desc = base + ptrdiff(ct->ctbs.recv.desc, blob);
- cmds = base + ptrdiff(ct->ctbs.recv.cmds, blob);
+ desc = base + CTB_RECV_DESC_OFFSET;
+ cmds = base + CTB_RECV_CMDS_OFFSET;
size = ct->ctbs.recv.size * 4;
err = ct_register_buffer(ct, false, desc, cmds, size);
if (unlikely(err))
goto err_out;
- desc = base + ptrdiff(ct->ctbs.send.desc, blob);
- cmds = base + ptrdiff(ct->ctbs.send.cmds, blob);
+ desc = base + CTB_SEND_DESC_OFFSET;
+ cmds = base + CTB_SEND_CMDS_OFFSET;
size = ct->ctbs.send.size * 4;
err = ct_register_buffer(ct, true, desc, cmds, size);
if (unlikely(err))
@@ -371,31 +400,33 @@ static int ct_write(struct intel_guc_ct *ct,
u32 fence, u32 flags)
{
struct intel_guc_ct_buffer *ctb = &ct->ctbs.send;
- struct guc_ct_buffer_desc *desc = ctb->desc;
u32 tail = ctb->tail;
u32 size = ctb->size;
u32 header;
u32 hxg;
u32 type;
- u32 *cmds = ctb->cmds;
+ u32 status = ct_desc_read(&ctb->desc_map, status);
unsigned int i;
- if (unlikely(desc->status))
+ if (unlikely(status))
goto corrupted;
GEM_BUG_ON(tail > size);
#ifdef CONFIG_DRM_I915_DEBUG_GUC
- if (unlikely(tail != READ_ONCE(desc->tail))) {
+ if (unlikely(tail != ct_desc_read(&ctb->desc_map, tail))) {
CT_ERROR(ct, "Tail was modified %u != %u\n",
- desc->tail, tail);
- desc->status |= GUC_CTB_STATUS_MISMATCH;
+ ct_desc_read(&ctb->desc_map, tail), tail);
+ status |= GUC_CTB_STATUS_MISMATCH;
+ ct_desc_write(&ctb->desc_map, status, status);
goto corrupted;
}
- if (unlikely(READ_ONCE(desc->head) >= size)) {
+ if (unlikely(ct_desc_read(&ctb->desc_map, head) >= size)) {
CT_ERROR(ct, "Invalid head offset %u >= %u)\n",
- desc->head, size);
- desc->status |= GUC_CTB_STATUS_OVERFLOW;
+ ct_desc_read(&ctb->desc_map, head), size);
+ status = ct_desc_read(&ctb->desc_map, status) |
+ GUC_CTB_STATUS_OVERFLOW;
+ ct_desc_write(&ctb->desc_map, status, status);
goto corrupted;
}
#endif
@@ -418,14 +449,14 @@ static int ct_write(struct intel_guc_ct *ct,
CT_DEBUG(ct, "writing (tail %u) %*ph %*ph %*ph\n",
tail, 4, &header, 4, &hxg, 4 * (len - 1), &action[1]);
- cmds[tail] = header;
+ iosys_map_wr(&ctb->cmds_map, (4 * tail), u32, header);
tail = (tail + 1) % size;
- cmds[tail] = hxg;
+ iosys_map_wr(&ctb->cmds_map, (4 * tail), u32, hxg);
tail = (tail + 1) % size;
for (i = 1; i < len; i++) {
- cmds[tail] = action[i];
+ iosys_map_wr(&ctb->cmds_map, (4 * tail), u32, action[i]);
tail = (tail + 1) % size;
}
GEM_BUG_ON(tail > size);
@@ -442,13 +473,14 @@ static int ct_write(struct intel_guc_ct *ct,
atomic_sub(len + GUC_CTB_HDR_LEN, &ctb->space);
/* now update descriptor */
- WRITE_ONCE(desc->tail, tail);
+ ct_desc_write(&ctb->desc_map, tail, tail);
return 0;
corrupted:
CT_ERROR(ct, "Corrupted descriptor head=%u tail=%u status=%#x\n",
- desc->head, desc->tail, desc->status);
+ ct_desc_read(&ctb->desc_map, head), ct_desc_read(&ctb->desc_map, tail),
+ ct_desc_read(&ctb->desc_map, status));
ctb->broken = true;
return -EPIPE;
}
@@ -499,20 +531,22 @@ static inline bool ct_deadlocked(struct intel_guc_ct *ct)
bool ret = ktime_ms_delta(ktime_get(), ct->stall_time) > timeout;
if (unlikely(ret)) {
- struct guc_ct_buffer_desc *send = ct->ctbs.send.desc;
- struct guc_ct_buffer_desc *recv = ct->ctbs.send.desc;
-
CT_ERROR(ct, "Communication stalled for %lld ms, desc status=%#x,%#x\n",
ktime_ms_delta(ktime_get(), ct->stall_time),
- send->status, recv->status);
+ ct_desc_read(&ct->ctbs.send.desc_map, status),
+ ct_desc_read(&ct->ctbs.recv.desc_map, status));
CT_ERROR(ct, "H2G Space: %u (Bytes)\n",
atomic_read(&ct->ctbs.send.space) * 4);
- CT_ERROR(ct, "Head: %u (Dwords)\n", ct->ctbs.send.desc->head);
- CT_ERROR(ct, "Tail: %u (Dwords)\n", ct->ctbs.send.desc->tail);
+ CT_ERROR(ct, "Head: %u (Dwords)\n",
+ ct_desc_read(&ct->ctbs.send.desc_map, head));
+ CT_ERROR(ct, "Tail: %u (Dwords)\n",
+ ct_desc_read(&ct->ctbs.send.desc_map, tail));
CT_ERROR(ct, "G2H Space: %u (Bytes)\n",
atomic_read(&ct->ctbs.recv.space) * 4);
- CT_ERROR(ct, "Head: %u\n (Dwords)", ct->ctbs.recv.desc->head);
- CT_ERROR(ct, "Tail: %u\n (Dwords)", ct->ctbs.recv.desc->tail);
+ CT_ERROR(ct, "Head: %u\n (Dwords)",
+ ct_desc_read(&ct->ctbs.recv.desc_map, head));
+ CT_ERROR(ct, "Tail: %u\n (Dwords)",
+ ct_desc_read(&ct->ctbs.recv.desc_map, tail));
ct->ctbs.send.broken = true;
}
@@ -549,18 +583,19 @@ static inline void g2h_release_space(struct intel_guc_ct *ct, u32 g2h_len_dw)
static inline bool h2g_has_room(struct intel_guc_ct *ct, u32 len_dw)
{
struct intel_guc_ct_buffer *ctb = &ct->ctbs.send;
- struct guc_ct_buffer_desc *desc = ctb->desc;
u32 head;
u32 space;
+ u32 status = ct_desc_read(&ctb->desc_map, status);
if (atomic_read(&ctb->space) >= len_dw)
return true;
- head = READ_ONCE(desc->head);
+ head = ct_desc_read(&ctb->desc_map, head);
if (unlikely(head > ctb->size)) {
CT_ERROR(ct, "Invalid head offset %u >= %u)\n",
head, ctb->size);
- desc->status |= GUC_CTB_STATUS_OVERFLOW;
+ status |= GUC_CTB_STATUS_OVERFLOW;
+ ct_desc_write(&ctb->desc_map, status, status);
ctb->broken = true;
return false;
}
@@ -803,11 +838,10 @@ static void ct_free_msg(struct ct_incoming_msg *msg)
static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg)
{
struct intel_guc_ct_buffer *ctb = &ct->ctbs.recv;
- struct guc_ct_buffer_desc *desc = ctb->desc;
u32 head = ctb->head;
- u32 tail = READ_ONCE(desc->tail);
+ u32 tail = ct_desc_read(&ctb->desc_map, tail);
u32 size = ctb->size;
- u32 *cmds = ctb->cmds;
+ u32 status = ct_desc_read(&ctb->desc_map, status);
s32 available;
unsigned int len;
unsigned int i;
@@ -816,23 +850,26 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg)
if (unlikely(ctb->broken))
return -EPIPE;
- if (unlikely(desc->status))
+ if (unlikely(status))
goto corrupted;
GEM_BUG_ON(head > size);
#ifdef CONFIG_DRM_I915_DEBUG_GUC
- if (unlikely(head != READ_ONCE(desc->head))) {
+ if (unlikely(head != ct_desc_read(&ctb->desc_map, head))) {
CT_ERROR(ct, "Head was modified %u != %u\n",
- desc->head, head);
- desc->status |= GUC_CTB_STATUS_MISMATCH;
+ ct_desc_read(&ctb->desc_map, head), head);
+ status |= GUC_CTB_STATUS_MISMATCH;
+ ct_desc_write(&ctb->desc_map, status, status);
goto corrupted;
}
#endif
if (unlikely(tail >= size)) {
CT_ERROR(ct, "Invalid tail offset %u >= %u)\n",
tail, size);
- desc->status |= GUC_CTB_STATUS_OVERFLOW;
+ status = ct_desc_read(&ctb->desc_map, status) |
+ GUC_CTB_STATUS_OVERFLOW;
+ ct_desc_write(&ctb->desc_map, status, status);
goto corrupted;
}
@@ -849,7 +886,7 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg)
CT_DEBUG(ct, "available %d (%u:%u:%u)\n", available, head, tail, size);
GEM_BUG_ON(available < 0);
- header = cmds[head];
+ header = iosys_map_rd(&ctb->cmds_map, (4 * head), u32);
head = (head + 1) % size;
/* message len with header */
@@ -857,11 +894,15 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg)
if (unlikely(len > (u32)available)) {
CT_ERROR(ct, "Incomplete message %*ph %*ph %*ph\n",
4, &header,
+ 4 * (head + available - 1 > size ? size - head :
+ available - 1), ((__px_vaddr(ct->vma->obj) +
+ CTB_RECV_CMDS_OFFSET) + (4 * head)),
4 * (head + available - 1 > size ?
- size - head : available - 1), &cmds[head],
- 4 * (head + available - 1 > size ?
- available - 1 - size + head : 0), &cmds[0]);
- desc->status |= GUC_CTB_STATUS_UNDERFLOW;
+ available - 1 - size + head : 0),
+ (__px_vaddr(ct->vma->obj) + CTB_RECV_CMDS_OFFSET));
+ status = ct_desc_read(&ctb->desc_map, status) |
+ GUC_CTB_STATUS_UNDERFLOW;
+ ct_desc_write(&ctb->desc_map, status, status);
goto corrupted;
}
@@ -869,17 +910,18 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg)
if (!*msg) {
CT_ERROR(ct, "No memory for message %*ph %*ph %*ph\n",
4, &header,
+ 4 * (head + available - 1 > size ? size - head :
+ available - 1), (ctb->cmds_map.vaddr + (4 * head)),
4 * (head + available - 1 > size ?
- size - head : available - 1), &cmds[head],
- 4 * (head + available - 1 > size ?
- available - 1 - size + head : 0), &cmds[0]);
+ available - 1 - size + head : 0), ctb->cmds_map.vaddr);
return available;
}
(*msg)->msg[0] = header;
for (i = 1; i < len; i++) {
- (*msg)->msg[i] = cmds[head];
+ (*msg)->msg[i] = iosys_map_rd(&ctb->cmds_map,
+ (4 * head), u32);
head = (head + 1) % size;
}
CT_DEBUG(ct, "received %*ph\n", 4 * len, (*msg)->msg);
@@ -888,13 +930,15 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg)
ctb->head = head;
/* now update descriptor */
- WRITE_ONCE(desc->head, head);
+ ct_desc_write(&ctb->desc_map, head, head);
return available - len;
corrupted:
CT_ERROR(ct, "Corrupted descriptor head=%u tail=%u status=%#x\n",
- desc->head, desc->tail, desc->status);
+ ct_desc_read(&ctb->desc_map, head),
+ ct_desc_read(&ctb->desc_map, tail),
+ ct_desc_read(&ctb->desc_map, status));
ctb->broken = true;
return -EPIPE;
}
@@ -1211,13 +1255,13 @@ void intel_guc_ct_print_info(struct intel_guc_ct *ct,
drm_printf(p, "H2G Space: %u\n",
atomic_read(&ct->ctbs.send.space) * 4);
drm_printf(p, "Head: %u\n",
- ct->ctbs.send.desc->head);
+ ct_desc_read(&ct->ctbs.send.desc_map, head));
drm_printf(p, "Tail: %u\n",
- ct->ctbs.send.desc->tail);
+ ct_desc_read(&ct->ctbs.send.desc_map, tail));
drm_printf(p, "G2H Space: %u\n",
atomic_read(&ct->ctbs.recv.space) * 4);
drm_printf(p, "Head: %u\n",
- ct->ctbs.recv.desc->head);
+ ct_desc_read(&ct->ctbs.recv.desc_map, head));
drm_printf(p, "Tail: %u\n",
- ct->ctbs.recv.desc->tail);
+ ct_desc_read(&ct->ctbs.recv.desc_map, tail));
}
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h
index f709a19c7e21..867fe13fb47d 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h
@@ -7,6 +7,7 @@
#define _INTEL_GUC_CT_H_
#include <linux/interrupt.h>
+#include <linux/iosys-map.h>
#include <linux/spinlock.h>
#include <linux/workqueue.h>
#include <linux/ktime.h>
@@ -32,8 +33,8 @@ struct drm_printer;
* holds the commands.
*
* @lock: protects access to the commands buffer and buffer descriptor
- * @desc: pointer to the buffer descriptor
- * @cmds: pointer to the commands buffer
+ * @desc: iosys map to the buffer descriptor
+ * @cmds: iosys map to the commands buffer
* @size: size of the commands buffer in dwords
* @resv_space: reserved space in buffer in dwords
* @head: local shadow copy of head in dwords
@@ -43,8 +44,8 @@ struct drm_printer;
*/
struct intel_guc_ct_buffer {
spinlock_t lock;
- struct guc_ct_buffer_desc *desc;
- u32 *cmds;
+ struct iosys_map desc_map;
+ struct iosys_map cmds_map;
u32 size;
u32 resv_space;
u32 tail;
--
2.33.0
^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [Intel-gfx] [PATCH 1/1] drm/i915/guc: Convert ct buffer to iosys_map
2022-03-22 8:44 ` [Intel-gfx] [PATCH 1/1] drm/i915/guc: Convert ct buffer to iosys_map Mullati Siva
@ 2022-04-02 4:13 ` Lucas De Marchi
0 siblings, 0 replies; 14+ messages in thread
From: Lucas De Marchi @ 2022-04-02 4:13 UTC (permalink / raw)
To: Mullati Siva; +Cc: intel-gfx
On Tue, Mar 22, 2022 at 02:14:37PM +0530, Mullati Siva wrote:
>From: Siva Mullati <siva.mullati@intel.com>
>
>Convert CT commands and descriptors to use iosys_map rather
>than plain pointer and save it in the intel_guc_ct_buffer struct.
>This will help with ct_write and ct_read for cmd send and receive
>after the initialization by abstracting the IO vs system memory.
>
>Signed-off-by: Siva Mullati <siva.mullati@intel.com>
>---
> drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 200 +++++++++++++---------
> drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h | 9 +-
> 2 files changed, 127 insertions(+), 82 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
>index f01325cd1b62..1c21ced44106 100644
>--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
>+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
>@@ -44,6 +44,11 @@ static inline struct drm_device *ct_to_drm(struct intel_guc_ct *ct)
> #define CT_PROBE_ERROR(_ct, _fmt, ...) \
> i915_probe_error(ct_to_i915(ct), "CT: " _fmt, ##__VA_ARGS__)
>
>+#define ct_desc_read(desc_map_, field_) \
>+ iosys_map_rd_field(desc_map_, 0, struct guc_ct_buffer_desc, field_)
>+#define ct_desc_write(desc_map_, field_, val_) \
>+ iosys_map_wr_field(desc_map_, 0, struct guc_ct_buffer_desc, field_, val_)
>+
> /**
> * DOC: CTB Blob
> *
>@@ -76,6 +81,11 @@ static inline struct drm_device *ct_to_drm(struct intel_guc_ct *ct)
> #define CTB_G2H_BUFFER_SIZE (4 * CTB_H2G_BUFFER_SIZE)
> #define G2H_ROOM_BUFFER_SIZE (CTB_G2H_BUFFER_SIZE / 4)
>
>+#define CTB_SEND_DESC_OFFSET (0X0000)
0, or even better... 0u, so you don't have to cast to unsigned in other
places
>+#define CTB_RECV_DESC_OFFSET (CTB_DESC_SIZE)
>+#define CTB_SEND_CMDS_OFFSET (2 * CTB_DESC_SIZE)
>+#define CTB_RECV_CMDS_OFFSET (2 * CTB_DESC_SIZE + CTB_H2G_BUFFER_SIZE)
>+
> struct ct_request {
> struct list_head link;
> u32 fence;
>@@ -113,9 +123,9 @@ void intel_guc_ct_init_early(struct intel_guc_ct *ct)
> init_waitqueue_head(&ct->wq);
> }
>
>-static void guc_ct_buffer_desc_init(struct guc_ct_buffer_desc *desc)
>+static void guc_ct_buffer_desc_init(struct iosys_map *desc)
> {
>- memset(desc, 0, sizeof(*desc));
>+ iosys_map_memset(desc, 0, 0, sizeof(struct guc_ct_buffer_desc));
> }
>
> static void guc_ct_buffer_reset(struct intel_guc_ct_buffer *ctb)
>@@ -128,17 +138,18 @@ static void guc_ct_buffer_reset(struct intel_guc_ct_buffer *ctb)
> space = CIRC_SPACE(ctb->tail, ctb->head, ctb->size) - ctb->resv_space;
> atomic_set(&ctb->space, space);
>
>- guc_ct_buffer_desc_init(ctb->desc);
>+ guc_ct_buffer_desc_init(&ctb->desc_map);
> }
>
> static void guc_ct_buffer_init(struct intel_guc_ct_buffer *ctb,
>- struct guc_ct_buffer_desc *desc,
>- u32 *cmds, u32 size_in_bytes, u32 resv_space)
>+ struct iosys_map *desc,
>+ struct iosys_map *cmds,
>+ u32 size_in_bytes, u32 resv_space)
> {
> GEM_BUG_ON(size_in_bytes % 4);
>
>- ctb->desc = desc;
>- ctb->cmds = cmds;
>+ ctb->desc_map = *desc;
>+ ctb->cmds_map = *cmds;
> ctb->size = size_in_bytes / 4;
> ctb->resv_space = resv_space / 4;
>
>@@ -218,12 +229,13 @@ static int ct_register_buffer(struct intel_guc_ct *ct, bool send,
> int intel_guc_ct_init(struct intel_guc_ct *ct)
> {
> struct intel_guc *guc = ct_to_guc(ct);
>- struct guc_ct_buffer_desc *desc;
>+ struct iosys_map blob_map;
>+ struct iosys_map desc_map;
>+ struct iosys_map cmds_map;
> u32 blob_size;
> u32 cmds_size;
> u32 resv_space;
> void *blob;
>- u32 *cmds;
> int err;
>
> err = i915_inject_probe_error(guc_to_gt(guc)->i915, -ENXIO);
>@@ -242,27 +254,35 @@ int intel_guc_ct_init(struct intel_guc_ct *ct)
>
> CT_DEBUG(ct, "base=%#x size=%u\n", intel_guc_ggtt_offset(guc, ct->vma), blob_size);
>
>- /* store pointers to desc and cmds for send ctb */
>- desc = blob;
>- cmds = blob + 2 * CTB_DESC_SIZE;
>+ if (i915_gem_object_is_lmem(ct->vma->obj))
>+ iosys_map_set_vaddr_iomem(&blob_map,
>+ (void __iomem *)blob);
>+ else
>+ iosys_map_set_vaddr(&blob_map, blob);
>+
>+ /* store sysmap to desc_map and cmds_map for send ctb */
>+ desc_map = IOSYS_MAP_INIT_OFFSET(&blob_map, CTB_SEND_DESC_OFFSET);
>+ cmds_map = IOSYS_MAP_INIT_OFFSET(&blob_map, CTB_SEND_CMDS_OFFSET);
> cmds_size = CTB_H2G_BUFFER_SIZE;
> resv_space = 0;
>- CT_DEBUG(ct, "%s desc %#tx cmds %#tx size %u/%u\n", "send",
>- ptrdiff(desc, blob), ptrdiff(cmds, blob), cmds_size,
>- resv_space);
>+ CT_DEBUG(ct, "%s desc %#x cmds %#x size %u/%u\n", "send",
>+ (u32)CTB_SEND_DESC_OFFSET, (u32)CTB_SEND_CMDS_OFFSET,
>+ cmds_size, resv_space);
>
>- guc_ct_buffer_init(&ct->ctbs.send, desc, cmds, cmds_size, resv_space);
>+ guc_ct_buffer_init(&ct->ctbs.send,
>+ &desc_map, &cmds_map, cmds_size, resv_space);
>
>- /* store pointers to desc and cmds for recv ctb */
>- desc = blob + CTB_DESC_SIZE;
>- cmds = blob + 2 * CTB_DESC_SIZE + CTB_H2G_BUFFER_SIZE;
>+ /* store sysmap to desc_map and cmds_map for recv ctb */
>+ desc_map = IOSYS_MAP_INIT_OFFSET(&blob_map, CTB_RECV_DESC_OFFSET);
>+ cmds_map = IOSYS_MAP_INIT_OFFSET(&blob_map, CTB_RECV_CMDS_OFFSET);
> cmds_size = CTB_G2H_BUFFER_SIZE;
> resv_space = G2H_ROOM_BUFFER_SIZE;
>- CT_DEBUG(ct, "%s desc %#tx cmds %#tx size %u/%u\n", "recv",
>- ptrdiff(desc, blob), ptrdiff(cmds, blob), cmds_size,
>- resv_space);
>+ CT_DEBUG(ct, "%s desc %#x cmds %#x size %u/%u\n", "recv",
>+ (u32)CTB_RECV_DESC_OFFSET, (u32)CTB_RECV_CMDS_OFFSET,
>+ cmds_size, resv_space);
>
>- guc_ct_buffer_init(&ct->ctbs.recv, desc, cmds, cmds_size, resv_space);
>+ guc_ct_buffer_init(&ct->ctbs.recv,
>+ &desc_map, &cmds_map, cmds_size, resv_space);
>
> return 0;
> }
>@@ -279,6 +299,10 @@ void intel_guc_ct_fini(struct intel_guc_ct *ct)
>
> tasklet_kill(&ct->receive_tasklet);
> i915_vma_unpin_and_release(&ct->vma, I915_VMA_RELEASE_MAP);
>+ iosys_map_clear(&ct->ctbs.send.desc_map);
>+ iosys_map_clear(&ct->ctbs.send.cmds_map);
>+ iosys_map_clear(&ct->ctbs.recv.desc_map);
>+ iosys_map_clear(&ct->ctbs.recv.cmds_map);
> memset(ct, 0, sizeof(*ct));
> }
>
>@@ -291,8 +315,8 @@ void intel_guc_ct_fini(struct intel_guc_ct *ct)
> int intel_guc_ct_enable(struct intel_guc_ct *ct)
> {
> struct intel_guc *guc = ct_to_guc(ct);
>+ struct iosys_map blob_map;
> u32 base, desc, cmds, size;
>- void *blob;
> int err;
>
> GEM_BUG_ON(ct->enabled);
>@@ -302,9 +326,14 @@ int intel_guc_ct_enable(struct intel_guc_ct *ct)
> GEM_BUG_ON(!i915_gem_object_has_pinned_pages(ct->vma->obj));
> base = intel_guc_ggtt_offset(guc, ct->vma);
>
>+ if (i915_gem_object_is_lmem(ct->vma->obj))
>+ iosys_map_set_vaddr_iomem(&blob_map, (void __iomem *)
>+ __px_vaddr(ct->vma->obj));
>+ else
>+ iosys_map_set_vaddr(&blob_map, __px_vaddr(ct->vma->obj));
>+
> /* blob should start with send descriptor */
>- blob = __px_vaddr(ct->vma->obj);
>- GEM_BUG_ON(blob != ct->ctbs.send.desc);
>+ GEM_BUG_ON(!iosys_map_is_equal(&blob_map, &ct->ctbs.send.desc_map));
>
> /* (re)initialize descriptors */
> guc_ct_buffer_reset(&ct->ctbs.send);
>@@ -314,15 +343,15 @@ int intel_guc_ct_enable(struct intel_guc_ct *ct)
> * Register both CT buffers starting with RECV buffer.
> * Descriptors are in first half of the blob.
> */
>- desc = base + ptrdiff(ct->ctbs.recv.desc, blob);
>- cmds = base + ptrdiff(ct->ctbs.recv.cmds, blob);
>+ desc = base + CTB_RECV_DESC_OFFSET;
>+ cmds = base + CTB_RECV_CMDS_OFFSET;
> size = ct->ctbs.recv.size * 4;
> err = ct_register_buffer(ct, false, desc, cmds, size);
> if (unlikely(err))
> goto err_out;
>
>- desc = base + ptrdiff(ct->ctbs.send.desc, blob);
>- cmds = base + ptrdiff(ct->ctbs.send.cmds, blob);
>+ desc = base + CTB_SEND_DESC_OFFSET;
>+ cmds = base + CTB_SEND_CMDS_OFFSET;
> size = ct->ctbs.send.size * 4;
> err = ct_register_buffer(ct, true, desc, cmds, size);
> if (unlikely(err))
>@@ -371,31 +400,33 @@ static int ct_write(struct intel_guc_ct *ct,
> u32 fence, u32 flags)
> {
> struct intel_guc_ct_buffer *ctb = &ct->ctbs.send;
>- struct guc_ct_buffer_desc *desc = ctb->desc;
> u32 tail = ctb->tail;
> u32 size = ctb->size;
> u32 header;
> u32 hxg;
> u32 type;
>- u32 *cmds = ctb->cmds;
>+ u32 status = ct_desc_read(&ctb->desc_map, status);
> unsigned int i;
>
>- if (unlikely(desc->status))
>+ if (unlikely(status))
> goto corrupted;
>
> GEM_BUG_ON(tail > size);
>
> #ifdef CONFIG_DRM_I915_DEBUG_GUC
>- if (unlikely(tail != READ_ONCE(desc->tail))) {
>+ if (unlikely(tail != ct_desc_read(&ctb->desc_map, tail))) {
> CT_ERROR(ct, "Tail was modified %u != %u\n",
>- desc->tail, tail);
>- desc->status |= GUC_CTB_STATUS_MISMATCH;
>+ ct_desc_read(&ctb->desc_map, tail), tail);
>+ status |= GUC_CTB_STATUS_MISMATCH;
>+ ct_desc_write(&ctb->desc_map, status, status);
> goto corrupted;
> }
>- if (unlikely(READ_ONCE(desc->head) >= size)) {
>+ if (unlikely(ct_desc_read(&ctb->desc_map, head) >= size)) {
> CT_ERROR(ct, "Invalid head offset %u >= %u)\n",
>- desc->head, size);
>- desc->status |= GUC_CTB_STATUS_OVERFLOW;
>+ ct_desc_read(&ctb->desc_map, head), size);
>+ status = ct_desc_read(&ctb->desc_map, status) |
>+ GUC_CTB_STATUS_OVERFLOW;
>+ ct_desc_write(&ctb->desc_map, status, status);
> goto corrupted;
> }
> #endif
>@@ -418,14 +449,14 @@ static int ct_write(struct intel_guc_ct *ct,
> CT_DEBUG(ct, "writing (tail %u) %*ph %*ph %*ph\n",
> tail, 4, &header, 4, &hxg, 4 * (len - 1), &action[1]);
>
>- cmds[tail] = header;
>+ iosys_map_wr(&ctb->cmds_map, (4 * tail), u32, header);
excess parenthesis -------------^
> tail = (tail + 1) % size;
>
>- cmds[tail] = hxg;
>+ iosys_map_wr(&ctb->cmds_map, (4 * tail), u32, hxg);
and in other places like here
> tail = (tail + 1) % size;
>
> for (i = 1; i < len; i++) {
>- cmds[tail] = action[i];
>+ iosys_map_wr(&ctb->cmds_map, (4 * tail), u32, action[i]);
> tail = (tail + 1) % size;
> }
> GEM_BUG_ON(tail > size);
>@@ -442,13 +473,14 @@ static int ct_write(struct intel_guc_ct *ct,
> atomic_sub(len + GUC_CTB_HDR_LEN, &ctb->space);
>
> /* now update descriptor */
>- WRITE_ONCE(desc->tail, tail);
>+ ct_desc_write(&ctb->desc_map, tail, tail);
too bad we will lose the _ONCE annotations. Eventually we may
want to remove the memcpy[_fromio()] function call, but then we will
need to pay attention to these. Not something to do here though, just
thinking out loud.
... lots of changes in a single patch, but apparently it's ok.
with above changes
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
thanks
Lucas De Marchi
>
> return 0;
>
> corrupted:
> CT_ERROR(ct, "Corrupted descriptor head=%u tail=%u status=%#x\n",
>- desc->head, desc->tail, desc->status);
>+ ct_desc_read(&ctb->desc_map, head), ct_desc_read(&ctb->desc_map, tail),
>+ ct_desc_read(&ctb->desc_map, status));
> ctb->broken = true;
> return -EPIPE;
> }
>@@ -499,20 +531,22 @@ static inline bool ct_deadlocked(struct intel_guc_ct *ct)
> bool ret = ktime_ms_delta(ktime_get(), ct->stall_time) > timeout;
>
> if (unlikely(ret)) {
>- struct guc_ct_buffer_desc *send = ct->ctbs.send.desc;
>- struct guc_ct_buffer_desc *recv = ct->ctbs.send.desc;
>-
> CT_ERROR(ct, "Communication stalled for %lld ms, desc status=%#x,%#x\n",
> ktime_ms_delta(ktime_get(), ct->stall_time),
>- send->status, recv->status);
>+ ct_desc_read(&ct->ctbs.send.desc_map, status),
>+ ct_desc_read(&ct->ctbs.recv.desc_map, status));
> CT_ERROR(ct, "H2G Space: %u (Bytes)\n",
> atomic_read(&ct->ctbs.send.space) * 4);
>- CT_ERROR(ct, "Head: %u (Dwords)\n", ct->ctbs.send.desc->head);
>- CT_ERROR(ct, "Tail: %u (Dwords)\n", ct->ctbs.send.desc->tail);
>+ CT_ERROR(ct, "Head: %u (Dwords)\n",
>+ ct_desc_read(&ct->ctbs.send.desc_map, head));
>+ CT_ERROR(ct, "Tail: %u (Dwords)\n",
>+ ct_desc_read(&ct->ctbs.send.desc_map, tail));
> CT_ERROR(ct, "G2H Space: %u (Bytes)\n",
> atomic_read(&ct->ctbs.recv.space) * 4);
>- CT_ERROR(ct, "Head: %u\n (Dwords)", ct->ctbs.recv.desc->head);
>- CT_ERROR(ct, "Tail: %u\n (Dwords)", ct->ctbs.recv.desc->tail);
>+ CT_ERROR(ct, "Head: %u\n (Dwords)",
>+ ct_desc_read(&ct->ctbs.recv.desc_map, head));
>+ CT_ERROR(ct, "Tail: %u\n (Dwords)",
>+ ct_desc_read(&ct->ctbs.recv.desc_map, tail));
>
> ct->ctbs.send.broken = true;
> }
>@@ -549,18 +583,19 @@ static inline void g2h_release_space(struct intel_guc_ct *ct, u32 g2h_len_dw)
> static inline bool h2g_has_room(struct intel_guc_ct *ct, u32 len_dw)
> {
> struct intel_guc_ct_buffer *ctb = &ct->ctbs.send;
>- struct guc_ct_buffer_desc *desc = ctb->desc;
> u32 head;
> u32 space;
>+ u32 status = ct_desc_read(&ctb->desc_map, status);
>
> if (atomic_read(&ctb->space) >= len_dw)
> return true;
>
>- head = READ_ONCE(desc->head);
>+ head = ct_desc_read(&ctb->desc_map, head);
> if (unlikely(head > ctb->size)) {
> CT_ERROR(ct, "Invalid head offset %u >= %u)\n",
> head, ctb->size);
>- desc->status |= GUC_CTB_STATUS_OVERFLOW;
>+ status |= GUC_CTB_STATUS_OVERFLOW;
>+ ct_desc_write(&ctb->desc_map, status, status);
> ctb->broken = true;
> return false;
> }
>@@ -803,11 +838,10 @@ static void ct_free_msg(struct ct_incoming_msg *msg)
> static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg)
> {
> struct intel_guc_ct_buffer *ctb = &ct->ctbs.recv;
>- struct guc_ct_buffer_desc *desc = ctb->desc;
> u32 head = ctb->head;
>- u32 tail = READ_ONCE(desc->tail);
>+ u32 tail = ct_desc_read(&ctb->desc_map, tail);
> u32 size = ctb->size;
>- u32 *cmds = ctb->cmds;
>+ u32 status = ct_desc_read(&ctb->desc_map, status);
> s32 available;
> unsigned int len;
> unsigned int i;
>@@ -816,23 +850,26 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg)
> if (unlikely(ctb->broken))
> return -EPIPE;
>
>- if (unlikely(desc->status))
>+ if (unlikely(status))
> goto corrupted;
>
> GEM_BUG_ON(head > size);
>
> #ifdef CONFIG_DRM_I915_DEBUG_GUC
>- if (unlikely(head != READ_ONCE(desc->head))) {
>+ if (unlikely(head != ct_desc_read(&ctb->desc_map, head))) {
> CT_ERROR(ct, "Head was modified %u != %u\n",
>- desc->head, head);
>- desc->status |= GUC_CTB_STATUS_MISMATCH;
>+ ct_desc_read(&ctb->desc_map, head), head);
>+ status |= GUC_CTB_STATUS_MISMATCH;
>+ ct_desc_write(&ctb->desc_map, status, status);
> goto corrupted;
> }
> #endif
> if (unlikely(tail >= size)) {
> CT_ERROR(ct, "Invalid tail offset %u >= %u)\n",
> tail, size);
>- desc->status |= GUC_CTB_STATUS_OVERFLOW;
>+ status = ct_desc_read(&ctb->desc_map, status) |
>+ GUC_CTB_STATUS_OVERFLOW;
>+ ct_desc_write(&ctb->desc_map, status, status);
> goto corrupted;
> }
>
>@@ -849,7 +886,7 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg)
> CT_DEBUG(ct, "available %d (%u:%u:%u)\n", available, head, tail, size);
> GEM_BUG_ON(available < 0);
>
>- header = cmds[head];
>+ header = iosys_map_rd(&ctb->cmds_map, (4 * head), u32);
> head = (head + 1) % size;
>
> /* message len with header */
>@@ -857,11 +894,15 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg)
> if (unlikely(len > (u32)available)) {
> CT_ERROR(ct, "Incomplete message %*ph %*ph %*ph\n",
> 4, &header,
>+ 4 * (head + available - 1 > size ? size - head :
>+ available - 1), ((__px_vaddr(ct->vma->obj) +
>+ CTB_RECV_CMDS_OFFSET) + (4 * head)),
> 4 * (head + available - 1 > size ?
>- size - head : available - 1), &cmds[head],
>- 4 * (head + available - 1 > size ?
>- available - 1 - size + head : 0), &cmds[0]);
>- desc->status |= GUC_CTB_STATUS_UNDERFLOW;
>+ available - 1 - size + head : 0),
>+ (__px_vaddr(ct->vma->obj) + CTB_RECV_CMDS_OFFSET));
>+ status = ct_desc_read(&ctb->desc_map, status) |
>+ GUC_CTB_STATUS_UNDERFLOW;
>+ ct_desc_write(&ctb->desc_map, status, status);
> goto corrupted;
> }
>
>@@ -869,17 +910,18 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg)
> if (!*msg) {
> CT_ERROR(ct, "No memory for message %*ph %*ph %*ph\n",
> 4, &header,
>+ 4 * (head + available - 1 > size ? size - head :
>+ available - 1), (ctb->cmds_map.vaddr + (4 * head)),
> 4 * (head + available - 1 > size ?
>- size - head : available - 1), &cmds[head],
>- 4 * (head + available - 1 > size ?
>- available - 1 - size + head : 0), &cmds[0]);
>+ available - 1 - size + head : 0), ctb->cmds_map.vaddr);
> return available;
> }
>
> (*msg)->msg[0] = header;
>
> for (i = 1; i < len; i++) {
>- (*msg)->msg[i] = cmds[head];
>+ (*msg)->msg[i] = iosys_map_rd(&ctb->cmds_map,
>+ (4 * head), u32);
> head = (head + 1) % size;
> }
> CT_DEBUG(ct, "received %*ph\n", 4 * len, (*msg)->msg);
>@@ -888,13 +930,15 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg)
> ctb->head = head;
>
> /* now update descriptor */
>- WRITE_ONCE(desc->head, head);
>+ ct_desc_write(&ctb->desc_map, head, head);
>
> return available - len;
>
> corrupted:
> CT_ERROR(ct, "Corrupted descriptor head=%u tail=%u status=%#x\n",
>- desc->head, desc->tail, desc->status);
>+ ct_desc_read(&ctb->desc_map, head),
>+ ct_desc_read(&ctb->desc_map, tail),
>+ ct_desc_read(&ctb->desc_map, status));
> ctb->broken = true;
> return -EPIPE;
> }
>@@ -1211,13 +1255,13 @@ void intel_guc_ct_print_info(struct intel_guc_ct *ct,
> drm_printf(p, "H2G Space: %u\n",
> atomic_read(&ct->ctbs.send.space) * 4);
> drm_printf(p, "Head: %u\n",
>- ct->ctbs.send.desc->head);
>+ ct_desc_read(&ct->ctbs.send.desc_map, head));
> drm_printf(p, "Tail: %u\n",
>- ct->ctbs.send.desc->tail);
>+ ct_desc_read(&ct->ctbs.send.desc_map, tail));
> drm_printf(p, "G2H Space: %u\n",
> atomic_read(&ct->ctbs.recv.space) * 4);
> drm_printf(p, "Head: %u\n",
>- ct->ctbs.recv.desc->head);
>+ ct_desc_read(&ct->ctbs.recv.desc_map, head));
> drm_printf(p, "Tail: %u\n",
>- ct->ctbs.recv.desc->tail);
>+ ct_desc_read(&ct->ctbs.recv.desc_map, tail));
> }
>diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h
>index f709a19c7e21..867fe13fb47d 100644
>--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h
>+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h
>@@ -7,6 +7,7 @@
> #define _INTEL_GUC_CT_H_
>
> #include <linux/interrupt.h>
>+#include <linux/iosys-map.h>
> #include <linux/spinlock.h>
> #include <linux/workqueue.h>
> #include <linux/ktime.h>
>@@ -32,8 +33,8 @@ struct drm_printer;
> * holds the commands.
> *
> * @lock: protects access to the commands buffer and buffer descriptor
>- * @desc: pointer to the buffer descriptor
>- * @cmds: pointer to the commands buffer
>+ * @desc: iosys map to the buffer descriptor
>+ * @cmds: iosys map to the commands buffer
> * @size: size of the commands buffer in dwords
> * @resv_space: reserved space in buffer in dwords
> * @head: local shadow copy of head in dwords
>@@ -43,8 +44,8 @@ struct drm_printer;
> */
> struct intel_guc_ct_buffer {
> spinlock_t lock;
>- struct guc_ct_buffer_desc *desc;
>- u32 *cmds;
>+ struct iosys_map desc_map;
>+ struct iosys_map cmds_map;
> u32 size;
> u32 resv_space;
> u32 tail;
>--
>2.33.0
>
^ permalink raw reply [flat|nested] 14+ messages in thread
* [Intel-gfx] [PATCH 1/1] drm/i915/guc: Convert ct buffer to iosys_map
2022-04-04 9:31 [Intel-gfx] [PATCH 0/1] drm/i915/guc: Refactor CT access to use iosys_map Mullati Siva
@ 2022-04-04 9:31 ` Mullati Siva
2022-04-14 12:11 ` Balasubramani Vivekanandan
2022-04-18 9:08 ` Balasubramani Vivekanandan
0 siblings, 2 replies; 14+ messages in thread
From: Mullati Siva @ 2022-04-04 9:31 UTC (permalink / raw)
To: intel-gfx, siva.mullati; +Cc: lucas.demarchi
From: Siva Mullati <siva.mullati@intel.com>
Convert CT commands and descriptors to use iosys_map rather
than plain pointer and save it in the intel_guc_ct_buffer struct.
This will help with ct_write and ct_read for cmd send and receive
after the initialization by abstracting the IO vs system memory.
Signed-off-by: Siva Mullati <siva.mullati@intel.com>
---
drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 200 +++++++++++++---------
drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h | 9 +-
2 files changed, 127 insertions(+), 82 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
index f01325cd1b62..64568dc90b05 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
@@ -44,6 +44,11 @@ static inline struct drm_device *ct_to_drm(struct intel_guc_ct *ct)
#define CT_PROBE_ERROR(_ct, _fmt, ...) \
i915_probe_error(ct_to_i915(ct), "CT: " _fmt, ##__VA_ARGS__)
+#define ct_desc_read(desc_map_, field_) \
+ iosys_map_rd_field(desc_map_, 0, struct guc_ct_buffer_desc, field_)
+#define ct_desc_write(desc_map_, field_, val_) \
+ iosys_map_wr_field(desc_map_, 0, struct guc_ct_buffer_desc, field_, val_)
+
/**
* DOC: CTB Blob
*
@@ -76,6 +81,11 @@ static inline struct drm_device *ct_to_drm(struct intel_guc_ct *ct)
#define CTB_G2H_BUFFER_SIZE (4 * CTB_H2G_BUFFER_SIZE)
#define G2H_ROOM_BUFFER_SIZE (CTB_G2H_BUFFER_SIZE / 4)
+#define CTB_SEND_DESC_OFFSET 0u
+#define CTB_RECV_DESC_OFFSET (CTB_DESC_SIZE)
+#define CTB_SEND_CMDS_OFFSET (2 * CTB_DESC_SIZE)
+#define CTB_RECV_CMDS_OFFSET (2 * CTB_DESC_SIZE + CTB_H2G_BUFFER_SIZE)
+
struct ct_request {
struct list_head link;
u32 fence;
@@ -113,9 +123,9 @@ void intel_guc_ct_init_early(struct intel_guc_ct *ct)
init_waitqueue_head(&ct->wq);
}
-static void guc_ct_buffer_desc_init(struct guc_ct_buffer_desc *desc)
+static void guc_ct_buffer_desc_init(struct iosys_map *desc)
{
- memset(desc, 0, sizeof(*desc));
+ iosys_map_memset(desc, 0, 0, sizeof(struct guc_ct_buffer_desc));
}
static void guc_ct_buffer_reset(struct intel_guc_ct_buffer *ctb)
@@ -128,17 +138,18 @@ static void guc_ct_buffer_reset(struct intel_guc_ct_buffer *ctb)
space = CIRC_SPACE(ctb->tail, ctb->head, ctb->size) - ctb->resv_space;
atomic_set(&ctb->space, space);
- guc_ct_buffer_desc_init(ctb->desc);
+ guc_ct_buffer_desc_init(&ctb->desc_map);
}
static void guc_ct_buffer_init(struct intel_guc_ct_buffer *ctb,
- struct guc_ct_buffer_desc *desc,
- u32 *cmds, u32 size_in_bytes, u32 resv_space)
+ struct iosys_map *desc,
+ struct iosys_map *cmds,
+ u32 size_in_bytes, u32 resv_space)
{
GEM_BUG_ON(size_in_bytes % 4);
- ctb->desc = desc;
- ctb->cmds = cmds;
+ ctb->desc_map = *desc;
+ ctb->cmds_map = *cmds;
ctb->size = size_in_bytes / 4;
ctb->resv_space = resv_space / 4;
@@ -218,12 +229,13 @@ static int ct_register_buffer(struct intel_guc_ct *ct, bool send,
int intel_guc_ct_init(struct intel_guc_ct *ct)
{
struct intel_guc *guc = ct_to_guc(ct);
- struct guc_ct_buffer_desc *desc;
+ struct iosys_map blob_map;
+ struct iosys_map desc_map;
+ struct iosys_map cmds_map;
u32 blob_size;
u32 cmds_size;
u32 resv_space;
void *blob;
- u32 *cmds;
int err;
err = i915_inject_probe_error(guc_to_gt(guc)->i915, -ENXIO);
@@ -242,27 +254,35 @@ int intel_guc_ct_init(struct intel_guc_ct *ct)
CT_DEBUG(ct, "base=%#x size=%u\n", intel_guc_ggtt_offset(guc, ct->vma), blob_size);
- /* store pointers to desc and cmds for send ctb */
- desc = blob;
- cmds = blob + 2 * CTB_DESC_SIZE;
+ if (i915_gem_object_is_lmem(ct->vma->obj))
+ iosys_map_set_vaddr_iomem(&blob_map,
+ (void __iomem *)blob);
+ else
+ iosys_map_set_vaddr(&blob_map, blob);
+
+ /* store sysmap to desc_map and cmds_map for send ctb */
+ desc_map = IOSYS_MAP_INIT_OFFSET(&blob_map, CTB_SEND_DESC_OFFSET);
+ cmds_map = IOSYS_MAP_INIT_OFFSET(&blob_map, CTB_SEND_CMDS_OFFSET);
cmds_size = CTB_H2G_BUFFER_SIZE;
resv_space = 0;
- CT_DEBUG(ct, "%s desc %#tx cmds %#tx size %u/%u\n", "send",
- ptrdiff(desc, blob), ptrdiff(cmds, blob), cmds_size,
- resv_space);
+ CT_DEBUG(ct, "%s desc %#x cmds %#x size %u/%u\n", "send",
+ CTB_SEND_DESC_OFFSET, (u32)CTB_SEND_CMDS_OFFSET,
+ cmds_size, resv_space);
- guc_ct_buffer_init(&ct->ctbs.send, desc, cmds, cmds_size, resv_space);
+ guc_ct_buffer_init(&ct->ctbs.send,
+ &desc_map, &cmds_map, cmds_size, resv_space);
- /* store pointers to desc and cmds for recv ctb */
- desc = blob + CTB_DESC_SIZE;
- cmds = blob + 2 * CTB_DESC_SIZE + CTB_H2G_BUFFER_SIZE;
+ /* store sysmap to desc_map and cmds_map for recv ctb */
+ desc_map = IOSYS_MAP_INIT_OFFSET(&blob_map, CTB_RECV_DESC_OFFSET);
+ cmds_map = IOSYS_MAP_INIT_OFFSET(&blob_map, CTB_RECV_CMDS_OFFSET);
cmds_size = CTB_G2H_BUFFER_SIZE;
resv_space = G2H_ROOM_BUFFER_SIZE;
- CT_DEBUG(ct, "%s desc %#tx cmds %#tx size %u/%u\n", "recv",
- ptrdiff(desc, blob), ptrdiff(cmds, blob), cmds_size,
- resv_space);
+ CT_DEBUG(ct, "%s desc %#x cmds %#x size %u/%u\n", "recv",
+ (u32)CTB_RECV_DESC_OFFSET, (u32)CTB_RECV_CMDS_OFFSET,
+ cmds_size, resv_space);
- guc_ct_buffer_init(&ct->ctbs.recv, desc, cmds, cmds_size, resv_space);
+ guc_ct_buffer_init(&ct->ctbs.recv,
+ &desc_map, &cmds_map, cmds_size, resv_space);
return 0;
}
@@ -279,6 +299,10 @@ void intel_guc_ct_fini(struct intel_guc_ct *ct)
tasklet_kill(&ct->receive_tasklet);
i915_vma_unpin_and_release(&ct->vma, I915_VMA_RELEASE_MAP);
+ iosys_map_clear(&ct->ctbs.send.desc_map);
+ iosys_map_clear(&ct->ctbs.send.cmds_map);
+ iosys_map_clear(&ct->ctbs.recv.desc_map);
+ iosys_map_clear(&ct->ctbs.recv.cmds_map);
memset(ct, 0, sizeof(*ct));
}
@@ -291,8 +315,8 @@ void intel_guc_ct_fini(struct intel_guc_ct *ct)
int intel_guc_ct_enable(struct intel_guc_ct *ct)
{
struct intel_guc *guc = ct_to_guc(ct);
+ struct iosys_map blob_map;
u32 base, desc, cmds, size;
- void *blob;
int err;
GEM_BUG_ON(ct->enabled);
@@ -302,9 +326,14 @@ int intel_guc_ct_enable(struct intel_guc_ct *ct)
GEM_BUG_ON(!i915_gem_object_has_pinned_pages(ct->vma->obj));
base = intel_guc_ggtt_offset(guc, ct->vma);
+ if (i915_gem_object_is_lmem(ct->vma->obj))
+ iosys_map_set_vaddr_iomem(&blob_map, (void __iomem *)
+ __px_vaddr(ct->vma->obj));
+ else
+ iosys_map_set_vaddr(&blob_map, __px_vaddr(ct->vma->obj));
+
/* blob should start with send descriptor */
- blob = __px_vaddr(ct->vma->obj);
- GEM_BUG_ON(blob != ct->ctbs.send.desc);
+ GEM_BUG_ON(!iosys_map_is_equal(&blob_map, &ct->ctbs.send.desc_map));
/* (re)initialize descriptors */
guc_ct_buffer_reset(&ct->ctbs.send);
@@ -314,15 +343,15 @@ int intel_guc_ct_enable(struct intel_guc_ct *ct)
* Register both CT buffers starting with RECV buffer.
* Descriptors are in first half of the blob.
*/
- desc = base + ptrdiff(ct->ctbs.recv.desc, blob);
- cmds = base + ptrdiff(ct->ctbs.recv.cmds, blob);
+ desc = base + CTB_RECV_DESC_OFFSET;
+ cmds = base + CTB_RECV_CMDS_OFFSET;
size = ct->ctbs.recv.size * 4;
err = ct_register_buffer(ct, false, desc, cmds, size);
if (unlikely(err))
goto err_out;
- desc = base + ptrdiff(ct->ctbs.send.desc, blob);
- cmds = base + ptrdiff(ct->ctbs.send.cmds, blob);
+ desc = base + CTB_SEND_DESC_OFFSET;
+ cmds = base + CTB_SEND_CMDS_OFFSET;
size = ct->ctbs.send.size * 4;
err = ct_register_buffer(ct, true, desc, cmds, size);
if (unlikely(err))
@@ -371,31 +400,33 @@ static int ct_write(struct intel_guc_ct *ct,
u32 fence, u32 flags)
{
struct intel_guc_ct_buffer *ctb = &ct->ctbs.send;
- struct guc_ct_buffer_desc *desc = ctb->desc;
u32 tail = ctb->tail;
u32 size = ctb->size;
u32 header;
u32 hxg;
u32 type;
- u32 *cmds = ctb->cmds;
+ u32 status = ct_desc_read(&ctb->desc_map, status);
unsigned int i;
- if (unlikely(desc->status))
+ if (unlikely(status))
goto corrupted;
GEM_BUG_ON(tail > size);
#ifdef CONFIG_DRM_I915_DEBUG_GUC
- if (unlikely(tail != READ_ONCE(desc->tail))) {
+ if (unlikely(tail != ct_desc_read(&ctb->desc_map, tail))) {
CT_ERROR(ct, "Tail was modified %u != %u\n",
- desc->tail, tail);
- desc->status |= GUC_CTB_STATUS_MISMATCH;
+ ct_desc_read(&ctb->desc_map, tail), tail);
+ status |= GUC_CTB_STATUS_MISMATCH;
+ ct_desc_write(&ctb->desc_map, status, status);
goto corrupted;
}
- if (unlikely(READ_ONCE(desc->head) >= size)) {
+ if (unlikely(ct_desc_read(&ctb->desc_map, head) >= size)) {
CT_ERROR(ct, "Invalid head offset %u >= %u)\n",
- desc->head, size);
- desc->status |= GUC_CTB_STATUS_OVERFLOW;
+ ct_desc_read(&ctb->desc_map, head), size);
+ status = ct_desc_read(&ctb->desc_map, status) |
+ GUC_CTB_STATUS_OVERFLOW;
+ ct_desc_write(&ctb->desc_map, status, status);
goto corrupted;
}
#endif
@@ -418,14 +449,14 @@ static int ct_write(struct intel_guc_ct *ct,
CT_DEBUG(ct, "writing (tail %u) %*ph %*ph %*ph\n",
tail, 4, &header, 4, &hxg, 4 * (len - 1), &action[1]);
- cmds[tail] = header;
+ iosys_map_wr(&ctb->cmds_map, 4 * tail, u32, header);
tail = (tail + 1) % size;
- cmds[tail] = hxg;
+ iosys_map_wr(&ctb->cmds_map, 4 * tail, u32, hxg);
tail = (tail + 1) % size;
for (i = 1; i < len; i++) {
- cmds[tail] = action[i];
+ iosys_map_wr(&ctb->cmds_map, 4 * tail, u32, action[i]);
tail = (tail + 1) % size;
}
GEM_BUG_ON(tail > size);
@@ -442,13 +473,14 @@ static int ct_write(struct intel_guc_ct *ct,
atomic_sub(len + GUC_CTB_HDR_LEN, &ctb->space);
/* now update descriptor */
- WRITE_ONCE(desc->tail, tail);
+ ct_desc_write(&ctb->desc_map, tail, tail);
return 0;
corrupted:
CT_ERROR(ct, "Corrupted descriptor head=%u tail=%u status=%#x\n",
- desc->head, desc->tail, desc->status);
+ ct_desc_read(&ctb->desc_map, head), ct_desc_read(&ctb->desc_map, tail),
+ ct_desc_read(&ctb->desc_map, status));
ctb->broken = true;
return -EPIPE;
}
@@ -499,20 +531,22 @@ static inline bool ct_deadlocked(struct intel_guc_ct *ct)
bool ret = ktime_ms_delta(ktime_get(), ct->stall_time) > timeout;
if (unlikely(ret)) {
- struct guc_ct_buffer_desc *send = ct->ctbs.send.desc;
- struct guc_ct_buffer_desc *recv = ct->ctbs.send.desc;
-
CT_ERROR(ct, "Communication stalled for %lld ms, desc status=%#x,%#x\n",
ktime_ms_delta(ktime_get(), ct->stall_time),
- send->status, recv->status);
+ ct_desc_read(&ct->ctbs.send.desc_map, status),
+ ct_desc_read(&ct->ctbs.recv.desc_map, status));
CT_ERROR(ct, "H2G Space: %u (Bytes)\n",
atomic_read(&ct->ctbs.send.space) * 4);
- CT_ERROR(ct, "Head: %u (Dwords)\n", ct->ctbs.send.desc->head);
- CT_ERROR(ct, "Tail: %u (Dwords)\n", ct->ctbs.send.desc->tail);
+ CT_ERROR(ct, "Head: %u (Dwords)\n",
+ ct_desc_read(&ct->ctbs.send.desc_map, head));
+ CT_ERROR(ct, "Tail: %u (Dwords)\n",
+ ct_desc_read(&ct->ctbs.send.desc_map, tail));
CT_ERROR(ct, "G2H Space: %u (Bytes)\n",
atomic_read(&ct->ctbs.recv.space) * 4);
- CT_ERROR(ct, "Head: %u\n (Dwords)", ct->ctbs.recv.desc->head);
- CT_ERROR(ct, "Tail: %u\n (Dwords)", ct->ctbs.recv.desc->tail);
+ CT_ERROR(ct, "Head: %u\n (Dwords)",
+ ct_desc_read(&ct->ctbs.recv.desc_map, head));
+ CT_ERROR(ct, "Tail: %u\n (Dwords)",
+ ct_desc_read(&ct->ctbs.recv.desc_map, tail));
ct->ctbs.send.broken = true;
}
@@ -549,18 +583,19 @@ static inline void g2h_release_space(struct intel_guc_ct *ct, u32 g2h_len_dw)
static inline bool h2g_has_room(struct intel_guc_ct *ct, u32 len_dw)
{
struct intel_guc_ct_buffer *ctb = &ct->ctbs.send;
- struct guc_ct_buffer_desc *desc = ctb->desc;
u32 head;
u32 space;
+ u32 status = ct_desc_read(&ctb->desc_map, status);
if (atomic_read(&ctb->space) >= len_dw)
return true;
- head = READ_ONCE(desc->head);
+ head = ct_desc_read(&ctb->desc_map, head);
if (unlikely(head > ctb->size)) {
CT_ERROR(ct, "Invalid head offset %u >= %u)\n",
head, ctb->size);
- desc->status |= GUC_CTB_STATUS_OVERFLOW;
+ status |= GUC_CTB_STATUS_OVERFLOW;
+ ct_desc_write(&ctb->desc_map, status, status);
ctb->broken = true;
return false;
}
@@ -803,11 +838,10 @@ static void ct_free_msg(struct ct_incoming_msg *msg)
static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg)
{
struct intel_guc_ct_buffer *ctb = &ct->ctbs.recv;
- struct guc_ct_buffer_desc *desc = ctb->desc;
u32 head = ctb->head;
- u32 tail = READ_ONCE(desc->tail);
+ u32 tail = ct_desc_read(&ctb->desc_map, tail);
u32 size = ctb->size;
- u32 *cmds = ctb->cmds;
+ u32 status = ct_desc_read(&ctb->desc_map, status);
s32 available;
unsigned int len;
unsigned int i;
@@ -816,23 +850,26 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg)
if (unlikely(ctb->broken))
return -EPIPE;
- if (unlikely(desc->status))
+ if (unlikely(status))
goto corrupted;
GEM_BUG_ON(head > size);
#ifdef CONFIG_DRM_I915_DEBUG_GUC
- if (unlikely(head != READ_ONCE(desc->head))) {
+ if (unlikely(head != ct_desc_read(&ctb->desc_map, head))) {
CT_ERROR(ct, "Head was modified %u != %u\n",
- desc->head, head);
- desc->status |= GUC_CTB_STATUS_MISMATCH;
+ ct_desc_read(&ctb->desc_map, head), head);
+ status |= GUC_CTB_STATUS_MISMATCH;
+ ct_desc_write(&ctb->desc_map, status, status);
goto corrupted;
}
#endif
if (unlikely(tail >= size)) {
CT_ERROR(ct, "Invalid tail offset %u >= %u)\n",
tail, size);
- desc->status |= GUC_CTB_STATUS_OVERFLOW;
+ status = ct_desc_read(&ctb->desc_map, status) |
+ GUC_CTB_STATUS_OVERFLOW;
+ ct_desc_write(&ctb->desc_map, status, status);
goto corrupted;
}
@@ -849,7 +886,7 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg)
CT_DEBUG(ct, "available %d (%u:%u:%u)\n", available, head, tail, size);
GEM_BUG_ON(available < 0);
- header = cmds[head];
+ header = iosys_map_rd(&ctb->cmds_map, (4 * head), u32);
head = (head + 1) % size;
/* message len with header */
@@ -857,11 +894,15 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg)
if (unlikely(len > (u32)available)) {
CT_ERROR(ct, "Incomplete message %*ph %*ph %*ph\n",
4, &header,
+ 4 * (head + available - 1 > size ? size - head :
+ available - 1), ((__px_vaddr(ct->vma->obj) +
+ CTB_RECV_CMDS_OFFSET) + (4 * head)),
4 * (head + available - 1 > size ?
- size - head : available - 1), &cmds[head],
- 4 * (head + available - 1 > size ?
- available - 1 - size + head : 0), &cmds[0]);
- desc->status |= GUC_CTB_STATUS_UNDERFLOW;
+ available - 1 - size + head : 0),
+ (__px_vaddr(ct->vma->obj) + CTB_RECV_CMDS_OFFSET));
+ status = ct_desc_read(&ctb->desc_map, status) |
+ GUC_CTB_STATUS_UNDERFLOW;
+ ct_desc_write(&ctb->desc_map, status, status);
goto corrupted;
}
@@ -869,17 +910,18 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg)
if (!*msg) {
CT_ERROR(ct, "No memory for message %*ph %*ph %*ph\n",
4, &header,
+ 4 * (head + available - 1 > size ? size - head :
+ available - 1), (ctb->cmds_map.vaddr + (4 * head)),
4 * (head + available - 1 > size ?
- size - head : available - 1), &cmds[head],
- 4 * (head + available - 1 > size ?
- available - 1 - size + head : 0), &cmds[0]);
+ available - 1 - size + head : 0), ctb->cmds_map.vaddr);
return available;
}
(*msg)->msg[0] = header;
for (i = 1; i < len; i++) {
- (*msg)->msg[i] = cmds[head];
+ (*msg)->msg[i] = iosys_map_rd(&ctb->cmds_map,
+ (4 * head), u32);
head = (head + 1) % size;
}
CT_DEBUG(ct, "received %*ph\n", 4 * len, (*msg)->msg);
@@ -888,13 +930,15 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg)
ctb->head = head;
/* now update descriptor */
- WRITE_ONCE(desc->head, head);
+ ct_desc_write(&ctb->desc_map, head, head);
return available - len;
corrupted:
CT_ERROR(ct, "Corrupted descriptor head=%u tail=%u status=%#x\n",
- desc->head, desc->tail, desc->status);
+ ct_desc_read(&ctb->desc_map, head),
+ ct_desc_read(&ctb->desc_map, tail),
+ ct_desc_read(&ctb->desc_map, status));
ctb->broken = true;
return -EPIPE;
}
@@ -1211,13 +1255,13 @@ void intel_guc_ct_print_info(struct intel_guc_ct *ct,
drm_printf(p, "H2G Space: %u\n",
atomic_read(&ct->ctbs.send.space) * 4);
drm_printf(p, "Head: %u\n",
- ct->ctbs.send.desc->head);
+ ct_desc_read(&ct->ctbs.send.desc_map, head));
drm_printf(p, "Tail: %u\n",
- ct->ctbs.send.desc->tail);
+ ct_desc_read(&ct->ctbs.send.desc_map, tail));
drm_printf(p, "G2H Space: %u\n",
atomic_read(&ct->ctbs.recv.space) * 4);
drm_printf(p, "Head: %u\n",
- ct->ctbs.recv.desc->head);
+ ct_desc_read(&ct->ctbs.recv.desc_map, head));
drm_printf(p, "Tail: %u\n",
- ct->ctbs.recv.desc->tail);
+ ct_desc_read(&ct->ctbs.recv.desc_map, tail));
}
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h
index f709a19c7e21..867fe13fb47d 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h
@@ -7,6 +7,7 @@
#define _INTEL_GUC_CT_H_
#include <linux/interrupt.h>
+#include <linux/iosys-map.h>
#include <linux/spinlock.h>
#include <linux/workqueue.h>
#include <linux/ktime.h>
@@ -32,8 +33,8 @@ struct drm_printer;
* holds the commands.
*
* @lock: protects access to the commands buffer and buffer descriptor
- * @desc: pointer to the buffer descriptor
- * @cmds: pointer to the commands buffer
+ * @desc: iosys map to the buffer descriptor
+ * @cmds: iosys map to the commands buffer
* @size: size of the commands buffer in dwords
* @resv_space: reserved space in buffer in dwords
* @head: local shadow copy of head in dwords
@@ -43,8 +44,8 @@ struct drm_printer;
*/
struct intel_guc_ct_buffer {
spinlock_t lock;
- struct guc_ct_buffer_desc *desc;
- u32 *cmds;
+ struct iosys_map desc_map;
+ struct iosys_map cmds_map;
u32 size;
u32 resv_space;
u32 tail;
--
2.33.0
^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [Intel-gfx] [PATCH 1/1] drm/i915/guc: Convert ct buffer to iosys_map
2022-04-04 9:31 ` [Intel-gfx] [PATCH 1/1] drm/i915/guc: Convert ct buffer to iosys_map Mullati Siva
@ 2022-04-14 12:11 ` Balasubramani Vivekanandan
2022-04-28 14:13 ` Siva Mullati
2022-04-18 9:08 ` Balasubramani Vivekanandan
1 sibling, 1 reply; 14+ messages in thread
From: Balasubramani Vivekanandan @ 2022-04-14 12:11 UTC (permalink / raw)
To: Mullati Siva, intel-gfx; +Cc: lucas.demarchi
On 04.04.2022 15:01, Mullati Siva wrote:
> From: Siva Mullati <siva.mullati@intel.com>
>
> Convert CT commands and descriptors to use iosys_map rather
> than plain pointer and save it in the intel_guc_ct_buffer struct.
> This will help with ct_write and ct_read for cmd send and receive
> after the initialization by abstracting the IO vs system memory.
>
> Signed-off-by: Siva Mullati <siva.mullati@intel.com>
> ---
> drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 200 +++++++++++++---------
> drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h | 9 +-
> 2 files changed, 127 insertions(+), 82 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
> index f01325cd1b62..64568dc90b05 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
> @@ -44,6 +44,11 @@ static inline struct drm_device *ct_to_drm(struct intel_guc_ct *ct)
> #define CT_PROBE_ERROR(_ct, _fmt, ...) \
> i915_probe_error(ct_to_i915(ct), "CT: " _fmt, ##__VA_ARGS__)
>
> +#define ct_desc_read(desc_map_, field_) \
> + iosys_map_rd_field(desc_map_, 0, struct guc_ct_buffer_desc, field_)
> +#define ct_desc_write(desc_map_, field_, val_) \
> + iosys_map_wr_field(desc_map_, 0, struct guc_ct_buffer_desc, field_, val_)
> +
Did you try to make the change Lucas mentioned in his comment on rev0,
to pass `struct guc_ct_buffer_desc *` as first argument to the above
macros? Was it not feasible?
> /**
> * DOC: CTB Blob
> *
> @@ -76,6 +81,11 @@ static inline struct drm_device *ct_to_drm(struct intel_guc_ct *ct)
> #define CTB_G2H_BUFFER_SIZE (4 * CTB_H2G_BUFFER_SIZE)
> #define G2H_ROOM_BUFFER_SIZE (CTB_G2H_BUFFER_SIZE / 4)
>
> +#define CTB_SEND_DESC_OFFSET 0u
> +#define CTB_RECV_DESC_OFFSET (CTB_DESC_SIZE)
> +#define CTB_SEND_CMDS_OFFSET (2 * CTB_DESC_SIZE)
> +#define CTB_RECV_CMDS_OFFSET (2 * CTB_DESC_SIZE + CTB_H2G_BUFFER_SIZE)
> +
> struct ct_request {
> struct list_head link;
> u32 fence;
> @@ -113,9 +123,9 @@ void intel_guc_ct_init_early(struct intel_guc_ct *ct)
> init_waitqueue_head(&ct->wq);
> }
>
> -static void guc_ct_buffer_desc_init(struct guc_ct_buffer_desc *desc)
> +static void guc_ct_buffer_desc_init(struct iosys_map *desc)
> {
> - memset(desc, 0, sizeof(*desc));
> + iosys_map_memset(desc, 0, 0, sizeof(struct guc_ct_buffer_desc));
> }
>
> static void guc_ct_buffer_reset(struct intel_guc_ct_buffer *ctb)
> @@ -128,17 +138,18 @@ static void guc_ct_buffer_reset(struct intel_guc_ct_buffer *ctb)
> space = CIRC_SPACE(ctb->tail, ctb->head, ctb->size) - ctb->resv_space;
> atomic_set(&ctb->space, space);
>
> - guc_ct_buffer_desc_init(ctb->desc);
> + guc_ct_buffer_desc_init(&ctb->desc_map);
> }
>
> static void guc_ct_buffer_init(struct intel_guc_ct_buffer *ctb,
> - struct guc_ct_buffer_desc *desc,
> - u32 *cmds, u32 size_in_bytes, u32 resv_space)
> + struct iosys_map *desc,
> + struct iosys_map *cmds,
> + u32 size_in_bytes, u32 resv_space)
> {
> GEM_BUG_ON(size_in_bytes % 4);
>
> - ctb->desc = desc;
> - ctb->cmds = cmds;
> + ctb->desc_map = *desc;
> + ctb->cmds_map = *cmds;
> ctb->size = size_in_bytes / 4;
> ctb->resv_space = resv_space / 4;
>
> @@ -218,12 +229,13 @@ static int ct_register_buffer(struct intel_guc_ct *ct, bool send,
> int intel_guc_ct_init(struct intel_guc_ct *ct)
> {
> struct intel_guc *guc = ct_to_guc(ct);
> - struct guc_ct_buffer_desc *desc;
> + struct iosys_map blob_map;
> + struct iosys_map desc_map;
> + struct iosys_map cmds_map;
> u32 blob_size;
> u32 cmds_size;
> u32 resv_space;
> void *blob;
> - u32 *cmds;
> int err;
>
> err = i915_inject_probe_error(guc_to_gt(guc)->i915, -ENXIO);
> @@ -242,27 +254,35 @@ int intel_guc_ct_init(struct intel_guc_ct *ct)
>
> CT_DEBUG(ct, "base=%#x size=%u\n", intel_guc_ggtt_offset(guc, ct->vma), blob_size);
>
> - /* store pointers to desc and cmds for send ctb */
> - desc = blob;
> - cmds = blob + 2 * CTB_DESC_SIZE;
> + if (i915_gem_object_is_lmem(ct->vma->obj))
> + iosys_map_set_vaddr_iomem(&blob_map,
> + (void __iomem *)blob);
> + else
> + iosys_map_set_vaddr(&blob_map, blob);
> +
> + /* store sysmap to desc_map and cmds_map for send ctb */
> + desc_map = IOSYS_MAP_INIT_OFFSET(&blob_map, CTB_SEND_DESC_OFFSET);
> + cmds_map = IOSYS_MAP_INIT_OFFSET(&blob_map, CTB_SEND_CMDS_OFFSET);
> cmds_size = CTB_H2G_BUFFER_SIZE;
> resv_space = 0;
> - CT_DEBUG(ct, "%s desc %#tx cmds %#tx size %u/%u\n", "send",
> - ptrdiff(desc, blob), ptrdiff(cmds, blob), cmds_size,
> - resv_space);
> + CT_DEBUG(ct, "%s desc %#x cmds %#x size %u/%u\n", "send",
> + CTB_SEND_DESC_OFFSET, (u32)CTB_SEND_CMDS_OFFSET,
> + cmds_size, resv_space);
>
> - guc_ct_buffer_init(&ct->ctbs.send, desc, cmds, cmds_size, resv_space);
> + guc_ct_buffer_init(&ct->ctbs.send,
> + &desc_map, &cmds_map, cmds_size, resv_space);
>
> - /* store pointers to desc and cmds for recv ctb */
> - desc = blob + CTB_DESC_SIZE;
> - cmds = blob + 2 * CTB_DESC_SIZE + CTB_H2G_BUFFER_SIZE;
> + /* store sysmap to desc_map and cmds_map for recv ctb */
> + desc_map = IOSYS_MAP_INIT_OFFSET(&blob_map, CTB_RECV_DESC_OFFSET);
> + cmds_map = IOSYS_MAP_INIT_OFFSET(&blob_map, CTB_RECV_CMDS_OFFSET);
> cmds_size = CTB_G2H_BUFFER_SIZE;
> resv_space = G2H_ROOM_BUFFER_SIZE;
> - CT_DEBUG(ct, "%s desc %#tx cmds %#tx size %u/%u\n", "recv",
> - ptrdiff(desc, blob), ptrdiff(cmds, blob), cmds_size,
> - resv_space);
> + CT_DEBUG(ct, "%s desc %#x cmds %#x size %u/%u\n", "recv",
> + (u32)CTB_RECV_DESC_OFFSET, (u32)CTB_RECV_CMDS_OFFSET,
> + cmds_size, resv_space);
>
> - guc_ct_buffer_init(&ct->ctbs.recv, desc, cmds, cmds_size, resv_space);
> + guc_ct_buffer_init(&ct->ctbs.recv,
> + &desc_map, &cmds_map, cmds_size, resv_space);
>
> return 0;
> }
> @@ -279,6 +299,10 @@ void intel_guc_ct_fini(struct intel_guc_ct *ct)
>
> tasklet_kill(&ct->receive_tasklet);
> i915_vma_unpin_and_release(&ct->vma, I915_VMA_RELEASE_MAP);
> + iosys_map_clear(&ct->ctbs.send.desc_map);
> + iosys_map_clear(&ct->ctbs.send.cmds_map);
> + iosys_map_clear(&ct->ctbs.recv.desc_map);
> + iosys_map_clear(&ct->ctbs.recv.cmds_map);
I think there is no need of clearing the iosys_map when were are zeroing
the complete structure area below.
> memset(ct, 0, sizeof(*ct));
> }
>
> @@ -291,8 +315,8 @@ void intel_guc_ct_fini(struct intel_guc_ct *ct)
> int intel_guc_ct_enable(struct intel_guc_ct *ct)
> {
> struct intel_guc *guc = ct_to_guc(ct);
> + struct iosys_map blob_map;
> u32 base, desc, cmds, size;
> - void *blob;
> int err;
>
> GEM_BUG_ON(ct->enabled);
> @@ -302,9 +326,14 @@ int intel_guc_ct_enable(struct intel_guc_ct *ct)
> GEM_BUG_ON(!i915_gem_object_has_pinned_pages(ct->vma->obj));
> base = intel_guc_ggtt_offset(guc, ct->vma);
>
> + if (i915_gem_object_is_lmem(ct->vma->obj))
> + iosys_map_set_vaddr_iomem(&blob_map, (void __iomem *)
> + __px_vaddr(ct->vma->obj));
> + else
> + iosys_map_set_vaddr(&blob_map, __px_vaddr(ct->vma->obj));
> +
> /* blob should start with send descriptor */
> - blob = __px_vaddr(ct->vma->obj);
> - GEM_BUG_ON(blob != ct->ctbs.send.desc);
> + GEM_BUG_ON(!iosys_map_is_equal(&blob_map, &ct->ctbs.send.desc_map));
>
> /* (re)initialize descriptors */
> guc_ct_buffer_reset(&ct->ctbs.send);
> @@ -314,15 +343,15 @@ int intel_guc_ct_enable(struct intel_guc_ct *ct)
> * Register both CT buffers starting with RECV buffer.
> * Descriptors are in first half of the blob.
> */
> - desc = base + ptrdiff(ct->ctbs.recv.desc, blob);
> - cmds = base + ptrdiff(ct->ctbs.recv.cmds, blob);
> + desc = base + CTB_RECV_DESC_OFFSET;
> + cmds = base + CTB_RECV_CMDS_OFFSET;
> size = ct->ctbs.recv.size * 4;
> err = ct_register_buffer(ct, false, desc, cmds, size);
> if (unlikely(err))
> goto err_out;
>
> - desc = base + ptrdiff(ct->ctbs.send.desc, blob);
> - cmds = base + ptrdiff(ct->ctbs.send.cmds, blob);
> + desc = base + CTB_SEND_DESC_OFFSET;
> + cmds = base + CTB_SEND_CMDS_OFFSET;
> size = ct->ctbs.send.size * 4;
> err = ct_register_buffer(ct, true, desc, cmds, size);
> if (unlikely(err))
> @@ -371,31 +400,33 @@ static int ct_write(struct intel_guc_ct *ct,
> u32 fence, u32 flags)
> {
> struct intel_guc_ct_buffer *ctb = &ct->ctbs.send;
> - struct guc_ct_buffer_desc *desc = ctb->desc;
> u32 tail = ctb->tail;
> u32 size = ctb->size;
> u32 header;
> u32 hxg;
> u32 type;
> - u32 *cmds = ctb->cmds;
> + u32 status = ct_desc_read(&ctb->desc_map, status);
> unsigned int i;
>
> - if (unlikely(desc->status))
> + if (unlikely(status))
> goto corrupted;
>
> GEM_BUG_ON(tail > size);
>
> #ifdef CONFIG_DRM_I915_DEBUG_GUC
> - if (unlikely(tail != READ_ONCE(desc->tail))) {
> + if (unlikely(tail != ct_desc_read(&ctb->desc_map, tail))) {
> CT_ERROR(ct, "Tail was modified %u != %u\n",
> - desc->tail, tail);
> - desc->status |= GUC_CTB_STATUS_MISMATCH;
> + ct_desc_read(&ctb->desc_map, tail), tail);
> + status |= GUC_CTB_STATUS_MISMATCH;
> + ct_desc_write(&ctb->desc_map, status, status);
> goto corrupted;
> }
> - if (unlikely(READ_ONCE(desc->head) >= size)) {
> + if (unlikely(ct_desc_read(&ctb->desc_map, head) >= size)) {
> CT_ERROR(ct, "Invalid head offset %u >= %u)\n",
> - desc->head, size);
> - desc->status |= GUC_CTB_STATUS_OVERFLOW;
> + ct_desc_read(&ctb->desc_map, head), size);
Can we avoid reading the head from ctb->desc_map twice? Since each
iosys_map read translates to memcpy, it is better to avoid repeating if
we can cache from the earlier read.
> + status = ct_desc_read(&ctb->desc_map, status) |
> + GUC_CTB_STATUS_OVERFLOW;
Same here, can we avoid reading status since we already have it read. We
can do the same like how it is done for the GUC_CTB_STATUS_MISMATCH case.
> + ct_desc_write(&ctb->desc_map, status, status);
> goto corrupted;
> }
> #endif
> @@ -418,14 +449,14 @@ static int ct_write(struct intel_guc_ct *ct,
> CT_DEBUG(ct, "writing (tail %u) %*ph %*ph %*ph\n",
> tail, 4, &header, 4, &hxg, 4 * (len - 1), &action[1]);
>
> - cmds[tail] = header;
> + iosys_map_wr(&ctb->cmds_map, 4 * tail, u32, header);
I prefer not to use the MAGIC number. My suggestion is to use
sizeof(tail) since we need the offset in bytes.
> tail = (tail + 1) % size;
>
> - cmds[tail] = hxg;
> + iosys_map_wr(&ctb->cmds_map, 4 * tail, u32, hxg);
MAGIC number again. There are numerous places in the patch, where
numbers are used. I prefer to remove it.
> tail = (tail + 1) % size;
>
> for (i = 1; i < len; i++) {
> - cmds[tail] = action[i];
> + iosys_map_wr(&ctb->cmds_map, 4 * tail, u32, action[i]);
> tail = (tail + 1) % size;
> }
> GEM_BUG_ON(tail > size);
> @@ -442,13 +473,14 @@ static int ct_write(struct intel_guc_ct *ct,
> atomic_sub(len + GUC_CTB_HDR_LEN, &ctb->space);
>
> /* now update descriptor */
> - WRITE_ONCE(desc->tail, tail);
> + ct_desc_write(&ctb->desc_map, tail, tail);
>
> return 0;
>
> corrupted:
> CT_ERROR(ct, "Corrupted descriptor head=%u tail=%u status=%#x\n",
> - desc->head, desc->tail, desc->status);
> + ct_desc_read(&ctb->desc_map, head), ct_desc_read(&ctb->desc_map, tail),
> + ct_desc_read(&ctb->desc_map, status));
> ctb->broken = true;
> return -EPIPE;
> }
> @@ -499,20 +531,22 @@ static inline bool ct_deadlocked(struct intel_guc_ct *ct)
> bool ret = ktime_ms_delta(ktime_get(), ct->stall_time) > timeout;
>
> if (unlikely(ret)) {
> - struct guc_ct_buffer_desc *send = ct->ctbs.send.desc;
> - struct guc_ct_buffer_desc *recv = ct->ctbs.send.desc;
> -
> CT_ERROR(ct, "Communication stalled for %lld ms, desc status=%#x,%#x\n",
> ktime_ms_delta(ktime_get(), ct->stall_time),
> - send->status, recv->status);
> + ct_desc_read(&ct->ctbs.send.desc_map, status),
> + ct_desc_read(&ct->ctbs.recv.desc_map, status));
> CT_ERROR(ct, "H2G Space: %u (Bytes)\n",
> atomic_read(&ct->ctbs.send.space) * 4);
> - CT_ERROR(ct, "Head: %u (Dwords)\n", ct->ctbs.send.desc->head);
> - CT_ERROR(ct, "Tail: %u (Dwords)\n", ct->ctbs.send.desc->tail);
> + CT_ERROR(ct, "Head: %u (Dwords)\n",
> + ct_desc_read(&ct->ctbs.send.desc_map, head));
> + CT_ERROR(ct, "Tail: %u (Dwords)\n",
> + ct_desc_read(&ct->ctbs.send.desc_map, tail));
> CT_ERROR(ct, "G2H Space: %u (Bytes)\n",
> atomic_read(&ct->ctbs.recv.space) * 4);
> - CT_ERROR(ct, "Head: %u\n (Dwords)", ct->ctbs.recv.desc->head);
> - CT_ERROR(ct, "Tail: %u\n (Dwords)", ct->ctbs.recv.desc->tail);
> + CT_ERROR(ct, "Head: %u\n (Dwords)",
> + ct_desc_read(&ct->ctbs.recv.desc_map, head));
> + CT_ERROR(ct, "Tail: %u\n (Dwords)",
> + ct_desc_read(&ct->ctbs.recv.desc_map, tail));
>
> ct->ctbs.send.broken = true;
> }
> @@ -549,18 +583,19 @@ static inline void g2h_release_space(struct intel_guc_ct *ct, u32 g2h_len_dw)
> static inline bool h2g_has_room(struct intel_guc_ct *ct, u32 len_dw)
> {
> struct intel_guc_ct_buffer *ctb = &ct->ctbs.send;
> - struct guc_ct_buffer_desc *desc = ctb->desc;
> u32 head;
> u32 space;
> + u32 status = ct_desc_read(&ctb->desc_map, status);
>
> if (atomic_read(&ctb->space) >= len_dw)
> return true;
>
> - head = READ_ONCE(desc->head);
> + head = ct_desc_read(&ctb->desc_map, head);
> if (unlikely(head > ctb->size)) {
> CT_ERROR(ct, "Invalid head offset %u >= %u)\n",
> head, ctb->size);
> - desc->status |= GUC_CTB_STATUS_OVERFLOW;
> + status |= GUC_CTB_STATUS_OVERFLOW;
> + ct_desc_write(&ctb->desc_map, status, status);
> ctb->broken = true;
> return false;
> }
> @@ -803,11 +838,10 @@ static void ct_free_msg(struct ct_incoming_msg *msg)
> static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg)
> {
> struct intel_guc_ct_buffer *ctb = &ct->ctbs.recv;
> - struct guc_ct_buffer_desc *desc = ctb->desc;
> u32 head = ctb->head;
> - u32 tail = READ_ONCE(desc->tail);
> + u32 tail = ct_desc_read(&ctb->desc_map, tail);
> u32 size = ctb->size;
> - u32 *cmds = ctb->cmds;
> + u32 status = ct_desc_read(&ctb->desc_map, status);
> s32 available;
> unsigned int len;
> unsigned int i;
> @@ -816,23 +850,26 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg)
> if (unlikely(ctb->broken))
> return -EPIPE;
>
> - if (unlikely(desc->status))
> + if (unlikely(status))
> goto corrupted;
>
> GEM_BUG_ON(head > size);
>
> #ifdef CONFIG_DRM_I915_DEBUG_GUC
> - if (unlikely(head != READ_ONCE(desc->head))) {
> + if (unlikely(head != ct_desc_read(&ctb->desc_map, head))) {
> CT_ERROR(ct, "Head was modified %u != %u\n",
> - desc->head, head);
> - desc->status |= GUC_CTB_STATUS_MISMATCH;
> + ct_desc_read(&ctb->desc_map, head), head);
head read twice here as well.
> + status |= GUC_CTB_STATUS_MISMATCH;
> + ct_desc_write(&ctb->desc_map, status, status);
> goto corrupted;
> }
> #endif
> if (unlikely(tail >= size)) {
> CT_ERROR(ct, "Invalid tail offset %u >= %u)\n",
> tail, size);
> - desc->status |= GUC_CTB_STATUS_OVERFLOW;
> + status = ct_desc_read(&ctb->desc_map, status) |
> + GUC_CTB_STATUS_OVERFLOW;
No need to read the status again as we already have it cached.
> + ct_desc_write(&ctb->desc_map, status, status);
> goto corrupted;
> }
>
> @@ -849,7 +886,7 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg)
> CT_DEBUG(ct, "available %d (%u:%u:%u)\n", available, head, tail, size);
> GEM_BUG_ON(available < 0);
>
> - header = cmds[head];
> + header = iosys_map_rd(&ctb->cmds_map, (4 * head), u32);
MAGIC numbers
> head = (head + 1) % size;
>
> /* message len with header */
> @@ -857,11 +894,15 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg)
> if (unlikely(len > (u32)available)) {
> CT_ERROR(ct, "Incomplete message %*ph %*ph %*ph\n",
> 4, &header,
> + 4 * (head + available - 1 > size ? size - head :
> + available - 1), ((__px_vaddr(ct->vma->obj) +
> + CTB_RECV_CMDS_OFFSET) + (4 * head)),
> 4 * (head + available - 1 > size ?
> - size - head : available - 1), &cmds[head],
> - 4 * (head + available - 1 > size ?
> - available - 1 - size + head : 0), &cmds[0]);
> - desc->status |= GUC_CTB_STATUS_UNDERFLOW;
> + available - 1 - size + head : 0),
> + (__px_vaddr(ct->vma->obj) + CTB_RECV_CMDS_OFFSET));
> + status = ct_desc_read(&ctb->desc_map, status) |
> + GUC_CTB_STATUS_UNDERFLOW;
No need to read status again
Regards,
Bala
> + ct_desc_write(&ctb->desc_map, status, status);
> goto corrupted;
> }
>
> @@ -869,17 +910,18 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg)
> if (!*msg) {
> CT_ERROR(ct, "No memory for message %*ph %*ph %*ph\n",
> 4, &header,
> + 4 * (head + available - 1 > size ? size - head :
> + available - 1), (ctb->cmds_map.vaddr + (4 * head)),
> 4 * (head + available - 1 > size ?
> - size - head : available - 1), &cmds[head],
> - 4 * (head + available - 1 > size ?
> - available - 1 - size + head : 0), &cmds[0]);
> + available - 1 - size + head : 0), ctb->cmds_map.vaddr);
> return available;
> }
>
> (*msg)->msg[0] = header;
>
> for (i = 1; i < len; i++) {
> - (*msg)->msg[i] = cmds[head];
> + (*msg)->msg[i] = iosys_map_rd(&ctb->cmds_map,
> + (4 * head), u32);
> head = (head + 1) % size;
> }
> CT_DEBUG(ct, "received %*ph\n", 4 * len, (*msg)->msg);
> @@ -888,13 +930,15 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg)
> ctb->head = head;
>
> /* now update descriptor */
> - WRITE_ONCE(desc->head, head);
> + ct_desc_write(&ctb->desc_map, head, head);
>
> return available - len;
>
> corrupted:
> CT_ERROR(ct, "Corrupted descriptor head=%u tail=%u status=%#x\n",
> - desc->head, desc->tail, desc->status);
> + ct_desc_read(&ctb->desc_map, head),
> + ct_desc_read(&ctb->desc_map, tail),
> + ct_desc_read(&ctb->desc_map, status));
> ctb->broken = true;
> return -EPIPE;
> }
> @@ -1211,13 +1255,13 @@ void intel_guc_ct_print_info(struct intel_guc_ct *ct,
> drm_printf(p, "H2G Space: %u\n",
> atomic_read(&ct->ctbs.send.space) * 4);
> drm_printf(p, "Head: %u\n",
> - ct->ctbs.send.desc->head);
> + ct_desc_read(&ct->ctbs.send.desc_map, head));
> drm_printf(p, "Tail: %u\n",
> - ct->ctbs.send.desc->tail);
> + ct_desc_read(&ct->ctbs.send.desc_map, tail));
> drm_printf(p, "G2H Space: %u\n",
> atomic_read(&ct->ctbs.recv.space) * 4);
> drm_printf(p, "Head: %u\n",
> - ct->ctbs.recv.desc->head);
> + ct_desc_read(&ct->ctbs.recv.desc_map, head));
> drm_printf(p, "Tail: %u\n",
> - ct->ctbs.recv.desc->tail);
> + ct_desc_read(&ct->ctbs.recv.desc_map, tail));
> }
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h
> index f709a19c7e21..867fe13fb47d 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h
> @@ -7,6 +7,7 @@
> #define _INTEL_GUC_CT_H_
>
> #include <linux/interrupt.h>
> +#include <linux/iosys-map.h>
> #include <linux/spinlock.h>
> #include <linux/workqueue.h>
> #include <linux/ktime.h>
> @@ -32,8 +33,8 @@ struct drm_printer;
> * holds the commands.
> *
> * @lock: protects access to the commands buffer and buffer descriptor
> - * @desc: pointer to the buffer descriptor
> - * @cmds: pointer to the commands buffer
> + * @desc: iosys map to the buffer descriptor
> + * @cmds: iosys map to the commands buffer
> * @size: size of the commands buffer in dwords
> * @resv_space: reserved space in buffer in dwords
> * @head: local shadow copy of head in dwords
> @@ -43,8 +44,8 @@ struct drm_printer;
> */
> struct intel_guc_ct_buffer {
> spinlock_t lock;
> - struct guc_ct_buffer_desc *desc;
> - u32 *cmds;
> + struct iosys_map desc_map;
> + struct iosys_map cmds_map;
> u32 size;
> u32 resv_space;
> u32 tail;
> --
> 2.33.0
>
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [Intel-gfx] [PATCH 1/1] drm/i915/guc: Convert ct buffer to iosys_map
2022-04-04 9:31 ` [Intel-gfx] [PATCH 1/1] drm/i915/guc: Convert ct buffer to iosys_map Mullati Siva
2022-04-14 12:11 ` Balasubramani Vivekanandan
@ 2022-04-18 9:08 ` Balasubramani Vivekanandan
1 sibling, 0 replies; 14+ messages in thread
From: Balasubramani Vivekanandan @ 2022-04-18 9:08 UTC (permalink / raw)
To: Mullati Siva, intel-gfx; +Cc: lucas.demarchi
On 04.04.2022 15:01, Mullati Siva wrote:
> From: Siva Mullati <siva.mullati@intel.com>
>
> Convert CT commands and descriptors to use iosys_map rather
> than plain pointer and save it in the intel_guc_ct_buffer struct.
> This will help with ct_write and ct_read for cmd send and receive
> after the initialization by abstracting the IO vs system memory.
>
> Signed-off-by: Siva Mullati <siva.mullati@intel.com>
> ---
> drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 200 +++++++++++++---------
> drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h | 9 +-
> 2 files changed, 127 insertions(+), 82 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
> index f01325cd1b62..64568dc90b05 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
> @@ -44,6 +44,11 @@ static inline struct drm_device *ct_to_drm(struct intel_guc_ct *ct)
> #define CT_PROBE_ERROR(_ct, _fmt, ...) \
> i915_probe_error(ct_to_i915(ct), "CT: " _fmt, ##__VA_ARGS__)
>
> +#define ct_desc_read(desc_map_, field_) \
> + iosys_map_rd_field(desc_map_, 0, struct guc_ct_buffer_desc, field_)
> +#define ct_desc_write(desc_map_, field_, val_) \
> + iosys_map_wr_field(desc_map_, 0, struct guc_ct_buffer_desc, field_, val_)
> +
> /**
> * DOC: CTB Blob
> *
> @@ -76,6 +81,11 @@ static inline struct drm_device *ct_to_drm(struct intel_guc_ct *ct)
> #define CTB_G2H_BUFFER_SIZE (4 * CTB_H2G_BUFFER_SIZE)
> #define G2H_ROOM_BUFFER_SIZE (CTB_G2H_BUFFER_SIZE / 4)
>
> +#define CTB_SEND_DESC_OFFSET 0u
> +#define CTB_RECV_DESC_OFFSET (CTB_DESC_SIZE)
> +#define CTB_SEND_CMDS_OFFSET (2 * CTB_DESC_SIZE)
> +#define CTB_RECV_CMDS_OFFSET (2 * CTB_DESC_SIZE + CTB_H2G_BUFFER_SIZE)
> +
> struct ct_request {
> struct list_head link;
> u32 fence;
> @@ -113,9 +123,9 @@ void intel_guc_ct_init_early(struct intel_guc_ct *ct)
> init_waitqueue_head(&ct->wq);
> }
>
> -static void guc_ct_buffer_desc_init(struct guc_ct_buffer_desc *desc)
> +static void guc_ct_buffer_desc_init(struct iosys_map *desc)
> {
> - memset(desc, 0, sizeof(*desc));
> + iosys_map_memset(desc, 0, 0, sizeof(struct guc_ct_buffer_desc));
> }
>
> static void guc_ct_buffer_reset(struct intel_guc_ct_buffer *ctb)
> @@ -128,17 +138,18 @@ static void guc_ct_buffer_reset(struct intel_guc_ct_buffer *ctb)
> space = CIRC_SPACE(ctb->tail, ctb->head, ctb->size) - ctb->resv_space;
> atomic_set(&ctb->space, space);
>
> - guc_ct_buffer_desc_init(ctb->desc);
> + guc_ct_buffer_desc_init(&ctb->desc_map);
> }
>
> static void guc_ct_buffer_init(struct intel_guc_ct_buffer *ctb,
> - struct guc_ct_buffer_desc *desc,
> - u32 *cmds, u32 size_in_bytes, u32 resv_space)
> + struct iosys_map *desc,
> + struct iosys_map *cmds,
> + u32 size_in_bytes, u32 resv_space)
> {
> GEM_BUG_ON(size_in_bytes % 4);
>
> - ctb->desc = desc;
> - ctb->cmds = cmds;
> + ctb->desc_map = *desc;
> + ctb->cmds_map = *cmds;
> ctb->size = size_in_bytes / 4;
> ctb->resv_space = resv_space / 4;
>
> @@ -218,12 +229,13 @@ static int ct_register_buffer(struct intel_guc_ct *ct, bool send,
> int intel_guc_ct_init(struct intel_guc_ct *ct)
> {
> struct intel_guc *guc = ct_to_guc(ct);
> - struct guc_ct_buffer_desc *desc;
> + struct iosys_map blob_map;
> + struct iosys_map desc_map;
> + struct iosys_map cmds_map;
> u32 blob_size;
> u32 cmds_size;
> u32 resv_space;
> void *blob;
> - u32 *cmds;
> int err;
>
> err = i915_inject_probe_error(guc_to_gt(guc)->i915, -ENXIO);
> @@ -242,27 +254,35 @@ int intel_guc_ct_init(struct intel_guc_ct *ct)
>
> CT_DEBUG(ct, "base=%#x size=%u\n", intel_guc_ggtt_offset(guc, ct->vma), blob_size);
>
> - /* store pointers to desc and cmds for send ctb */
> - desc = blob;
> - cmds = blob + 2 * CTB_DESC_SIZE;
> + if (i915_gem_object_is_lmem(ct->vma->obj))
> + iosys_map_set_vaddr_iomem(&blob_map,
> + (void __iomem *)blob);
> + else
> + iosys_map_set_vaddr(&blob_map, blob);
> +
> + /* store sysmap to desc_map and cmds_map for send ctb */
> + desc_map = IOSYS_MAP_INIT_OFFSET(&blob_map, CTB_SEND_DESC_OFFSET);
> + cmds_map = IOSYS_MAP_INIT_OFFSET(&blob_map, CTB_SEND_CMDS_OFFSET);
> cmds_size = CTB_H2G_BUFFER_SIZE;
> resv_space = 0;
> - CT_DEBUG(ct, "%s desc %#tx cmds %#tx size %u/%u\n", "send",
> - ptrdiff(desc, blob), ptrdiff(cmds, blob), cmds_size,
> - resv_space);
> + CT_DEBUG(ct, "%s desc %#x cmds %#x size %u/%u\n", "send",
> + CTB_SEND_DESC_OFFSET, (u32)CTB_SEND_CMDS_OFFSET,
> + cmds_size, resv_space);
>
> - guc_ct_buffer_init(&ct->ctbs.send, desc, cmds, cmds_size, resv_space);
> + guc_ct_buffer_init(&ct->ctbs.send,
> + &desc_map, &cmds_map, cmds_size, resv_space);
>
> - /* store pointers to desc and cmds for recv ctb */
> - desc = blob + CTB_DESC_SIZE;
> - cmds = blob + 2 * CTB_DESC_SIZE + CTB_H2G_BUFFER_SIZE;
> + /* store sysmap to desc_map and cmds_map for recv ctb */
> + desc_map = IOSYS_MAP_INIT_OFFSET(&blob_map, CTB_RECV_DESC_OFFSET);
> + cmds_map = IOSYS_MAP_INIT_OFFSET(&blob_map, CTB_RECV_CMDS_OFFSET);
> cmds_size = CTB_G2H_BUFFER_SIZE;
> resv_space = G2H_ROOM_BUFFER_SIZE;
> - CT_DEBUG(ct, "%s desc %#tx cmds %#tx size %u/%u\n", "recv",
> - ptrdiff(desc, blob), ptrdiff(cmds, blob), cmds_size,
> - resv_space);
> + CT_DEBUG(ct, "%s desc %#x cmds %#x size %u/%u\n", "recv",
> + (u32)CTB_RECV_DESC_OFFSET, (u32)CTB_RECV_CMDS_OFFSET,
> + cmds_size, resv_space);
>
> - guc_ct_buffer_init(&ct->ctbs.recv, desc, cmds, cmds_size, resv_space);
> + guc_ct_buffer_init(&ct->ctbs.recv,
> + &desc_map, &cmds_map, cmds_size, resv_space);
>
> return 0;
> }
> @@ -279,6 +299,10 @@ void intel_guc_ct_fini(struct intel_guc_ct *ct)
>
> tasklet_kill(&ct->receive_tasklet);
> i915_vma_unpin_and_release(&ct->vma, I915_VMA_RELEASE_MAP);
> + iosys_map_clear(&ct->ctbs.send.desc_map);
> + iosys_map_clear(&ct->ctbs.send.cmds_map);
> + iosys_map_clear(&ct->ctbs.recv.desc_map);
> + iosys_map_clear(&ct->ctbs.recv.cmds_map);
> memset(ct, 0, sizeof(*ct));
> }
>
> @@ -291,8 +315,8 @@ void intel_guc_ct_fini(struct intel_guc_ct *ct)
> int intel_guc_ct_enable(struct intel_guc_ct *ct)
> {
> struct intel_guc *guc = ct_to_guc(ct);
> + struct iosys_map blob_map;
> u32 base, desc, cmds, size;
> - void *blob;
> int err;
>
> GEM_BUG_ON(ct->enabled);
> @@ -302,9 +326,14 @@ int intel_guc_ct_enable(struct intel_guc_ct *ct)
> GEM_BUG_ON(!i915_gem_object_has_pinned_pages(ct->vma->obj));
> base = intel_guc_ggtt_offset(guc, ct->vma);
>
> + if (i915_gem_object_is_lmem(ct->vma->obj))
> + iosys_map_set_vaddr_iomem(&blob_map, (void __iomem *)
> + __px_vaddr(ct->vma->obj));
> + else
> + iosys_map_set_vaddr(&blob_map, __px_vaddr(ct->vma->obj));
> +
> /* blob should start with send descriptor */
> - blob = __px_vaddr(ct->vma->obj);
> - GEM_BUG_ON(blob != ct->ctbs.send.desc);
> + GEM_BUG_ON(!iosys_map_is_equal(&blob_map, &ct->ctbs.send.desc_map));
>
> /* (re)initialize descriptors */
> guc_ct_buffer_reset(&ct->ctbs.send);
> @@ -314,15 +343,15 @@ int intel_guc_ct_enable(struct intel_guc_ct *ct)
> * Register both CT buffers starting with RECV buffer.
> * Descriptors are in first half of the blob.
> */
> - desc = base + ptrdiff(ct->ctbs.recv.desc, blob);
> - cmds = base + ptrdiff(ct->ctbs.recv.cmds, blob);
> + desc = base + CTB_RECV_DESC_OFFSET;
> + cmds = base + CTB_RECV_CMDS_OFFSET;
> size = ct->ctbs.recv.size * 4;
> err = ct_register_buffer(ct, false, desc, cmds, size);
> if (unlikely(err))
> goto err_out;
>
> - desc = base + ptrdiff(ct->ctbs.send.desc, blob);
> - cmds = base + ptrdiff(ct->ctbs.send.cmds, blob);
> + desc = base + CTB_SEND_DESC_OFFSET;
> + cmds = base + CTB_SEND_CMDS_OFFSET;
> size = ct->ctbs.send.size * 4;
> err = ct_register_buffer(ct, true, desc, cmds, size);
> if (unlikely(err))
> @@ -371,31 +400,33 @@ static int ct_write(struct intel_guc_ct *ct,
> u32 fence, u32 flags)
> {
> struct intel_guc_ct_buffer *ctb = &ct->ctbs.send;
> - struct guc_ct_buffer_desc *desc = ctb->desc;
> u32 tail = ctb->tail;
> u32 size = ctb->size;
> u32 header;
> u32 hxg;
> u32 type;
> - u32 *cmds = ctb->cmds;
> + u32 status = ct_desc_read(&ctb->desc_map, status);
> unsigned int i;
>
> - if (unlikely(desc->status))
> + if (unlikely(status))
> goto corrupted;
>
> GEM_BUG_ON(tail > size);
>
> #ifdef CONFIG_DRM_I915_DEBUG_GUC
> - if (unlikely(tail != READ_ONCE(desc->tail))) {
> + if (unlikely(tail != ct_desc_read(&ctb->desc_map, tail))) {
> CT_ERROR(ct, "Tail was modified %u != %u\n",
> - desc->tail, tail);
> - desc->status |= GUC_CTB_STATUS_MISMATCH;
> + ct_desc_read(&ctb->desc_map, tail), tail);
> + status |= GUC_CTB_STATUS_MISMATCH;
> + ct_desc_write(&ctb->desc_map, status, status);
> goto corrupted;
> }
> - if (unlikely(READ_ONCE(desc->head) >= size)) {
> + if (unlikely(ct_desc_read(&ctb->desc_map, head) >= size)) {
> CT_ERROR(ct, "Invalid head offset %u >= %u)\n",
> - desc->head, size);
> - desc->status |= GUC_CTB_STATUS_OVERFLOW;
> + ct_desc_read(&ctb->desc_map, head), size);
> + status = ct_desc_read(&ctb->desc_map, status) |
> + GUC_CTB_STATUS_OVERFLOW;
> + ct_desc_write(&ctb->desc_map, status, status);
> goto corrupted;
> }
> #endif
> @@ -418,14 +449,14 @@ static int ct_write(struct intel_guc_ct *ct,
> CT_DEBUG(ct, "writing (tail %u) %*ph %*ph %*ph\n",
> tail, 4, &header, 4, &hxg, 4 * (len - 1), &action[1]);
>
> - cmds[tail] = header;
> + iosys_map_wr(&ctb->cmds_map, 4 * tail, u32, header);
> tail = (tail + 1) % size;
>
> - cmds[tail] = hxg;
> + iosys_map_wr(&ctb->cmds_map, 4 * tail, u32, hxg);
> tail = (tail + 1) % size;
>
> for (i = 1; i < len; i++) {
> - cmds[tail] = action[i];
> + iosys_map_wr(&ctb->cmds_map, 4 * tail, u32, action[i]);
> tail = (tail + 1) % size;
> }
> GEM_BUG_ON(tail > size);
> @@ -442,13 +473,14 @@ static int ct_write(struct intel_guc_ct *ct,
> atomic_sub(len + GUC_CTB_HDR_LEN, &ctb->space);
>
> /* now update descriptor */
> - WRITE_ONCE(desc->tail, tail);
> + ct_desc_write(&ctb->desc_map, tail, tail);
>
> return 0;
>
> corrupted:
> CT_ERROR(ct, "Corrupted descriptor head=%u tail=%u status=%#x\n",
> - desc->head, desc->tail, desc->status);
> + ct_desc_read(&ctb->desc_map, head), ct_desc_read(&ctb->desc_map, tail),
> + ct_desc_read(&ctb->desc_map, status));
> ctb->broken = true;
> return -EPIPE;
> }
> @@ -499,20 +531,22 @@ static inline bool ct_deadlocked(struct intel_guc_ct *ct)
> bool ret = ktime_ms_delta(ktime_get(), ct->stall_time) > timeout;
>
> if (unlikely(ret)) {
> - struct guc_ct_buffer_desc *send = ct->ctbs.send.desc;
> - struct guc_ct_buffer_desc *recv = ct->ctbs.send.desc;
> -
> CT_ERROR(ct, "Communication stalled for %lld ms, desc status=%#x,%#x\n",
> ktime_ms_delta(ktime_get(), ct->stall_time),
> - send->status, recv->status);
> + ct_desc_read(&ct->ctbs.send.desc_map, status),
> + ct_desc_read(&ct->ctbs.recv.desc_map, status));
> CT_ERROR(ct, "H2G Space: %u (Bytes)\n",
> atomic_read(&ct->ctbs.send.space) * 4);
> - CT_ERROR(ct, "Head: %u (Dwords)\n", ct->ctbs.send.desc->head);
> - CT_ERROR(ct, "Tail: %u (Dwords)\n", ct->ctbs.send.desc->tail);
> + CT_ERROR(ct, "Head: %u (Dwords)\n",
> + ct_desc_read(&ct->ctbs.send.desc_map, head));
> + CT_ERROR(ct, "Tail: %u (Dwords)\n",
> + ct_desc_read(&ct->ctbs.send.desc_map, tail));
> CT_ERROR(ct, "G2H Space: %u (Bytes)\n",
> atomic_read(&ct->ctbs.recv.space) * 4);
> - CT_ERROR(ct, "Head: %u\n (Dwords)", ct->ctbs.recv.desc->head);
> - CT_ERROR(ct, "Tail: %u\n (Dwords)", ct->ctbs.recv.desc->tail);
> + CT_ERROR(ct, "Head: %u\n (Dwords)",
> + ct_desc_read(&ct->ctbs.recv.desc_map, head));
> + CT_ERROR(ct, "Tail: %u\n (Dwords)",
> + ct_desc_read(&ct->ctbs.recv.desc_map, tail));
>
> ct->ctbs.send.broken = true;
> }
> @@ -549,18 +583,19 @@ static inline void g2h_release_space(struct intel_guc_ct *ct, u32 g2h_len_dw)
> static inline bool h2g_has_room(struct intel_guc_ct *ct, u32 len_dw)
> {
> struct intel_guc_ct_buffer *ctb = &ct->ctbs.send;
> - struct guc_ct_buffer_desc *desc = ctb->desc;
> u32 head;
> u32 space;
> + u32 status = ct_desc_read(&ctb->desc_map, status);
>
> if (atomic_read(&ctb->space) >= len_dw)
> return true;
>
> - head = READ_ONCE(desc->head);
> + head = ct_desc_read(&ctb->desc_map, head);
> if (unlikely(head > ctb->size)) {
> CT_ERROR(ct, "Invalid head offset %u >= %u)\n",
> head, ctb->size);
> - desc->status |= GUC_CTB_STATUS_OVERFLOW;
> + status |= GUC_CTB_STATUS_OVERFLOW;
> + ct_desc_write(&ctb->desc_map, status, status);
> ctb->broken = true;
> return false;
> }
> @@ -803,11 +838,10 @@ static void ct_free_msg(struct ct_incoming_msg *msg)
> static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg)
> {
> struct intel_guc_ct_buffer *ctb = &ct->ctbs.recv;
> - struct guc_ct_buffer_desc *desc = ctb->desc;
> u32 head = ctb->head;
> - u32 tail = READ_ONCE(desc->tail);
> + u32 tail = ct_desc_read(&ctb->desc_map, tail);
> u32 size = ctb->size;
> - u32 *cmds = ctb->cmds;
> + u32 status = ct_desc_read(&ctb->desc_map, status);
> s32 available;
> unsigned int len;
> unsigned int i;
> @@ -816,23 +850,26 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg)
> if (unlikely(ctb->broken))
> return -EPIPE;
>
> - if (unlikely(desc->status))
> + if (unlikely(status))
> goto corrupted;
>
> GEM_BUG_ON(head > size);
>
> #ifdef CONFIG_DRM_I915_DEBUG_GUC
> - if (unlikely(head != READ_ONCE(desc->head))) {
> + if (unlikely(head != ct_desc_read(&ctb->desc_map, head))) {
> CT_ERROR(ct, "Head was modified %u != %u\n",
> - desc->head, head);
> - desc->status |= GUC_CTB_STATUS_MISMATCH;
> + ct_desc_read(&ctb->desc_map, head), head);
> + status |= GUC_CTB_STATUS_MISMATCH;
> + ct_desc_write(&ctb->desc_map, status, status);
> goto corrupted;
> }
> #endif
> if (unlikely(tail >= size)) {
> CT_ERROR(ct, "Invalid tail offset %u >= %u)\n",
> tail, size);
> - desc->status |= GUC_CTB_STATUS_OVERFLOW;
> + status = ct_desc_read(&ctb->desc_map, status) |
> + GUC_CTB_STATUS_OVERFLOW;
> + ct_desc_write(&ctb->desc_map, status, status);
> goto corrupted;
> }
>
> @@ -849,7 +886,7 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg)
> CT_DEBUG(ct, "available %d (%u:%u:%u)\n", available, head, tail, size);
> GEM_BUG_ON(available < 0);
>
> - header = cmds[head];
> + header = iosys_map_rd(&ctb->cmds_map, (4 * head), u32);
> head = (head + 1) % size;
>
> /* message len with header */
> @@ -857,11 +894,15 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg)
> if (unlikely(len > (u32)available)) {
> CT_ERROR(ct, "Incomplete message %*ph %*ph %*ph\n",
> 4, &header,
> + 4 * (head + available - 1 > size ? size - head :
> + available - 1), ((__px_vaddr(ct->vma->obj) +
> + CTB_RECV_CMDS_OFFSET) + (4 * head)),
> 4 * (head + available - 1 > size ?
> - size - head : available - 1), &cmds[head],
> - 4 * (head + available - 1 > size ?
> - available - 1 - size + head : 0), &cmds[0]);
> - desc->status |= GUC_CTB_STATUS_UNDERFLOW;
> + available - 1 - size + head : 0),
> + (__px_vaddr(ct->vma->obj) + CTB_RECV_CMDS_OFFSET));
> + status = ct_desc_read(&ctb->desc_map, status) |
> + GUC_CTB_STATUS_UNDERFLOW;
> + ct_desc_write(&ctb->desc_map, status, status);
> goto corrupted;
> }
>
> @@ -869,17 +910,18 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg)
> if (!*msg) {
> CT_ERROR(ct, "No memory for message %*ph %*ph %*ph\n",
> 4, &header,
> + 4 * (head + available - 1 > size ? size - head :
> + available - 1), (ctb->cmds_map.vaddr + (4 * head)),
We cannot directly use the vaddr here as the cmds_map may contain system
memory or io memory address. You need to check the address type and use
the right member.
> 4 * (head + available - 1 > size ?
> - size - head : available - 1), &cmds[head],
> - 4 * (head + available - 1 > size ?
> - available - 1 - size + head : 0), &cmds[0]);
> + available - 1 - size + head : 0), ctb->cmds_map.vaddr);
Also here.
> return available;
> }
>
> (*msg)->msg[0] = header;
>
> for (i = 1; i < len; i++) {
> - (*msg)->msg[i] = cmds[head];
> + (*msg)->msg[i] = iosys_map_rd(&ctb->cmds_map,
> + (4 * head), u32);
> head = (head + 1) % size;
> }
> CT_DEBUG(ct, "received %*ph\n", 4 * len, (*msg)->msg);
> @@ -888,13 +930,15 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg)
> ctb->head = head;
>
> /* now update descriptor */
> - WRITE_ONCE(desc->head, head);
> + ct_desc_write(&ctb->desc_map, head, head);
>
> return available - len;
>
> corrupted:
> CT_ERROR(ct, "Corrupted descriptor head=%u tail=%u status=%#x\n",
> - desc->head, desc->tail, desc->status);
> + ct_desc_read(&ctb->desc_map, head),
> + ct_desc_read(&ctb->desc_map, tail),
> + ct_desc_read(&ctb->desc_map, status));
> ctb->broken = true;
> return -EPIPE;
> }
> @@ -1211,13 +1255,13 @@ void intel_guc_ct_print_info(struct intel_guc_ct *ct,
> drm_printf(p, "H2G Space: %u\n",
> atomic_read(&ct->ctbs.send.space) * 4);
> drm_printf(p, "Head: %u\n",
> - ct->ctbs.send.desc->head);
> + ct_desc_read(&ct->ctbs.send.desc_map, head));
> drm_printf(p, "Tail: %u\n",
> - ct->ctbs.send.desc->tail);
> + ct_desc_read(&ct->ctbs.send.desc_map, tail));
> drm_printf(p, "G2H Space: %u\n",
> atomic_read(&ct->ctbs.recv.space) * 4);
> drm_printf(p, "Head: %u\n",
> - ct->ctbs.recv.desc->head);
> + ct_desc_read(&ct->ctbs.recv.desc_map, head));
> drm_printf(p, "Tail: %u\n",
> - ct->ctbs.recv.desc->tail);
> + ct_desc_read(&ct->ctbs.recv.desc_map, tail));
> }
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h
> index f709a19c7e21..867fe13fb47d 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h
> @@ -7,6 +7,7 @@
> #define _INTEL_GUC_CT_H_
>
> #include <linux/interrupt.h>
> +#include <linux/iosys-map.h>
> #include <linux/spinlock.h>
> #include <linux/workqueue.h>
> #include <linux/ktime.h>
> @@ -32,8 +33,8 @@ struct drm_printer;
> * holds the commands.
> *
> * @lock: protects access to the commands buffer and buffer descriptor
> - * @desc: pointer to the buffer descriptor
> - * @cmds: pointer to the commands buffer
> + * @desc: iosys map to the buffer descriptor
> + * @cmds: iosys map to the commands buffer
> * @size: size of the commands buffer in dwords
> * @resv_space: reserved space in buffer in dwords
> * @head: local shadow copy of head in dwords
> @@ -43,8 +44,8 @@ struct drm_printer;
> */
> struct intel_guc_ct_buffer {
> spinlock_t lock;
> - struct guc_ct_buffer_desc *desc;
> - u32 *cmds;
> + struct iosys_map desc_map;
> + struct iosys_map cmds_map;
> u32 size;
> u32 resv_space;
> u32 tail;
> --
> 2.33.0
>
^ permalink raw reply [flat|nested] 14+ messages in thread
* [Intel-gfx] [PATCH 0/1] Refactor CT access to use iosys_map
@ 2022-04-21 17:26 Mullati Siva
2022-04-21 17:26 ` [Intel-gfx] [PATCH 1/1] drm/i915/guc: Convert ct buffer to iosys_map Mullati Siva
` (3 more replies)
0 siblings, 4 replies; 14+ messages in thread
From: Mullati Siva @ 2022-04-21 17:26 UTC (permalink / raw)
To: intel-gfx, siva.mullati; +Cc: lucas.demarchi
From: Siva Mullati <siva.mullati@intel.com>
ver2: remove newly added iosys map api from ver1
ver3: address review comments
ver4: remove accessing vaddr
This is continuation to the below patch series to use iosys map
APIs, to use CT commands and descriptors.
https://patchwork.freedesktop.org/series/99711/
Siva Mullati (1):
drm/i915/guc: Convert ct buffer to iosys_map
drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 197 +++++++++++++---------
drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h | 9 +-
2 files changed, 124 insertions(+), 82 deletions(-)
--
2.33.0
^ permalink raw reply [flat|nested] 14+ messages in thread
* [Intel-gfx] [PATCH 1/1] drm/i915/guc: Convert ct buffer to iosys_map
2022-04-21 17:26 [Intel-gfx] [PATCH 0/1] Refactor CT access to use iosys_map Mullati Siva
@ 2022-04-21 17:26 ` Mullati Siva
2022-04-21 21:40 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Refactor CT access to use iosys_map Patchwork
` (2 subsequent siblings)
3 siblings, 0 replies; 14+ messages in thread
From: Mullati Siva @ 2022-04-21 17:26 UTC (permalink / raw)
To: intel-gfx, siva.mullati; +Cc: lucas.demarchi
From: Siva Mullati <siva.mullati@intel.com>
Convert CT commands and descriptors to use iosys_map rather
than plain pointer and save it in the intel_guc_ct_buffer struct.
This will help with ct_write and ct_read for cmd send and receive
after the initialization by abstracting the IO vs system memory.
Signed-off-by: Siva Mullati <siva.mullati@intel.com>
---
drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 197 +++++++++++++---------
drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h | 9 +-
2 files changed, 124 insertions(+), 82 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
index f01325cd1b62..5bd03d3112f7 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
@@ -44,6 +44,11 @@ static inline struct drm_device *ct_to_drm(struct intel_guc_ct *ct)
#define CT_PROBE_ERROR(_ct, _fmt, ...) \
i915_probe_error(ct_to_i915(ct), "CT: " _fmt, ##__VA_ARGS__)
+#define ct_desc_read(desc_map_, field_) \
+ iosys_map_rd_field(desc_map_, 0, struct guc_ct_buffer_desc, field_)
+#define ct_desc_write(desc_map_, field_, val_) \
+ iosys_map_wr_field(desc_map_, 0, struct guc_ct_buffer_desc, field_, val_)
+
/**
* DOC: CTB Blob
*
@@ -76,6 +81,11 @@ static inline struct drm_device *ct_to_drm(struct intel_guc_ct *ct)
#define CTB_G2H_BUFFER_SIZE (4 * CTB_H2G_BUFFER_SIZE)
#define G2H_ROOM_BUFFER_SIZE (CTB_G2H_BUFFER_SIZE / 4)
+#define CTB_SEND_DESC_OFFSET 0u
+#define CTB_RECV_DESC_OFFSET (CTB_DESC_SIZE)
+#define CTB_SEND_CMDS_OFFSET (2 * CTB_DESC_SIZE)
+#define CTB_RECV_CMDS_OFFSET (2 * CTB_DESC_SIZE + CTB_H2G_BUFFER_SIZE)
+
struct ct_request {
struct list_head link;
u32 fence;
@@ -113,9 +123,9 @@ void intel_guc_ct_init_early(struct intel_guc_ct *ct)
init_waitqueue_head(&ct->wq);
}
-static void guc_ct_buffer_desc_init(struct guc_ct_buffer_desc *desc)
+static void guc_ct_buffer_desc_init(struct iosys_map *desc)
{
- memset(desc, 0, sizeof(*desc));
+ iosys_map_memset(desc, 0, 0, sizeof(struct guc_ct_buffer_desc));
}
static void guc_ct_buffer_reset(struct intel_guc_ct_buffer *ctb)
@@ -128,17 +138,18 @@ static void guc_ct_buffer_reset(struct intel_guc_ct_buffer *ctb)
space = CIRC_SPACE(ctb->tail, ctb->head, ctb->size) - ctb->resv_space;
atomic_set(&ctb->space, space);
- guc_ct_buffer_desc_init(ctb->desc);
+ guc_ct_buffer_desc_init(&ctb->desc_map);
}
static void guc_ct_buffer_init(struct intel_guc_ct_buffer *ctb,
- struct guc_ct_buffer_desc *desc,
- u32 *cmds, u32 size_in_bytes, u32 resv_space)
+ struct iosys_map *desc,
+ struct iosys_map *cmds,
+ u32 size_in_bytes, u32 resv_space)
{
GEM_BUG_ON(size_in_bytes % 4);
- ctb->desc = desc;
- ctb->cmds = cmds;
+ ctb->desc_map = *desc;
+ ctb->cmds_map = *cmds;
ctb->size = size_in_bytes / 4;
ctb->resv_space = resv_space / 4;
@@ -218,12 +229,13 @@ static int ct_register_buffer(struct intel_guc_ct *ct, bool send,
int intel_guc_ct_init(struct intel_guc_ct *ct)
{
struct intel_guc *guc = ct_to_guc(ct);
- struct guc_ct_buffer_desc *desc;
+ struct iosys_map blob_map;
+ struct iosys_map desc_map;
+ struct iosys_map cmds_map;
u32 blob_size;
u32 cmds_size;
u32 resv_space;
void *blob;
- u32 *cmds;
int err;
err = i915_inject_probe_error(guc_to_gt(guc)->i915, -ENXIO);
@@ -242,27 +254,35 @@ int intel_guc_ct_init(struct intel_guc_ct *ct)
CT_DEBUG(ct, "base=%#x size=%u\n", intel_guc_ggtt_offset(guc, ct->vma), blob_size);
- /* store pointers to desc and cmds for send ctb */
- desc = blob;
- cmds = blob + 2 * CTB_DESC_SIZE;
+ if (i915_gem_object_is_lmem(ct->vma->obj))
+ iosys_map_set_vaddr_iomem(&blob_map,
+ (void __iomem *)blob);
+ else
+ iosys_map_set_vaddr(&blob_map, blob);
+
+ /* store sysmap to desc_map and cmds_map for send ctb */
+ desc_map = IOSYS_MAP_INIT_OFFSET(&blob_map, CTB_SEND_DESC_OFFSET);
+ cmds_map = IOSYS_MAP_INIT_OFFSET(&blob_map, CTB_SEND_CMDS_OFFSET);
cmds_size = CTB_H2G_BUFFER_SIZE;
resv_space = 0;
- CT_DEBUG(ct, "%s desc %#tx cmds %#tx size %u/%u\n", "send",
- ptrdiff(desc, blob), ptrdiff(cmds, blob), cmds_size,
- resv_space);
+ CT_DEBUG(ct, "%s desc %#x cmds %#x size %u/%u\n", "send",
+ CTB_SEND_DESC_OFFSET, (u32)CTB_SEND_CMDS_OFFSET,
+ cmds_size, resv_space);
- guc_ct_buffer_init(&ct->ctbs.send, desc, cmds, cmds_size, resv_space);
+ guc_ct_buffer_init(&ct->ctbs.send,
+ &desc_map, &cmds_map, cmds_size, resv_space);
- /* store pointers to desc and cmds for recv ctb */
- desc = blob + CTB_DESC_SIZE;
- cmds = blob + 2 * CTB_DESC_SIZE + CTB_H2G_BUFFER_SIZE;
+ /* store sysmap to desc_map and cmds_map for recv ctb */
+ desc_map = IOSYS_MAP_INIT_OFFSET(&blob_map, CTB_RECV_DESC_OFFSET);
+ cmds_map = IOSYS_MAP_INIT_OFFSET(&blob_map, CTB_RECV_CMDS_OFFSET);
cmds_size = CTB_G2H_BUFFER_SIZE;
resv_space = G2H_ROOM_BUFFER_SIZE;
- CT_DEBUG(ct, "%s desc %#tx cmds %#tx size %u/%u\n", "recv",
- ptrdiff(desc, blob), ptrdiff(cmds, blob), cmds_size,
- resv_space);
+ CT_DEBUG(ct, "%s desc %#x cmds %#x size %u/%u\n", "recv",
+ (u32)CTB_RECV_DESC_OFFSET, (u32)CTB_RECV_CMDS_OFFSET,
+ cmds_size, resv_space);
- guc_ct_buffer_init(&ct->ctbs.recv, desc, cmds, cmds_size, resv_space);
+ guc_ct_buffer_init(&ct->ctbs.recv,
+ &desc_map, &cmds_map, cmds_size, resv_space);
return 0;
}
@@ -291,8 +311,8 @@ void intel_guc_ct_fini(struct intel_guc_ct *ct)
int intel_guc_ct_enable(struct intel_guc_ct *ct)
{
struct intel_guc *guc = ct_to_guc(ct);
+ struct iosys_map blob_map;
u32 base, desc, cmds, size;
- void *blob;
int err;
GEM_BUG_ON(ct->enabled);
@@ -302,9 +322,14 @@ int intel_guc_ct_enable(struct intel_guc_ct *ct)
GEM_BUG_ON(!i915_gem_object_has_pinned_pages(ct->vma->obj));
base = intel_guc_ggtt_offset(guc, ct->vma);
+ if (i915_gem_object_is_lmem(ct->vma->obj))
+ iosys_map_set_vaddr_iomem(&blob_map, (void __iomem *)
+ __px_vaddr(ct->vma->obj));
+ else
+ iosys_map_set_vaddr(&blob_map, __px_vaddr(ct->vma->obj));
+
/* blob should start with send descriptor */
- blob = __px_vaddr(ct->vma->obj);
- GEM_BUG_ON(blob != ct->ctbs.send.desc);
+ GEM_BUG_ON(!iosys_map_is_equal(&blob_map, &ct->ctbs.send.desc_map));
/* (re)initialize descriptors */
guc_ct_buffer_reset(&ct->ctbs.send);
@@ -314,15 +339,15 @@ int intel_guc_ct_enable(struct intel_guc_ct *ct)
* Register both CT buffers starting with RECV buffer.
* Descriptors are in first half of the blob.
*/
- desc = base + ptrdiff(ct->ctbs.recv.desc, blob);
- cmds = base + ptrdiff(ct->ctbs.recv.cmds, blob);
+ desc = base + CTB_RECV_DESC_OFFSET;
+ cmds = base + CTB_RECV_CMDS_OFFSET;
size = ct->ctbs.recv.size * 4;
err = ct_register_buffer(ct, false, desc, cmds, size);
if (unlikely(err))
goto err_out;
- desc = base + ptrdiff(ct->ctbs.send.desc, blob);
- cmds = base + ptrdiff(ct->ctbs.send.cmds, blob);
+ desc = base + CTB_SEND_DESC_OFFSET;
+ cmds = base + CTB_SEND_CMDS_OFFSET;
size = ct->ctbs.send.size * 4;
err = ct_register_buffer(ct, true, desc, cmds, size);
if (unlikely(err))
@@ -371,31 +396,32 @@ static int ct_write(struct intel_guc_ct *ct,
u32 fence, u32 flags)
{
struct intel_guc_ct_buffer *ctb = &ct->ctbs.send;
- struct guc_ct_buffer_desc *desc = ctb->desc;
u32 tail = ctb->tail;
u32 size = ctb->size;
u32 header;
u32 hxg;
u32 type;
- u32 *cmds = ctb->cmds;
+ u32 status = ct_desc_read(&ctb->desc_map, status);
unsigned int i;
- if (unlikely(desc->status))
+ if (unlikely(status))
goto corrupted;
GEM_BUG_ON(tail > size);
#ifdef CONFIG_DRM_I915_DEBUG_GUC
- if (unlikely(tail != READ_ONCE(desc->tail))) {
+ if (unlikely(tail != ct_desc_read(&ctb->desc_map, tail))) {
CT_ERROR(ct, "Tail was modified %u != %u\n",
- desc->tail, tail);
- desc->status |= GUC_CTB_STATUS_MISMATCH;
+ ct_desc_read(&ctb->desc_map, tail), tail);
+ status |= GUC_CTB_STATUS_MISMATCH;
+ ct_desc_write(&ctb->desc_map, status, status);
goto corrupted;
}
- if (unlikely(READ_ONCE(desc->head) >= size)) {
+ if (unlikely(ct_desc_read(&ctb->desc_map, head) >= size)) {
CT_ERROR(ct, "Invalid head offset %u >= %u)\n",
- desc->head, size);
- desc->status |= GUC_CTB_STATUS_OVERFLOW;
+ ct_desc_read(&ctb->desc_map, head), size);
+ status |= GUC_CTB_STATUS_OVERFLOW;
+ ct_desc_write(&ctb->desc_map, status, status);
goto corrupted;
}
#endif
@@ -418,14 +444,15 @@ static int ct_write(struct intel_guc_ct *ct,
CT_DEBUG(ct, "writing (tail %u) %*ph %*ph %*ph\n",
tail, 4, &header, 4, &hxg, 4 * (len - 1), &action[1]);
- cmds[tail] = header;
+ iosys_map_wr(&ctb->cmds_map, sizeof(u32) * tail, u32, header);
tail = (tail + 1) % size;
- cmds[tail] = hxg;
+ iosys_map_wr(&ctb->cmds_map, sizeof(u32) * tail, u32, hxg);
tail = (tail + 1) % size;
for (i = 1; i < len; i++) {
- cmds[tail] = action[i];
+ iosys_map_wr(&ctb->cmds_map,
+ sizeof(u32) * tail, u32, action[i]);
tail = (tail + 1) % size;
}
GEM_BUG_ON(tail > size);
@@ -442,13 +469,14 @@ static int ct_write(struct intel_guc_ct *ct,
atomic_sub(len + GUC_CTB_HDR_LEN, &ctb->space);
/* now update descriptor */
- WRITE_ONCE(desc->tail, tail);
+ ct_desc_write(&ctb->desc_map, tail, tail);
return 0;
corrupted:
CT_ERROR(ct, "Corrupted descriptor head=%u tail=%u status=%#x\n",
- desc->head, desc->tail, desc->status);
+ ct_desc_read(&ctb->desc_map, head), ct_desc_read(&ctb->desc_map, tail),
+ ct_desc_read(&ctb->desc_map, status));
ctb->broken = true;
return -EPIPE;
}
@@ -499,20 +527,22 @@ static inline bool ct_deadlocked(struct intel_guc_ct *ct)
bool ret = ktime_ms_delta(ktime_get(), ct->stall_time) > timeout;
if (unlikely(ret)) {
- struct guc_ct_buffer_desc *send = ct->ctbs.send.desc;
- struct guc_ct_buffer_desc *recv = ct->ctbs.send.desc;
-
CT_ERROR(ct, "Communication stalled for %lld ms, desc status=%#x,%#x\n",
ktime_ms_delta(ktime_get(), ct->stall_time),
- send->status, recv->status);
+ ct_desc_read(&ct->ctbs.send.desc_map, status),
+ ct_desc_read(&ct->ctbs.recv.desc_map, status));
CT_ERROR(ct, "H2G Space: %u (Bytes)\n",
atomic_read(&ct->ctbs.send.space) * 4);
- CT_ERROR(ct, "Head: %u (Dwords)\n", ct->ctbs.send.desc->head);
- CT_ERROR(ct, "Tail: %u (Dwords)\n", ct->ctbs.send.desc->tail);
+ CT_ERROR(ct, "Head: %u (Dwords)\n",
+ ct_desc_read(&ct->ctbs.send.desc_map, head));
+ CT_ERROR(ct, "Tail: %u (Dwords)\n",
+ ct_desc_read(&ct->ctbs.send.desc_map, tail));
CT_ERROR(ct, "G2H Space: %u (Bytes)\n",
atomic_read(&ct->ctbs.recv.space) * 4);
- CT_ERROR(ct, "Head: %u\n (Dwords)", ct->ctbs.recv.desc->head);
- CT_ERROR(ct, "Tail: %u\n (Dwords)", ct->ctbs.recv.desc->tail);
+ CT_ERROR(ct, "Head: %u\n (Dwords)",
+ ct_desc_read(&ct->ctbs.recv.desc_map, head));
+ CT_ERROR(ct, "Tail: %u\n (Dwords)",
+ ct_desc_read(&ct->ctbs.recv.desc_map, tail));
ct->ctbs.send.broken = true;
}
@@ -549,18 +579,19 @@ static inline void g2h_release_space(struct intel_guc_ct *ct, u32 g2h_len_dw)
static inline bool h2g_has_room(struct intel_guc_ct *ct, u32 len_dw)
{
struct intel_guc_ct_buffer *ctb = &ct->ctbs.send;
- struct guc_ct_buffer_desc *desc = ctb->desc;
u32 head;
u32 space;
+ u32 status = ct_desc_read(&ctb->desc_map, status);
if (atomic_read(&ctb->space) >= len_dw)
return true;
- head = READ_ONCE(desc->head);
+ head = ct_desc_read(&ctb->desc_map, head);
if (unlikely(head > ctb->size)) {
CT_ERROR(ct, "Invalid head offset %u >= %u)\n",
head, ctb->size);
- desc->status |= GUC_CTB_STATUS_OVERFLOW;
+ status |= GUC_CTB_STATUS_OVERFLOW;
+ ct_desc_write(&ctb->desc_map, status, status);
ctb->broken = true;
return false;
}
@@ -803,11 +834,10 @@ static void ct_free_msg(struct ct_incoming_msg *msg)
static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg)
{
struct intel_guc_ct_buffer *ctb = &ct->ctbs.recv;
- struct guc_ct_buffer_desc *desc = ctb->desc;
u32 head = ctb->head;
- u32 tail = READ_ONCE(desc->tail);
+ u32 tail = ct_desc_read(&ctb->desc_map, tail);
u32 size = ctb->size;
- u32 *cmds = ctb->cmds;
+ u32 status = ct_desc_read(&ctb->desc_map, status);
s32 available;
unsigned int len;
unsigned int i;
@@ -816,23 +846,25 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg)
if (unlikely(ctb->broken))
return -EPIPE;
- if (unlikely(desc->status))
+ if (unlikely(status))
goto corrupted;
GEM_BUG_ON(head > size);
#ifdef CONFIG_DRM_I915_DEBUG_GUC
- if (unlikely(head != READ_ONCE(desc->head))) {
+ if (unlikely(head != ct_desc_read(&ctb->desc_map, head))) {
CT_ERROR(ct, "Head was modified %u != %u\n",
- desc->head, head);
- desc->status |= GUC_CTB_STATUS_MISMATCH;
+ ct_desc_read(&ctb->desc_map, head), head);
+ status |= GUC_CTB_STATUS_MISMATCH;
+ ct_desc_write(&ctb->desc_map, status, status);
goto corrupted;
}
#endif
if (unlikely(tail >= size)) {
CT_ERROR(ct, "Invalid tail offset %u >= %u)\n",
tail, size);
- desc->status |= GUC_CTB_STATUS_OVERFLOW;
+ status |= GUC_CTB_STATUS_OVERFLOW;
+ ct_desc_write(&ctb->desc_map, status, status);
goto corrupted;
}
@@ -849,7 +881,7 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg)
CT_DEBUG(ct, "available %d (%u:%u:%u)\n", available, head, tail, size);
GEM_BUG_ON(available < 0);
- header = cmds[head];
+ header = iosys_map_rd(&ctb->cmds_map, sizeof(u32) * head, u32);
head = (head + 1) % size;
/* message len with header */
@@ -857,11 +889,15 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg)
if (unlikely(len > (u32)available)) {
CT_ERROR(ct, "Incomplete message %*ph %*ph %*ph\n",
4, &header,
+ 4 * (head + available - 1 > size ? size - head :
+ available - 1), ((__px_vaddr(ct->vma->obj) +
+ CTB_RECV_CMDS_OFFSET) + (4 * head)),
4 * (head + available - 1 > size ?
- size - head : available - 1), &cmds[head],
- 4 * (head + available - 1 > size ?
- available - 1 - size + head : 0), &cmds[0]);
- desc->status |= GUC_CTB_STATUS_UNDERFLOW;
+ available - 1 - size + head : 0),
+ (__px_vaddr(ct->vma->obj) + CTB_RECV_CMDS_OFFSET));
+ status = ct_desc_read(&ctb->desc_map, status) |
+ GUC_CTB_STATUS_UNDERFLOW;
+ ct_desc_write(&ctb->desc_map, status, status);
goto corrupted;
}
@@ -869,17 +905,20 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg)
if (!*msg) {
CT_ERROR(ct, "No memory for message %*ph %*ph %*ph\n",
4, &header,
+ 4 * (head + available - 1 > size ? size - head :
+ available - 1), ((__px_vaddr(ct->vma->obj) +
+ CTB_RECV_CMDS_OFFSET) + (4 * head)),
4 * (head + available - 1 > size ?
- size - head : available - 1), &cmds[head],
- 4 * (head + available - 1 > size ?
- available - 1 - size + head : 0), &cmds[0]);
+ available - 1 - size + head : 0),
+ (__px_vaddr(ct->vma->obj) + CTB_RECV_CMDS_OFFSET));
return available;
}
(*msg)->msg[0] = header;
for (i = 1; i < len; i++) {
- (*msg)->msg[i] = cmds[head];
+ (*msg)->msg[i] = iosys_map_rd(&ctb->cmds_map,
+ sizeof(u32) * head, u32);
head = (head + 1) % size;
}
CT_DEBUG(ct, "received %*ph\n", 4 * len, (*msg)->msg);
@@ -888,13 +927,15 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg)
ctb->head = head;
/* now update descriptor */
- WRITE_ONCE(desc->head, head);
+ ct_desc_write(&ctb->desc_map, head, head);
return available - len;
corrupted:
CT_ERROR(ct, "Corrupted descriptor head=%u tail=%u status=%#x\n",
- desc->head, desc->tail, desc->status);
+ ct_desc_read(&ctb->desc_map, head),
+ ct_desc_read(&ctb->desc_map, tail),
+ ct_desc_read(&ctb->desc_map, status));
ctb->broken = true;
return -EPIPE;
}
@@ -1211,13 +1252,13 @@ void intel_guc_ct_print_info(struct intel_guc_ct *ct,
drm_printf(p, "H2G Space: %u\n",
atomic_read(&ct->ctbs.send.space) * 4);
drm_printf(p, "Head: %u\n",
- ct->ctbs.send.desc->head);
+ ct_desc_read(&ct->ctbs.send.desc_map, head));
drm_printf(p, "Tail: %u\n",
- ct->ctbs.send.desc->tail);
+ ct_desc_read(&ct->ctbs.send.desc_map, tail));
drm_printf(p, "G2H Space: %u\n",
atomic_read(&ct->ctbs.recv.space) * 4);
drm_printf(p, "Head: %u\n",
- ct->ctbs.recv.desc->head);
+ ct_desc_read(&ct->ctbs.recv.desc_map, head));
drm_printf(p, "Tail: %u\n",
- ct->ctbs.recv.desc->tail);
+ ct_desc_read(&ct->ctbs.recv.desc_map, tail));
}
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h
index f709a19c7e21..867fe13fb47d 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h
@@ -7,6 +7,7 @@
#define _INTEL_GUC_CT_H_
#include <linux/interrupt.h>
+#include <linux/iosys-map.h>
#include <linux/spinlock.h>
#include <linux/workqueue.h>
#include <linux/ktime.h>
@@ -32,8 +33,8 @@ struct drm_printer;
* holds the commands.
*
* @lock: protects access to the commands buffer and buffer descriptor
- * @desc: pointer to the buffer descriptor
- * @cmds: pointer to the commands buffer
+ * @desc: iosys map to the buffer descriptor
+ * @cmds: iosys map to the commands buffer
* @size: size of the commands buffer in dwords
* @resv_space: reserved space in buffer in dwords
* @head: local shadow copy of head in dwords
@@ -43,8 +44,8 @@ struct drm_printer;
*/
struct intel_guc_ct_buffer {
spinlock_t lock;
- struct guc_ct_buffer_desc *desc;
- u32 *cmds;
+ struct iosys_map desc_map;
+ struct iosys_map cmds_map;
u32 size;
u32 resv_space;
u32 tail;
--
2.33.0
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Refactor CT access to use iosys_map
2022-04-21 17:26 [Intel-gfx] [PATCH 0/1] Refactor CT access to use iosys_map Mullati Siva
2022-04-21 17:26 ` [Intel-gfx] [PATCH 1/1] drm/i915/guc: Convert ct buffer to iosys_map Mullati Siva
@ 2022-04-21 21:40 ` Patchwork
2022-04-21 22:06 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-04-22 2:36 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
3 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2022-04-21 21:40 UTC (permalink / raw)
To: Mullati Siva; +Cc: intel-gfx
== Series Details ==
Series: Refactor CT access to use iosys_map
URL : https://patchwork.freedesktop.org/series/102949/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 14+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for Refactor CT access to use iosys_map
2022-04-21 17:26 [Intel-gfx] [PATCH 0/1] Refactor CT access to use iosys_map Mullati Siva
2022-04-21 17:26 ` [Intel-gfx] [PATCH 1/1] drm/i915/guc: Convert ct buffer to iosys_map Mullati Siva
2022-04-21 21:40 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Refactor CT access to use iosys_map Patchwork
@ 2022-04-21 22:06 ` Patchwork
2022-04-22 2:36 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
3 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2022-04-21 22:06 UTC (permalink / raw)
To: Mullati Siva; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 9879 bytes --]
== Series Details ==
Series: Refactor CT access to use iosys_map
URL : https://patchwork.freedesktop.org/series/102949/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11537 -> Patchwork_102949v1
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/index.html
Participating hosts (45 -> 46)
------------------------------
Additional (3): fi-cml-u2 fi-bdw-gvtdvm fi-bdw-5557u
Missing (2): bat-dg2-8 fi-bsw-cyan
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_102949v1:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_suspend@system-suspend-without-i915:
- {bat-dg2-9}: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11537/bat-dg2-9/igt@i915_suspend@system-suspend-without-i915.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/bat-dg2-9/igt@i915_suspend@system-suspend-without-i915.html
Known issues
------------
Here are the changes found in Patchwork_102949v1 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@fbdev@write:
- fi-bdw-gvtdvm: NOTRUN -> [SKIP][3] ([fdo#109271]) +5 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/fi-bdw-gvtdvm/igt@fbdev@write.html
* igt@gem_exec_fence@basic-busy@bcs0:
- fi-cml-u2: NOTRUN -> [SKIP][4] ([i915#1208]) +1 similar issue
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/fi-cml-u2/igt@gem_exec_fence@basic-busy@bcs0.html
* igt@gem_exec_suspend@basic-s0@smem:
- fi-bdw-gvtdvm: NOTRUN -> [INCOMPLETE][5] ([i915#4831])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/fi-bdw-gvtdvm/igt@gem_exec_suspend@basic-s0@smem.html
* igt@gem_huc_copy@huc-copy:
- fi-cml-u2: NOTRUN -> [SKIP][6] ([i915#2190])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/fi-cml-u2/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@parallel-random-engines:
- fi-cml-u2: NOTRUN -> [SKIP][7] ([i915#4613]) +3 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/fi-cml-u2/igt@gem_lmem_swapping@parallel-random-engines.html
* igt@i915_selftest@live@gt_engines:
- bat-dg1-5: [PASS][8] -> [INCOMPLETE][9] ([i915#4418])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11537/bat-dg1-5/igt@i915_selftest@live@gt_engines.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/bat-dg1-5/igt@i915_selftest@live@gt_engines.html
* igt@i915_selftest@live@hangcheck:
- fi-hsw-4770: [PASS][10] -> [INCOMPLETE][11] ([i915#4785])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11537/fi-hsw-4770/igt@i915_selftest@live@hangcheck.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/fi-hsw-4770/igt@i915_selftest@live@hangcheck.html
* igt@kms_busy@basic@flip:
- bat-adlp-4: [PASS][12] -> [DMESG-WARN][13] ([i915#3576])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11537/bat-adlp-4/igt@kms_busy@basic@flip.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/bat-adlp-4/igt@kms_busy@basic@flip.html
* igt@kms_chamelium@dp-hpd-fast:
- fi-cml-u2: NOTRUN -> [SKIP][14] ([fdo#109284] / [fdo#111827]) +8 similar issues
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/fi-cml-u2/igt@kms_chamelium@dp-hpd-fast.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-cml-u2: NOTRUN -> [SKIP][15] ([fdo#109278]) +1 similar issue
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/fi-cml-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@kms_force_connector_basic@force-load-detect:
- fi-cml-u2: NOTRUN -> [SKIP][16] ([fdo#109285])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/fi-cml-u2/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-cml-u2: NOTRUN -> [SKIP][17] ([fdo#109278] / [i915#533])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/fi-cml-u2/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
* igt@kms_setmode@basic-clone-single-crtc:
- fi-cml-u2: NOTRUN -> [SKIP][18] ([i915#3555])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/fi-cml-u2/igt@kms_setmode@basic-clone-single-crtc.html
* igt@prime_vgem@basic-userptr:
- fi-cml-u2: NOTRUN -> [SKIP][19] ([i915#3301])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/fi-cml-u2/igt@prime_vgem@basic-userptr.html
* igt@runner@aborted:
- bat-dg1-5: NOTRUN -> [FAIL][20] ([i915#4312] / [i915#5257])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/bat-dg1-5/igt@runner@aborted.html
- fi-bdw-5557u: NOTRUN -> [FAIL][21] ([i915#4312])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/fi-bdw-5557u/igt@runner@aborted.html
#### Possible fixes ####
* igt@i915_selftest@live@gt_heartbeat:
- {fi-tgl-dsi}: [DMESG-FAIL][22] ([i915#5334]) -> [PASS][23]
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11537/fi-tgl-dsi/igt@i915_selftest@live@gt_heartbeat.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/fi-tgl-dsi/igt@i915_selftest@live@gt_heartbeat.html
* igt@i915_selftest@live@hangcheck:
- fi-snb-2600: [INCOMPLETE][24] ([i915#3921]) -> [PASS][25]
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11537/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
* igt@kms_flip@basic-flip-vs-modeset@a-edp1:
- {bat-adlp-6}: [DMESG-WARN][26] ([i915#3576]) -> [PASS][27]
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11537/bat-adlp-6/igt@kms_flip@basic-flip-vs-modeset@a-edp1.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/bat-adlp-6/igt@kms_flip@basic-flip-vs-modeset@a-edp1.html
* igt@kms_flip@basic-plain-flip@a-edp1:
- bat-adlp-4: [DMESG-WARN][28] ([i915#3576]) -> [PASS][29] +1 similar issue
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11537/bat-adlp-4/igt@kms_flip@basic-plain-flip@a-edp1.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/bat-adlp-4/igt@kms_flip@basic-plain-flip@a-edp1.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109308]: https://bugs.freedesktop.org/show_bug.cgi?id=109308
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
[i915#1208]: https://gitlab.freedesktop.org/drm/intel/issues/1208
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3576]: https://gitlab.freedesktop.org/drm/intel/issues/3576
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4391]: https://gitlab.freedesktop.org/drm/intel/issues/4391
[i915#4418]: https://gitlab.freedesktop.org/drm/intel/issues/4418
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4785]: https://gitlab.freedesktop.org/drm/intel/issues/4785
[i915#4831]: https://gitlab.freedesktop.org/drm/intel/issues/4831
[i915#4897]: https://gitlab.freedesktop.org/drm/intel/issues/4897
[i915#5257]: https://gitlab.freedesktop.org/drm/intel/issues/5257
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
[i915#5341]: https://gitlab.freedesktop.org/drm/intel/issues/5341
[i915#5647]: https://gitlab.freedesktop.org/drm/intel/issues/5647
Build changes
-------------
* Linux: CI_DRM_11537 -> Patchwork_102949v1
CI-20190529: 20190529
CI_DRM_11537: d3f1b43f64dc51bfbb59fab5c6b950159c77207e @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6444: df584c804e3a44431b0e5ae21c190b6e9acb35ab @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_102949v1: d3f1b43f64dc51bfbb59fab5c6b950159c77207e @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
6b2030289de8 drm/i915/guc: Convert ct buffer to iosys_map
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/index.html
[-- Attachment #2: Type: text/html, Size: 10266 bytes --]
^ permalink raw reply [flat|nested] 14+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for Refactor CT access to use iosys_map
2022-04-21 17:26 [Intel-gfx] [PATCH 0/1] Refactor CT access to use iosys_map Mullati Siva
` (2 preceding siblings ...)
2022-04-21 22:06 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2022-04-22 2:36 ` Patchwork
3 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2022-04-22 2:36 UTC (permalink / raw)
To: Mullati Siva; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 56106 bytes --]
== Series Details ==
Series: Refactor CT access to use iosys_map
URL : https://patchwork.freedesktop.org/series/102949/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11537_full -> Patchwork_102949v1_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_102949v1_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_102949v1_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (13 -> 13)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_102949v1_full:
### IGT changes ###
#### Possible regressions ####
* igt@i915_selftest@live@hangcheck:
- shard-tglb: [PASS][1] -> [DMESG-WARN][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11537/shard-tglb6/igt@i915_selftest@live@hangcheck.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-tglb3/igt@i915_selftest@live@hangcheck.html
* igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-pwrite:
- shard-tglb: [PASS][3] -> [INCOMPLETE][4] +1 similar issue
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11537/shard-tglb8/igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-pwrite.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-tglb8/igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-pwrite.html
Known issues
------------
Here are the changes found in Patchwork_102949v1_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_isolation@preservation-s3@vcs0:
- shard-apl: NOTRUN -> [DMESG-WARN][5] ([i915#180])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-apl8/igt@gem_ctx_isolation@preservation-s3@vcs0.html
* igt@gem_eio@in-flight-contexts-1us:
- shard-tglb: [PASS][6] -> [TIMEOUT][7] ([i915#3063])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11537/shard-tglb2/igt@gem_eio@in-flight-contexts-1us.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-tglb7/igt@gem_eio@in-flight-contexts-1us.html
* igt@gem_eio@unwedge-stress:
- shard-tglb: [PASS][8] -> [FAIL][9] ([i915#232])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11537/shard-tglb7/igt@gem_eio@unwedge-stress.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-tglb1/igt@gem_eio@unwedge-stress.html
- shard-skl: [PASS][10] -> [TIMEOUT][11] ([i915#3063])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11537/shard-skl8/igt@gem_eio@unwedge-stress.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-skl7/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_balancer@parallel-contexts:
- shard-kbl: NOTRUN -> [DMESG-WARN][12] ([i915#5076] / [i915#5614])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-kbl6/igt@gem_exec_balancer@parallel-contexts.html
* igt@gem_exec_balancer@parallel-ordering:
- shard-kbl: NOTRUN -> [DMESG-FAIL][13] ([i915#5076] / [i915#5614])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-kbl3/igt@gem_exec_balancer@parallel-ordering.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-iclb: [PASS][14] -> [FAIL][15] ([i915#2842])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11537/shard-iclb7/igt@gem_exec_fair@basic-none-share@rcs0.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-iclb1/igt@gem_exec_fair@basic-none-share@rcs0.html
- shard-tglb: [PASS][16] -> [FAIL][17] ([i915#2842])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11537/shard-tglb2/igt@gem_exec_fair@basic-none-share@rcs0.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-tglb8/igt@gem_exec_fair@basic-none-share@rcs0.html
* igt@gem_exec_fair@basic-none@vcs0:
- shard-kbl: [PASS][18] -> [FAIL][19] ([i915#2842]) +1 similar issue
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11537/shard-kbl4/igt@gem_exec_fair@basic-none@vcs0.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-kbl1/igt@gem_exec_fair@basic-none@vcs0.html
* igt@gem_exec_flush@basic-uc-set-default:
- shard-snb: [PASS][20] -> [SKIP][21] ([fdo#109271]) +3 similar issues
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11537/shard-snb5/igt@gem_exec_flush@basic-uc-set-default.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-snb6/igt@gem_exec_flush@basic-uc-set-default.html
* igt@gem_exec_params@no-vebox:
- shard-iclb: NOTRUN -> [SKIP][22] ([fdo#109283])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-iclb7/igt@gem_exec_params@no-vebox.html
- shard-tglb: NOTRUN -> [SKIP][23] ([fdo#109283] / [i915#4877])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-tglb3/igt@gem_exec_params@no-vebox.html
* igt@gem_exec_whisper@basic-queues-priority:
- shard-glk: [PASS][24] -> [DMESG-WARN][25] ([i915#118])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11537/shard-glk4/igt@gem_exec_whisper@basic-queues-priority.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-glk5/igt@gem_exec_whisper@basic-queues-priority.html
* igt@gem_huc_copy@huc-copy:
- shard-tglb: [PASS][26] -> [SKIP][27] ([i915#2190])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11537/shard-tglb5/igt@gem_huc_copy@huc-copy.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-tglb6/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@parallel-random-verify-ccs:
- shard-skl: NOTRUN -> [SKIP][28] ([fdo#109271] / [i915#4613]) +3 similar issues
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-skl1/igt@gem_lmem_swapping@parallel-random-verify-ccs.html
* igt@gem_lmem_swapping@smem-oom:
- shard-iclb: NOTRUN -> [SKIP][29] ([i915#4613])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-iclb7/igt@gem_lmem_swapping@smem-oom.html
* igt@gem_lmem_swapping@verify-random-ccs:
- shard-kbl: NOTRUN -> [SKIP][30] ([fdo#109271] / [i915#4613])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-kbl3/igt@gem_lmem_swapping@verify-random-ccs.html
* igt@gem_pread@exhaustion:
- shard-skl: NOTRUN -> [WARN][31] ([i915#2658])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-skl1/igt@gem_pread@exhaustion.html
* igt@gem_render_copy@x-tiled-to-vebox-y-tiled:
- shard-iclb: NOTRUN -> [SKIP][32] ([i915#768])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-iclb7/igt@gem_render_copy@x-tiled-to-vebox-y-tiled.html
* igt@gem_userptr_blits@vma-merge:
- shard-apl: NOTRUN -> [FAIL][33] ([i915#3318])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-apl7/igt@gem_userptr_blits@vma-merge.html
- shard-glk: NOTRUN -> [FAIL][34] ([i915#3318])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-glk2/igt@gem_userptr_blits@vma-merge.html
- shard-kbl: NOTRUN -> [FAIL][35] ([i915#3318])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-kbl6/igt@gem_userptr_blits@vma-merge.html
* igt@i915_pm_dc@dc6-dpms:
- shard-skl: NOTRUN -> [FAIL][36] ([i915#454])
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-skl7/igt@i915_pm_dc@dc6-dpms.html
* igt@i915_suspend@debugfs-reader:
- shard-kbl: [PASS][37] -> [INCOMPLETE][38] ([i915#3614])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11537/shard-kbl7/igt@i915_suspend@debugfs-reader.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-kbl4/igt@i915_suspend@debugfs-reader.html
* igt@kms_big_fb@4-tiled-16bpp-rotate-270:
- shard-iclb: NOTRUN -> [SKIP][39] ([i915#5286])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-iclb8/igt@kms_big_fb@4-tiled-16bpp-rotate-270.html
* igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-async-flip:
- shard-tglb: NOTRUN -> [SKIP][40] ([i915#5286])
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-tglb5/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html
* igt@kms_big_fb@linear-16bpp-rotate-270:
- shard-iclb: NOTRUN -> [SKIP][41] ([fdo#110725] / [fdo#111614])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-iclb7/igt@kms_big_fb@linear-16bpp-rotate-270.html
* igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-hflip:
- shard-kbl: NOTRUN -> [SKIP][42] ([fdo#109271] / [i915#3777])
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-kbl3/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-hflip.html
* igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip:
- shard-skl: NOTRUN -> [SKIP][43] ([fdo#109271] / [i915#3777]) +2 similar issues
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-skl1/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html
* igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip:
- shard-apl: NOTRUN -> [SKIP][44] ([fdo#109271] / [i915#3777])
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-apl8/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip.html
* igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-async-flip:
- shard-skl: NOTRUN -> [FAIL][45] ([i915#3763])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-skl1/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-async-flip:
- shard-skl: NOTRUN -> [FAIL][46] ([i915#3743]) +1 similar issue
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-skl1/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-async-flip.html
* igt@kms_ccs@pipe-a-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc:
- shard-kbl: NOTRUN -> [SKIP][47] ([fdo#109271] / [i915#3886]) +1 similar issue
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-kbl3/igt@kms_ccs@pipe-a-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc:
- shard-iclb: NOTRUN -> [SKIP][48] ([fdo#109278] / [i915#3886]) +1 similar issue
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-iclb7/igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-a-random-ccs-data-y_tiled_gen12_rc_ccs_cc:
- shard-apl: NOTRUN -> [SKIP][49] ([fdo#109271] / [i915#3886]) +2 similar issues
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-apl4/igt@kms_ccs@pipe-a-random-ccs-data-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-b-bad-pixel-format-y_tiled_gen12_rc_ccs_cc:
- shard-glk: NOTRUN -> [SKIP][50] ([fdo#109271] / [i915#3886])
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-glk3/igt@kms_ccs@pipe-b-bad-pixel-format-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-c-bad-pixel-format-yf_tiled_ccs:
- shard-tglb: NOTRUN -> [SKIP][51] ([fdo#111615] / [i915#3689])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-tglb3/igt@kms_ccs@pipe-c-bad-pixel-format-yf_tiled_ccs.html
* igt@kms_ccs@pipe-c-missing-ccs-buffer-y_tiled_gen12_mc_ccs:
- shard-skl: NOTRUN -> [SKIP][52] ([fdo#109271] / [i915#3886]) +8 similar issues
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-skl10/igt@kms_ccs@pipe-c-missing-ccs-buffer-y_tiled_gen12_mc_ccs.html
* igt@kms_chamelium@hdmi-audio:
- shard-iclb: NOTRUN -> [SKIP][53] ([fdo#109284] / [fdo#111827]) +1 similar issue
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-iclb8/igt@kms_chamelium@hdmi-audio.html
* igt@kms_chamelium@hdmi-edid-change-during-suspend:
- shard-apl: NOTRUN -> [SKIP][54] ([fdo#109271] / [fdo#111827]) +8 similar issues
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-apl4/igt@kms_chamelium@hdmi-edid-change-during-suspend.html
* igt@kms_chamelium@hdmi-hpd-for-each-pipe:
- shard-glk: NOTRUN -> [SKIP][55] ([fdo#109271] / [fdo#111827]) +1 similar issue
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-glk2/igt@kms_chamelium@hdmi-hpd-for-each-pipe.html
* igt@kms_chamelium@hdmi-hpd-storm:
- shard-tglb: NOTRUN -> [SKIP][56] ([fdo#109284] / [fdo#111827])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-tglb3/igt@kms_chamelium@hdmi-hpd-storm.html
* igt@kms_color_chamelium@pipe-b-ctm-max:
- shard-skl: NOTRUN -> [SKIP][57] ([fdo#109271] / [fdo#111827]) +13 similar issues
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-skl1/igt@kms_color_chamelium@pipe-b-ctm-max.html
* igt@kms_color_chamelium@pipe-b-gamma:
- shard-kbl: NOTRUN -> [SKIP][58] ([fdo#109271] / [fdo#111827]) +2 similar issues
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-kbl3/igt@kms_color_chamelium@pipe-b-gamma.html
* igt@kms_color_chamelium@pipe-d-ctm-green-to-red:
- shard-iclb: NOTRUN -> [SKIP][59] ([fdo#109278] / [fdo#109284] / [fdo#111827])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-iclb7/igt@kms_color_chamelium@pipe-d-ctm-green-to-red.html
* igt@kms_content_protection@srm:
- shard-apl: NOTRUN -> [TIMEOUT][60] ([i915#1319])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-apl4/igt@kms_content_protection@srm.html
* igt@kms_cursor_crc@pipe-c-cursor-max-size-random:
- shard-iclb: NOTRUN -> [SKIP][61] ([fdo#109278]) +4 similar issues
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-iclb7/igt@kms_cursor_crc@pipe-c-cursor-max-size-random.html
- shard-tglb: NOTRUN -> [SKIP][62] ([i915#3359])
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-tglb3/igt@kms_cursor_crc@pipe-c-cursor-max-size-random.html
* igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size:
- shard-tglb: NOTRUN -> [SKIP][63] ([fdo#109274] / [fdo#111825])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-tglb3/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size.html
- shard-iclb: NOTRUN -> [SKIP][64] ([fdo#109274] / [fdo#109278])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-iclb7/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size.html
* igt@kms_cursor_legacy@pipe-d-torture-move:
- shard-skl: NOTRUN -> [SKIP][65] ([fdo#109271]) +216 similar issues
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-skl10/igt@kms_cursor_legacy@pipe-d-torture-move.html
* igt@kms_flip@flip-vs-suspend-interruptible@a-dp1:
- shard-kbl: [PASS][66] -> [DMESG-WARN][67] ([i915#180]) +8 similar issues
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11537/shard-kbl7/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-kbl4/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
* igt@kms_flip@flip-vs-suspend@c-edp1:
- shard-skl: [PASS][68] -> [INCOMPLETE][69] ([i915#4839])
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11537/shard-skl1/igt@kms_flip@flip-vs-suspend@c-edp1.html
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-skl4/igt@kms_flip@flip-vs-suspend@c-edp1.html
* igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1:
- shard-skl: [PASS][70] -> [FAIL][71] ([i915#2122]) +1 similar issue
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11537/shard-skl8/igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1.html
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-skl4/igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-mmap-wc:
- shard-iclb: NOTRUN -> [SKIP][72] ([fdo#109280]) +2 similar issues
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-iclb7/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-onoff:
- shard-tglb: NOTRUN -> [SKIP][73] ([fdo#109280] / [fdo#111825])
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-tglb3/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-onoff.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-mmap-wc:
- shard-kbl: NOTRUN -> [SKIP][74] ([fdo#109271]) +49 similar issues
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-kbl3/igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@psr-2p-scndscrn-shrfb-msflip-blt:
- shard-glk: NOTRUN -> [SKIP][75] ([fdo#109271]) +19 similar issues
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-glk2/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-shrfb-msflip-blt.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
- shard-skl: NOTRUN -> [INCOMPLETE][76] ([i915#4444])
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-skl6/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-basic:
- shard-apl: NOTRUN -> [FAIL][77] ([fdo#108145] / [i915#265])
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-apl8/igt@kms_plane_alpha_blend@pipe-a-alpha-basic.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb:
- shard-skl: NOTRUN -> [FAIL][78] ([fdo#108145] / [i915#265])
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-skl10/igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb.html
* igt@kms_psr2_sf@overlay-plane-update-continuous-sf:
- shard-skl: NOTRUN -> [SKIP][79] ([fdo#109271] / [i915#658]) +1 similar issue
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-skl1/igt@kms_psr2_sf@overlay-plane-update-continuous-sf.html
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area:
- shard-kbl: NOTRUN -> [SKIP][80] ([fdo#109271] / [i915#658])
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-kbl3/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area.html
* igt@kms_vblank@pipe-c-ts-continuation-suspend:
- shard-apl: [PASS][81] -> [DMESG-WARN][82] ([i915#180])
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11537/shard-apl3/igt@kms_vblank@pipe-c-ts-continuation-suspend.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-apl6/igt@kms_vblank@pipe-c-ts-continuation-suspend.html
* igt@kms_vblank@pipe-d-wait-forked-hang:
- shard-apl: NOTRUN -> [SKIP][83] ([fdo#109271]) +102 similar issues
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-apl4/igt@kms_vblank@pipe-d-wait-forked-hang.html
* igt@kms_vblank@pipe-d-wait-idle:
- shard-skl: NOTRUN -> [SKIP][84] ([fdo#109271] / [i915#533]) +1 similar issue
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-skl1/igt@kms_vblank@pipe-d-wait-idle.html
* igt@kms_writeback@writeback-invalid-parameters:
- shard-apl: NOTRUN -> [SKIP][85] ([fdo#109271] / [i915#2437])
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-apl8/igt@kms_writeback@writeback-invalid-parameters.html
* igt@nouveau_crc@pipe-d-source-outp-inactive:
- shard-tglb: NOTRUN -> [SKIP][86] ([i915#2530]) +1 similar issue
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-tglb3/igt@nouveau_crc@pipe-d-source-outp-inactive.html
- shard-iclb: NOTRUN -> [SKIP][87] ([fdo#109278] / [i915#2530])
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-iclb7/igt@nouveau_crc@pipe-d-source-outp-inactive.html
* igt@perf@polling-parameterized:
- shard-skl: NOTRUN -> [FAIL][88] ([i915#5639])
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-skl10/igt@perf@polling-parameterized.html
- shard-tglb: [PASS][89] -> [FAIL][90] ([i915#5639])
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11537/shard-tglb5/igt@perf@polling-parameterized.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-tglb2/igt@perf@polling-parameterized.html
* igt@perf@stress-open-close:
- shard-glk: [PASS][91] -> [DMESG-FAIL][92] ([i915#5386])
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11537/shard-glk1/igt@perf@stress-open-close.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-glk8/igt@perf@stress-open-close.html
* igt@prime_nv_api@i915_nv_double_import:
- shard-tglb: NOTRUN -> [SKIP][93] ([fdo#109291])
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-tglb3/igt@prime_nv_api@i915_nv_double_import.html
- shard-iclb: NOTRUN -> [SKIP][94] ([fdo#109291])
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-iclb7/igt@prime_nv_api@i915_nv_double_import.html
* igt@syncobj_timeline@invalid-transfer-non-existent-point:
- shard-apl: NOTRUN -> [DMESG-WARN][95] ([i915#5098])
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-apl3/igt@syncobj_timeline@invalid-transfer-non-existent-point.html
- shard-glk: NOTRUN -> [DMESG-WARN][96] ([i915#5098])
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-glk3/igt@syncobj_timeline@invalid-transfer-non-existent-point.html
* igt@sysfs_clients@fair-0:
- shard-skl: NOTRUN -> [SKIP][97] ([fdo#109271] / [i915#2994]) +3 similar issues
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-skl10/igt@sysfs_clients@fair-0.html
#### Possible fixes ####
* igt@gem_eio@in-flight-contexts-1us:
- {shard-rkl}: [TIMEOUT][98] ([i915#3063]) -> [PASS][99]
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11537/shard-rkl-6/igt@gem_eio@in-flight-contexts-1us.html
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-rkl-1/igt@gem_eio@in-flight-contexts-1us.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- {shard-tglu}: [FAIL][100] ([i915#2842]) -> [PASS][101]
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11537/shard-tglu-2/igt@gem_exec_fair@basic-none-share@rcs0.html
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-tglu-4/igt@gem_exec_fair@basic-none-share@rcs0.html
* igt@gem_exec_fair@basic-none@vcs1:
- shard-kbl: [FAIL][102] ([i915#2842]) -> [PASS][103]
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11537/shard-kbl4/igt@gem_exec_fair@basic-none@vcs1.html
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-kbl1/igt@gem_exec_fair@basic-none@vcs1.html
* igt@gem_exec_fair@basic-none@vecs0:
- shard-apl: [FAIL][104] ([i915#2842]) -> [PASS][105]
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11537/shard-apl8/igt@gem_exec_fair@basic-none@vecs0.html
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-apl8/igt@gem_exec_fair@basic-none@vecs0.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-glk: [FAIL][106] ([i915#2842]) -> [PASS][107] +1 similar issue
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11537/shard-glk3/igt@gem_exec_fair@basic-throttle@rcs0.html
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-glk6/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@gem_exec_flush@basic-uc-rw-default:
- shard-snb: [SKIP][108] ([fdo#109271]) -> [PASS][109] +1 similar issue
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11537/shard-snb6/igt@gem_exec_flush@basic-uc-rw-default.html
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-snb2/igt@gem_exec_flush@basic-uc-rw-default.html
* igt@gem_exec_whisper@basic-fds-priority:
- shard-glk: [DMESG-WARN][110] ([i915#118]) -> [PASS][111] +1 similar issue
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11537/shard-glk2/igt@gem_exec_whisper@basic-fds-priority.html
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-glk3/igt@gem_exec_whisper@basic-fds-priority.html
* igt@gem_mmap_wc@set-cache-level:
- {shard-rkl}: [SKIP][112] ([i915#1850]) -> [PASS][113]
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11537/shard-rkl-4/igt@gem_mmap_wc@set-cache-level.html
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-rkl-6/igt@gem_mmap_wc@set-cache-level.html
* igt@gem_workarounds@suspend-resume:
- shard-kbl: [DMESG-WARN][114] ([i915#180]) -> [PASS][115] +1 similar issue
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11537/shard-kbl4/igt@gem_workarounds@suspend-resume.html
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-kbl3/igt@gem_workarounds@suspend-resume.html
* igt@gen9_exec_parse@allowed-single:
- shard-glk: [DMESG-WARN][116] ([i915#5566] / [i915#716]) -> [PASS][117] +1 similar issue
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11537/shard-glk2/igt@gen9_exec_parse@allowed-single.html
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-glk3/igt@gen9_exec_parse@allowed-single.html
- shard-apl: [DMESG-WARN][118] ([i915#5566] / [i915#716]) -> [PASS][119] +1 similar issue
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11537/shard-apl8/igt@gen9_exec_parse@allowed-single.html
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-apl3/igt@gen9_exec_parse@allowed-single.html
* igt@i915_pm_dc@dc6-psr:
- shard-iclb: [FAIL][120] ([i915#454]) -> [PASS][121]
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11537/shard-iclb3/igt@i915_pm_dc@dc6-psr.html
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-iclb1/igt@i915_pm_dc@dc6-psr.html
* igt@i915_pm_rpm@i2c:
- {shard-rkl}: [SKIP][122] ([fdo#109308]) -> [PASS][123]
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11537/shard-rkl-4/igt@i915_pm_rpm@i2c.html
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-rkl-6/igt@i915_pm_rpm@i2c.html
* igt@kms_atomic@test-only:
- {shard-rkl}: [SKIP][124] ([i915#1845] / [i915#4098]) -> [PASS][125] +15 similar issues
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11537/shard-rkl-2/igt@kms_atomic@test-only.html
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-rkl-6/igt@kms_atomic@test-only.html
* igt@kms_big_fb@y-tiled-32bpp-rotate-270:
- {shard-rkl}: ([SKIP][126], [SKIP][127]) ([i915#1845] / [i915#4098]) -> [PASS][128] +1 similar issue
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11537/shard-rkl-4/igt@kms_big_fb@y-tiled-32bpp-rotate-270.html
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11537/shard-rkl-2/igt@kms_big_fb@y-tiled-32bpp-rotate-270.html
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-rkl-6/igt@kms_big_fb@y-tiled-32bpp-rotate-270.html
* igt@kms_cursor_crc@pipe-a-cursor-64x21-offscreen:
- {shard-rkl}: ([SKIP][129], [PASS][130]) ([fdo#112022] / [i915#4070]) -> [PASS][131]
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11537/shard-rkl-2/igt@kms_cursor_crc@pipe-a-cursor-64x21-offscreen.html
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11537/shard-rkl-6/igt@kms_cursor_crc@pipe-a-cursor-64x21-offscreen.html
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-rkl-6/igt@kms_cursor_crc@pipe-a-cursor-64x21-offscreen.html
* igt@kms_cursor_crc@pipe-a-cursor-alpha-opaque:
- {shard-rkl}: [SKIP][132] ([fdo#112022] / [i915#4070]) -> [PASS][133] +2 similar issues
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11537/shard-rkl-4/igt@kms_cursor_crc@pipe-a-cursor-alpha-opaque.html
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-rkl-6/igt@kms_cursor_crc@pipe-a-cursor-alpha-opaque.html
* igt@kms_cursor_edge_walk@pipe-a-256x256-bottom-edge:
- {shard-rkl}: [SKIP][134] ([i915#1849] / [i915#4070] / [i915#4098]) -> [PASS][135]
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11537/shard-rkl-2/igt@kms_cursor_edge_walk@pipe-a-256x256-bottom-edge.html
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-rkl-6/igt@kms_cursor_edge_walk@pipe-a-256x256-bottom-edge.html
* igt@kms_cursor_legacy@basic-flip-after-cursor-legacy:
- {shard-rkl}: [SKIP][136] ([fdo#111825] / [i915#4070]) -> [PASS][137] +4 similar issues
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11537/shard-rkl-4/igt@kms_cursor_legacy@basic-flip-after-cursor-legacy.html
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-rkl-6/igt@kms_cursor_legacy@basic-flip-after-cursor-legacy.html
* igt@kms_cursor_legacy@flip-vs-cursor-varying-size:
- shard-iclb: [FAIL][138] -> [PASS][139]
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11537/shard-iclb7/igt@kms_cursor_legacy@flip-vs-cursor-varying-size.html
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-iclb6/igt@kms_cursor_legacy@flip-vs-cursor-varying-size.html
* igt@kms_cursor_legacy@pipe-c-forked-move:
- {shard-rkl}: ([SKIP][140], [SKIP][141]) ([i915#4070]) -> [PASS][142]
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11537/shard-rkl-2/igt@kms_cursor_legacy@pipe-c-forked-move.html
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11537/shard-rkl-2/igt@kms_cursor_legacy@pipe-c-forked-move.html
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-rkl-5/igt@kms_cursor_legacy@pipe-c-forked-move.html
* igt@kms_cursor_legacy@short-flip-after-cursor-atomic-transitions-varying-size:
- {shard-rkl}: ([SKIP][143], [SKIP][144]) ([fdo#111825] / [i915#4070]) -> [PASS][145]
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11537/shard-rkl-5/igt@kms_cursor_legacy@short-flip-after-cursor-atomic-transitions-varying-size.html
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11537/shard-rkl-4/igt@kms_cursor_legacy@short-flip-after-cursor-atomic-transitions-varying-size.html
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-rkl-6/igt@kms_cursor_legacy@short-flip-after-cursor-atomic-transitions-varying-size.html
* igt@kms_draw_crc@draw-method-xrgb8888-pwrite-untiled:
- {shard-rkl}: [SKIP][146] ([fdo#111314] / [i915#4098] / [i915#4369]) -> [PASS][147] +1 similar issue
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11537/shard-rkl-1/igt@kms_draw_crc@draw-method-xrgb8888-pwrite-untiled.html
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-rkl-6/igt@kms_draw_crc@draw-method-xrgb8888-pwrite-untiled.html
* igt@kms_draw_crc@draw-method-xrgb8888-pwrite-xtiled:
- {shard-rkl}: ([SKIP][148], [SKIP][149]) ([fdo#111314] / [i915#4098] / [i915#4369]) -> [PASS][150]
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11537/shard-rkl-4/igt@kms_draw_crc@draw-method-xrgb8888-pwrite-xtiled.html
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11537/shard-rkl-2/igt@kms_draw_crc@draw-method-xrgb8888-pwrite-xtiled.html
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-rkl-6/igt@kms_draw_crc@draw-method-xrgb8888-pwrite-xtiled.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-apl: [INCOMPLETE][151] ([i915#180]) -> [PASS][152]
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11537/shard-apl1/igt@kms_fbcon_fbt@fbc-suspend.html
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-apl4/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_flip@flip-vs-suspend@a-dp1:
- shard-apl: [DMESG-WARN][153] ([i915#180]) -> [PASS][154]
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11537/shard-apl6/igt@kms_flip@flip-vs-suspend@a-dp1.html
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-apl8/igt@kms_flip@flip-vs-suspend@a-dp1.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-blt:
- {shard-rkl}: ([SKIP][155], [SKIP][156]) ([i915#1849] / [i915#4098]) -> [PASS][157] +2 similar issues
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11537/shard-rkl-4/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-blt.html
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11537/shard-rkl-1/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-blt.html
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-rkl-6/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-shrfb-scaledprimary:
- {shard-rkl}: ([PASS][158], [SKIP][159]) ([i915#1849] / [i915#4098]) -> [PASS][160]
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11537/shard-rkl-6/igt@kms_frontbuffer_tracking@fbcpsr-shrfb-scaledprimary.html
[159]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11537/shard-rkl-2/igt@kms_frontbuffer_tracking@fbcpsr-shrfb-scaledprimary.html
[160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-rkl-6/igt@kms_frontbuffer_tracking@fbcpsr-shrfb-scaledprimary.html
* igt@kms_invalid_mode@int-max-clock:
- {shard-rkl}: [SKIP][161] ([i915#4278]) -> [PASS][162]
[161]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11537/shard-rkl-5/igt@kms_invalid_mode@int-max-clock.html
[162]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-rkl-6/igt@kms_invalid_mode@int-max-clock.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- {shard-rkl}: [SKIP][163] ([i915#1849] / [i915#4098]) -> [PASS][164] +6 similar issues
[163]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11537/shard-rkl-1/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
[164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-rkl-6/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
* igt@kms_plane_alpha_blend@pipe-b-coverage-vs-premult-vs-constant:
- {shard-rkl}: [SKIP][165] ([i915#4070] / [i915#4098]) -> [PASS][166]
[165]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11537/shard-rkl-4/igt@kms_plane_alpha_blend@pipe-b-coverage-vs-premult-vs-constant.html
[166]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-rkl-6/igt@kms_plane_alpha_blend@pipe-b-coverage-vs-premult-vs-constant.html
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: [FAIL][167] ([fdo#108145] / [i915#265]) -> [PASS][168] +1 similar issue
[167]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11537/shard-skl4/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
[168]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-skl10/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
#### Warnings ####
* igt@gem_exec_balancer@parallel-ordering:
- shard-iclb: [DMESG-FAIL][169] ([i915#5614]) -> [SKIP][170] ([i915#4525])
[169]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11537/shard-iclb1/igt@gem_exec_balancer@parallel-ordering.html
[170]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-iclb8/igt@gem_exec_balancer@parallel-ordering.html
* igt@gem_exec_balancer@parallel-out-fence:
- shard-iclb: [SKIP][171] ([i915#4525]) -> [DMESG-WARN][172] ([i915#5614]) +2 similar issues
[171]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11537/shard-iclb3/igt@gem_exec_balancer@parallel-out-fence.html
[172]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-iclb4/igt@gem_exec_balancer@parallel-out-fence.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-kbl: [FAIL][173] ([i915#4767]) -> [INCOMPLETE][174] ([i915#180])
[173]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11537/shard-kbl3/igt@kms_fbcon_fbt@fbc-suspend.html
[174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-kbl1/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_flip@2x-flip-vs-suspend:
- shard-skl: [SKIP][175] ([fdo#109271] / [i915#1888]) -> [SKIP][176] ([fdo#109271])
[175]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11537/shard-skl8/igt@kms_flip@2x-flip-vs-suspend.html
[176]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-skl4/igt@kms_flip@2x-flip-vs-suspend.html
* igt@runner@aborted:
- shard-kbl: ([FAIL][177], [FAIL][178], [FAIL][179], [FAIL][180], [FAIL][181], [FAIL][182], [FAIL][183], [FAIL][184], [FAIL][185], [FAIL][186], [FAIL][187], [FAIL][188]) ([i915#180] / [i915#3002] / [i915#4312] / [i915#5257]) -> ([FAIL][189], [FAIL][190], [FAIL][191], [FAIL][192], [FAIL][193], [FAIL][194], [FAIL][195], [FAIL][196], [FAIL][197], [FAIL][198], [FAIL][199], [FAIL][200], [FAIL][201], [FAIL][202], [FAIL][203], [FAIL][204], [FAIL][205], [FAIL][206]) ([fdo#109271] / [i915#180] / [i915#3002] / [i915#4312] / [i915#5257] / [i915#92])
[177]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11537/shard-kbl7/igt@runner@aborted.html
[178]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11537/shard-kbl6/igt@runner@aborted.html
[179]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11537/shard-kbl7/igt@runner@aborted.html
[180]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11537/shard-kbl4/igt@runner@aborted.html
[181]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11537/shard-kbl3/igt@runner@aborted.html
[182]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11537/shard-kbl3/igt@runner@aborted.html
[183]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11537/shard-kbl7/igt@runner@aborted.html
[184]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11537/shard-kbl1/igt@runner@aborted.html
[185]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11537/shard-kbl4/igt@runner@aborted.html
[186]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11537/shard-kbl4/igt@runner@aborted.html
[187]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11537/shard-kbl6/igt@runner@aborted.html
[188]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11537/shard-kbl7/igt@runner@aborted.html
[189]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-kbl6/igt@runner@aborted.html
[190]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-kbl7/igt@runner@aborted.html
[191]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-kbl7/igt@runner@aborted.html
[192]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-kbl6/igt@runner@aborted.html
[193]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-kbl6/igt@runner@aborted.html
[194]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-kbl7/igt@runner@aborted.html
[195]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-kbl7/igt@runner@aborted.html
[196]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-kbl7/igt@runner@aborted.html
[197]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-kbl4/igt@runner@aborted.html
[198]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-kbl4/igt@runner@aborted.html
[199]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-kbl4/igt@runner@aborted.html
[200]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-kbl3/igt@runner@aborted.html
[201]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-kbl3/igt@runner@aborted.html
[202]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-kbl1/igt@runner@aborted.html
[203]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-kbl3/igt@runner@aborted.html
[204]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-kbl3/igt@runner@aborted.html
[205]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-kbl3/igt@runner@aborted.html
[206]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-kbl1/igt@runner@aborted.html
- shard-apl: ([FAIL][207], [FAIL][208], [FAIL][209], [FAIL][210], [FAIL][211], [FAIL][212], [FAIL][213]) ([fdo#109271] / [i915#180] / [i915#3002] / [i915#4312] / [i915#5257]) -> ([FAIL][214], [FAIL][215], [FAIL][216], [FAIL][217], [FAIL][218]) ([i915#180] / [i915#3002] / [i915#4312] / [i915#5257])
[207]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11537/shard-apl2/igt@runner@aborted.html
[208]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11537/shard-apl8/igt@runner@aborted.html
[209]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11537/shard-apl7/igt@runner@aborted.html
[210]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11537/shard-apl3/igt@runner@aborted.html
[211]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11537/shard-apl3/igt@runner@aborted.html
[212]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11537/shard-apl6/igt@runner@aborted.html
[213]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11537/shard-apl1/igt@runner@aborted.html
[214]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-apl7/igt@runner@aborted.html
[215]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-apl6/igt@runner@aborted.html
[216]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-apl1/igt@runner@aborted.html
[217]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-apl8/igt@runner@aborted.html
[218]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/shard-apl3/igt@runner@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[IGT#2]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/2
[fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[fdo#109300]: https://bugs.freedesktop.org/show_bug.cgi?id=109300
[fdo#109302]: https://bugs.freedesktop.org/show_bug.cgi?id=109302
[fdo#109307]: https://bugs.freedesktop.org/show_bug.cgi?id=109307
[fdo#109308]: https://bugs.freedesktop.org/show_bug.cgi?id=109308
[fdo#109309]: https://bugs.freedesktop.org/show_bug.cgi?id=109309
[fdo#109312]: https://bugs.freedesktop.org/show_bug.cgi?id=109312
[fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
[fdo#110725]: https://bugs.freedesktop.org/show_bug.cgi?id=110725
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111314]: https://bugs.freedesktop.org/show_bug.cgi?id=111314
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[fdo#112022]: https://bugs.freedesktop.org/show_bug.cgi?id=112022
[fdo#112054]: https://bugs.freedesktop.org/show_bug.cgi?id=112054
[fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283
[i915#1063]: https://gitlab.freedesktop.org/drm/intel/issues/1063
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1149]: https://gitlab.freedesktop.org/drm/intel/issues/1149
[i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
[i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
[i915#1257]: https://gitlab.freedesktop.org/drm/intel/issues/1257
[i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319
[i915#132]: https://gitlab.freedesktop.org/drm/intel/issues/132
[i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
[i915#1755]: https://gitlab.freedesktop.org/drm/intel/issues/1755
[i915#1769]: https://gitlab.freedesktop.org/drm/intel/issues/1769
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
[i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
[i915#1850]: https://gitlab.freedesktop.org/drm/intel/issues/1850
[i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
[i915#1902]: https://gitlab.freedesktop.org/drm/intel/issues/1902
[i915#1911]: https://gitlab.freedesktop.org/drm/intel/issues/1911
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2232]: https://gitlab.freedesktop.org/drm/intel/issues/2232
[i915#232]: https://gitlab.freedesktop.org/drm/intel/issues/232
[i915#2433]: https://gitlab.freedesktop.org/drm/intel/issues/2433
[i915#2435]: https://gitlab.freedesktop.org/drm/intel/issues/2435
[i915#2436]: https://gitlab.freedesktop.org/drm/intel/issues/2436
[i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
[i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
[i915#2530]: https://gitlab.freedesktop.org/drm/intel/issues/2530
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
[i915#2681]: https://gitlab.freedesktop.org/drm/intel/issues/2681
[i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
[i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2849]: https://gitlab.freedesktop.org/drm/intel/issues/2849
[i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
[i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
[i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994
[i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002
[i915#3012]: https://gitlab.freedesktop.org/drm/intel/issues/3012
[i915#3063]: https://gitlab.freedesktop.org/drm/intel/issues/3063
[i915#3116]: https://gitlab.freedesktop.org/drm/intel/issues/3116
[i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299
[i915#3318]: https://gitlab.freedesktop.org/drm/intel/issues/3318
[i915#3319]: https://gitlab.freedesktop.org/drm/intel/issues/3319
[i915#3323]: https://gitlab.freedesktop.org/drm/intel/issues/3323
[i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
[i915#3361]: https://gitlab.freedesktop.org/drm/intel/issues/3361
[i915#3376]: https://gitlab.freedesktop.org/drm/intel/issues/3376
[i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
[i915#3469]: https://gitlab.freedesktop.org/drm/intel/issues/3469
[i915#3536]: https://gitlab.freedesktop.org/drm/intel/issues/3536
[i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3558]: https://gitlab.freedesktop.org/drm/intel/issues/3558
[i915#3614]: https://gitlab.freedesktop.org/drm/intel/issues/3614
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3701]: https://gitlab.freedesktop.org/drm/intel/issues/3701
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734
[i915#3736]: https://gitlab.freedesktop.org/drm/intel/issues/3736
[i915#3742]: https://gitlab.freedesktop.org/drm/intel/issues/3742
[i915#3743]: https://gitlab.freedesktop.org/drm/intel/issues/3743
[i915#3763]: https://gitlab.freedesktop.org/drm/intel/issues/3763
[i915#3777]: https://gitlab.freedesktop.org/drm/intel/issues/3777
[i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#3936]: https://gitlab.freedesktop.org/drm/intel/issues/3936
[i915#3938]: https://gitlab.freedesktop.org/drm/intel/issues/3938
[i915#3952]: https://gitlab.freedesktop.org/drm/intel/issues/3952
[i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955
[i915#3966]: https://gitlab.freedesktop.org/drm/intel/issues/3966
[i915#4016]: https://gitlab.freedesktop.org/drm/intel/issues/4016
[i915#4032]: https://gitlab.freedesktop.org/drm/intel/issues/4032
[i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
[i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215
[i915#426]: https://gitlab.freedesktop.org/drm/intel/issues/426
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#4278]: https://gitlab.freedesktop.org/drm/intel/issues/4278
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4369]: https://gitlab.freedesktop.org/drm/intel/issues/4369
[i915#4387]: https://gitlab.freedesktop.org/drm/intel/issues/4387
[i915#4444]: https://gitlab.freedesktop.org/drm/intel/issues/4444
[i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525
[i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
[i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4767]: https://gitlab.freedesktop.org/drm/intel/issues/4767
[i915#4771]: https://gitlab.freedesktop.org/drm/intel/issues/4771
[i915#4807]: https://gitlab.freedesktop.org/drm/intel/issues/4807
[i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
[i915#4833]: https://gitlab.freedesktop.org/drm/intel/issues/4833
[i915#4839]: https://gitlab.freedesktop.org/drm/intel/issues/4839
[i915#4842]: https://gitlab.freedesktop.org/drm/intel/issues/4842
[i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852
[i915#4853]: https://gitlab.freedesktop.org/drm/intel/issues/4853
[i915#4855]: https://gitlab.freedesktop.org/drm/intel/issues/4855
[i915#4859]: https://gitlab.freedesktop.org/drm/intel/issues/4859
[i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860
[i915#4873]: https://gitlab.freedesktop.org/drm/intel/issues/4873
[i915#4874]: https://gitlab.freedesktop.org/drm/intel/issues/4874
[i915#4877]: https://gitlab.freedesktop.org/drm/intel/issues/4877
[i915#4880]: https://gitlab.freedesktop.org/drm/intel/issues/4880
[i915#4881]: https://gitlab.freedesktop.org/drm/intel/issues/4881
[i915#4893]: https://gitlab.freedesktop.org/drm/intel/issues/4893
[i915#4941]: https://gitlab.freedesktop.org/drm/intel/issues/4941
[i915#5076]: https://gitlab.freedesktop.org/drm/intel/issues/5076
[i915#5080]: https://gitlab.freedesktop.org/drm/intel/issues/5080
[i915#5098]: https://gitlab.freedesktop.org/drm/intel/issues/5098
[i915#5115]: https://gitlab.freedesktop.org/drm/intel/issues/5115
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5257]: https://gitlab.freedesktop.org/drm/intel/issues/5257
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5287]: https://gitlab.freedesktop.org/drm/intel/issues/5287
[i915#5288]: https://gitlab.freedesktop.org/drm/intel/issues/5288
[i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
[i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#5341]: https://gitlab.freedesktop.org/drm/intel/issues/5341
[i915#5386]: https://gitlab.freedesktop.org/drm/intel/issues/5386
[i915#5439]: https://gitlab.freedesktop.org/drm/intel/issues/5439
[i915#5563]: https://gitlab.freedesktop.org/drm/intel/issues/5563
[i915#5566]: https://gitlab.freedesktop.org/drm/intel/issues/5566
[i915#5614]: https://gitlab.freedesktop.org/drm/intel/issues/5614
[i915#5639]: https://gitlab.freedesktop.org/drm/intel/issues/5639
[i915#5691]: https://gitlab.freedesktop.org/drm/intel/issues/5691
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
[i915#768]: https://gitlab.freedesktop.org/drm/intel/issues/768
[i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92
Build changes
-------------
* Linux: CI_DRM_11537 -> Patchwork_102949v1
CI-20190529: 20190529
CI_DRM_11537: d3f1b43f64dc51bfbb59fab5c6b950159c77207e @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6444: df584c804e3a44431b0e5ae21c190b6e9acb35ab @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_102949v1: d3f1b43f64dc51bfbb59fab5c6b950159c77207e @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102949v1/index.html
[-- Attachment #2: Type: text/html, Size: 60291 bytes --]
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [Intel-gfx] [PATCH 1/1] drm/i915/guc: Convert ct buffer to iosys_map
2022-04-14 12:11 ` Balasubramani Vivekanandan
@ 2022-04-28 14:13 ` Siva Mullati
2022-04-29 9:07 ` Balasubramani Vivekanandan
0 siblings, 1 reply; 14+ messages in thread
From: Siva Mullati @ 2022-04-28 14:13 UTC (permalink / raw)
To: Balasubramani Vivekanandan, intel-gfx; +Cc: lucas.demarchi
On 14/04/22 17:41, Balasubramani Vivekanandan wrote:
> On 04.04.2022 15:01, Mullati Siva wrote:
>> From: Siva Mullati <siva.mullati@intel.com>
>>
>> Convert CT commands and descriptors to use iosys_map rather
>> than plain pointer and save it in the intel_guc_ct_buffer struct.
>> This will help with ct_write and ct_read for cmd send and receive
>> after the initialization by abstracting the IO vs system memory.
>>
>> Signed-off-by: Siva Mullati <siva.mullati@intel.com>
>> ---
>> drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 200 +++++++++++++---------
>> drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h | 9 +-
>> 2 files changed, 127 insertions(+), 82 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
>> index f01325cd1b62..64568dc90b05 100644
>> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
>> @@ -44,6 +44,11 @@ static inline struct drm_device *ct_to_drm(struct intel_guc_ct *ct)
>> #define CT_PROBE_ERROR(_ct, _fmt, ...) \
>> i915_probe_error(ct_to_i915(ct), "CT: " _fmt, ##__VA_ARGS__)
>>
>> +#define ct_desc_read(desc_map_, field_) \
>> + iosys_map_rd_field(desc_map_, 0, struct guc_ct_buffer_desc, field_)
>> +#define ct_desc_write(desc_map_, field_, val_) \
>> + iosys_map_wr_field(desc_map_, 0, struct guc_ct_buffer_desc, field_, val_)
>> +
> Did you try to make the change Lucas mentioned in his comment on rev0,
> to pass `struct guc_ct_buffer_desc *` as first argument to the above
> macros? Was it not feasible?
It is not feasible.
>> /**
>> * DOC: CTB Blob
>> *
>> @@ -76,6 +81,11 @@ static inline struct drm_device *ct_to_drm(struct intel_guc_ct *ct)
>> #define CTB_G2H_BUFFER_SIZE (4 * CTB_H2G_BUFFER_SIZE)
>> #define G2H_ROOM_BUFFER_SIZE (CTB_G2H_BUFFER_SIZE / 4)
>>
>> +#define CTB_SEND_DESC_OFFSET 0u
>> +#define CTB_RECV_DESC_OFFSET (CTB_DESC_SIZE)
>> +#define CTB_SEND_CMDS_OFFSET (2 * CTB_DESC_SIZE)
>> +#define CTB_RECV_CMDS_OFFSET (2 * CTB_DESC_SIZE + CTB_H2G_BUFFER_SIZE)
>> +
>> struct ct_request {
>> struct list_head link;
>> u32 fence;
>> @@ -113,9 +123,9 @@ void intel_guc_ct_init_early(struct intel_guc_ct *ct)
>> init_waitqueue_head(&ct->wq);
>> }
>>
>> -static void guc_ct_buffer_desc_init(struct guc_ct_buffer_desc *desc)
>> +static void guc_ct_buffer_desc_init(struct iosys_map *desc)
>> {
>> - memset(desc, 0, sizeof(*desc));
>> + iosys_map_memset(desc, 0, 0, sizeof(struct guc_ct_buffer_desc));
>> }
>>
>> static void guc_ct_buffer_reset(struct intel_guc_ct_buffer *ctb)
>> @@ -128,17 +138,18 @@ static void guc_ct_buffer_reset(struct intel_guc_ct_buffer *ctb)
>> space = CIRC_SPACE(ctb->tail, ctb->head, ctb->size) - ctb->resv_space;
>> atomic_set(&ctb->space, space);
>>
>> - guc_ct_buffer_desc_init(ctb->desc);
>> + guc_ct_buffer_desc_init(&ctb->desc_map);
>> }
>>
>> static void guc_ct_buffer_init(struct intel_guc_ct_buffer *ctb,
>> - struct guc_ct_buffer_desc *desc,
>> - u32 *cmds, u32 size_in_bytes, u32 resv_space)
>> + struct iosys_map *desc,
>> + struct iosys_map *cmds,
>> + u32 size_in_bytes, u32 resv_space)
>> {
>> GEM_BUG_ON(size_in_bytes % 4);
>>
>> - ctb->desc = desc;
>> - ctb->cmds = cmds;
>> + ctb->desc_map = *desc;
>> + ctb->cmds_map = *cmds;
>> ctb->size = size_in_bytes / 4;
>> ctb->resv_space = resv_space / 4;
>>
>> @@ -218,12 +229,13 @@ static int ct_register_buffer(struct intel_guc_ct *ct, bool send,
>> int intel_guc_ct_init(struct intel_guc_ct *ct)
>> {
>> struct intel_guc *guc = ct_to_guc(ct);
>> - struct guc_ct_buffer_desc *desc;
>> + struct iosys_map blob_map;
>> + struct iosys_map desc_map;
>> + struct iosys_map cmds_map;
>> u32 blob_size;
>> u32 cmds_size;
>> u32 resv_space;
>> void *blob;
>> - u32 *cmds;
>> int err;
>>
>> err = i915_inject_probe_error(guc_to_gt(guc)->i915, -ENXIO);
>> @@ -242,27 +254,35 @@ int intel_guc_ct_init(struct intel_guc_ct *ct)
>>
>> CT_DEBUG(ct, "base=%#x size=%u\n", intel_guc_ggtt_offset(guc, ct->vma), blob_size);
>>
>> - /* store pointers to desc and cmds for send ctb */
>> - desc = blob;
>> - cmds = blob + 2 * CTB_DESC_SIZE;
>> + if (i915_gem_object_is_lmem(ct->vma->obj))
>> + iosys_map_set_vaddr_iomem(&blob_map,
>> + (void __iomem *)blob);
>> + else
>> + iosys_map_set_vaddr(&blob_map, blob);
>> +
>> + /* store sysmap to desc_map and cmds_map for send ctb */
>> + desc_map = IOSYS_MAP_INIT_OFFSET(&blob_map, CTB_SEND_DESC_OFFSET);
>> + cmds_map = IOSYS_MAP_INIT_OFFSET(&blob_map, CTB_SEND_CMDS_OFFSET);
>> cmds_size = CTB_H2G_BUFFER_SIZE;
>> resv_space = 0;
>> - CT_DEBUG(ct, "%s desc %#tx cmds %#tx size %u/%u\n", "send",
>> - ptrdiff(desc, blob), ptrdiff(cmds, blob), cmds_size,
>> - resv_space);
>> + CT_DEBUG(ct, "%s desc %#x cmds %#x size %u/%u\n", "send",
>> + CTB_SEND_DESC_OFFSET, (u32)CTB_SEND_CMDS_OFFSET,
>> + cmds_size, resv_space);
>>
>> - guc_ct_buffer_init(&ct->ctbs.send, desc, cmds, cmds_size, resv_space);
>> + guc_ct_buffer_init(&ct->ctbs.send,
>> + &desc_map, &cmds_map, cmds_size, resv_space);
>>
>> - /* store pointers to desc and cmds for recv ctb */
>> - desc = blob + CTB_DESC_SIZE;
>> - cmds = blob + 2 * CTB_DESC_SIZE + CTB_H2G_BUFFER_SIZE;
>> + /* store sysmap to desc_map and cmds_map for recv ctb */
>> + desc_map = IOSYS_MAP_INIT_OFFSET(&blob_map, CTB_RECV_DESC_OFFSET);
>> + cmds_map = IOSYS_MAP_INIT_OFFSET(&blob_map, CTB_RECV_CMDS_OFFSET);
>> cmds_size = CTB_G2H_BUFFER_SIZE;
>> resv_space = G2H_ROOM_BUFFER_SIZE;
>> - CT_DEBUG(ct, "%s desc %#tx cmds %#tx size %u/%u\n", "recv",
>> - ptrdiff(desc, blob), ptrdiff(cmds, blob), cmds_size,
>> - resv_space);
>> + CT_DEBUG(ct, "%s desc %#x cmds %#x size %u/%u\n", "recv",
>> + (u32)CTB_RECV_DESC_OFFSET, (u32)CTB_RECV_CMDS_OFFSET,
>> + cmds_size, resv_space);
>>
>> - guc_ct_buffer_init(&ct->ctbs.recv, desc, cmds, cmds_size, resv_space);
>> + guc_ct_buffer_init(&ct->ctbs.recv,
>> + &desc_map, &cmds_map, cmds_size, resv_space);
>>
>> return 0;
>> }
>> @@ -279,6 +299,10 @@ void intel_guc_ct_fini(struct intel_guc_ct *ct)
>>
>> tasklet_kill(&ct->receive_tasklet);
>> i915_vma_unpin_and_release(&ct->vma, I915_VMA_RELEASE_MAP);
>> + iosys_map_clear(&ct->ctbs.send.desc_map);
>> + iosys_map_clear(&ct->ctbs.send.cmds_map);
>> + iosys_map_clear(&ct->ctbs.recv.desc_map);
>> + iosys_map_clear(&ct->ctbs.recv.cmds_map);
> I think there is no need of clearing the iosys_map when were are zeroing
> the complete structure area below.
Yes, I have updated this in latest revision.
>> memset(ct, 0, sizeof(*ct));
>> }
>>
>> @@ -291,8 +315,8 @@ void intel_guc_ct_fini(struct intel_guc_ct *ct)
>> int intel_guc_ct_enable(struct intel_guc_ct *ct)
>> {
>> struct intel_guc *guc = ct_to_guc(ct);
>> + struct iosys_map blob_map;
>> u32 base, desc, cmds, size;
>> - void *blob;
>> int err;
>>
>> GEM_BUG_ON(ct->enabled);
>> @@ -302,9 +326,14 @@ int intel_guc_ct_enable(struct intel_guc_ct *ct)
>> GEM_BUG_ON(!i915_gem_object_has_pinned_pages(ct->vma->obj));
>> base = intel_guc_ggtt_offset(guc, ct->vma);
>>
>> + if (i915_gem_object_is_lmem(ct->vma->obj))
>> + iosys_map_set_vaddr_iomem(&blob_map, (void __iomem *)
>> + __px_vaddr(ct->vma->obj));
>> + else
>> + iosys_map_set_vaddr(&blob_map, __px_vaddr(ct->vma->obj));
>> +
>> /* blob should start with send descriptor */
>> - blob = __px_vaddr(ct->vma->obj);
>> - GEM_BUG_ON(blob != ct->ctbs.send.desc);
>> + GEM_BUG_ON(!iosys_map_is_equal(&blob_map, &ct->ctbs.send.desc_map));
>>
>> /* (re)initialize descriptors */
>> guc_ct_buffer_reset(&ct->ctbs.send);
>> @@ -314,15 +343,15 @@ int intel_guc_ct_enable(struct intel_guc_ct *ct)
>> * Register both CT buffers starting with RECV buffer.
>> * Descriptors are in first half of the blob.
>> */
>> - desc = base + ptrdiff(ct->ctbs.recv.desc, blob);
>> - cmds = base + ptrdiff(ct->ctbs.recv.cmds, blob);
>> + desc = base + CTB_RECV_DESC_OFFSET;
>> + cmds = base + CTB_RECV_CMDS_OFFSET;
>> size = ct->ctbs.recv.size * 4;
>> err = ct_register_buffer(ct, false, desc, cmds, size);
>> if (unlikely(err))
>> goto err_out;
>>
>> - desc = base + ptrdiff(ct->ctbs.send.desc, blob);
>> - cmds = base + ptrdiff(ct->ctbs.send.cmds, blob);
>> + desc = base + CTB_SEND_DESC_OFFSET;
>> + cmds = base + CTB_SEND_CMDS_OFFSET;
>> size = ct->ctbs.send.size * 4;
>> err = ct_register_buffer(ct, true, desc, cmds, size);
>> if (unlikely(err))
>> @@ -371,31 +400,33 @@ static int ct_write(struct intel_guc_ct *ct,
>> u32 fence, u32 flags)
>> {
>> struct intel_guc_ct_buffer *ctb = &ct->ctbs.send;
>> - struct guc_ct_buffer_desc *desc = ctb->desc;
>> u32 tail = ctb->tail;
>> u32 size = ctb->size;
>> u32 header;
>> u32 hxg;
>> u32 type;
>> - u32 *cmds = ctb->cmds;
>> + u32 status = ct_desc_read(&ctb->desc_map, status);
>> unsigned int i;
>>
>> - if (unlikely(desc->status))
>> + if (unlikely(status))
>> goto corrupted;
>>
>> GEM_BUG_ON(tail > size);
>>
>> #ifdef CONFIG_DRM_I915_DEBUG_GUC
>> - if (unlikely(tail != READ_ONCE(desc->tail))) {
>> + if (unlikely(tail != ct_desc_read(&ctb->desc_map, tail))) {
>> CT_ERROR(ct, "Tail was modified %u != %u\n",
>> - desc->tail, tail);
>> - desc->status |= GUC_CTB_STATUS_MISMATCH;
>> + ct_desc_read(&ctb->desc_map, tail), tail);
>> + status |= GUC_CTB_STATUS_MISMATCH;
>> + ct_desc_write(&ctb->desc_map, status, status);
>> goto corrupted;
>> }
>> - if (unlikely(READ_ONCE(desc->head) >= size)) {
>> + if (unlikely(ct_desc_read(&ctb->desc_map, head) >= size)) {
>> CT_ERROR(ct, "Invalid head offset %u >= %u)\n",
>> - desc->head, size);
>> - desc->status |= GUC_CTB_STATUS_OVERFLOW;
>> + ct_desc_read(&ctb->desc_map, head), size);
> Can we avoid reading the head from ctb->desc_map twice? Since each
> iosys_map read translates to memcpy, it is better to avoid repeating if
> we can cache from the earlier read.
Do you see real need of having a variable to cache value locally, considering the path is very unlikely to hit.
>> + status = ct_desc_read(&ctb->desc_map, status) |
>> + GUC_CTB_STATUS_OVERFLOW;
> Same here, can we avoid reading status since we already have it read. We
> can do the same like how it is done for the GUC_CTB_STATUS_MISMATCH case.
Addressed in latest patch
>> + ct_desc_write(&ctb->desc_map, status, status);
>> goto corrupted;
>> }
>> #endif
>> @@ -418,14 +449,14 @@ static int ct_write(struct intel_guc_ct *ct,
>> CT_DEBUG(ct, "writing (tail %u) %*ph %*ph %*ph\n",
>> tail, 4, &header, 4, &hxg, 4 * (len - 1), &action[1]);
>>
>> - cmds[tail] = header;
>> + iosys_map_wr(&ctb->cmds_map, 4 * tail, u32, header);
> I prefer not to use the MAGIC number. My suggestion is to use
> sizeof(tail) since we need the offset in bytes.
I tried avoiding it, can't use sizeof(tail). Here tail is just an index which might be a misleading if we use it in this case, cmds would have been the right one but this has been changed to iosys map. Currently updated with sizeof(u32).
>> tail = (tail + 1) % size;
>>
>> - cmds[tail] = hxg;
>> + iosys_map_wr(&ctb->cmds_map, 4 * tail, u32, hxg);
> MAGIC number again. There are numerous places in the patch, where
> numbers are used. I prefer to remove it.
>> tail = (tail + 1) % size;
>>
>> for (i = 1; i < len; i++) {
>> - cmds[tail] = action[i];
>> + iosys_map_wr(&ctb->cmds_map, 4 * tail, u32, action[i]);
>> tail = (tail + 1) % size;
>> }
>> GEM_BUG_ON(tail > size);
>> @@ -442,13 +473,14 @@ static int ct_write(struct intel_guc_ct *ct,
>> atomic_sub(len + GUC_CTB_HDR_LEN, &ctb->space);
>>
>> /* now update descriptor */
>> - WRITE_ONCE(desc->tail, tail);
>> + ct_desc_write(&ctb->desc_map, tail, tail);
>>
>> return 0;
>>
>> corrupted:
>> CT_ERROR(ct, "Corrupted descriptor head=%u tail=%u status=%#x\n",
>> - desc->head, desc->tail, desc->status);
>> + ct_desc_read(&ctb->desc_map, head), ct_desc_read(&ctb->desc_map, tail),
>> + ct_desc_read(&ctb->desc_map, status));
>> ctb->broken = true;
>> return -EPIPE;
>> }
>> @@ -499,20 +531,22 @@ static inline bool ct_deadlocked(struct intel_guc_ct *ct)
>> bool ret = ktime_ms_delta(ktime_get(), ct->stall_time) > timeout;
>>
>> if (unlikely(ret)) {
>> - struct guc_ct_buffer_desc *send = ct->ctbs.send.desc;
>> - struct guc_ct_buffer_desc *recv = ct->ctbs.send.desc;
>> -
>> CT_ERROR(ct, "Communication stalled for %lld ms, desc status=%#x,%#x\n",
>> ktime_ms_delta(ktime_get(), ct->stall_time),
>> - send->status, recv->status);
>> + ct_desc_read(&ct->ctbs.send.desc_map, status),
>> + ct_desc_read(&ct->ctbs.recv.desc_map, status));
>> CT_ERROR(ct, "H2G Space: %u (Bytes)\n",
>> atomic_read(&ct->ctbs.send.space) * 4);
>> - CT_ERROR(ct, "Head: %u (Dwords)\n", ct->ctbs.send.desc->head);
>> - CT_ERROR(ct, "Tail: %u (Dwords)\n", ct->ctbs.send.desc->tail);
>> + CT_ERROR(ct, "Head: %u (Dwords)\n",
>> + ct_desc_read(&ct->ctbs.send.desc_map, head));
>> + CT_ERROR(ct, "Tail: %u (Dwords)\n",
>> + ct_desc_read(&ct->ctbs.send.desc_map, tail));
>> CT_ERROR(ct, "G2H Space: %u (Bytes)\n",
>> atomic_read(&ct->ctbs.recv.space) * 4);
>> - CT_ERROR(ct, "Head: %u\n (Dwords)", ct->ctbs.recv.desc->head);
>> - CT_ERROR(ct, "Tail: %u\n (Dwords)", ct->ctbs.recv.desc->tail);
>> + CT_ERROR(ct, "Head: %u\n (Dwords)",
>> + ct_desc_read(&ct->ctbs.recv.desc_map, head));
>> + CT_ERROR(ct, "Tail: %u\n (Dwords)",
>> + ct_desc_read(&ct->ctbs.recv.desc_map, tail));
>>
>> ct->ctbs.send.broken = true;
>> }
>> @@ -549,18 +583,19 @@ static inline void g2h_release_space(struct intel_guc_ct *ct, u32 g2h_len_dw)
>> static inline bool h2g_has_room(struct intel_guc_ct *ct, u32 len_dw)
>> {
>> struct intel_guc_ct_buffer *ctb = &ct->ctbs.send;
>> - struct guc_ct_buffer_desc *desc = ctb->desc;
>> u32 head;
>> u32 space;
>> + u32 status = ct_desc_read(&ctb->desc_map, status);
>>
>> if (atomic_read(&ctb->space) >= len_dw)
>> return true;
>>
>> - head = READ_ONCE(desc->head);
>> + head = ct_desc_read(&ctb->desc_map, head);
>> if (unlikely(head > ctb->size)) {
>> CT_ERROR(ct, "Invalid head offset %u >= %u)\n",
>> head, ctb->size);
>> - desc->status |= GUC_CTB_STATUS_OVERFLOW;
>> + status |= GUC_CTB_STATUS_OVERFLOW;
>> + ct_desc_write(&ctb->desc_map, status, status);
>> ctb->broken = true;
>> return false;
>> }
>> @@ -803,11 +838,10 @@ static void ct_free_msg(struct ct_incoming_msg *msg)
>> static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg)
>> {
>> struct intel_guc_ct_buffer *ctb = &ct->ctbs.recv;
>> - struct guc_ct_buffer_desc *desc = ctb->desc;
>> u32 head = ctb->head;
>> - u32 tail = READ_ONCE(desc->tail);
>> + u32 tail = ct_desc_read(&ctb->desc_map, tail);
>> u32 size = ctb->size;
>> - u32 *cmds = ctb->cmds;
>> + u32 status = ct_desc_read(&ctb->desc_map, status);
>> s32 available;
>> unsigned int len;
>> unsigned int i;
>> @@ -816,23 +850,26 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg)
>> if (unlikely(ctb->broken))
>> return -EPIPE;
>>
>> - if (unlikely(desc->status))
>> + if (unlikely(status))
>> goto corrupted;
>>
>> GEM_BUG_ON(head > size);
>>
>> #ifdef CONFIG_DRM_I915_DEBUG_GUC
>> - if (unlikely(head != READ_ONCE(desc->head))) {
>> + if (unlikely(head != ct_desc_read(&ctb->desc_map, head))) {
>> CT_ERROR(ct, "Head was modified %u != %u\n",
>> - desc->head, head);
>> - desc->status |= GUC_CTB_STATUS_MISMATCH;
>> + ct_desc_read(&ctb->desc_map, head), head);
> head read twice here as well.
Same answer.
>> + status |= GUC_CTB_STATUS_MISMATCH;
>> + ct_desc_write(&ctb->desc_map, status, status);
>> goto corrupted;
>> }
>> #endif
>> if (unlikely(tail >= size)) {
>> CT_ERROR(ct, "Invalid tail offset %u >= %u)\n",
>> tail, size);
>> - desc->status |= GUC_CTB_STATUS_OVERFLOW;
>> + status = ct_desc_read(&ctb->desc_map, status) |
>> + GUC_CTB_STATUS_OVERFLOW;
> No need to read the status again as we already have it cached.
addressed.
>> + ct_desc_write(&ctb->desc_map, status, status);
>> goto corrupted;
>> }
>>
>> @@ -849,7 +886,7 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg)
>> CT_DEBUG(ct, "available %d (%u:%u:%u)\n", available, head, tail, size);
>> GEM_BUG_ON(available < 0);
>>
>> - header = cmds[head];
>> + header = iosys_map_rd(&ctb->cmds_map, (4 * head), u32);
> MAGIC numbers
>> head = (head + 1) % size;
>>
>> /* message len with header */
>> @@ -857,11 +894,15 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg)
>> if (unlikely(len > (u32)available)) {
>> CT_ERROR(ct, "Incomplete message %*ph %*ph %*ph\n",
>> 4, &header,
>> + 4 * (head + available - 1 > size ? size - head :
>> + available - 1), ((__px_vaddr(ct->vma->obj) +
>> + CTB_RECV_CMDS_OFFSET) + (4 * head)),
>> 4 * (head + available - 1 > size ?
>> - size - head : available - 1), &cmds[head],
>> - 4 * (head + available - 1 > size ?
>> - available - 1 - size + head : 0), &cmds[0]);
>> - desc->status |= GUC_CTB_STATUS_UNDERFLOW;
>> + available - 1 - size + head : 0),
>> + (__px_vaddr(ct->vma->obj) + CTB_RECV_CMDS_OFFSET));
>> + status = ct_desc_read(&ctb->desc_map, status) |
>> + GUC_CTB_STATUS_UNDERFLOW;
> No need to read status again
>
> Regards,
> Bala
>> + ct_desc_write(&ctb->desc_map, status, status);
>> goto corrupted;
>> }
>>
>> @@ -869,17 +910,18 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg)
>> if (!*msg) {
>> CT_ERROR(ct, "No memory for message %*ph %*ph %*ph\n",
>> 4, &header,
>> + 4 * (head + available - 1 > size ? size - head :
>> + available - 1), (ctb->cmds_map.vaddr + (4 * head)),
>> 4 * (head + available - 1 > size ?
>> - size - head : available - 1), &cmds[head],
>> - 4 * (head + available - 1 > size ?
>> - available - 1 - size + head : 0), &cmds[0]);
>> + available - 1 - size + head : 0), ctb->cmds_map.vaddr);
>> return available;
>> }
>>
>> (*msg)->msg[0] = header;
>>
>> for (i = 1; i < len; i++) {
>> - (*msg)->msg[i] = cmds[head];
>> + (*msg)->msg[i] = iosys_map_rd(&ctb->cmds_map,
>> + (4 * head), u32);
>> head = (head + 1) % size;
>> }
>> CT_DEBUG(ct, "received %*ph\n", 4 * len, (*msg)->msg);
>> @@ -888,13 +930,15 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg)
>> ctb->head = head;
>>
>> /* now update descriptor */
>> - WRITE_ONCE(desc->head, head);
>> + ct_desc_write(&ctb->desc_map, head, head);
>>
>> return available - len;
>>
>> corrupted:
>> CT_ERROR(ct, "Corrupted descriptor head=%u tail=%u status=%#x\n",
>> - desc->head, desc->tail, desc->status);
>> + ct_desc_read(&ctb->desc_map, head),
>> + ct_desc_read(&ctb->desc_map, tail),
>> + ct_desc_read(&ctb->desc_map, status));
>> ctb->broken = true;
>> return -EPIPE;
>> }
>> @@ -1211,13 +1255,13 @@ void intel_guc_ct_print_info(struct intel_guc_ct *ct,
>> drm_printf(p, "H2G Space: %u\n",
>> atomic_read(&ct->ctbs.send.space) * 4);
>> drm_printf(p, "Head: %u\n",
>> - ct->ctbs.send.desc->head);
>> + ct_desc_read(&ct->ctbs.send.desc_map, head));
>> drm_printf(p, "Tail: %u\n",
>> - ct->ctbs.send.desc->tail);
>> + ct_desc_read(&ct->ctbs.send.desc_map, tail));
>> drm_printf(p, "G2H Space: %u\n",
>> atomic_read(&ct->ctbs.recv.space) * 4);
>> drm_printf(p, "Head: %u\n",
>> - ct->ctbs.recv.desc->head);
>> + ct_desc_read(&ct->ctbs.recv.desc_map, head));
>> drm_printf(p, "Tail: %u\n",
>> - ct->ctbs.recv.desc->tail);
>> + ct_desc_read(&ct->ctbs.recv.desc_map, tail));
>> }
>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h
>> index f709a19c7e21..867fe13fb47d 100644
>> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h
>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h
>> @@ -7,6 +7,7 @@
>> #define _INTEL_GUC_CT_H_
>>
>> #include <linux/interrupt.h>
>> +#include <linux/iosys-map.h>
>> #include <linux/spinlock.h>
>> #include <linux/workqueue.h>
>> #include <linux/ktime.h>
>> @@ -32,8 +33,8 @@ struct drm_printer;
>> * holds the commands.
>> *
>> * @lock: protects access to the commands buffer and buffer descriptor
>> - * @desc: pointer to the buffer descriptor
>> - * @cmds: pointer to the commands buffer
>> + * @desc: iosys map to the buffer descriptor
>> + * @cmds: iosys map to the commands buffer
>> * @size: size of the commands buffer in dwords
>> * @resv_space: reserved space in buffer in dwords
>> * @head: local shadow copy of head in dwords
>> @@ -43,8 +44,8 @@ struct drm_printer;
>> */
>> struct intel_guc_ct_buffer {
>> spinlock_t lock;
>> - struct guc_ct_buffer_desc *desc;
>> - u32 *cmds;
>> + struct iosys_map desc_map;
>> + struct iosys_map cmds_map;
>> u32 size;
>> u32 resv_space;
>> u32 tail;
>> --
>> 2.33.0
>>
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [Intel-gfx] [PATCH 1/1] drm/i915/guc: Convert ct buffer to iosys_map
2022-04-28 14:13 ` Siva Mullati
@ 2022-04-29 9:07 ` Balasubramani Vivekanandan
0 siblings, 0 replies; 14+ messages in thread
From: Balasubramani Vivekanandan @ 2022-04-29 9:07 UTC (permalink / raw)
To: Siva Mullati, intel-gfx; +Cc: lucas.demarchi
On 28.04.2022 19:43, Siva Mullati wrote:
>
> On 14/04/22 17:41, Balasubramani Vivekanandan wrote:
> > On 04.04.2022 15:01, Mullati Siva wrote:
> >> From: Siva Mullati <siva.mullati@intel.com>
> >>
> >> Convert CT commands and descriptors to use iosys_map rather
> >> than plain pointer and save it in the intel_guc_ct_buffer struct.
> >> This will help with ct_write and ct_read for cmd send and receive
> >> after the initialization by abstracting the IO vs system memory.
> >>
> >> Signed-off-by: Siva Mullati <siva.mullati@intel.com>
> >> ---
> >> drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 200 +++++++++++++---------
> >> drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h | 9 +-
> >> 2 files changed, 127 insertions(+), 82 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
> >> index f01325cd1b62..64568dc90b05 100644
> >> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
> >> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
> >> @@ -44,6 +44,11 @@ static inline struct drm_device *ct_to_drm(struct intel_guc_ct *ct)
> >> #define CT_PROBE_ERROR(_ct, _fmt, ...) \
> >> i915_probe_error(ct_to_i915(ct), "CT: " _fmt, ##__VA_ARGS__)
> >>
> >> +#define ct_desc_read(desc_map_, field_) \
> >> + iosys_map_rd_field(desc_map_, 0, struct guc_ct_buffer_desc, field_)
> >> +#define ct_desc_write(desc_map_, field_, val_) \
> >> + iosys_map_wr_field(desc_map_, 0, struct guc_ct_buffer_desc, field_, val_)
> >> +
> > Did you try to make the change Lucas mentioned in his comment on rev0,
> > to pass `struct guc_ct_buffer_desc *` as first argument to the above
> > macros? Was it not feasible?
> It is not feasible.
> >> /**
> >> * DOC: CTB Blob
> >> *
> >> @@ -76,6 +81,11 @@ static inline struct drm_device *ct_to_drm(struct intel_guc_ct *ct)
> >> #define CTB_G2H_BUFFER_SIZE (4 * CTB_H2G_BUFFER_SIZE)
> >> #define G2H_ROOM_BUFFER_SIZE (CTB_G2H_BUFFER_SIZE / 4)
> >>
> >> +#define CTB_SEND_DESC_OFFSET 0u
> >> +#define CTB_RECV_DESC_OFFSET (CTB_DESC_SIZE)
> >> +#define CTB_SEND_CMDS_OFFSET (2 * CTB_DESC_SIZE)
> >> +#define CTB_RECV_CMDS_OFFSET (2 * CTB_DESC_SIZE + CTB_H2G_BUFFER_SIZE)
> >> +
> >> struct ct_request {
> >> struct list_head link;
> >> u32 fence;
> >> @@ -113,9 +123,9 @@ void intel_guc_ct_init_early(struct intel_guc_ct *ct)
> >> init_waitqueue_head(&ct->wq);
> >> }
> >>
> >> -static void guc_ct_buffer_desc_init(struct guc_ct_buffer_desc *desc)
> >> +static void guc_ct_buffer_desc_init(struct iosys_map *desc)
> >> {
> >> - memset(desc, 0, sizeof(*desc));
> >> + iosys_map_memset(desc, 0, 0, sizeof(struct guc_ct_buffer_desc));
> >> }
> >>
> >> static void guc_ct_buffer_reset(struct intel_guc_ct_buffer *ctb)
> >> @@ -128,17 +138,18 @@ static void guc_ct_buffer_reset(struct intel_guc_ct_buffer *ctb)
> >> space = CIRC_SPACE(ctb->tail, ctb->head, ctb->size) - ctb->resv_space;
> >> atomic_set(&ctb->space, space);
> >>
> >> - guc_ct_buffer_desc_init(ctb->desc);
> >> + guc_ct_buffer_desc_init(&ctb->desc_map);
> >> }
> >>
> >> static void guc_ct_buffer_init(struct intel_guc_ct_buffer *ctb,
> >> - struct guc_ct_buffer_desc *desc,
> >> - u32 *cmds, u32 size_in_bytes, u32 resv_space)
> >> + struct iosys_map *desc,
> >> + struct iosys_map *cmds,
> >> + u32 size_in_bytes, u32 resv_space)
> >> {
> >> GEM_BUG_ON(size_in_bytes % 4);
> >>
> >> - ctb->desc = desc;
> >> - ctb->cmds = cmds;
> >> + ctb->desc_map = *desc;
> >> + ctb->cmds_map = *cmds;
> >> ctb->size = size_in_bytes / 4;
> >> ctb->resv_space = resv_space / 4;
> >>
> >> @@ -218,12 +229,13 @@ static int ct_register_buffer(struct intel_guc_ct *ct, bool send,
> >> int intel_guc_ct_init(struct intel_guc_ct *ct)
> >> {
> >> struct intel_guc *guc = ct_to_guc(ct);
> >> - struct guc_ct_buffer_desc *desc;
> >> + struct iosys_map blob_map;
> >> + struct iosys_map desc_map;
> >> + struct iosys_map cmds_map;
> >> u32 blob_size;
> >> u32 cmds_size;
> >> u32 resv_space;
> >> void *blob;
> >> - u32 *cmds;
> >> int err;
> >>
> >> err = i915_inject_probe_error(guc_to_gt(guc)->i915, -ENXIO);
> >> @@ -242,27 +254,35 @@ int intel_guc_ct_init(struct intel_guc_ct *ct)
> >>
> >> CT_DEBUG(ct, "base=%#x size=%u\n", intel_guc_ggtt_offset(guc, ct->vma), blob_size);
> >>
> >> - /* store pointers to desc and cmds for send ctb */
> >> - desc = blob;
> >> - cmds = blob + 2 * CTB_DESC_SIZE;
> >> + if (i915_gem_object_is_lmem(ct->vma->obj))
> >> + iosys_map_set_vaddr_iomem(&blob_map,
> >> + (void __iomem *)blob);
> >> + else
> >> + iosys_map_set_vaddr(&blob_map, blob);
> >> +
> >> + /* store sysmap to desc_map and cmds_map for send ctb */
> >> + desc_map = IOSYS_MAP_INIT_OFFSET(&blob_map, CTB_SEND_DESC_OFFSET);
> >> + cmds_map = IOSYS_MAP_INIT_OFFSET(&blob_map, CTB_SEND_CMDS_OFFSET);
> >> cmds_size = CTB_H2G_BUFFER_SIZE;
> >> resv_space = 0;
> >> - CT_DEBUG(ct, "%s desc %#tx cmds %#tx size %u/%u\n", "send",
> >> - ptrdiff(desc, blob), ptrdiff(cmds, blob), cmds_size,
> >> - resv_space);
> >> + CT_DEBUG(ct, "%s desc %#x cmds %#x size %u/%u\n", "send",
> >> + CTB_SEND_DESC_OFFSET, (u32)CTB_SEND_CMDS_OFFSET,
> >> + cmds_size, resv_space);
> >>
> >> - guc_ct_buffer_init(&ct->ctbs.send, desc, cmds, cmds_size, resv_space);
> >> + guc_ct_buffer_init(&ct->ctbs.send,
> >> + &desc_map, &cmds_map, cmds_size, resv_space);
> >>
> >> - /* store pointers to desc and cmds for recv ctb */
> >> - desc = blob + CTB_DESC_SIZE;
> >> - cmds = blob + 2 * CTB_DESC_SIZE + CTB_H2G_BUFFER_SIZE;
> >> + /* store sysmap to desc_map and cmds_map for recv ctb */
> >> + desc_map = IOSYS_MAP_INIT_OFFSET(&blob_map, CTB_RECV_DESC_OFFSET);
> >> + cmds_map = IOSYS_MAP_INIT_OFFSET(&blob_map, CTB_RECV_CMDS_OFFSET);
> >> cmds_size = CTB_G2H_BUFFER_SIZE;
> >> resv_space = G2H_ROOM_BUFFER_SIZE;
> >> - CT_DEBUG(ct, "%s desc %#tx cmds %#tx size %u/%u\n", "recv",
> >> - ptrdiff(desc, blob), ptrdiff(cmds, blob), cmds_size,
> >> - resv_space);
> >> + CT_DEBUG(ct, "%s desc %#x cmds %#x size %u/%u\n", "recv",
> >> + (u32)CTB_RECV_DESC_OFFSET, (u32)CTB_RECV_CMDS_OFFSET,
> >> + cmds_size, resv_space);
> >>
> >> - guc_ct_buffer_init(&ct->ctbs.recv, desc, cmds, cmds_size, resv_space);
> >> + guc_ct_buffer_init(&ct->ctbs.recv,
> >> + &desc_map, &cmds_map, cmds_size, resv_space);
> >>
> >> return 0;
> >> }
> >> @@ -279,6 +299,10 @@ void intel_guc_ct_fini(struct intel_guc_ct *ct)
> >>
> >> tasklet_kill(&ct->receive_tasklet);
> >> i915_vma_unpin_and_release(&ct->vma, I915_VMA_RELEASE_MAP);
> >> + iosys_map_clear(&ct->ctbs.send.desc_map);
> >> + iosys_map_clear(&ct->ctbs.send.cmds_map);
> >> + iosys_map_clear(&ct->ctbs.recv.desc_map);
> >> + iosys_map_clear(&ct->ctbs.recv.cmds_map);
> > I think there is no need of clearing the iosys_map when were are zeroing
> > the complete structure area below.
> Yes, I have updated this in latest revision.
> >> memset(ct, 0, sizeof(*ct));
> >> }
> >>
> >> @@ -291,8 +315,8 @@ void intel_guc_ct_fini(struct intel_guc_ct *ct)
> >> int intel_guc_ct_enable(struct intel_guc_ct *ct)
> >> {
> >> struct intel_guc *guc = ct_to_guc(ct);
> >> + struct iosys_map blob_map;
> >> u32 base, desc, cmds, size;
> >> - void *blob;
> >> int err;
> >>
> >> GEM_BUG_ON(ct->enabled);
> >> @@ -302,9 +326,14 @@ int intel_guc_ct_enable(struct intel_guc_ct *ct)
> >> GEM_BUG_ON(!i915_gem_object_has_pinned_pages(ct->vma->obj));
> >> base = intel_guc_ggtt_offset(guc, ct->vma);
> >>
> >> + if (i915_gem_object_is_lmem(ct->vma->obj))
> >> + iosys_map_set_vaddr_iomem(&blob_map, (void __iomem *)
> >> + __px_vaddr(ct->vma->obj));
> >> + else
> >> + iosys_map_set_vaddr(&blob_map, __px_vaddr(ct->vma->obj));
> >> +
> >> /* blob should start with send descriptor */
> >> - blob = __px_vaddr(ct->vma->obj);
> >> - GEM_BUG_ON(blob != ct->ctbs.send.desc);
> >> + GEM_BUG_ON(!iosys_map_is_equal(&blob_map, &ct->ctbs.send.desc_map));
> >>
> >> /* (re)initialize descriptors */
> >> guc_ct_buffer_reset(&ct->ctbs.send);
> >> @@ -314,15 +343,15 @@ int intel_guc_ct_enable(struct intel_guc_ct *ct)
> >> * Register both CT buffers starting with RECV buffer.
> >> * Descriptors are in first half of the blob.
> >> */
> >> - desc = base + ptrdiff(ct->ctbs.recv.desc, blob);
> >> - cmds = base + ptrdiff(ct->ctbs.recv.cmds, blob);
> >> + desc = base + CTB_RECV_DESC_OFFSET;
> >> + cmds = base + CTB_RECV_CMDS_OFFSET;
> >> size = ct->ctbs.recv.size * 4;
> >> err = ct_register_buffer(ct, false, desc, cmds, size);
> >> if (unlikely(err))
> >> goto err_out;
> >>
> >> - desc = base + ptrdiff(ct->ctbs.send.desc, blob);
> >> - cmds = base + ptrdiff(ct->ctbs.send.cmds, blob);
> >> + desc = base + CTB_SEND_DESC_OFFSET;
> >> + cmds = base + CTB_SEND_CMDS_OFFSET;
> >> size = ct->ctbs.send.size * 4;
> >> err = ct_register_buffer(ct, true, desc, cmds, size);
> >> if (unlikely(err))
> >> @@ -371,31 +400,33 @@ static int ct_write(struct intel_guc_ct *ct,
> >> u32 fence, u32 flags)
> >> {
> >> struct intel_guc_ct_buffer *ctb = &ct->ctbs.send;
> >> - struct guc_ct_buffer_desc *desc = ctb->desc;
> >> u32 tail = ctb->tail;
> >> u32 size = ctb->size;
> >> u32 header;
> >> u32 hxg;
> >> u32 type;
> >> - u32 *cmds = ctb->cmds;
> >> + u32 status = ct_desc_read(&ctb->desc_map, status);
> >> unsigned int i;
> >>
> >> - if (unlikely(desc->status))
> >> + if (unlikely(status))
> >> goto corrupted;
> >>
> >> GEM_BUG_ON(tail > size);
> >>
> >> #ifdef CONFIG_DRM_I915_DEBUG_GUC
> >> - if (unlikely(tail != READ_ONCE(desc->tail))) {
> >> + if (unlikely(tail != ct_desc_read(&ctb->desc_map, tail))) {
> >> CT_ERROR(ct, "Tail was modified %u != %u\n",
> >> - desc->tail, tail);
> >> - desc->status |= GUC_CTB_STATUS_MISMATCH;
> >> + ct_desc_read(&ctb->desc_map, tail), tail);
> >> + status |= GUC_CTB_STATUS_MISMATCH;
> >> + ct_desc_write(&ctb->desc_map, status, status);
> >> goto corrupted;
> >> }
> >> - if (unlikely(READ_ONCE(desc->head) >= size)) {
> >> + if (unlikely(ct_desc_read(&ctb->desc_map, head) >= size)) {
> >> CT_ERROR(ct, "Invalid head offset %u >= %u)\n",
> >> - desc->head, size);
> >> - desc->status |= GUC_CTB_STATUS_OVERFLOW;
> >> + ct_desc_read(&ctb->desc_map, head), size);
> > Can we avoid reading the head from ctb->desc_map twice? Since each
> > iosys_map read translates to memcpy, it is better to avoid repeating if
> > we can cache from the earlier read.
> Do you see real need of having a variable to cache value locally, considering the path is very unlikely to hit.
At first I thought reading the head twice just affects performance, but
after our discussion, I realized it can potentially mislead debugging.
As it is possible that head can be updated concurrently, we might print
a different value than what was really used in the if condition.
Printing a different value can mislead debugging. So we should print the
same value used in the condition.
Even in the original code, READ_ONCE is used only in the condition not
while printing.
> >> + status = ct_desc_read(&ctb->desc_map, status) |
> >> + GUC_CTB_STATUS_OVERFLOW;
> > Same here, can we avoid reading status since we already have it read. We
> > can do the same like how it is done for the GUC_CTB_STATUS_MISMATCH case.
> Addressed in latest patch
> >> + ct_desc_write(&ctb->desc_map, status, status);
> >> goto corrupted;
> >> }
> >> #endif
> >> @@ -418,14 +449,14 @@ static int ct_write(struct intel_guc_ct *ct,
> >> CT_DEBUG(ct, "writing (tail %u) %*ph %*ph %*ph\n",
> >> tail, 4, &header, 4, &hxg, 4 * (len - 1), &action[1]);
> >>
> >> - cmds[tail] = header;
> >> + iosys_map_wr(&ctb->cmds_map, 4 * tail, u32, header);
> > I prefer not to use the MAGIC number. My suggestion is to use
> > sizeof(tail) since we need the offset in bytes.
> I tried avoiding it, can't use sizeof(tail). Here tail is just an index which might be a misleading if we use it in this case, cmds would have been the right one but this has been changed to iosys map. Currently updated with sizeof(u32).
> >> tail = (tail + 1) % size;
> >>
> >> - cmds[tail] = hxg;
> >> + iosys_map_wr(&ctb->cmds_map, 4 * tail, u32, hxg);
> > MAGIC number again. There are numerous places in the patch, where
> > numbers are used. I prefer to remove it.
> >> tail = (tail + 1) % size;
> >>
> >> for (i = 1; i < len; i++) {
> >> - cmds[tail] = action[i];
> >> + iosys_map_wr(&ctb->cmds_map, 4 * tail, u32, action[i]);
> >> tail = (tail + 1) % size;
> >> }
> >> GEM_BUG_ON(tail > size);
> >> @@ -442,13 +473,14 @@ static int ct_write(struct intel_guc_ct *ct,
> >> atomic_sub(len + GUC_CTB_HDR_LEN, &ctb->space);
> >>
> >> /* now update descriptor */
> >> - WRITE_ONCE(desc->tail, tail);
> >> + ct_desc_write(&ctb->desc_map, tail, tail);
> >>
> >> return 0;
> >>
> >> corrupted:
> >> CT_ERROR(ct, "Corrupted descriptor head=%u tail=%u status=%#x\n",
> >> - desc->head, desc->tail, desc->status);
> >> + ct_desc_read(&ctb->desc_map, head), ct_desc_read(&ctb->desc_map, tail),
> >> + ct_desc_read(&ctb->desc_map, status));
> >> ctb->broken = true;
> >> return -EPIPE;
> >> }
> >> @@ -499,20 +531,22 @@ static inline bool ct_deadlocked(struct intel_guc_ct *ct)
> >> bool ret = ktime_ms_delta(ktime_get(), ct->stall_time) > timeout;
> >>
> >> if (unlikely(ret)) {
> >> - struct guc_ct_buffer_desc *send = ct->ctbs.send.desc;
> >> - struct guc_ct_buffer_desc *recv = ct->ctbs.send.desc;
> >> -
> >> CT_ERROR(ct, "Communication stalled for %lld ms, desc status=%#x,%#x\n",
> >> ktime_ms_delta(ktime_get(), ct->stall_time),
> >> - send->status, recv->status);
> >> + ct_desc_read(&ct->ctbs.send.desc_map, status),
> >> + ct_desc_read(&ct->ctbs.recv.desc_map, status));
> >> CT_ERROR(ct, "H2G Space: %u (Bytes)\n",
> >> atomic_read(&ct->ctbs.send.space) * 4);
> >> - CT_ERROR(ct, "Head: %u (Dwords)\n", ct->ctbs.send.desc->head);
> >> - CT_ERROR(ct, "Tail: %u (Dwords)\n", ct->ctbs.send.desc->tail);
> >> + CT_ERROR(ct, "Head: %u (Dwords)\n",
> >> + ct_desc_read(&ct->ctbs.send.desc_map, head));
> >> + CT_ERROR(ct, "Tail: %u (Dwords)\n",
> >> + ct_desc_read(&ct->ctbs.send.desc_map, tail));
> >> CT_ERROR(ct, "G2H Space: %u (Bytes)\n",
> >> atomic_read(&ct->ctbs.recv.space) * 4);
> >> - CT_ERROR(ct, "Head: %u\n (Dwords)", ct->ctbs.recv.desc->head);
> >> - CT_ERROR(ct, "Tail: %u\n (Dwords)", ct->ctbs.recv.desc->tail);
> >> + CT_ERROR(ct, "Head: %u\n (Dwords)",
> >> + ct_desc_read(&ct->ctbs.recv.desc_map, head));
> >> + CT_ERROR(ct, "Tail: %u\n (Dwords)",
> >> + ct_desc_read(&ct->ctbs.recv.desc_map, tail));
> >>
> >> ct->ctbs.send.broken = true;
> >> }
> >> @@ -549,18 +583,19 @@ static inline void g2h_release_space(struct intel_guc_ct *ct, u32 g2h_len_dw)
> >> static inline bool h2g_has_room(struct intel_guc_ct *ct, u32 len_dw)
> >> {
> >> struct intel_guc_ct_buffer *ctb = &ct->ctbs.send;
> >> - struct guc_ct_buffer_desc *desc = ctb->desc;
> >> u32 head;
> >> u32 space;
> >> + u32 status = ct_desc_read(&ctb->desc_map, status);
> >>
> >> if (atomic_read(&ctb->space) >= len_dw)
> >> return true;
> >>
> >> - head = READ_ONCE(desc->head);
> >> + head = ct_desc_read(&ctb->desc_map, head);
> >> if (unlikely(head > ctb->size)) {
> >> CT_ERROR(ct, "Invalid head offset %u >= %u)\n",
> >> head, ctb->size);
> >> - desc->status |= GUC_CTB_STATUS_OVERFLOW;
> >> + status |= GUC_CTB_STATUS_OVERFLOW;
> >> + ct_desc_write(&ctb->desc_map, status, status);
> >> ctb->broken = true;
> >> return false;
> >> }
> >> @@ -803,11 +838,10 @@ static void ct_free_msg(struct ct_incoming_msg *msg)
> >> static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg)
> >> {
> >> struct intel_guc_ct_buffer *ctb = &ct->ctbs.recv;
> >> - struct guc_ct_buffer_desc *desc = ctb->desc;
> >> u32 head = ctb->head;
> >> - u32 tail = READ_ONCE(desc->tail);
> >> + u32 tail = ct_desc_read(&ctb->desc_map, tail);
> >> u32 size = ctb->size;
> >> - u32 *cmds = ctb->cmds;
> >> + u32 status = ct_desc_read(&ctb->desc_map, status);
> >> s32 available;
> >> unsigned int len;
> >> unsigned int i;
> >> @@ -816,23 +850,26 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg)
> >> if (unlikely(ctb->broken))
> >> return -EPIPE;
> >>
> >> - if (unlikely(desc->status))
> >> + if (unlikely(status))
> >> goto corrupted;
> >>
> >> GEM_BUG_ON(head > size);
> >>
> >> #ifdef CONFIG_DRM_I915_DEBUG_GUC
> >> - if (unlikely(head != READ_ONCE(desc->head))) {
> >> + if (unlikely(head != ct_desc_read(&ctb->desc_map, head))) {
> >> CT_ERROR(ct, "Head was modified %u != %u\n",
> >> - desc->head, head);
> >> - desc->status |= GUC_CTB_STATUS_MISMATCH;
> >> + ct_desc_read(&ctb->desc_map, head), head);
> > head read twice here as well.
> Same answer.
> >> + status |= GUC_CTB_STATUS_MISMATCH;
> >> + ct_desc_write(&ctb->desc_map, status, status);
> >> goto corrupted;
> >> }
> >> #endif
> >> if (unlikely(tail >= size)) {
> >> CT_ERROR(ct, "Invalid tail offset %u >= %u)\n",
> >> tail, size);
> >> - desc->status |= GUC_CTB_STATUS_OVERFLOW;
> >> + status = ct_desc_read(&ctb->desc_map, status) |
> >> + GUC_CTB_STATUS_OVERFLOW;
> > No need to read the status again as we already have it cached.
> addressed.
> >> + ct_desc_write(&ctb->desc_map, status, status);
> >> goto corrupted;
> >> }
> >>
> >> @@ -849,7 +886,7 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg)
> >> CT_DEBUG(ct, "available %d (%u:%u:%u)\n", available, head, tail, size);
> >> GEM_BUG_ON(available < 0);
> >>
> >> - header = cmds[head];
> >> + header = iosys_map_rd(&ctb->cmds_map, (4 * head), u32);
> > MAGIC numbers
> >> head = (head + 1) % size;
> >>
> >> /* message len with header */
> >> @@ -857,11 +894,15 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg)
> >> if (unlikely(len > (u32)available)) {
> >> CT_ERROR(ct, "Incomplete message %*ph %*ph %*ph\n",
> >> 4, &header,
> >> + 4 * (head + available - 1 > size ? size - head :
> >> + available - 1), ((__px_vaddr(ct->vma->obj) +
> >> + CTB_RECV_CMDS_OFFSET) + (4 * head)),
> >> 4 * (head + available - 1 > size ?
> >> - size - head : available - 1), &cmds[head],
> >> - 4 * (head + available - 1 > size ?
> >> - available - 1 - size + head : 0), &cmds[0]);
> >> - desc->status |= GUC_CTB_STATUS_UNDERFLOW;
> >> + available - 1 - size + head : 0),
> >> + (__px_vaddr(ct->vma->obj) + CTB_RECV_CMDS_OFFSET));
> >> + status = ct_desc_read(&ctb->desc_map, status) |
> >> + GUC_CTB_STATUS_UNDERFLOW;
> > No need to read status again
> >
> > Regards,
> > Bala
> >> + ct_desc_write(&ctb->desc_map, status, status);
> >> goto corrupted;
> >> }
> >>
> >> @@ -869,17 +910,18 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg)
> >> if (!*msg) {
> >> CT_ERROR(ct, "No memory for message %*ph %*ph %*ph\n",
> >> 4, &header,
> >> + 4 * (head + available - 1 > size ? size - head :
> >> + available - 1), (ctb->cmds_map.vaddr + (4 * head)),
> >> 4 * (head + available - 1 > size ?
> >> - size - head : available - 1), &cmds[head],
> >> - 4 * (head + available - 1 > size ?
> >> - available - 1 - size + head : 0), &cmds[0]);
> >> + available - 1 - size + head : 0), ctb->cmds_map.vaddr);
> >> return available;
> >> }
> >>
> >> (*msg)->msg[0] = header;
> >>
> >> for (i = 1; i < len; i++) {
> >> - (*msg)->msg[i] = cmds[head];
> >> + (*msg)->msg[i] = iosys_map_rd(&ctb->cmds_map,
> >> + (4 * head), u32);
> >> head = (head + 1) % size;
> >> }
> >> CT_DEBUG(ct, "received %*ph\n", 4 * len, (*msg)->msg);
> >> @@ -888,13 +930,15 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg)
> >> ctb->head = head;
> >>
> >> /* now update descriptor */
> >> - WRITE_ONCE(desc->head, head);
> >> + ct_desc_write(&ctb->desc_map, head, head);
> >>
> >> return available - len;
> >>
> >> corrupted:
> >> CT_ERROR(ct, "Corrupted descriptor head=%u tail=%u status=%#x\n",
> >> - desc->head, desc->tail, desc->status);
> >> + ct_desc_read(&ctb->desc_map, head),
> >> + ct_desc_read(&ctb->desc_map, tail),
> >> + ct_desc_read(&ctb->desc_map, status));
> >> ctb->broken = true;
> >> return -EPIPE;
> >> }
> >> @@ -1211,13 +1255,13 @@ void intel_guc_ct_print_info(struct intel_guc_ct *ct,
> >> drm_printf(p, "H2G Space: %u\n",
> >> atomic_read(&ct->ctbs.send.space) * 4);
> >> drm_printf(p, "Head: %u\n",
> >> - ct->ctbs.send.desc->head);
> >> + ct_desc_read(&ct->ctbs.send.desc_map, head));
> >> drm_printf(p, "Tail: %u\n",
> >> - ct->ctbs.send.desc->tail);
> >> + ct_desc_read(&ct->ctbs.send.desc_map, tail));
> >> drm_printf(p, "G2H Space: %u\n",
> >> atomic_read(&ct->ctbs.recv.space) * 4);
> >> drm_printf(p, "Head: %u\n",
> >> - ct->ctbs.recv.desc->head);
> >> + ct_desc_read(&ct->ctbs.recv.desc_map, head));
> >> drm_printf(p, "Tail: %u\n",
> >> - ct->ctbs.recv.desc->tail);
> >> + ct_desc_read(&ct->ctbs.recv.desc_map, tail));
> >> }
> >> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h
> >> index f709a19c7e21..867fe13fb47d 100644
> >> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h
> >> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h
> >> @@ -7,6 +7,7 @@
> >> #define _INTEL_GUC_CT_H_
> >>
> >> #include <linux/interrupt.h>
> >> +#include <linux/iosys-map.h>
> >> #include <linux/spinlock.h>
> >> #include <linux/workqueue.h>
> >> #include <linux/ktime.h>
> >> @@ -32,8 +33,8 @@ struct drm_printer;
> >> * holds the commands.
> >> *
> >> * @lock: protects access to the commands buffer and buffer descriptor
> >> - * @desc: pointer to the buffer descriptor
> >> - * @cmds: pointer to the commands buffer
> >> + * @desc: iosys map to the buffer descriptor
> >> + * @cmds: iosys map to the commands buffer
> >> * @size: size of the commands buffer in dwords
> >> * @resv_space: reserved space in buffer in dwords
> >> * @head: local shadow copy of head in dwords
> >> @@ -43,8 +44,8 @@ struct drm_printer;
> >> */
> >> struct intel_guc_ct_buffer {
> >> spinlock_t lock;
> >> - struct guc_ct_buffer_desc *desc;
> >> - u32 *cmds;
> >> + struct iosys_map desc_map;
> >> + struct iosys_map cmds_map;
> >> u32 size;
> >> u32 resv_space;
> >> u32 tail;
> >> --
> >> 2.33.0
> >>
^ permalink raw reply [flat|nested] 14+ messages in thread
* [Intel-gfx] [PATCH 1/1] drm/i915/guc: Convert ct buffer to iosys_map
2022-05-09 6:49 [Intel-gfx] [PATCH 0/1] drm/i915/guc: " Mullati Siva
@ 2022-05-09 6:49 ` Mullati Siva
2022-05-11 15:15 ` Balasubramani Vivekanandan
0 siblings, 1 reply; 14+ messages in thread
From: Mullati Siva @ 2022-05-09 6:49 UTC (permalink / raw)
To: intel-gfx, siva.mullati; +Cc: lucas.demarchi
From: Siva Mullati <siva.mullati@intel.com>
Convert CT commands and descriptors to use iosys_map rather
than plain pointer and save it in the intel_guc_ct_buffer struct.
This will help with ct_write and ct_read for cmd send and receive
after the initialization by abstracting the IO vs system memory.
Signed-off-by: Siva Mullati <siva.mullati@intel.com>
---
drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 195 +++++++++++++---------
drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h | 9 +-
2 files changed, 122 insertions(+), 82 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
index f01325cd1b62..bd5b4312d968 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
@@ -44,6 +44,11 @@ static inline struct drm_device *ct_to_drm(struct intel_guc_ct *ct)
#define CT_PROBE_ERROR(_ct, _fmt, ...) \
i915_probe_error(ct_to_i915(ct), "CT: " _fmt, ##__VA_ARGS__)
+#define ct_desc_read(desc_map_, field_) \
+ iosys_map_rd_field(desc_map_, 0, struct guc_ct_buffer_desc, field_)
+#define ct_desc_write(desc_map_, field_, val_) \
+ iosys_map_wr_field(desc_map_, 0, struct guc_ct_buffer_desc, field_, val_)
+
/**
* DOC: CTB Blob
*
@@ -76,6 +81,11 @@ static inline struct drm_device *ct_to_drm(struct intel_guc_ct *ct)
#define CTB_G2H_BUFFER_SIZE (4 * CTB_H2G_BUFFER_SIZE)
#define G2H_ROOM_BUFFER_SIZE (CTB_G2H_BUFFER_SIZE / 4)
+#define CTB_SEND_DESC_OFFSET 0u
+#define CTB_RECV_DESC_OFFSET (CTB_DESC_SIZE)
+#define CTB_SEND_CMDS_OFFSET (2 * CTB_DESC_SIZE)
+#define CTB_RECV_CMDS_OFFSET (2 * CTB_DESC_SIZE + CTB_H2G_BUFFER_SIZE)
+
struct ct_request {
struct list_head link;
u32 fence;
@@ -113,9 +123,9 @@ void intel_guc_ct_init_early(struct intel_guc_ct *ct)
init_waitqueue_head(&ct->wq);
}
-static void guc_ct_buffer_desc_init(struct guc_ct_buffer_desc *desc)
+static void guc_ct_buffer_desc_init(struct iosys_map *desc)
{
- memset(desc, 0, sizeof(*desc));
+ iosys_map_memset(desc, 0, 0, sizeof(struct guc_ct_buffer_desc));
}
static void guc_ct_buffer_reset(struct intel_guc_ct_buffer *ctb)
@@ -128,17 +138,18 @@ static void guc_ct_buffer_reset(struct intel_guc_ct_buffer *ctb)
space = CIRC_SPACE(ctb->tail, ctb->head, ctb->size) - ctb->resv_space;
atomic_set(&ctb->space, space);
- guc_ct_buffer_desc_init(ctb->desc);
+ guc_ct_buffer_desc_init(&ctb->desc_map);
}
static void guc_ct_buffer_init(struct intel_guc_ct_buffer *ctb,
- struct guc_ct_buffer_desc *desc,
- u32 *cmds, u32 size_in_bytes, u32 resv_space)
+ struct iosys_map *desc,
+ struct iosys_map *cmds,
+ u32 size_in_bytes, u32 resv_space)
{
GEM_BUG_ON(size_in_bytes % 4);
- ctb->desc = desc;
- ctb->cmds = cmds;
+ ctb->desc_map = *desc;
+ ctb->cmds_map = *cmds;
ctb->size = size_in_bytes / 4;
ctb->resv_space = resv_space / 4;
@@ -218,12 +229,13 @@ static int ct_register_buffer(struct intel_guc_ct *ct, bool send,
int intel_guc_ct_init(struct intel_guc_ct *ct)
{
struct intel_guc *guc = ct_to_guc(ct);
- struct guc_ct_buffer_desc *desc;
+ struct iosys_map blob_map;
+ struct iosys_map desc_map;
+ struct iosys_map cmds_map;
u32 blob_size;
u32 cmds_size;
u32 resv_space;
void *blob;
- u32 *cmds;
int err;
err = i915_inject_probe_error(guc_to_gt(guc)->i915, -ENXIO);
@@ -242,27 +254,35 @@ int intel_guc_ct_init(struct intel_guc_ct *ct)
CT_DEBUG(ct, "base=%#x size=%u\n", intel_guc_ggtt_offset(guc, ct->vma), blob_size);
- /* store pointers to desc and cmds for send ctb */
- desc = blob;
- cmds = blob + 2 * CTB_DESC_SIZE;
+ if (i915_gem_object_is_lmem(ct->vma->obj))
+ iosys_map_set_vaddr_iomem(&blob_map,
+ (void __iomem *)blob);
+ else
+ iosys_map_set_vaddr(&blob_map, blob);
+
+ /* store sysmap to desc_map and cmds_map for send ctb */
+ desc_map = IOSYS_MAP_INIT_OFFSET(&blob_map, CTB_SEND_DESC_OFFSET);
+ cmds_map = IOSYS_MAP_INIT_OFFSET(&blob_map, CTB_SEND_CMDS_OFFSET);
cmds_size = CTB_H2G_BUFFER_SIZE;
resv_space = 0;
- CT_DEBUG(ct, "%s desc %#tx cmds %#tx size %u/%u\n", "send",
- ptrdiff(desc, blob), ptrdiff(cmds, blob), cmds_size,
- resv_space);
+ CT_DEBUG(ct, "%s desc %#x cmds %#x size %u/%u\n", "send",
+ CTB_SEND_DESC_OFFSET, (u32)CTB_SEND_CMDS_OFFSET,
+ cmds_size, resv_space);
- guc_ct_buffer_init(&ct->ctbs.send, desc, cmds, cmds_size, resv_space);
+ guc_ct_buffer_init(&ct->ctbs.send,
+ &desc_map, &cmds_map, cmds_size, resv_space);
- /* store pointers to desc and cmds for recv ctb */
- desc = blob + CTB_DESC_SIZE;
- cmds = blob + 2 * CTB_DESC_SIZE + CTB_H2G_BUFFER_SIZE;
+ /* store sysmap to desc_map and cmds_map for recv ctb */
+ desc_map = IOSYS_MAP_INIT_OFFSET(&blob_map, CTB_RECV_DESC_OFFSET);
+ cmds_map = IOSYS_MAP_INIT_OFFSET(&blob_map, CTB_RECV_CMDS_OFFSET);
cmds_size = CTB_G2H_BUFFER_SIZE;
resv_space = G2H_ROOM_BUFFER_SIZE;
- CT_DEBUG(ct, "%s desc %#tx cmds %#tx size %u/%u\n", "recv",
- ptrdiff(desc, blob), ptrdiff(cmds, blob), cmds_size,
- resv_space);
+ CT_DEBUG(ct, "%s desc %#x cmds %#x size %u/%u\n", "recv",
+ (u32)CTB_RECV_DESC_OFFSET, (u32)CTB_RECV_CMDS_OFFSET,
+ cmds_size, resv_space);
- guc_ct_buffer_init(&ct->ctbs.recv, desc, cmds, cmds_size, resv_space);
+ guc_ct_buffer_init(&ct->ctbs.recv,
+ &desc_map, &cmds_map, cmds_size, resv_space);
return 0;
}
@@ -291,8 +311,8 @@ void intel_guc_ct_fini(struct intel_guc_ct *ct)
int intel_guc_ct_enable(struct intel_guc_ct *ct)
{
struct intel_guc *guc = ct_to_guc(ct);
+ struct iosys_map blob_map;
u32 base, desc, cmds, size;
- void *blob;
int err;
GEM_BUG_ON(ct->enabled);
@@ -302,9 +322,14 @@ int intel_guc_ct_enable(struct intel_guc_ct *ct)
GEM_BUG_ON(!i915_gem_object_has_pinned_pages(ct->vma->obj));
base = intel_guc_ggtt_offset(guc, ct->vma);
+ if (i915_gem_object_is_lmem(ct->vma->obj))
+ iosys_map_set_vaddr_iomem(&blob_map, (void __iomem *)
+ __px_vaddr(ct->vma->obj));
+ else
+ iosys_map_set_vaddr(&blob_map, __px_vaddr(ct->vma->obj));
+
/* blob should start with send descriptor */
- blob = __px_vaddr(ct->vma->obj);
- GEM_BUG_ON(blob != ct->ctbs.send.desc);
+ GEM_BUG_ON(!iosys_map_is_equal(&blob_map, &ct->ctbs.send.desc_map));
/* (re)initialize descriptors */
guc_ct_buffer_reset(&ct->ctbs.send);
@@ -314,15 +339,15 @@ int intel_guc_ct_enable(struct intel_guc_ct *ct)
* Register both CT buffers starting with RECV buffer.
* Descriptors are in first half of the blob.
*/
- desc = base + ptrdiff(ct->ctbs.recv.desc, blob);
- cmds = base + ptrdiff(ct->ctbs.recv.cmds, blob);
+ desc = base + CTB_RECV_DESC_OFFSET;
+ cmds = base + CTB_RECV_CMDS_OFFSET;
size = ct->ctbs.recv.size * 4;
err = ct_register_buffer(ct, false, desc, cmds, size);
if (unlikely(err))
goto err_out;
- desc = base + ptrdiff(ct->ctbs.send.desc, blob);
- cmds = base + ptrdiff(ct->ctbs.send.cmds, blob);
+ desc = base + CTB_SEND_DESC_OFFSET;
+ cmds = base + CTB_SEND_CMDS_OFFSET;
size = ct->ctbs.send.size * 4;
err = ct_register_buffer(ct, true, desc, cmds, size);
if (unlikely(err))
@@ -371,31 +396,33 @@ static int ct_write(struct intel_guc_ct *ct,
u32 fence, u32 flags)
{
struct intel_guc_ct_buffer *ctb = &ct->ctbs.send;
- struct guc_ct_buffer_desc *desc = ctb->desc;
u32 tail = ctb->tail;
u32 size = ctb->size;
u32 header;
u32 hxg;
u32 type;
- u32 *cmds = ctb->cmds;
+ u32 status = ct_desc_read(&ctb->desc_map, status);
+ u32 desc_head = ct_desc_read(&ctb->desc_map, head);
unsigned int i;
- if (unlikely(desc->status))
+ if (unlikely(status))
goto corrupted;
GEM_BUG_ON(tail > size);
#ifdef CONFIG_DRM_I915_DEBUG_GUC
- if (unlikely(tail != READ_ONCE(desc->tail))) {
+ if (unlikely(tail != ct_desc_read(&ctb->desc_map, tail))) {
CT_ERROR(ct, "Tail was modified %u != %u\n",
- desc->tail, tail);
- desc->status |= GUC_CTB_STATUS_MISMATCH;
+ ct_desc_read(&ctb->desc_map, tail), tail);
+ status |= GUC_CTB_STATUS_MISMATCH;
+ ct_desc_write(&ctb->desc_map, status, status);
goto corrupted;
}
- if (unlikely(READ_ONCE(desc->head) >= size)) {
+ if (unlikely(desc_head >= size)) {
CT_ERROR(ct, "Invalid head offset %u >= %u)\n",
- desc->head, size);
- desc->status |= GUC_CTB_STATUS_OVERFLOW;
+ desc_head, size);
+ status |= GUC_CTB_STATUS_OVERFLOW;
+ ct_desc_write(&ctb->desc_map, status, status);
goto corrupted;
}
#endif
@@ -418,14 +445,15 @@ static int ct_write(struct intel_guc_ct *ct,
CT_DEBUG(ct, "writing (tail %u) %*ph %*ph %*ph\n",
tail, 4, &header, 4, &hxg, 4 * (len - 1), &action[1]);
- cmds[tail] = header;
+ iosys_map_wr(&ctb->cmds_map, sizeof(u32) * tail, u32, header);
tail = (tail + 1) % size;
- cmds[tail] = hxg;
+ iosys_map_wr(&ctb->cmds_map, sizeof(u32) * tail, u32, hxg);
tail = (tail + 1) % size;
for (i = 1; i < len; i++) {
- cmds[tail] = action[i];
+ iosys_map_wr(&ctb->cmds_map,
+ sizeof(u32) * tail, u32, action[i]);
tail = (tail + 1) % size;
}
GEM_BUG_ON(tail > size);
@@ -442,13 +470,13 @@ static int ct_write(struct intel_guc_ct *ct,
atomic_sub(len + GUC_CTB_HDR_LEN, &ctb->space);
/* now update descriptor */
- WRITE_ONCE(desc->tail, tail);
+ ct_desc_write(&ctb->desc_map, tail, tail);
return 0;
corrupted:
CT_ERROR(ct, "Corrupted descriptor head=%u tail=%u status=%#x\n",
- desc->head, desc->tail, desc->status);
+ desc_head, ct_desc_read(&ctb->desc_map, tail), status);
ctb->broken = true;
return -EPIPE;
}
@@ -499,20 +527,22 @@ static inline bool ct_deadlocked(struct intel_guc_ct *ct)
bool ret = ktime_ms_delta(ktime_get(), ct->stall_time) > timeout;
if (unlikely(ret)) {
- struct guc_ct_buffer_desc *send = ct->ctbs.send.desc;
- struct guc_ct_buffer_desc *recv = ct->ctbs.send.desc;
-
CT_ERROR(ct, "Communication stalled for %lld ms, desc status=%#x,%#x\n",
ktime_ms_delta(ktime_get(), ct->stall_time),
- send->status, recv->status);
+ ct_desc_read(&ct->ctbs.send.desc_map, status),
+ ct_desc_read(&ct->ctbs.recv.desc_map, status));
CT_ERROR(ct, "H2G Space: %u (Bytes)\n",
atomic_read(&ct->ctbs.send.space) * 4);
- CT_ERROR(ct, "Head: %u (Dwords)\n", ct->ctbs.send.desc->head);
- CT_ERROR(ct, "Tail: %u (Dwords)\n", ct->ctbs.send.desc->tail);
+ CT_ERROR(ct, "Head: %u (Dwords)\n",
+ ct_desc_read(&ct->ctbs.send.desc_map, head));
+ CT_ERROR(ct, "Tail: %u (Dwords)\n",
+ ct_desc_read(&ct->ctbs.send.desc_map, tail));
CT_ERROR(ct, "G2H Space: %u (Bytes)\n",
atomic_read(&ct->ctbs.recv.space) * 4);
- CT_ERROR(ct, "Head: %u\n (Dwords)", ct->ctbs.recv.desc->head);
- CT_ERROR(ct, "Tail: %u\n (Dwords)", ct->ctbs.recv.desc->tail);
+ CT_ERROR(ct, "Head: %u\n (Dwords)",
+ ct_desc_read(&ct->ctbs.recv.desc_map, head));
+ CT_ERROR(ct, "Tail: %u\n (Dwords)",
+ ct_desc_read(&ct->ctbs.recv.desc_map, tail));
ct->ctbs.send.broken = true;
}
@@ -549,18 +579,19 @@ static inline void g2h_release_space(struct intel_guc_ct *ct, u32 g2h_len_dw)
static inline bool h2g_has_room(struct intel_guc_ct *ct, u32 len_dw)
{
struct intel_guc_ct_buffer *ctb = &ct->ctbs.send;
- struct guc_ct_buffer_desc *desc = ctb->desc;
u32 head;
u32 space;
+ u32 status = ct_desc_read(&ctb->desc_map, status);
if (atomic_read(&ctb->space) >= len_dw)
return true;
- head = READ_ONCE(desc->head);
+ head = ct_desc_read(&ctb->desc_map, head);
if (unlikely(head > ctb->size)) {
CT_ERROR(ct, "Invalid head offset %u >= %u)\n",
head, ctb->size);
- desc->status |= GUC_CTB_STATUS_OVERFLOW;
+ status |= GUC_CTB_STATUS_OVERFLOW;
+ ct_desc_write(&ctb->desc_map, status, status);
ctb->broken = true;
return false;
}
@@ -803,11 +834,11 @@ static void ct_free_msg(struct ct_incoming_msg *msg)
static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg)
{
struct intel_guc_ct_buffer *ctb = &ct->ctbs.recv;
- struct guc_ct_buffer_desc *desc = ctb->desc;
u32 head = ctb->head;
- u32 tail = READ_ONCE(desc->tail);
+ u32 tail = ct_desc_read(&ctb->desc_map, tail);
u32 size = ctb->size;
- u32 *cmds = ctb->cmds;
+ u32 status = ct_desc_read(&ctb->desc_map, status);
+ u32 desc_head = ct_desc_read(&ctb->desc_map, head);
s32 available;
unsigned int len;
unsigned int i;
@@ -816,23 +847,25 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg)
if (unlikely(ctb->broken))
return -EPIPE;
- if (unlikely(desc->status))
+ if (unlikely(status))
goto corrupted;
GEM_BUG_ON(head > size);
#ifdef CONFIG_DRM_I915_DEBUG_GUC
- if (unlikely(head != READ_ONCE(desc->head))) {
+ if (unlikely(head != desc_head)) {
CT_ERROR(ct, "Head was modified %u != %u\n",
- desc->head, head);
- desc->status |= GUC_CTB_STATUS_MISMATCH;
+ desc_head, head);
+ status |= GUC_CTB_STATUS_MISMATCH;
+ ct_desc_write(&ctb->desc_map, status, status);
goto corrupted;
}
#endif
if (unlikely(tail >= size)) {
CT_ERROR(ct, "Invalid tail offset %u >= %u)\n",
tail, size);
- desc->status |= GUC_CTB_STATUS_OVERFLOW;
+ status |= GUC_CTB_STATUS_OVERFLOW;
+ ct_desc_write(&ctb->desc_map, status, status);
goto corrupted;
}
@@ -849,7 +882,7 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg)
CT_DEBUG(ct, "available %d (%u:%u:%u)\n", available, head, tail, size);
GEM_BUG_ON(available < 0);
- header = cmds[head];
+ header = iosys_map_rd(&ctb->cmds_map, sizeof(u32) * head, u32);
head = (head + 1) % size;
/* message len with header */
@@ -857,11 +890,14 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg)
if (unlikely(len > (u32)available)) {
CT_ERROR(ct, "Incomplete message %*ph %*ph %*ph\n",
4, &header,
+ 4 * (head + available - 1 > size ? size - head :
+ available - 1), ((__px_vaddr(ct->vma->obj) +
+ CTB_RECV_CMDS_OFFSET) + (4 * head)),
4 * (head + available - 1 > size ?
- size - head : available - 1), &cmds[head],
- 4 * (head + available - 1 > size ?
- available - 1 - size + head : 0), &cmds[0]);
- desc->status |= GUC_CTB_STATUS_UNDERFLOW;
+ available - 1 - size + head : 0),
+ (__px_vaddr(ct->vma->obj) + CTB_RECV_CMDS_OFFSET));
+ status |= GUC_CTB_STATUS_UNDERFLOW;
+ ct_desc_write(&ctb->desc_map, status, status);
goto corrupted;
}
@@ -869,17 +905,20 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg)
if (!*msg) {
CT_ERROR(ct, "No memory for message %*ph %*ph %*ph\n",
4, &header,
+ 4 * (head + available - 1 > size ? size - head :
+ available - 1), ((__px_vaddr(ct->vma->obj) +
+ CTB_RECV_CMDS_OFFSET) + (4 * head)),
4 * (head + available - 1 > size ?
- size - head : available - 1), &cmds[head],
- 4 * (head + available - 1 > size ?
- available - 1 - size + head : 0), &cmds[0]);
+ available - 1 - size + head : 0),
+ (__px_vaddr(ct->vma->obj) + CTB_RECV_CMDS_OFFSET));
return available;
}
(*msg)->msg[0] = header;
for (i = 1; i < len; i++) {
- (*msg)->msg[i] = cmds[head];
+ (*msg)->msg[i] = iosys_map_rd(&ctb->cmds_map,
+ sizeof(u32) * head, u32);
head = (head + 1) % size;
}
CT_DEBUG(ct, "received %*ph\n", 4 * len, (*msg)->msg);
@@ -888,13 +927,13 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg)
ctb->head = head;
/* now update descriptor */
- WRITE_ONCE(desc->head, head);
+ ct_desc_write(&ctb->desc_map, head, head);
return available - len;
corrupted:
CT_ERROR(ct, "Corrupted descriptor head=%u tail=%u status=%#x\n",
- desc->head, desc->tail, desc->status);
+ desc_head, ct_desc_read(&ctb->desc_map, tail), status);
ctb->broken = true;
return -EPIPE;
}
@@ -1211,13 +1250,13 @@ void intel_guc_ct_print_info(struct intel_guc_ct *ct,
drm_printf(p, "H2G Space: %u\n",
atomic_read(&ct->ctbs.send.space) * 4);
drm_printf(p, "Head: %u\n",
- ct->ctbs.send.desc->head);
+ ct_desc_read(&ct->ctbs.send.desc_map, head));
drm_printf(p, "Tail: %u\n",
- ct->ctbs.send.desc->tail);
+ ct_desc_read(&ct->ctbs.send.desc_map, tail));
drm_printf(p, "G2H Space: %u\n",
atomic_read(&ct->ctbs.recv.space) * 4);
drm_printf(p, "Head: %u\n",
- ct->ctbs.recv.desc->head);
+ ct_desc_read(&ct->ctbs.recv.desc_map, head));
drm_printf(p, "Tail: %u\n",
- ct->ctbs.recv.desc->tail);
+ ct_desc_read(&ct->ctbs.recv.desc_map, tail));
}
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h
index f709a19c7e21..867fe13fb47d 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h
@@ -7,6 +7,7 @@
#define _INTEL_GUC_CT_H_
#include <linux/interrupt.h>
+#include <linux/iosys-map.h>
#include <linux/spinlock.h>
#include <linux/workqueue.h>
#include <linux/ktime.h>
@@ -32,8 +33,8 @@ struct drm_printer;
* holds the commands.
*
* @lock: protects access to the commands buffer and buffer descriptor
- * @desc: pointer to the buffer descriptor
- * @cmds: pointer to the commands buffer
+ * @desc: iosys map to the buffer descriptor
+ * @cmds: iosys map to the commands buffer
* @size: size of the commands buffer in dwords
* @resv_space: reserved space in buffer in dwords
* @head: local shadow copy of head in dwords
@@ -43,8 +44,8 @@ struct drm_printer;
*/
struct intel_guc_ct_buffer {
spinlock_t lock;
- struct guc_ct_buffer_desc *desc;
- u32 *cmds;
+ struct iosys_map desc_map;
+ struct iosys_map cmds_map;
u32 size;
u32 resv_space;
u32 tail;
--
2.33.0
^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [Intel-gfx] [PATCH 1/1] drm/i915/guc: Convert ct buffer to iosys_map
2022-05-09 6:49 ` [Intel-gfx] [PATCH 1/1] drm/i915/guc: Convert ct buffer to iosys_map Mullati Siva
@ 2022-05-11 15:15 ` Balasubramani Vivekanandan
0 siblings, 0 replies; 14+ messages in thread
From: Balasubramani Vivekanandan @ 2022-05-11 15:15 UTC (permalink / raw)
To: Mullati Siva, intel-gfx; +Cc: lucas.demarchi
On 09.05.2022 12:19, Mullati Siva wrote:
> From: Siva Mullati <siva.mullati@intel.com>
>
> Convert CT commands and descriptors to use iosys_map rather
> than plain pointer and save it in the intel_guc_ct_buffer struct.
> This will help with ct_write and ct_read for cmd send and receive
> after the initialization by abstracting the IO vs system memory.
>
> Signed-off-by: Siva Mullati <siva.mullati@intel.com>
Acked-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
> ---
> drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 195 +++++++++++++---------
> drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h | 9 +-
> 2 files changed, 122 insertions(+), 82 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
> index f01325cd1b62..bd5b4312d968 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
> @@ -44,6 +44,11 @@ static inline struct drm_device *ct_to_drm(struct intel_guc_ct *ct)
> #define CT_PROBE_ERROR(_ct, _fmt, ...) \
> i915_probe_error(ct_to_i915(ct), "CT: " _fmt, ##__VA_ARGS__)
>
> +#define ct_desc_read(desc_map_, field_) \
> + iosys_map_rd_field(desc_map_, 0, struct guc_ct_buffer_desc, field_)
> +#define ct_desc_write(desc_map_, field_, val_) \
> + iosys_map_wr_field(desc_map_, 0, struct guc_ct_buffer_desc, field_, val_)
> +
> /**
> * DOC: CTB Blob
> *
> @@ -76,6 +81,11 @@ static inline struct drm_device *ct_to_drm(struct intel_guc_ct *ct)
> #define CTB_G2H_BUFFER_SIZE (4 * CTB_H2G_BUFFER_SIZE)
> #define G2H_ROOM_BUFFER_SIZE (CTB_G2H_BUFFER_SIZE / 4)
>
> +#define CTB_SEND_DESC_OFFSET 0u
> +#define CTB_RECV_DESC_OFFSET (CTB_DESC_SIZE)
> +#define CTB_SEND_CMDS_OFFSET (2 * CTB_DESC_SIZE)
> +#define CTB_RECV_CMDS_OFFSET (2 * CTB_DESC_SIZE + CTB_H2G_BUFFER_SIZE)
> +
> struct ct_request {
> struct list_head link;
> u32 fence;
> @@ -113,9 +123,9 @@ void intel_guc_ct_init_early(struct intel_guc_ct *ct)
> init_waitqueue_head(&ct->wq);
> }
>
> -static void guc_ct_buffer_desc_init(struct guc_ct_buffer_desc *desc)
> +static void guc_ct_buffer_desc_init(struct iosys_map *desc)
> {
> - memset(desc, 0, sizeof(*desc));
> + iosys_map_memset(desc, 0, 0, sizeof(struct guc_ct_buffer_desc));
> }
>
> static void guc_ct_buffer_reset(struct intel_guc_ct_buffer *ctb)
> @@ -128,17 +138,18 @@ static void guc_ct_buffer_reset(struct intel_guc_ct_buffer *ctb)
> space = CIRC_SPACE(ctb->tail, ctb->head, ctb->size) - ctb->resv_space;
> atomic_set(&ctb->space, space);
>
> - guc_ct_buffer_desc_init(ctb->desc);
> + guc_ct_buffer_desc_init(&ctb->desc_map);
> }
>
> static void guc_ct_buffer_init(struct intel_guc_ct_buffer *ctb,
> - struct guc_ct_buffer_desc *desc,
> - u32 *cmds, u32 size_in_bytes, u32 resv_space)
> + struct iosys_map *desc,
> + struct iosys_map *cmds,
> + u32 size_in_bytes, u32 resv_space)
> {
> GEM_BUG_ON(size_in_bytes % 4);
>
> - ctb->desc = desc;
> - ctb->cmds = cmds;
> + ctb->desc_map = *desc;
> + ctb->cmds_map = *cmds;
> ctb->size = size_in_bytes / 4;
> ctb->resv_space = resv_space / 4;
>
> @@ -218,12 +229,13 @@ static int ct_register_buffer(struct intel_guc_ct *ct, bool send,
> int intel_guc_ct_init(struct intel_guc_ct *ct)
> {
> struct intel_guc *guc = ct_to_guc(ct);
> - struct guc_ct_buffer_desc *desc;
> + struct iosys_map blob_map;
> + struct iosys_map desc_map;
> + struct iosys_map cmds_map;
> u32 blob_size;
> u32 cmds_size;
> u32 resv_space;
> void *blob;
> - u32 *cmds;
> int err;
>
> err = i915_inject_probe_error(guc_to_gt(guc)->i915, -ENXIO);
> @@ -242,27 +254,35 @@ int intel_guc_ct_init(struct intel_guc_ct *ct)
>
> CT_DEBUG(ct, "base=%#x size=%u\n", intel_guc_ggtt_offset(guc, ct->vma), blob_size);
>
> - /* store pointers to desc and cmds for send ctb */
> - desc = blob;
> - cmds = blob + 2 * CTB_DESC_SIZE;
> + if (i915_gem_object_is_lmem(ct->vma->obj))
> + iosys_map_set_vaddr_iomem(&blob_map,
> + (void __iomem *)blob);
> + else
> + iosys_map_set_vaddr(&blob_map, blob);
> +
> + /* store sysmap to desc_map and cmds_map for send ctb */
> + desc_map = IOSYS_MAP_INIT_OFFSET(&blob_map, CTB_SEND_DESC_OFFSET);
> + cmds_map = IOSYS_MAP_INIT_OFFSET(&blob_map, CTB_SEND_CMDS_OFFSET);
> cmds_size = CTB_H2G_BUFFER_SIZE;
> resv_space = 0;
> - CT_DEBUG(ct, "%s desc %#tx cmds %#tx size %u/%u\n", "send",
> - ptrdiff(desc, blob), ptrdiff(cmds, blob), cmds_size,
> - resv_space);
> + CT_DEBUG(ct, "%s desc %#x cmds %#x size %u/%u\n", "send",
> + CTB_SEND_DESC_OFFSET, (u32)CTB_SEND_CMDS_OFFSET,
> + cmds_size, resv_space);
>
> - guc_ct_buffer_init(&ct->ctbs.send, desc, cmds, cmds_size, resv_space);
> + guc_ct_buffer_init(&ct->ctbs.send,
> + &desc_map, &cmds_map, cmds_size, resv_space);
>
> - /* store pointers to desc and cmds for recv ctb */
> - desc = blob + CTB_DESC_SIZE;
> - cmds = blob + 2 * CTB_DESC_SIZE + CTB_H2G_BUFFER_SIZE;
> + /* store sysmap to desc_map and cmds_map for recv ctb */
> + desc_map = IOSYS_MAP_INIT_OFFSET(&blob_map, CTB_RECV_DESC_OFFSET);
> + cmds_map = IOSYS_MAP_INIT_OFFSET(&blob_map, CTB_RECV_CMDS_OFFSET);
> cmds_size = CTB_G2H_BUFFER_SIZE;
> resv_space = G2H_ROOM_BUFFER_SIZE;
> - CT_DEBUG(ct, "%s desc %#tx cmds %#tx size %u/%u\n", "recv",
> - ptrdiff(desc, blob), ptrdiff(cmds, blob), cmds_size,
> - resv_space);
> + CT_DEBUG(ct, "%s desc %#x cmds %#x size %u/%u\n", "recv",
> + (u32)CTB_RECV_DESC_OFFSET, (u32)CTB_RECV_CMDS_OFFSET,
> + cmds_size, resv_space);
>
> - guc_ct_buffer_init(&ct->ctbs.recv, desc, cmds, cmds_size, resv_space);
> + guc_ct_buffer_init(&ct->ctbs.recv,
> + &desc_map, &cmds_map, cmds_size, resv_space);
>
> return 0;
> }
> @@ -291,8 +311,8 @@ void intel_guc_ct_fini(struct intel_guc_ct *ct)
> int intel_guc_ct_enable(struct intel_guc_ct *ct)
> {
> struct intel_guc *guc = ct_to_guc(ct);
> + struct iosys_map blob_map;
> u32 base, desc, cmds, size;
> - void *blob;
> int err;
>
> GEM_BUG_ON(ct->enabled);
> @@ -302,9 +322,14 @@ int intel_guc_ct_enable(struct intel_guc_ct *ct)
> GEM_BUG_ON(!i915_gem_object_has_pinned_pages(ct->vma->obj));
> base = intel_guc_ggtt_offset(guc, ct->vma);
>
> + if (i915_gem_object_is_lmem(ct->vma->obj))
> + iosys_map_set_vaddr_iomem(&blob_map, (void __iomem *)
> + __px_vaddr(ct->vma->obj));
> + else
> + iosys_map_set_vaddr(&blob_map, __px_vaddr(ct->vma->obj));
> +
> /* blob should start with send descriptor */
> - blob = __px_vaddr(ct->vma->obj);
> - GEM_BUG_ON(blob != ct->ctbs.send.desc);
> + GEM_BUG_ON(!iosys_map_is_equal(&blob_map, &ct->ctbs.send.desc_map));
>
> /* (re)initialize descriptors */
> guc_ct_buffer_reset(&ct->ctbs.send);
> @@ -314,15 +339,15 @@ int intel_guc_ct_enable(struct intel_guc_ct *ct)
> * Register both CT buffers starting with RECV buffer.
> * Descriptors are in first half of the blob.
> */
> - desc = base + ptrdiff(ct->ctbs.recv.desc, blob);
> - cmds = base + ptrdiff(ct->ctbs.recv.cmds, blob);
> + desc = base + CTB_RECV_DESC_OFFSET;
> + cmds = base + CTB_RECV_CMDS_OFFSET;
> size = ct->ctbs.recv.size * 4;
> err = ct_register_buffer(ct, false, desc, cmds, size);
> if (unlikely(err))
> goto err_out;
>
> - desc = base + ptrdiff(ct->ctbs.send.desc, blob);
> - cmds = base + ptrdiff(ct->ctbs.send.cmds, blob);
> + desc = base + CTB_SEND_DESC_OFFSET;
> + cmds = base + CTB_SEND_CMDS_OFFSET;
> size = ct->ctbs.send.size * 4;
> err = ct_register_buffer(ct, true, desc, cmds, size);
> if (unlikely(err))
> @@ -371,31 +396,33 @@ static int ct_write(struct intel_guc_ct *ct,
> u32 fence, u32 flags)
> {
> struct intel_guc_ct_buffer *ctb = &ct->ctbs.send;
> - struct guc_ct_buffer_desc *desc = ctb->desc;
> u32 tail = ctb->tail;
> u32 size = ctb->size;
> u32 header;
> u32 hxg;
> u32 type;
> - u32 *cmds = ctb->cmds;
> + u32 status = ct_desc_read(&ctb->desc_map, status);
> + u32 desc_head = ct_desc_read(&ctb->desc_map, head);
> unsigned int i;
>
> - if (unlikely(desc->status))
> + if (unlikely(status))
> goto corrupted;
>
> GEM_BUG_ON(tail > size);
>
> #ifdef CONFIG_DRM_I915_DEBUG_GUC
> - if (unlikely(tail != READ_ONCE(desc->tail))) {
> + if (unlikely(tail != ct_desc_read(&ctb->desc_map, tail))) {
> CT_ERROR(ct, "Tail was modified %u != %u\n",
> - desc->tail, tail);
> - desc->status |= GUC_CTB_STATUS_MISMATCH;
> + ct_desc_read(&ctb->desc_map, tail), tail);
> + status |= GUC_CTB_STATUS_MISMATCH;
> + ct_desc_write(&ctb->desc_map, status, status);
> goto corrupted;
> }
> - if (unlikely(READ_ONCE(desc->head) >= size)) {
> + if (unlikely(desc_head >= size)) {
> CT_ERROR(ct, "Invalid head offset %u >= %u)\n",
> - desc->head, size);
> - desc->status |= GUC_CTB_STATUS_OVERFLOW;
> + desc_head, size);
> + status |= GUC_CTB_STATUS_OVERFLOW;
> + ct_desc_write(&ctb->desc_map, status, status);
> goto corrupted;
> }
> #endif
> @@ -418,14 +445,15 @@ static int ct_write(struct intel_guc_ct *ct,
> CT_DEBUG(ct, "writing (tail %u) %*ph %*ph %*ph\n",
> tail, 4, &header, 4, &hxg, 4 * (len - 1), &action[1]);
>
> - cmds[tail] = header;
> + iosys_map_wr(&ctb->cmds_map, sizeof(u32) * tail, u32, header);
> tail = (tail + 1) % size;
>
> - cmds[tail] = hxg;
> + iosys_map_wr(&ctb->cmds_map, sizeof(u32) * tail, u32, hxg);
> tail = (tail + 1) % size;
>
> for (i = 1; i < len; i++) {
> - cmds[tail] = action[i];
> + iosys_map_wr(&ctb->cmds_map,
> + sizeof(u32) * tail, u32, action[i]);
> tail = (tail + 1) % size;
> }
> GEM_BUG_ON(tail > size);
> @@ -442,13 +470,13 @@ static int ct_write(struct intel_guc_ct *ct,
> atomic_sub(len + GUC_CTB_HDR_LEN, &ctb->space);
>
> /* now update descriptor */
> - WRITE_ONCE(desc->tail, tail);
> + ct_desc_write(&ctb->desc_map, tail, tail);
>
> return 0;
>
> corrupted:
> CT_ERROR(ct, "Corrupted descriptor head=%u tail=%u status=%#x\n",
> - desc->head, desc->tail, desc->status);
> + desc_head, ct_desc_read(&ctb->desc_map, tail), status);
> ctb->broken = true;
> return -EPIPE;
> }
> @@ -499,20 +527,22 @@ static inline bool ct_deadlocked(struct intel_guc_ct *ct)
> bool ret = ktime_ms_delta(ktime_get(), ct->stall_time) > timeout;
>
> if (unlikely(ret)) {
> - struct guc_ct_buffer_desc *send = ct->ctbs.send.desc;
> - struct guc_ct_buffer_desc *recv = ct->ctbs.send.desc;
> -
> CT_ERROR(ct, "Communication stalled for %lld ms, desc status=%#x,%#x\n",
> ktime_ms_delta(ktime_get(), ct->stall_time),
> - send->status, recv->status);
> + ct_desc_read(&ct->ctbs.send.desc_map, status),
> + ct_desc_read(&ct->ctbs.recv.desc_map, status));
> CT_ERROR(ct, "H2G Space: %u (Bytes)\n",
> atomic_read(&ct->ctbs.send.space) * 4);
> - CT_ERROR(ct, "Head: %u (Dwords)\n", ct->ctbs.send.desc->head);
> - CT_ERROR(ct, "Tail: %u (Dwords)\n", ct->ctbs.send.desc->tail);
> + CT_ERROR(ct, "Head: %u (Dwords)\n",
> + ct_desc_read(&ct->ctbs.send.desc_map, head));
> + CT_ERROR(ct, "Tail: %u (Dwords)\n",
> + ct_desc_read(&ct->ctbs.send.desc_map, tail));
> CT_ERROR(ct, "G2H Space: %u (Bytes)\n",
> atomic_read(&ct->ctbs.recv.space) * 4);
> - CT_ERROR(ct, "Head: %u\n (Dwords)", ct->ctbs.recv.desc->head);
> - CT_ERROR(ct, "Tail: %u\n (Dwords)", ct->ctbs.recv.desc->tail);
> + CT_ERROR(ct, "Head: %u\n (Dwords)",
> + ct_desc_read(&ct->ctbs.recv.desc_map, head));
> + CT_ERROR(ct, "Tail: %u\n (Dwords)",
> + ct_desc_read(&ct->ctbs.recv.desc_map, tail));
>
> ct->ctbs.send.broken = true;
> }
> @@ -549,18 +579,19 @@ static inline void g2h_release_space(struct intel_guc_ct *ct, u32 g2h_len_dw)
> static inline bool h2g_has_room(struct intel_guc_ct *ct, u32 len_dw)
> {
> struct intel_guc_ct_buffer *ctb = &ct->ctbs.send;
> - struct guc_ct_buffer_desc *desc = ctb->desc;
> u32 head;
> u32 space;
> + u32 status = ct_desc_read(&ctb->desc_map, status);
>
> if (atomic_read(&ctb->space) >= len_dw)
> return true;
>
> - head = READ_ONCE(desc->head);
> + head = ct_desc_read(&ctb->desc_map, head);
> if (unlikely(head > ctb->size)) {
> CT_ERROR(ct, "Invalid head offset %u >= %u)\n",
> head, ctb->size);
> - desc->status |= GUC_CTB_STATUS_OVERFLOW;
> + status |= GUC_CTB_STATUS_OVERFLOW;
> + ct_desc_write(&ctb->desc_map, status, status);
> ctb->broken = true;
> return false;
> }
> @@ -803,11 +834,11 @@ static void ct_free_msg(struct ct_incoming_msg *msg)
> static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg)
> {
> struct intel_guc_ct_buffer *ctb = &ct->ctbs.recv;
> - struct guc_ct_buffer_desc *desc = ctb->desc;
> u32 head = ctb->head;
> - u32 tail = READ_ONCE(desc->tail);
> + u32 tail = ct_desc_read(&ctb->desc_map, tail);
> u32 size = ctb->size;
> - u32 *cmds = ctb->cmds;
> + u32 status = ct_desc_read(&ctb->desc_map, status);
> + u32 desc_head = ct_desc_read(&ctb->desc_map, head);
> s32 available;
> unsigned int len;
> unsigned int i;
> @@ -816,23 +847,25 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg)
> if (unlikely(ctb->broken))
> return -EPIPE;
>
> - if (unlikely(desc->status))
> + if (unlikely(status))
> goto corrupted;
>
> GEM_BUG_ON(head > size);
>
> #ifdef CONFIG_DRM_I915_DEBUG_GUC
> - if (unlikely(head != READ_ONCE(desc->head))) {
> + if (unlikely(head != desc_head)) {
> CT_ERROR(ct, "Head was modified %u != %u\n",
> - desc->head, head);
> - desc->status |= GUC_CTB_STATUS_MISMATCH;
> + desc_head, head);
> + status |= GUC_CTB_STATUS_MISMATCH;
> + ct_desc_write(&ctb->desc_map, status, status);
> goto corrupted;
> }
> #endif
> if (unlikely(tail >= size)) {
> CT_ERROR(ct, "Invalid tail offset %u >= %u)\n",
> tail, size);
> - desc->status |= GUC_CTB_STATUS_OVERFLOW;
> + status |= GUC_CTB_STATUS_OVERFLOW;
> + ct_desc_write(&ctb->desc_map, status, status);
> goto corrupted;
> }
>
> @@ -849,7 +882,7 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg)
> CT_DEBUG(ct, "available %d (%u:%u:%u)\n", available, head, tail, size);
> GEM_BUG_ON(available < 0);
>
> - header = cmds[head];
> + header = iosys_map_rd(&ctb->cmds_map, sizeof(u32) * head, u32);
> head = (head + 1) % size;
>
> /* message len with header */
> @@ -857,11 +890,14 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg)
> if (unlikely(len > (u32)available)) {
> CT_ERROR(ct, "Incomplete message %*ph %*ph %*ph\n",
> 4, &header,
> + 4 * (head + available - 1 > size ? size - head :
> + available - 1), ((__px_vaddr(ct->vma->obj) +
> + CTB_RECV_CMDS_OFFSET) + (4 * head)),
> 4 * (head + available - 1 > size ?
> - size - head : available - 1), &cmds[head],
> - 4 * (head + available - 1 > size ?
> - available - 1 - size + head : 0), &cmds[0]);
> - desc->status |= GUC_CTB_STATUS_UNDERFLOW;
> + available - 1 - size + head : 0),
> + (__px_vaddr(ct->vma->obj) + CTB_RECV_CMDS_OFFSET));
> + status |= GUC_CTB_STATUS_UNDERFLOW;
> + ct_desc_write(&ctb->desc_map, status, status);
> goto corrupted;
> }
>
> @@ -869,17 +905,20 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg)
> if (!*msg) {
> CT_ERROR(ct, "No memory for message %*ph %*ph %*ph\n",
> 4, &header,
> + 4 * (head + available - 1 > size ? size - head :
> + available - 1), ((__px_vaddr(ct->vma->obj) +
> + CTB_RECV_CMDS_OFFSET) + (4 * head)),
> 4 * (head + available - 1 > size ?
> - size - head : available - 1), &cmds[head],
> - 4 * (head + available - 1 > size ?
> - available - 1 - size + head : 0), &cmds[0]);
> + available - 1 - size + head : 0),
> + (__px_vaddr(ct->vma->obj) + CTB_RECV_CMDS_OFFSET));
> return available;
> }
>
> (*msg)->msg[0] = header;
>
> for (i = 1; i < len; i++) {
> - (*msg)->msg[i] = cmds[head];
> + (*msg)->msg[i] = iosys_map_rd(&ctb->cmds_map,
> + sizeof(u32) * head, u32);
> head = (head + 1) % size;
> }
> CT_DEBUG(ct, "received %*ph\n", 4 * len, (*msg)->msg);
> @@ -888,13 +927,13 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg)
> ctb->head = head;
>
> /* now update descriptor */
> - WRITE_ONCE(desc->head, head);
> + ct_desc_write(&ctb->desc_map, head, head);
>
> return available - len;
>
> corrupted:
> CT_ERROR(ct, "Corrupted descriptor head=%u tail=%u status=%#x\n",
> - desc->head, desc->tail, desc->status);
> + desc_head, ct_desc_read(&ctb->desc_map, tail), status);
> ctb->broken = true;
> return -EPIPE;
> }
> @@ -1211,13 +1250,13 @@ void intel_guc_ct_print_info(struct intel_guc_ct *ct,
> drm_printf(p, "H2G Space: %u\n",
> atomic_read(&ct->ctbs.send.space) * 4);
> drm_printf(p, "Head: %u\n",
> - ct->ctbs.send.desc->head);
> + ct_desc_read(&ct->ctbs.send.desc_map, head));
> drm_printf(p, "Tail: %u\n",
> - ct->ctbs.send.desc->tail);
> + ct_desc_read(&ct->ctbs.send.desc_map, tail));
> drm_printf(p, "G2H Space: %u\n",
> atomic_read(&ct->ctbs.recv.space) * 4);
> drm_printf(p, "Head: %u\n",
> - ct->ctbs.recv.desc->head);
> + ct_desc_read(&ct->ctbs.recv.desc_map, head));
> drm_printf(p, "Tail: %u\n",
> - ct->ctbs.recv.desc->tail);
> + ct_desc_read(&ct->ctbs.recv.desc_map, tail));
> }
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h
> index f709a19c7e21..867fe13fb47d 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h
> @@ -7,6 +7,7 @@
> #define _INTEL_GUC_CT_H_
>
> #include <linux/interrupt.h>
> +#include <linux/iosys-map.h>
> #include <linux/spinlock.h>
> #include <linux/workqueue.h>
> #include <linux/ktime.h>
> @@ -32,8 +33,8 @@ struct drm_printer;
> * holds the commands.
> *
> * @lock: protects access to the commands buffer and buffer descriptor
> - * @desc: pointer to the buffer descriptor
> - * @cmds: pointer to the commands buffer
> + * @desc: iosys map to the buffer descriptor
> + * @cmds: iosys map to the commands buffer
> * @size: size of the commands buffer in dwords
> * @resv_space: reserved space in buffer in dwords
> * @head: local shadow copy of head in dwords
> @@ -43,8 +44,8 @@ struct drm_printer;
> */
> struct intel_guc_ct_buffer {
> spinlock_t lock;
> - struct guc_ct_buffer_desc *desc;
> - u32 *cmds;
> + struct iosys_map desc_map;
> + struct iosys_map cmds_map;
> u32 size;
> u32 resv_space;
> u32 tail;
> --
> 2.33.0
>
^ permalink raw reply [flat|nested] 14+ messages in thread
end of thread, other threads:[~2022-05-11 15:15 UTC | newest]
Thread overview: 14+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2022-04-21 17:26 [Intel-gfx] [PATCH 0/1] Refactor CT access to use iosys_map Mullati Siva
2022-04-21 17:26 ` [Intel-gfx] [PATCH 1/1] drm/i915/guc: Convert ct buffer to iosys_map Mullati Siva
2022-04-21 21:40 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Refactor CT access to use iosys_map Patchwork
2022-04-21 22:06 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-04-22 2:36 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
-- strict thread matches above, loose matches on Subject: below --
2022-05-09 6:49 [Intel-gfx] [PATCH 0/1] drm/i915/guc: " Mullati Siva
2022-05-09 6:49 ` [Intel-gfx] [PATCH 1/1] drm/i915/guc: Convert ct buffer to iosys_map Mullati Siva
2022-05-11 15:15 ` Balasubramani Vivekanandan
2022-04-04 9:31 [Intel-gfx] [PATCH 0/1] drm/i915/guc: Refactor CT access to use iosys_map Mullati Siva
2022-04-04 9:31 ` [Intel-gfx] [PATCH 1/1] drm/i915/guc: Convert ct buffer to iosys_map Mullati Siva
2022-04-14 12:11 ` Balasubramani Vivekanandan
2022-04-28 14:13 ` Siva Mullati
2022-04-29 9:07 ` Balasubramani Vivekanandan
2022-04-18 9:08 ` Balasubramani Vivekanandan
2022-03-22 8:44 [Intel-gfx] [PATCH 0/1] drm/i915/guc: Refactor CT access to use iosys_map Mullati Siva
2022-03-22 8:44 ` [Intel-gfx] [PATCH 1/1] drm/i915/guc: Convert ct buffer to iosys_map Mullati Siva
2022-04-02 4:13 ` Lucas De Marchi
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