From: Matt Roper <matthew.d.roper@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: dri-devel@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH 01/11] drm/i915/pvc: add initial Ponte Vecchio definitions
Date: Mon, 2 May 2022 09:34:07 -0700 [thread overview]
Message-ID: <20220502163417.2635462-2-matthew.d.roper@intel.com> (raw)
In-Reply-To: <20220502163417.2635462-1-matthew.d.roper@intel.com>
From: Stuart Summers <stuart.summers@intel.com>
Additional blitter and media engines will be enabled later.
Bspec: 44481, 44482
Signed-off-by: Stuart Summers <stuart.summers@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_pci.c | 21 +++++++++++++++++++++
drivers/gpu/drm/i915/intel_device_info.c | 1 +
drivers/gpu/drm/i915/intel_device_info.h | 1 +
4 files changed, 25 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 24111bf42ce0..2dddc27a1b0e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1062,6 +1062,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define IS_ALDERLAKE_P(dev_priv) IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_P)
#define IS_XEHPSDV(dev_priv) IS_PLATFORM(dev_priv, INTEL_XEHPSDV)
#define IS_DG2(dev_priv) IS_PLATFORM(dev_priv, INTEL_DG2)
+#define IS_PONTEVECCHIO(dev_priv) IS_PLATFORM(dev_priv, INTEL_PONTEVECCHIO)
+
#define IS_DG2_G10(dev_priv) \
IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G10)
#define IS_DG2_G11(dev_priv) \
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 7739d6c33481..498708b33924 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -1074,6 +1074,27 @@ static const struct intel_device_info ats_m_info = {
.require_force_probe = 1,
};
+#define XE_HPC_FEATURES \
+ XE_HP_FEATURES, \
+ .dma_mask_size = 52
+
+__maybe_unused
+static const struct intel_device_info pvc_info = {
+ XE_HPC_FEATURES,
+ XE_HPM_FEATURES,
+ DGFX_FEATURES,
+ .graphics.rel = 60,
+ .media.rel = 60,
+ PLATFORM(INTEL_PONTEVECCHIO),
+ .display = { 0 },
+ .has_flat_ccs = 0,
+ .platform_engine_mask =
+ BIT(BCS0) |
+ BIT(VCS0) |
+ BIT(CCS0) | BIT(CCS1) | BIT(CCS2) | BIT(CCS3),
+ .require_force_probe = 1,
+};
+
#undef PLATFORM
/*
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 63e05cd15a90..f0bf23726ed8 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -72,6 +72,7 @@ static const char * const platform_names[] = {
PLATFORM_NAME(ALDERLAKE_P),
PLATFORM_NAME(XEHPSDV),
PLATFORM_NAME(DG2),
+ PLATFORM_NAME(PONTEVECCHIO),
};
#undef PLATFORM_NAME
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 20c351c8d5bd..e7d2cf7d65c8 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -88,6 +88,7 @@ enum intel_platform {
INTEL_ALDERLAKE_P,
INTEL_XEHPSDV,
INTEL_DG2,
+ INTEL_PONTEVECCHIO,
INTEL_MAX_PLATFORMS
};
--
2.35.1
next prev parent reply other threads:[~2022-05-02 16:34 UTC|newest]
Thread overview: 49+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-02 16:34 [Intel-gfx] [PATCH 00/11] i915: Introduce Ponte Vecchio Matt Roper
2022-05-02 16:34 ` Matt Roper [this message]
2022-05-02 20:44 ` [Intel-gfx] [PATCH 01/11] drm/i915/pvc: add initial Ponte Vecchio definitions Lucas De Marchi
2022-05-02 16:34 ` [Intel-gfx] [PATCH 02/11] drm/i915/pvc: Add forcewake support Matt Roper
2022-05-02 22:33 ` Summers, Stuart
2022-05-05 0:34 ` Matt Roper
2022-05-02 16:34 ` [Intel-gfx] [PATCH 03/11] drm/i915/pvc: Define MOCS table for PVC Matt Roper
2022-05-02 16:50 ` Matt Roper
2022-05-02 18:39 ` Lucas De Marchi
2022-05-02 18:50 ` Matt Roper
2022-05-02 19:27 ` Lucas De Marchi
2022-05-02 19:42 ` Matt Roper
2022-05-02 21:03 ` Lucas De Marchi
2022-05-02 21:14 ` Matt Roper
2022-05-03 6:22 ` Lucas De Marchi
2022-05-02 16:34 ` [Intel-gfx] [PATCH 04/11] drm/i915/pvc: Read correct RP_STATE_CAP register Matt Roper
2022-05-02 16:55 ` Rodrigo Vivi
2022-05-02 16:34 ` [Intel-gfx] [PATCH 05/11] drm/i915/pvc: Remove additional 3D flags from PIPE_CONTROL Matt Roper
2022-05-02 16:34 ` [Intel-gfx] [PATCH 06/11] drm/i915/pvc: Reduce stack usage in reset selftest with extra blitter engine Matt Roper
2022-05-02 18:46 ` Souza, Jose
2022-05-03 8:25 ` Tvrtko Ursulin
2022-05-02 16:34 ` [Intel-gfx] [PATCH 07/11] drm/i915/pvc: Engines definitions for new copy engines Matt Roper
2022-05-02 18:45 ` Souza, Jose
2022-05-03 8:05 ` Tvrtko Ursulin
2022-05-05 20:59 ` Matt Roper
2022-05-06 7:21 ` Tvrtko Ursulin
2022-05-06 14:29 ` Matt Roper
2022-05-02 16:34 ` [Intel-gfx] [PATCH 08/11] drm/i915/pvc: Interrupt support " Matt Roper
2022-05-02 22:23 ` Summers, Stuart
2022-05-02 16:34 ` [Intel-gfx] [PATCH 09/11] drm/i915/pvc: Reset " Matt Roper
2022-05-02 18:44 ` Souza, Jose
2022-05-02 22:23 ` Summers, Stuart
2022-05-02 16:34 ` [Intel-gfx] [PATCH 10/11] drm/i915/pvc: skip all copy engines from aux table invalidate Matt Roper
2022-05-02 18:40 ` Souza, Jose
2022-05-02 22:58 ` Kumar Valsan, Prathap
2022-05-02 16:34 ` [Intel-gfx] [PATCH 11/11] drm/i915/pvc: read fuses for link copy engines Matt Roper
2022-05-02 18:48 ` Souza, Jose
2022-05-03 8:19 ` Tvrtko Ursulin
2022-05-02 16:58 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for i915: Introduce Ponte Vecchio Patchwork
2022-05-02 16:58 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-05-02 17:22 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-05-02 22:58 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2022-05-03 17:32 ` Matt Roper
2022-05-04 17:03 ` Vudum, Lakshminarayana
2022-05-03 8:21 ` [Intel-gfx] [PATCH 00/11] " Tvrtko Ursulin
2022-05-03 14:56 ` Matt Roper
2022-05-03 15:01 ` Tvrtko Ursulin
2022-05-04 16:22 ` [Intel-gfx] ✓ Fi.CI.IGT: success for " Patchwork
2022-05-04 16:43 ` Patchwork
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