[Intel-gfx] [PATCH i-g-t 1/2] tests/i915/gem_caching: handle discrete

[Intel-gfx] [PATCH i-g-t 1/2] tests/i915/gem_caching: handle discrete

[Matthew Auld]

Test should still be valid, even if we can't explicitly control the PTE
caching bits, like on discrete, where the caching should already be
enabled by default for system memory objects.

References: https://gitlab.freedesktop.org/drm/intel/-/issues/4873
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Nirmoy Das <nirmoy.das@linux.intel.com>
---
 tests/i915/gem_caching.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/tests/i915/gem_caching.c b/tests/i915/gem_caching.c
index 4e844952..eb0170ab 100644
--- a/tests/i915/gem_caching.c
+++ b/tests/i915/gem_caching.c
@@ -147,7 +147,8 @@ igt_main
 
 		igt_require_gem(data.fd);
 		gem_require_blitter(data.fd);
-		gem_require_caching(data.fd);
+		if (!gem_has_lmem(data.fd))
+			gem_require_caching(data.fd);
 
 		data.devid = intel_get_drm_devid(data.fd);
 		if (IS_GEN2(data.devid)) /* chipset only handles cached -> uncached */
@@ -162,7 +163,8 @@ igt_main
 		scratch_buf = intel_buf_create(data.bops, BO_SIZE/4, 1,
 					       32, 0, I915_TILING_NONE, 0);
 
-		gem_set_caching(data.fd, scratch_buf->handle, 1);
+		if (!gem_has_lmem(data.fd))
+			gem_set_caching(data.fd, scratch_buf->handle, 1);
 
 		staging_buf = intel_buf_create(data.bops, BO_SIZE/4, 1,
 					       32, 0, I915_TILING_NONE, 0);
-- 
2.34.1

[Intel-gfx] [PATCH i-g-t 2/2] tests/i915/gem_workarounds: handle discrete

[Matthew Auld]

On discrete the object should already be using I915_CACHING_CACHED, by
default, for system memory objects, although we can no longer explicitly
control the PTE caching bits.

References: https://gitlab.freedesktop.org/drm/intel/-/issues/4873
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Nirmoy Das <nirmoy.das@linux.intel.com>
---
 tests/i915/gem_workarounds.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/tests/i915/gem_workarounds.c b/tests/i915/gem_workarounds.c
index 3d185127..70967b3f 100644
--- a/tests/i915/gem_workarounds.c
+++ b/tests/i915/gem_workarounds.c
@@ -107,7 +107,8 @@ static int workaround_fail_count(int i915, const intel_ctx_t *ctx)
 
 	memset(obj, 0, sizeof(obj));
 	obj[0].handle = gem_create(i915, result_sz);
-	gem_set_caching(i915, obj[0].handle, I915_CACHING_CACHED);
+	if (!gem_has_lmem(i915))
+		gem_set_caching(i915, obj[0].handle, I915_CACHING_CACHED);
 	obj[1].handle = gem_create(i915, batch_sz);
 	obj[1].relocs_ptr = to_user_pointer(reloc);
 	obj[1].relocation_count = !ahnd ? num_wa_regs : 0;
-- 
2.34.1

Re: [Intel-gfx] [PATCH i-g-t 1/2] tests/i915/gem_caching: handle discrete

[Das, Nirmoy]

The series is Reviewed-by: Nirmoy Das <nirmoy.das@intel.com>

On 5/4/2022 5:08 PM, Matthew Auld wrote:
> Test should still be valid, even if we can't explicitly control the PTE
> caching bits, like on discrete, where the caching should already be
> enabled by default for system memory objects.
>
> References: https://gitlab.freedesktop.org/drm/intel/-/issues/4873
> Signed-off-by: Matthew Auld <matthew.auld@intel.com>
> Cc: Nirmoy Das <nirmoy.das@linux.intel.com>
> ---
>   tests/i915/gem_caching.c | 6 ++++--
>   1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/tests/i915/gem_caching.c b/tests/i915/gem_caching.c
> index 4e844952..eb0170ab 100644
> --- a/tests/i915/gem_caching.c
> +++ b/tests/i915/gem_caching.c
> @@ -147,7 +147,8 @@ igt_main
>   
>   		igt_require_gem(data.fd);
>   		gem_require_blitter(data.fd);
> -		gem_require_caching(data.fd);
> +		if (!gem_has_lmem(data.fd))
> +			gem_require_caching(data.fd);
>   
>   		data.devid = intel_get_drm_devid(data.fd);
>   		if (IS_GEN2(data.devid)) /* chipset only handles cached -> uncached */
> @@ -162,7 +163,8 @@ igt_main
>   		scratch_buf = intel_buf_create(data.bops, BO_SIZE/4, 1,
>   					       32, 0, I915_TILING_NONE, 0);
>   
> -		gem_set_caching(data.fd, scratch_buf->handle, 1);
> +		if (!gem_has_lmem(data.fd))
> +			gem_set_caching(data.fd, scratch_buf->handle, 1);
>   
>   		staging_buf = intel_buf_create(data.bops, BO_SIZE/4, 1,
>   					       32, 0, I915_TILING_NONE, 0);