* [Intel-gfx] [PATCH] drm/i915/regs: split out intel audio register definitions
@ 2022-06-02 9:45 Jani Nikula
2022-06-02 10:19 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
` (4 more replies)
0 siblings, 5 replies; 7+ messages in thread
From: Jani Nikula @ 2022-06-02 9:45 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
Split out audio registers to a header of its own to reduce the size of
i915_reg.h.
TODO: Remove direct audio register access from intel_ddi.c. However,
unification of audio get config is cumbersome due to the audio enable
bit being in the DP or HDMI registers on older platforms.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_audio.c | 1 +
.../gpu/drm/i915/display/intel_audio_regs.h | 160 ++++++++++++++++++
drivers/gpu/drm/i915/display/intel_ddi.c | 1 +
drivers/gpu/drm/i915/i915_reg.h | 151 -----------------
drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 2 +
5 files changed, 164 insertions(+), 151 deletions(-)
create mode 100644 drivers/gpu/drm/i915/display/intel_audio_regs.h
diff --git a/drivers/gpu/drm/i915/display/intel_audio.c b/drivers/gpu/drm/i915/display/intel_audio.c
index f0f0dfce27ce..6c9ee905f132 100644
--- a/drivers/gpu/drm/i915/display/intel_audio.c
+++ b/drivers/gpu/drm/i915/display/intel_audio.c
@@ -30,6 +30,7 @@
#include "i915_drv.h"
#include "intel_atomic.h"
#include "intel_audio.h"
+#include "intel_audio_regs.h"
#include "intel_cdclk.h"
#include "intel_crtc.h"
#include "intel_de.h"
diff --git a/drivers/gpu/drm/i915/display/intel_audio_regs.h b/drivers/gpu/drm/i915/display/intel_audio_regs.h
new file mode 100644
index 000000000000..d1e5844e3484
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_audio_regs.h
@@ -0,0 +1,160 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#ifndef __INTEL_AUDIO_REGS_H__
+#define __INTEL_AUDIO_REGS_H__
+
+#include "i915_reg_defs.h"
+
+#define G4X_AUD_VID_DID _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x62020)
+#define INTEL_AUDIO_DEVCL 0x808629FB
+#define INTEL_AUDIO_DEVBLC 0x80862801
+#define INTEL_AUDIO_DEVCTG 0x80862802
+
+#define G4X_AUD_CNTL_ST _MMIO(0x620B4)
+#define G4X_ELDV_DEVCL_DEVBLC (1 << 13)
+#define G4X_ELDV_DEVCTG (1 << 14)
+#define G4X_ELD_ADDR_MASK (0xf << 5)
+#define G4X_ELD_ACK (1 << 4)
+#define G4X_HDMIW_HDMIEDID _MMIO(0x6210C)
+
+#define _IBX_HDMIW_HDMIEDID_A 0xE2050
+#define _IBX_HDMIW_HDMIEDID_B 0xE2150
+#define IBX_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _IBX_HDMIW_HDMIEDID_A, \
+ _IBX_HDMIW_HDMIEDID_B)
+#define _IBX_AUD_CNTL_ST_A 0xE20B4
+#define _IBX_AUD_CNTL_ST_B 0xE21B4
+#define IBX_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _IBX_AUD_CNTL_ST_A, \
+ _IBX_AUD_CNTL_ST_B)
+#define IBX_ELD_BUFFER_SIZE_MASK (0x1f << 10)
+#define IBX_ELD_ADDRESS_MASK (0x1f << 5)
+#define IBX_ELD_ACK (1 << 4)
+#define IBX_AUD_CNTL_ST2 _MMIO(0xE20C0)
+#define IBX_CP_READY(port) ((1 << 1) << (((port) - 1) * 4))
+#define IBX_ELD_VALID(port) ((1 << 0) << (((port) - 1) * 4))
+
+#define _CPT_HDMIW_HDMIEDID_A 0xE5050
+#define _CPT_HDMIW_HDMIEDID_B 0xE5150
+#define CPT_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _CPT_HDMIW_HDMIEDID_A, _CPT_HDMIW_HDMIEDID_B)
+#define _CPT_AUD_CNTL_ST_A 0xE50B4
+#define _CPT_AUD_CNTL_ST_B 0xE51B4
+#define CPT_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _CPT_AUD_CNTL_ST_A, _CPT_AUD_CNTL_ST_B)
+#define CPT_AUD_CNTRL_ST2 _MMIO(0xE50C0)
+
+#define _VLV_HDMIW_HDMIEDID_A (VLV_DISPLAY_BASE + 0x62050)
+#define _VLV_HDMIW_HDMIEDID_B (VLV_DISPLAY_BASE + 0x62150)
+#define VLV_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _VLV_HDMIW_HDMIEDID_A, _VLV_HDMIW_HDMIEDID_B)
+#define _VLV_AUD_CNTL_ST_A (VLV_DISPLAY_BASE + 0x620B4)
+#define _VLV_AUD_CNTL_ST_B (VLV_DISPLAY_BASE + 0x621B4)
+#define VLV_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _VLV_AUD_CNTL_ST_A, _VLV_AUD_CNTL_ST_B)
+#define VLV_AUD_CNTL_ST2 _MMIO(VLV_DISPLAY_BASE + 0x620C0)
+
+#define _IBX_AUD_CONFIG_A 0xe2000
+#define _IBX_AUD_CONFIG_B 0xe2100
+#define IBX_AUD_CFG(pipe) _MMIO_PIPE(pipe, _IBX_AUD_CONFIG_A, _IBX_AUD_CONFIG_B)
+#define _CPT_AUD_CONFIG_A 0xe5000
+#define _CPT_AUD_CONFIG_B 0xe5100
+#define CPT_AUD_CFG(pipe) _MMIO_PIPE(pipe, _CPT_AUD_CONFIG_A, _CPT_AUD_CONFIG_B)
+#define _VLV_AUD_CONFIG_A (VLV_DISPLAY_BASE + 0x62000)
+#define _VLV_AUD_CONFIG_B (VLV_DISPLAY_BASE + 0x62100)
+#define VLV_AUD_CFG(pipe) _MMIO_PIPE(pipe, _VLV_AUD_CONFIG_A, _VLV_AUD_CONFIG_B)
+
+#define AUD_CONFIG_N_VALUE_INDEX (1 << 29)
+#define AUD_CONFIG_N_PROG_ENABLE (1 << 28)
+#define AUD_CONFIG_UPPER_N_SHIFT 20
+#define AUD_CONFIG_UPPER_N_MASK (0xff << 20)
+#define AUD_CONFIG_LOWER_N_SHIFT 4
+#define AUD_CONFIG_LOWER_N_MASK (0xfff << 4)
+#define AUD_CONFIG_N_MASK (AUD_CONFIG_UPPER_N_MASK | AUD_CONFIG_LOWER_N_MASK)
+#define AUD_CONFIG_N(n) \
+ (((((n) >> 12) & 0xff) << AUD_CONFIG_UPPER_N_SHIFT) | \
+ (((n) & 0xfff) << AUD_CONFIG_LOWER_N_SHIFT))
+#define AUD_CONFIG_PIXEL_CLOCK_HDMI_SHIFT 16
+#define AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK (0xf << 16)
+#define AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 (0 << 16)
+#define AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 (1 << 16)
+#define AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 (2 << 16)
+#define AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 (3 << 16)
+#define AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 (4 << 16)
+#define AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 (5 << 16)
+#define AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 (6 << 16)
+#define AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 (7 << 16)
+#define AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 (8 << 16)
+#define AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 (9 << 16)
+#define AUD_CONFIG_PIXEL_CLOCK_HDMI_296703 (10 << 16)
+#define AUD_CONFIG_PIXEL_CLOCK_HDMI_297000 (11 << 16)
+#define AUD_CONFIG_PIXEL_CLOCK_HDMI_593407 (12 << 16)
+#define AUD_CONFIG_PIXEL_CLOCK_HDMI_594000 (13 << 16)
+#define AUD_CONFIG_DISABLE_NCTS (1 << 3)
+
+#define _HSW_AUD_CONFIG_A 0x65000
+#define _HSW_AUD_CONFIG_B 0x65100
+#define HSW_AUD_CFG(trans) _MMIO_TRANS(trans, _HSW_AUD_CONFIG_A, _HSW_AUD_CONFIG_B)
+
+#define _HSW_AUD_MISC_CTRL_A 0x65010
+#define _HSW_AUD_MISC_CTRL_B 0x65110
+#define HSW_AUD_MISC_CTRL(trans) _MMIO_TRANS(trans, _HSW_AUD_MISC_CTRL_A, _HSW_AUD_MISC_CTRL_B)
+
+#define _HSW_AUD_M_CTS_ENABLE_A 0x65028
+#define _HSW_AUD_M_CTS_ENABLE_B 0x65128
+#define HSW_AUD_M_CTS_ENABLE(trans) _MMIO_TRANS(trans, _HSW_AUD_M_CTS_ENABLE_A, _HSW_AUD_M_CTS_ENABLE_B)
+#define AUD_M_CTS_M_VALUE_INDEX (1 << 21)
+#define AUD_M_CTS_M_PROG_ENABLE (1 << 20)
+#define AUD_CONFIG_M_MASK 0xfffff
+
+#define _HSW_AUD_DIP_ELD_CTRL_ST_A 0x650b4
+#define _HSW_AUD_DIP_ELD_CTRL_ST_B 0x651b4
+#define HSW_AUD_DIP_ELD_CTRL(trans) _MMIO_TRANS(trans, _HSW_AUD_DIP_ELD_CTRL_ST_A, _HSW_AUD_DIP_ELD_CTRL_ST_B)
+
+/* Audio Digital Converter */
+#define _HSW_AUD_DIG_CNVT_1 0x65080
+#define _HSW_AUD_DIG_CNVT_2 0x65180
+#define AUD_DIG_CNVT(trans) _MMIO_TRANS(trans, _HSW_AUD_DIG_CNVT_1, _HSW_AUD_DIG_CNVT_2)
+#define DIP_PORT_SEL_MASK 0x3
+
+#define _HSW_AUD_EDID_DATA_A 0x65050
+#define _HSW_AUD_EDID_DATA_B 0x65150
+#define HSW_AUD_EDID_DATA(trans) _MMIO_TRANS(trans, _HSW_AUD_EDID_DATA_A, _HSW_AUD_EDID_DATA_B)
+
+#define HSW_AUD_PIPE_CONV_CFG _MMIO(0x6507c)
+#define HSW_AUD_PIN_ELD_CP_VLD _MMIO(0x650c0)
+#define AUDIO_INACTIVE(trans) ((1 << 3) << ((trans) * 4))
+#define AUDIO_OUTPUT_ENABLE(trans) ((1 << 2) << ((trans) * 4))
+#define AUDIO_CP_READY(trans) ((1 << 1) << ((trans) * 4))
+#define AUDIO_ELD_VALID(trans) ((1 << 0) << ((trans) * 4))
+
+#define _AUD_TCA_DP_2DOT0_CTRL 0x650bc
+#define _AUD_TCB_DP_2DOT0_CTRL 0x651bc
+#define AUD_DP_2DOT0_CTRL(trans) _MMIO_TRANS(trans, _AUD_TCA_DP_2DOT0_CTRL, _AUD_TCB_DP_2DOT0_CTRL)
+#define AUD_ENABLE_SDP_SPLIT REG_BIT(31)
+
+#define HSW_AUD_CHICKENBIT _MMIO(0x65f10)
+#define SKL_AUD_CODEC_WAKE_SIGNAL (1 << 15)
+
+#define AUD_FREQ_CNTRL _MMIO(0x65900)
+#define AUD_PIN_BUF_CTL _MMIO(0x48414)
+#define AUD_PIN_BUF_ENABLE REG_BIT(31)
+
+#define AUD_TS_CDCLK_M _MMIO(0x65ea0)
+#define AUD_TS_CDCLK_M_EN REG_BIT(31)
+#define AUD_TS_CDCLK_N _MMIO(0x65ea4)
+
+/* Display Audio Config Reg */
+#define AUD_CONFIG_BE _MMIO(0x65ef0)
+#define HBLANK_EARLY_ENABLE_ICL(pipe) (0x1 << (20 - (pipe)))
+#define HBLANK_EARLY_ENABLE_TGL(pipe) (0x1 << (24 + (pipe)))
+#define HBLANK_START_COUNT_MASK(pipe) (0x7 << (3 + ((pipe) * 6)))
+#define HBLANK_START_COUNT(pipe, val) (((val) & 0x7) << (3 + ((pipe)) * 6))
+#define NUMBER_SAMPLES_PER_LINE_MASK(pipe) (0x3 << ((pipe) * 6))
+#define NUMBER_SAMPLES_PER_LINE(pipe, val) (((val) & 0x3) << ((pipe) * 6))
+
+#define HBLANK_START_COUNT_8 0
+#define HBLANK_START_COUNT_16 1
+#define HBLANK_START_COUNT_32 2
+#define HBLANK_START_COUNT_64 3
+#define HBLANK_START_COUNT_96 4
+#define HBLANK_START_COUNT_128 5
+
+#endif /* __INTEL_AUDIO_REGS_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 915e8e3e8f38..c08e5407e170 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -32,6 +32,7 @@
#include "i915_drv.h"
#include "intel_audio.h"
+#include "intel_audio_regs.h"
#include "intel_backlight.h"
#include "intel_combo_phy.h"
#include "intel_combo_phy_regs.h"
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0a5064e32284..672b1cdc06b9 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6831,163 +6831,12 @@
(((reg) & GEN7_L3CDERRST1_SUBBANK_MASK) >> 8)
#define GEN7_L3CDERRST1_ENABLE (1 << 7)
-/* Audio */
-#define G4X_AUD_VID_DID _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x62020)
-#define INTEL_AUDIO_DEVCL 0x808629FB
-#define INTEL_AUDIO_DEVBLC 0x80862801
-#define INTEL_AUDIO_DEVCTG 0x80862802
-
-#define G4X_AUD_CNTL_ST _MMIO(0x620B4)
-#define G4X_ELDV_DEVCL_DEVBLC (1 << 13)
-#define G4X_ELDV_DEVCTG (1 << 14)
-#define G4X_ELD_ADDR_MASK (0xf << 5)
-#define G4X_ELD_ACK (1 << 4)
-#define G4X_HDMIW_HDMIEDID _MMIO(0x6210C)
-
-#define _IBX_HDMIW_HDMIEDID_A 0xE2050
-#define _IBX_HDMIW_HDMIEDID_B 0xE2150
-#define IBX_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _IBX_HDMIW_HDMIEDID_A, \
- _IBX_HDMIW_HDMIEDID_B)
-#define _IBX_AUD_CNTL_ST_A 0xE20B4
-#define _IBX_AUD_CNTL_ST_B 0xE21B4
-#define IBX_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _IBX_AUD_CNTL_ST_A, \
- _IBX_AUD_CNTL_ST_B)
-#define IBX_ELD_BUFFER_SIZE_MASK (0x1f << 10)
-#define IBX_ELD_ADDRESS_MASK (0x1f << 5)
-#define IBX_ELD_ACK (1 << 4)
-#define IBX_AUD_CNTL_ST2 _MMIO(0xE20C0)
-#define IBX_CP_READY(port) ((1 << 1) << (((port) - 1) * 4))
-#define IBX_ELD_VALID(port) ((1 << 0) << (((port) - 1) * 4))
-
-#define _CPT_HDMIW_HDMIEDID_A 0xE5050
-#define _CPT_HDMIW_HDMIEDID_B 0xE5150
-#define CPT_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _CPT_HDMIW_HDMIEDID_A, _CPT_HDMIW_HDMIEDID_B)
-#define _CPT_AUD_CNTL_ST_A 0xE50B4
-#define _CPT_AUD_CNTL_ST_B 0xE51B4
-#define CPT_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _CPT_AUD_CNTL_ST_A, _CPT_AUD_CNTL_ST_B)
-#define CPT_AUD_CNTRL_ST2 _MMIO(0xE50C0)
-
-#define _VLV_HDMIW_HDMIEDID_A (VLV_DISPLAY_BASE + 0x62050)
-#define _VLV_HDMIW_HDMIEDID_B (VLV_DISPLAY_BASE + 0x62150)
-#define VLV_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _VLV_HDMIW_HDMIEDID_A, _VLV_HDMIW_HDMIEDID_B)
-#define _VLV_AUD_CNTL_ST_A (VLV_DISPLAY_BASE + 0x620B4)
-#define _VLV_AUD_CNTL_ST_B (VLV_DISPLAY_BASE + 0x621B4)
-#define VLV_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _VLV_AUD_CNTL_ST_A, _VLV_AUD_CNTL_ST_B)
-#define VLV_AUD_CNTL_ST2 _MMIO(VLV_DISPLAY_BASE + 0x620C0)
-
/* These are the 4 32-bit write offset registers for each stream
* output buffer. It determines the offset from the
* 3DSTATE_SO_BUFFERs that the next streamed vertex output goes to.
*/
#define GEN7_SO_WRITE_OFFSET(n) _MMIO(0x5280 + (n) * 4)
-#define _IBX_AUD_CONFIG_A 0xe2000
-#define _IBX_AUD_CONFIG_B 0xe2100
-#define IBX_AUD_CFG(pipe) _MMIO_PIPE(pipe, _IBX_AUD_CONFIG_A, _IBX_AUD_CONFIG_B)
-#define _CPT_AUD_CONFIG_A 0xe5000
-#define _CPT_AUD_CONFIG_B 0xe5100
-#define CPT_AUD_CFG(pipe) _MMIO_PIPE(pipe, _CPT_AUD_CONFIG_A, _CPT_AUD_CONFIG_B)
-#define _VLV_AUD_CONFIG_A (VLV_DISPLAY_BASE + 0x62000)
-#define _VLV_AUD_CONFIG_B (VLV_DISPLAY_BASE + 0x62100)
-#define VLV_AUD_CFG(pipe) _MMIO_PIPE(pipe, _VLV_AUD_CONFIG_A, _VLV_AUD_CONFIG_B)
-
-#define AUD_CONFIG_N_VALUE_INDEX (1 << 29)
-#define AUD_CONFIG_N_PROG_ENABLE (1 << 28)
-#define AUD_CONFIG_UPPER_N_SHIFT 20
-#define AUD_CONFIG_UPPER_N_MASK (0xff << 20)
-#define AUD_CONFIG_LOWER_N_SHIFT 4
-#define AUD_CONFIG_LOWER_N_MASK (0xfff << 4)
-#define AUD_CONFIG_N_MASK (AUD_CONFIG_UPPER_N_MASK | AUD_CONFIG_LOWER_N_MASK)
-#define AUD_CONFIG_N(n) \
- (((((n) >> 12) & 0xff) << AUD_CONFIG_UPPER_N_SHIFT) | \
- (((n) & 0xfff) << AUD_CONFIG_LOWER_N_SHIFT))
-#define AUD_CONFIG_PIXEL_CLOCK_HDMI_SHIFT 16
-#define AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK (0xf << 16)
-#define AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 (0 << 16)
-#define AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 (1 << 16)
-#define AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 (2 << 16)
-#define AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 (3 << 16)
-#define AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 (4 << 16)
-#define AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 (5 << 16)
-#define AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 (6 << 16)
-#define AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 (7 << 16)
-#define AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 (8 << 16)
-#define AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 (9 << 16)
-#define AUD_CONFIG_PIXEL_CLOCK_HDMI_296703 (10 << 16)
-#define AUD_CONFIG_PIXEL_CLOCK_HDMI_297000 (11 << 16)
-#define AUD_CONFIG_PIXEL_CLOCK_HDMI_593407 (12 << 16)
-#define AUD_CONFIG_PIXEL_CLOCK_HDMI_594000 (13 << 16)
-#define AUD_CONFIG_DISABLE_NCTS (1 << 3)
-
-/* HSW Audio */
-#define _HSW_AUD_CONFIG_A 0x65000
-#define _HSW_AUD_CONFIG_B 0x65100
-#define HSW_AUD_CFG(trans) _MMIO_TRANS(trans, _HSW_AUD_CONFIG_A, _HSW_AUD_CONFIG_B)
-
-#define _HSW_AUD_MISC_CTRL_A 0x65010
-#define _HSW_AUD_MISC_CTRL_B 0x65110
-#define HSW_AUD_MISC_CTRL(trans) _MMIO_TRANS(trans, _HSW_AUD_MISC_CTRL_A, _HSW_AUD_MISC_CTRL_B)
-
-#define _HSW_AUD_M_CTS_ENABLE_A 0x65028
-#define _HSW_AUD_M_CTS_ENABLE_B 0x65128
-#define HSW_AUD_M_CTS_ENABLE(trans) _MMIO_TRANS(trans, _HSW_AUD_M_CTS_ENABLE_A, _HSW_AUD_M_CTS_ENABLE_B)
-#define AUD_M_CTS_M_VALUE_INDEX (1 << 21)
-#define AUD_M_CTS_M_PROG_ENABLE (1 << 20)
-#define AUD_CONFIG_M_MASK 0xfffff
-
-#define _HSW_AUD_DIP_ELD_CTRL_ST_A 0x650b4
-#define _HSW_AUD_DIP_ELD_CTRL_ST_B 0x651b4
-#define HSW_AUD_DIP_ELD_CTRL(trans) _MMIO_TRANS(trans, _HSW_AUD_DIP_ELD_CTRL_ST_A, _HSW_AUD_DIP_ELD_CTRL_ST_B)
-
-/* Audio Digital Converter */
-#define _HSW_AUD_DIG_CNVT_1 0x65080
-#define _HSW_AUD_DIG_CNVT_2 0x65180
-#define AUD_DIG_CNVT(trans) _MMIO_TRANS(trans, _HSW_AUD_DIG_CNVT_1, _HSW_AUD_DIG_CNVT_2)
-#define DIP_PORT_SEL_MASK 0x3
-
-#define _HSW_AUD_EDID_DATA_A 0x65050
-#define _HSW_AUD_EDID_DATA_B 0x65150
-#define HSW_AUD_EDID_DATA(trans) _MMIO_TRANS(trans, _HSW_AUD_EDID_DATA_A, _HSW_AUD_EDID_DATA_B)
-
-#define HSW_AUD_PIPE_CONV_CFG _MMIO(0x6507c)
-#define HSW_AUD_PIN_ELD_CP_VLD _MMIO(0x650c0)
-#define AUDIO_INACTIVE(trans) ((1 << 3) << ((trans) * 4))
-#define AUDIO_OUTPUT_ENABLE(trans) ((1 << 2) << ((trans) * 4))
-#define AUDIO_CP_READY(trans) ((1 << 1) << ((trans) * 4))
-#define AUDIO_ELD_VALID(trans) ((1 << 0) << ((trans) * 4))
-
-#define _AUD_TCA_DP_2DOT0_CTRL 0x650bc
-#define _AUD_TCB_DP_2DOT0_CTRL 0x651bc
-#define AUD_DP_2DOT0_CTRL(trans) _MMIO_TRANS(trans, _AUD_TCA_DP_2DOT0_CTRL, _AUD_TCB_DP_2DOT0_CTRL)
-#define AUD_ENABLE_SDP_SPLIT REG_BIT(31)
-
-#define HSW_AUD_CHICKENBIT _MMIO(0x65f10)
-#define SKL_AUD_CODEC_WAKE_SIGNAL (1 << 15)
-
-#define AUD_FREQ_CNTRL _MMIO(0x65900)
-#define AUD_PIN_BUF_CTL _MMIO(0x48414)
-#define AUD_PIN_BUF_ENABLE REG_BIT(31)
-
-#define AUD_TS_CDCLK_M _MMIO(0x65ea0)
-#define AUD_TS_CDCLK_M_EN REG_BIT(31)
-#define AUD_TS_CDCLK_N _MMIO(0x65ea4)
-
-/* Display Audio Config Reg */
-#define AUD_CONFIG_BE _MMIO(0x65ef0)
-#define HBLANK_EARLY_ENABLE_ICL(pipe) (0x1 << (20 - (pipe)))
-#define HBLANK_EARLY_ENABLE_TGL(pipe) (0x1 << (24 + (pipe)))
-#define HBLANK_START_COUNT_MASK(pipe) (0x7 << (3 + ((pipe) * 6)))
-#define HBLANK_START_COUNT(pipe, val) (((val) & 0x7) << (3 + ((pipe)) * 6))
-#define NUMBER_SAMPLES_PER_LINE_MASK(pipe) (0x3 << ((pipe) * 6))
-#define NUMBER_SAMPLES_PER_LINE(pipe, val) (((val) & 0x3) << ((pipe) * 6))
-
-#define HBLANK_START_COUNT_8 0
-#define HBLANK_START_COUNT_16 1
-#define HBLANK_START_COUNT_32 2
-#define HBLANK_START_COUNT_64 3
-#define HBLANK_START_COUNT_96 4
-#define HBLANK_START_COUNT_128 5
-
/*
* HSW - ICL power wells
*
diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
index 72dac1718f3e..157e166672d7 100644
--- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
+++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
@@ -3,10 +3,12 @@
* Copyright © 2020 Intel Corporation
*/
+#include "display/intel_audio_regs.h"
#include "display/intel_dmc_regs.h"
#include "display/vlv_dsi_pll_regs.h"
#include "gt/intel_gt_regs.h"
#include "gvt/gvt.h"
+
#include "i915_drv.h"
#include "i915_pvinfo.h"
#include "i915_reg.h"
--
2.30.2
^ permalink raw reply related [flat|nested] 7+ messages in thread* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/regs: split out intel audio register definitions 2022-06-02 9:45 [Intel-gfx] [PATCH] drm/i915/regs: split out intel audio register definitions Jani Nikula @ 2022-06-02 10:19 ` Patchwork 2022-06-02 10:19 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork ` (3 subsequent siblings) 4 siblings, 0 replies; 7+ messages in thread From: Patchwork @ 2022-06-02 10:19 UTC (permalink / raw) To: Jani Nikula; +Cc: intel-gfx == Series Details == Series: drm/i915/regs: split out intel audio register definitions URL : https://patchwork.freedesktop.org/series/104645/ State : warning == Summary == Error: dim checkpatch failed 977753637a20 drm/i915/regs: split out intel audio register definitions Traceback (most recent call last): File "scripts/spdxcheck.py", line 10, in <module> import git ModuleNotFoundError: No module named 'git' -:28: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #28: new file mode 100644 -:72: WARNING:LONG_LINE: line length of 102 exceeds 100 columns #72: FILE: drivers/gpu/drm/i915/display/intel_audio_regs.h:40: +#define CPT_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _CPT_HDMIW_HDMIEDID_A, _CPT_HDMIW_HDMIEDID_B) -:80: WARNING:LONG_LINE: line length of 102 exceeds 100 columns #80: FILE: drivers/gpu/drm/i915/display/intel_audio_regs.h:48: +#define VLV_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _VLV_HDMIW_HDMIEDID_A, _VLV_HDMIW_HDMIEDID_B) -:103: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'n' - possible side-effects? #103: FILE: drivers/gpu/drm/i915/display/intel_audio_regs.h:71: +#define AUD_CONFIG_N(n) \ + (((((n) >> 12) & 0xff) << AUD_CONFIG_UPPER_N_SHIFT) | \ + (((n) & 0xfff) << AUD_CONFIG_LOWER_N_SHIFT)) -:130: WARNING:LONG_LINE: line length of 102 exceeds 100 columns #130: FILE: drivers/gpu/drm/i915/display/intel_audio_regs.h:98: +#define HSW_AUD_MISC_CTRL(trans) _MMIO_TRANS(trans, _HSW_AUD_MISC_CTRL_A, _HSW_AUD_MISC_CTRL_B) -:134: WARNING:LONG_LINE: line length of 108 exceeds 100 columns #134: FILE: drivers/gpu/drm/i915/display/intel_audio_regs.h:102: +#define HSW_AUD_M_CTS_ENABLE(trans) _MMIO_TRANS(trans, _HSW_AUD_M_CTS_ENABLE_A, _HSW_AUD_M_CTS_ENABLE_B) -:141: WARNING:LONG_LINE: line length of 114 exceeds 100 columns #141: FILE: drivers/gpu/drm/i915/display/intel_audio_regs.h:109: +#define HSW_AUD_DIP_ELD_CTRL(trans) _MMIO_TRANS(trans, _HSW_AUD_DIP_ELD_CTRL_ST_A, _HSW_AUD_DIP_ELD_CTRL_ST_B) -:151: WARNING:LONG_LINE: line length of 102 exceeds 100 columns #151: FILE: drivers/gpu/drm/i915/display/intel_audio_regs.h:119: +#define HSW_AUD_EDID_DATA(trans) _MMIO_TRANS(trans, _HSW_AUD_EDID_DATA_A, _HSW_AUD_EDID_DATA_B) -:162: WARNING:LONG_LINE: line length of 106 exceeds 100 columns #162: FILE: drivers/gpu/drm/i915/display/intel_audio_regs.h:130: +#define AUD_DP_2DOT0_CTRL(trans) _MMIO_TRANS(trans, _AUD_TCA_DP_2DOT0_CTRL, _AUD_TCB_DP_2DOT0_CTRL) total: 0 errors, 8 warnings, 1 checks, 349 lines checked ^ permalink raw reply [flat|nested] 7+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/regs: split out intel audio register definitions 2022-06-02 9:45 [Intel-gfx] [PATCH] drm/i915/regs: split out intel audio register definitions Jani Nikula 2022-06-02 10:19 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork @ 2022-06-02 10:19 ` Patchwork 2022-06-02 10:42 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork ` (2 subsequent siblings) 4 siblings, 0 replies; 7+ messages in thread From: Patchwork @ 2022-06-02 10:19 UTC (permalink / raw) To: Jani Nikula; +Cc: intel-gfx == Series Details == Series: drm/i915/regs: split out intel audio register definitions URL : https://patchwork.freedesktop.org/series/104645/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. ^ permalink raw reply [flat|nested] 7+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/regs: split out intel audio register definitions 2022-06-02 9:45 [Intel-gfx] [PATCH] drm/i915/regs: split out intel audio register definitions Jani Nikula 2022-06-02 10:19 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork 2022-06-02 10:19 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork @ 2022-06-02 10:42 ` Patchwork 2022-06-02 13:00 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork 2022-06-02 22:53 ` [Intel-gfx] [PATCH] " Matt Roper 4 siblings, 0 replies; 7+ messages in thread From: Patchwork @ 2022-06-02 10:42 UTC (permalink / raw) To: Jani Nikula; +Cc: intel-gfx [-- Attachment #1: Type: text/plain, Size: 9352 bytes --] == Series Details == Series: drm/i915/regs: split out intel audio register definitions URL : https://patchwork.freedesktop.org/series/104645/ State : success == Summary == CI Bug Log - changes from CI_DRM_11719 -> Patchwork_104645v1 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/index.html Participating hosts (47 -> 44) ------------------------------ Additional (2): bat-dg2-8 fi-tgl-u2 Missing (5): fi-kbl-soraka fi-hsw-4200u bat-dg2-9 fi-hsw-4770 fi-bdw-samus Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_104645v1: ### IGT changes ### #### Suppressed #### The following results come from untrusted machines, tests, or statuses. They do not affect the overall result. * igt@i915_pm_rpm@basic-rte: - {bat-dg2-8}: NOTRUN -> [DMESG-WARN][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/bat-dg2-8/igt@i915_pm_rpm@basic-rte.html Known issues ------------ Here are the changes found in Patchwork_104645v1 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@gem_huc_copy@huc-copy: - fi-tgl-u2: NOTRUN -> [SKIP][2] ([i915#2190]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/fi-tgl-u2/igt@gem_huc_copy@huc-copy.html * igt@i915_selftest@live@gem: - fi-blb-e6850: NOTRUN -> [DMESG-FAIL][3] ([i915#4528]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/fi-blb-e6850/igt@i915_selftest@live@gem.html * igt@i915_selftest@live@gtt: - fi-bdw-5557u: NOTRUN -> [DMESG-FAIL][4] ([i915#3674]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/fi-bdw-5557u/igt@i915_selftest@live@gtt.html * igt@i915_selftest@live@hangcheck: - fi-bdw-5557u: NOTRUN -> [INCOMPLETE][5] ([i915#3921]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/fi-bdw-5557u/igt@i915_selftest@live@hangcheck.html * igt@kms_chamelium@common-hpd-after-suspend: - fi-cfl-8109u: NOTRUN -> [SKIP][6] ([fdo#109271] / [fdo#111827]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/fi-cfl-8109u/igt@kms_chamelium@common-hpd-after-suspend.html * igt@kms_chamelium@hdmi-edid-read: - fi-tgl-u2: NOTRUN -> [SKIP][7] ([fdo#109284] / [fdo#111827]) +7 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/fi-tgl-u2/igt@kms_chamelium@hdmi-edid-read.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: - fi-tgl-u2: NOTRUN -> [SKIP][8] ([i915#4103]) +1 similar issue [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/fi-tgl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html * igt@kms_flip@basic-flip-vs-wf_vblank@a-edp1: - fi-bsw-kefka: [PASS][9] -> [FAIL][10] ([i915#2122]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11719/fi-bsw-kefka/igt@kms_flip@basic-flip-vs-wf_vblank@a-edp1.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/fi-bsw-kefka/igt@kms_flip@basic-flip-vs-wf_vblank@a-edp1.html * igt@kms_force_connector_basic@force-load-detect: - fi-tgl-u2: NOTRUN -> [SKIP][11] ([fdo#109285]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/fi-tgl-u2/igt@kms_force_connector_basic@force-load-detect.html * igt@kms_setmode@basic-clone-single-crtc: - fi-tgl-u2: NOTRUN -> [SKIP][12] ([i915#3555]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/fi-tgl-u2/igt@kms_setmode@basic-clone-single-crtc.html * igt@prime_vgem@basic-userptr: - fi-tgl-u2: NOTRUN -> [SKIP][13] ([fdo#109295] / [i915#3301]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/fi-tgl-u2/igt@prime_vgem@basic-userptr.html #### Possible fixes #### * igt@i915_pm_rpm@module-reload: - fi-cfl-8109u: [DMESG-FAIL][14] ([i915#62]) -> [PASS][15] [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11719/fi-cfl-8109u/igt@i915_pm_rpm@module-reload.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/fi-cfl-8109u/igt@i915_pm_rpm@module-reload.html * igt@i915_selftest@live@coherency: - fi-bdw-5557u: [INCOMPLETE][16] ([i915#5674] / [i915#5685]) -> [PASS][17] [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11719/fi-bdw-5557u/igt@i915_selftest@live@coherency.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/fi-bdw-5557u/igt@i915_selftest@live@coherency.html * igt@i915_selftest@live@hangcheck: - bat-dg1-5: [DMESG-FAIL][18] ([i915#4494] / [i915#4957]) -> [PASS][19] [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11719/bat-dg1-5/igt@i915_selftest@live@hangcheck.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/bat-dg1-5/igt@i915_selftest@live@hangcheck.html * igt@i915_selftest@live@requests: - fi-blb-e6850: [DMESG-FAIL][20] ([i915#4528]) -> [PASS][21] [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11719/fi-blb-e6850/igt@i915_selftest@live@requests.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/fi-blb-e6850/igt@i915_selftest@live@requests.html * igt@kms_addfb_basic@too-high: - {bat-adlm-1}: [DMESG-WARN][22] ([i915#4391]) -> [PASS][23] [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11719/bat-adlm-1/igt@kms_addfb_basic@too-high.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/bat-adlm-1/igt@kms_addfb_basic@too-high.html * igt@kms_frontbuffer_tracking@basic: - fi-cfl-8109u: [DMESG-WARN][24] ([i915#62]) -> [PASS][25] +15 similar issues [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11719/fi-cfl-8109u/igt@kms_frontbuffer_tracking@basic.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/fi-cfl-8109u/igt@kms_frontbuffer_tracking@basic.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284 [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285 [fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072 [i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155 [i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122 [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190 [i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582 [i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301 [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555 [i915#3595]: https://gitlab.freedesktop.org/drm/intel/issues/3595 [i915#3674]: https://gitlab.freedesktop.org/drm/intel/issues/3674 [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708 [i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921 [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077 [i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079 [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083 [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103 [i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212 [i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213 [i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215 [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312 [i915#4391]: https://gitlab.freedesktop.org/drm/intel/issues/4391 [i915#4494]: https://gitlab.freedesktop.org/drm/intel/issues/4494 [i915#4528]: https://gitlab.freedesktop.org/drm/intel/issues/4528 [i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579 [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613 [i915#4957]: https://gitlab.freedesktop.org/drm/intel/issues/4957 [i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190 [i915#5274]: https://gitlab.freedesktop.org/drm/intel/issues/5274 [i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354 [i915#5674]: https://gitlab.freedesktop.org/drm/intel/issues/5674 [i915#5685]: https://gitlab.freedesktop.org/drm/intel/issues/5685 [i915#6132]: https://gitlab.freedesktop.org/drm/intel/issues/6132 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 Build changes ------------- * Linux: CI_DRM_11719 -> Patchwork_104645v1 CI-20190529: 20190529 CI_DRM_11719: 30f22faccf454263bc2a1c9212b8ab6efbb3425b @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6505: edb1a467fb622b23b927e28ff603fa43851fea97 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_104645v1: 30f22faccf454263bc2a1c9212b8ab6efbb3425b @ git://anongit.freedesktop.org/gfx-ci/linux ### Linux commits b334ddedfea7 drm/i915/regs: split out intel audio register definitions == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/index.html [-- Attachment #2: Type: text/html, Size: 9389 bytes --] ^ permalink raw reply [flat|nested] 7+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/regs: split out intel audio register definitions 2022-06-02 9:45 [Intel-gfx] [PATCH] drm/i915/regs: split out intel audio register definitions Jani Nikula ` (2 preceding siblings ...) 2022-06-02 10:42 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork @ 2022-06-02 13:00 ` Patchwork 2022-06-02 22:53 ` [Intel-gfx] [PATCH] " Matt Roper 4 siblings, 0 replies; 7+ messages in thread From: Patchwork @ 2022-06-02 13:00 UTC (permalink / raw) To: Jani Nikula; +Cc: intel-gfx [-- Attachment #1: Type: text/plain, Size: 53711 bytes --] == Series Details == Series: drm/i915/regs: split out intel audio register definitions URL : https://patchwork.freedesktop.org/series/104645/ State : failure == Summary == CI Bug Log - changes from CI_DRM_11719_full -> Patchwork_104645v1_full ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_104645v1_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_104645v1_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (13 -> 13) ------------------------------ No changes in participating hosts Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_104645v1_full: ### IGT changes ### #### Possible regressions #### * igt@kms_atomic_transition@modeset-transition-nonblocking@1x-outputs: - shard-iclb: [PASS][1] -> [FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11719/shard-iclb7/igt@kms_atomic_transition@modeset-transition-nonblocking@1x-outputs.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-iclb7/igt@kms_atomic_transition@modeset-transition-nonblocking@1x-outputs.html #### Suppressed #### The following results come from untrusted machines, tests, or statuses. They do not affect the overall result. * igt@kms_flip@wf_vblank-ts-check@a-edp1: - {shard-rkl}: NOTRUN -> [FAIL][3] +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-rkl-6/igt@kms_flip@wf_vblank-ts-check@a-edp1.html Known issues ------------ Here are the changes found in Patchwork_104645v1_full that come from known issues: ### CI changes ### #### Possible fixes #### * boot: - shard-apl: ([PASS][4], [PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [FAIL][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25], [PASS][26], [PASS][27], [PASS][28]) ([i915#4386]) -> ([PASS][29], [PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49], [PASS][50], [PASS][51], [PASS][52], [PASS][53]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11719/shard-apl8/boot.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11719/shard-apl8/boot.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11719/shard-apl8/boot.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11719/shard-apl8/boot.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11719/shard-apl7/boot.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11719/shard-apl7/boot.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11719/shard-apl7/boot.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11719/shard-apl6/boot.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11719/shard-apl6/boot.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11719/shard-apl6/boot.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11719/shard-apl4/boot.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11719/shard-apl4/boot.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11719/shard-apl4/boot.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11719/shard-apl3/boot.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11719/shard-apl3/boot.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11719/shard-apl3/boot.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11719/shard-apl3/boot.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11719/shard-apl2/boot.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11719/shard-apl2/boot.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11719/shard-apl2/boot.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11719/shard-apl2/boot.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11719/shard-apl2/boot.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11719/shard-apl1/boot.html [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11719/shard-apl1/boot.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11719/shard-apl1/boot.html [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-apl2/boot.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-apl4/boot.html [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-apl3/boot.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-apl3/boot.html [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-apl3/boot.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-apl2/boot.html [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-apl2/boot.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-apl1/boot.html [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-apl1/boot.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-apl1/boot.html [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-apl8/boot.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-apl8/boot.html [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-apl8/boot.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-apl7/boot.html [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-apl7/boot.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-apl7/boot.html [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-apl7/boot.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-apl6/boot.html [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-apl6/boot.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-apl6/boot.html [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-apl6/boot.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-apl6/boot.html [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-apl4/boot.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-apl4/boot.html [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-apl4/boot.html ### IGT changes ### #### Issues hit #### * igt@gem_exec_balancer@parallel-keep-in-fence: - shard-iclb: [PASS][54] -> [SKIP][55] ([i915#4525]) +1 similar issue [54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11719/shard-iclb2/igt@gem_exec_balancer@parallel-keep-in-fence.html [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-iclb5/igt@gem_exec_balancer@parallel-keep-in-fence.html * igt@gem_exec_capture@pi@vecs0: - shard-iclb: [PASS][56] -> [INCOMPLETE][57] ([i915#3371]) [56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11719/shard-iclb5/igt@gem_exec_capture@pi@vecs0.html [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-iclb8/igt@gem_exec_capture@pi@vecs0.html * igt@gem_exec_flush@basic-uc-set-default: - shard-snb: [PASS][58] -> [SKIP][59] ([fdo#109271]) +2 similar issues [58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11719/shard-snb7/igt@gem_exec_flush@basic-uc-set-default.html [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-snb6/igt@gem_exec_flush@basic-uc-set-default.html * igt@gem_lmem_swapping@heavy-verify-random: - shard-skl: NOTRUN -> [SKIP][60] ([fdo#109271] / [i915#4613]) +1 similar issue [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-skl10/igt@gem_lmem_swapping@heavy-verify-random.html * igt@gem_lmem_swapping@parallel-multi: - shard-kbl: NOTRUN -> [SKIP][61] ([fdo#109271] / [i915#4613]) [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-kbl7/igt@gem_lmem_swapping@parallel-multi.html * igt@gem_lmem_swapping@parallel-random: - shard-glk: NOTRUN -> [SKIP][62] ([fdo#109271] / [i915#4613]) [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-glk5/igt@gem_lmem_swapping@parallel-random.html * igt@gem_lmem_swapping@random: - shard-iclb: NOTRUN -> [SKIP][63] ([i915#4613]) [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-iclb7/igt@gem_lmem_swapping@random.html * igt@gem_lmem_swapping@verify-random: - shard-apl: NOTRUN -> [SKIP][64] ([fdo#109271] / [i915#4613]) +1 similar issue [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-apl7/igt@gem_lmem_swapping@verify-random.html * igt@gem_render_copy@yf-tiled-mc-ccs-to-vebox-yf-tiled: - shard-iclb: NOTRUN -> [SKIP][65] ([i915#768]) [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-iclb3/igt@gem_render_copy@yf-tiled-mc-ccs-to-vebox-yf-tiled.html * igt@gem_userptr_blits@coherency-unsync: - shard-iclb: NOTRUN -> [SKIP][66] ([i915#3297]) [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-iclb3/igt@gem_userptr_blits@coherency-unsync.html * igt@gem_userptr_blits@input-checking: - shard-kbl: NOTRUN -> [DMESG-WARN][67] ([i915#4991]) [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-kbl4/igt@gem_userptr_blits@input-checking.html * igt@gem_workarounds@suspend-resume-context: - shard-apl: [PASS][68] -> [DMESG-WARN][69] ([i915#180]) +2 similar issues [68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11719/shard-apl2/igt@gem_workarounds@suspend-resume-context.html [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-apl1/igt@gem_workarounds@suspend-resume-context.html * igt@gen9_exec_parse@bb-chained: - shard-iclb: NOTRUN -> [SKIP][70] ([i915#2856]) [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-iclb3/igt@gen9_exec_parse@bb-chained.html * igt@i915_pm_dc@dc3co-vpb-simulation: - shard-apl: NOTRUN -> [SKIP][71] ([fdo#109271] / [i915#658]) [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-apl7/igt@i915_pm_dc@dc3co-vpb-simulation.html * igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip: - shard-iclb: NOTRUN -> [SKIP][72] ([i915#5286]) [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-iclb3/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html * igt@kms_big_fb@x-tiled-8bpp-rotate-270: - shard-skl: NOTRUN -> [SKIP][73] ([fdo#109271]) +101 similar issues [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-skl1/igt@kms_big_fb@x-tiled-8bpp-rotate-270.html * igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-async-flip: - shard-skl: NOTRUN -> [FAIL][74] ([i915#3743]) +1 similar issue [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-skl10/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-async-flip.html * igt@kms_big_fb@yf-tiled-8bpp-rotate-180: - shard-iclb: NOTRUN -> [SKIP][75] ([fdo#110723]) +1 similar issue [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-iclb3/igt@kms_big_fb@yf-tiled-8bpp-rotate-180.html * igt@kms_ccs@pipe-a-bad-pixel-format-y_tiled_gen12_mc_ccs: - shard-skl: NOTRUN -> [SKIP][76] ([fdo#109271] / [i915#3886]) +3 similar issues [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-skl1/igt@kms_ccs@pipe-a-bad-pixel-format-y_tiled_gen12_mc_ccs.html * igt@kms_ccs@pipe-b-bad-rotation-90-y_tiled_gen12_mc_ccs: - shard-glk: NOTRUN -> [SKIP][77] ([fdo#109271] / [i915#3886]) +2 similar issues [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-glk8/igt@kms_ccs@pipe-b-bad-rotation-90-y_tiled_gen12_mc_ccs.html * igt@kms_ccs@pipe-b-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc: - shard-apl: NOTRUN -> [SKIP][78] ([fdo#109271] / [i915#3886]) +3 similar issues [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-apl7/igt@kms_ccs@pipe-b-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc.html * igt@kms_ccs@pipe-c-bad-aux-stride-y_tiled_gen12_rc_ccs_cc: - shard-kbl: NOTRUN -> [SKIP][79] ([fdo#109271] / [i915#3886]) +3 similar issues [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-kbl4/igt@kms_ccs@pipe-c-bad-aux-stride-y_tiled_gen12_rc_ccs_cc.html * igt@kms_ccs@pipe-c-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc: - shard-iclb: NOTRUN -> [SKIP][80] ([fdo#109278] / [i915#3886]) +1 similar issue [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-iclb7/igt@kms_ccs@pipe-c-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc.html * igt@kms_chamelium@dp-hpd-enable-disable-mode: - shard-glk: NOTRUN -> [SKIP][81] ([fdo#109271] / [fdo#111827]) +3 similar issues [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-glk5/igt@kms_chamelium@dp-hpd-enable-disable-mode.html * igt@kms_chamelium@hdmi-hpd-storm: - shard-apl: NOTRUN -> [SKIP][82] ([fdo#109271] / [fdo#111827]) +8 similar issues [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-apl7/igt@kms_chamelium@hdmi-hpd-storm.html * igt@kms_chamelium@hdmi-hpd-with-enabled-mode: - shard-iclb: NOTRUN -> [SKIP][83] ([fdo#109284] / [fdo#111827]) [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-iclb3/igt@kms_chamelium@hdmi-hpd-with-enabled-mode.html * igt@kms_color@pipe-d-invalid-gamma-lut-sizes: - shard-glk: NOTRUN -> [SKIP][84] ([fdo#109271]) +65 similar issues [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-glk5/igt@kms_color@pipe-d-invalid-gamma-lut-sizes.html * igt@kms_color_chamelium@pipe-a-ctm-0-75: - shard-skl: NOTRUN -> [SKIP][85] ([fdo#109271] / [fdo#111827]) +4 similar issues [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-skl1/igt@kms_color_chamelium@pipe-a-ctm-0-75.html * igt@kms_color_chamelium@pipe-a-ctm-negative: - shard-kbl: NOTRUN -> [SKIP][86] ([fdo#109271] / [fdo#111827]) +5 similar issues [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-kbl4/igt@kms_color_chamelium@pipe-a-ctm-negative.html * igt@kms_content_protection@mei_interface: - shard-iclb: NOTRUN -> [SKIP][87] ([fdo#109300] / [fdo#111066]) [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-iclb7/igt@kms_content_protection@mei_interface.html * igt@kms_cursor_crc@pipe-a-cursor-512x512-random: - shard-iclb: NOTRUN -> [SKIP][88] ([fdo#109278] / [fdo#109279]) [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-iclb3/igt@kms_cursor_crc@pipe-a-cursor-512x512-random.html * igt@kms_cursor_crc@pipe-c-cursor-32x10-rapid-movement: - shard-iclb: NOTRUN -> [SKIP][89] ([fdo#109278]) +12 similar issues [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-iclb3/igt@kms_cursor_crc@pipe-c-cursor-32x10-rapid-movement.html * igt@kms_cursor_legacy@cursorb-vs-flipa-toggle: - shard-iclb: NOTRUN -> [SKIP][90] ([fdo#109274] / [fdo#109278]) [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-iclb3/igt@kms_cursor_legacy@cursorb-vs-flipa-toggle.html * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions: - shard-glk: [PASS][91] -> [FAIL][92] ([i915#2346]) [91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11719/shard-glk7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-glk2/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html * igt@kms_cursor_legacy@pipe-d-torture-bo: - shard-kbl: NOTRUN -> [SKIP][93] ([fdo#109271] / [i915#533]) [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-kbl7/igt@kms_cursor_legacy@pipe-d-torture-bo.html * igt@kms_draw_crc@draw-method-xrgb2101010-mmap-cpu-xtiled: - shard-iclb: [PASS][94] -> [FAIL][95] ([i915#1888] / [i915#2546]) [94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11719/shard-iclb7/igt@kms_draw_crc@draw-method-xrgb2101010-mmap-cpu-xtiled.html [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-iclb7/igt@kms_draw_crc@draw-method-xrgb2101010-mmap-cpu-xtiled.html * igt@kms_draw_crc@draw-method-xrgb8888-mmap-cpu-4tiled: - shard-iclb: NOTRUN -> [SKIP][96] ([i915#5287]) [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-iclb7/igt@kms_draw_crc@draw-method-xrgb8888-mmap-cpu-4tiled.html * igt@kms_fbcon_fbt@psr-suspend: - shard-kbl: NOTRUN -> [SKIP][97] ([fdo#109271]) +53 similar issues [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-kbl7/igt@kms_fbcon_fbt@psr-suspend.html * igt@kms_flip@2x-plain-flip-fb-recreate: - shard-apl: NOTRUN -> [SKIP][98] ([fdo#109271]) +111 similar issues [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-apl7/igt@kms_flip@2x-plain-flip-fb-recreate.html * igt@kms_flip@plain-flip-ts-check@b-edp1: - shard-skl: [PASS][99] -> [FAIL][100] ([i915#2122]) +1 similar issue [99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11719/shard-skl4/igt@kms_flip@plain-flip-ts-check@b-edp1.html [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-skl2/igt@kms_flip@plain-flip-ts-check@b-edp1.html * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling: - shard-iclb: [PASS][101] -> [SKIP][102] ([i915#3701]) [101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11719/shard-iclb5/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling.html [102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling.html * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-blt: - shard-glk: [PASS][103] -> [FAIL][104] ([i915#1888] / [i915#2546]) [103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11719/shard-glk6/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-blt.html [104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-glk8/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-blt.html * igt@kms_frontbuffer_tracking@psr-2p-pri-indfb-multidraw: - shard-iclb: NOTRUN -> [SKIP][105] ([fdo#109280]) +9 similar issues [105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-iclb3/igt@kms_frontbuffer_tracking@psr-2p-pri-indfb-multidraw.html * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: - shard-kbl: [PASS][106] -> [DMESG-WARN][107] ([i915#180]) +4 similar issues [106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11719/shard-kbl3/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b.html [107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-kbl6/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b.html * igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb: - shard-kbl: NOTRUN -> [FAIL][108] ([fdo#108145] / [i915#265]) [108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-kbl4/igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb.html * igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max: - shard-glk: NOTRUN -> [FAIL][109] ([fdo#108145] / [i915#265]) +1 similar issue [109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-glk5/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max.html * igt@kms_plane_alpha_blend@pipe-c-alpha-basic: - shard-apl: NOTRUN -> [FAIL][110] ([fdo#108145] / [i915#265]) [110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-apl7/igt@kms_plane_alpha_blend@pipe-c-alpha-basic.html * igt@kms_psr2_sf@cursor-plane-move-continuous-sf: - shard-skl: NOTRUN -> [SKIP][111] ([fdo#109271] / [i915#658]) +1 similar issue [111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-skl10/igt@kms_psr2_sf@cursor-plane-move-continuous-sf.html * igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb: - shard-iclb: NOTRUN -> [SKIP][112] ([i915#658]) [112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-iclb7/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb.html * igt@kms_psr@psr2_cursor_plane_move: - shard-iclb: NOTRUN -> [SKIP][113] ([fdo#109441]) [113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-iclb3/igt@kms_psr@psr2_cursor_plane_move.html * igt@kms_psr@psr2_primary_blt: - shard-iclb: [PASS][114] -> [SKIP][115] ([fdo#109441]) [114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11719/shard-iclb2/igt@kms_psr@psr2_primary_blt.html [115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-iclb1/igt@kms_psr@psr2_primary_blt.html * igt@kms_setmode@invalid-clone-single-crtc: - shard-iclb: NOTRUN -> [SKIP][116] ([i915#3555]) [116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-iclb7/igt@kms_setmode@invalid-clone-single-crtc.html * igt@prime_nv_pcopy@test3_2: - shard-iclb: NOTRUN -> [SKIP][117] ([fdo#109291]) [117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-iclb3/igt@prime_nv_pcopy@test3_2.html * igt@sysfs_clients@pidname: - shard-skl: NOTRUN -> [SKIP][118] ([fdo#109271] / [i915#2994]) [118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-skl1/igt@sysfs_clients@pidname.html - shard-apl: NOTRUN -> [SKIP][119] ([fdo#109271] / [i915#2994]) [119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-apl7/igt@sysfs_clients@pidname.html * igt@sysfs_clients@sema-50: - shard-iclb: NOTRUN -> [SKIP][120] ([i915#2994]) [120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-iclb3/igt@sysfs_clients@sema-50.html #### Possible fixes #### * igt@fbdev@read: - {shard-rkl}: [SKIP][121] ([i915#2582]) -> [PASS][122] [121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11719/shard-rkl-5/igt@fbdev@read.html [122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-rkl-6/igt@fbdev@read.html * igt@gem_ctx_isolation@preservation-s3@vcs0: - shard-kbl: [DMESG-WARN][123] ([i915#180]) -> [PASS][124] +7 similar issues [123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11719/shard-kbl1/igt@gem_ctx_isolation@preservation-s3@vcs0.html [124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-kbl3/igt@gem_ctx_isolation@preservation-s3@vcs0.html * igt@gem_eio@unwedge-stress: - shard-iclb: [TIMEOUT][125] ([i915#3070]) -> [PASS][126] [125]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11719/shard-iclb2/igt@gem_eio@unwedge-stress.html [126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-iclb1/igt@gem_eio@unwedge-stress.html - {shard-tglu}: [TIMEOUT][127] ([i915#3063]) -> [PASS][128] [127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11719/shard-tglu-2/igt@gem_eio@unwedge-stress.html [128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-tglu-1/igt@gem_eio@unwedge-stress.html * igt@gem_exec_balancer@parallel-contexts: - shard-iclb: [SKIP][129] ([i915#4525]) -> [PASS][130] +2 similar issues [129]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11719/shard-iclb5/igt@gem_exec_balancer@parallel-contexts.html [130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-iclb2/igt@gem_exec_balancer@parallel-contexts.html * igt@gem_exec_fair@basic-pace-share@rcs0: - {shard-tglu}: [FAIL][131] ([i915#2842]) -> [PASS][132] [131]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11719/shard-tglu-2/igt@gem_exec_fair@basic-pace-share@rcs0.html [132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-tglu-1/igt@gem_exec_fair@basic-pace-share@rcs0.html * igt@gem_exec_fair@basic-pace-solo@rcs0: - shard-kbl: [FAIL][133] ([i915#2842]) -> [PASS][134] [133]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11719/shard-kbl6/igt@gem_exec_fair@basic-pace-solo@rcs0.html [134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-kbl4/igt@gem_exec_fair@basic-pace-solo@rcs0.html * igt@gem_exec_flush@basic-uc-ro-default: - shard-snb: [SKIP][135] ([fdo#109271]) -> [PASS][136] +4 similar issues [135]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11719/shard-snb6/igt@gem_exec_flush@basic-uc-ro-default.html [136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-snb5/igt@gem_exec_flush@basic-uc-ro-default.html * igt@gem_exec_whisper@basic-fds-forked-all: - shard-iclb: [INCOMPLETE][137] ([i915#5498] / [i915#5843]) -> [PASS][138] [137]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11719/shard-iclb7/igt@gem_exec_whisper@basic-fds-forked-all.html [138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-iclb3/igt@gem_exec_whisper@basic-fds-forked-all.html * igt@gem_huc_copy@huc-copy: - shard-tglb: [SKIP][139] ([i915#2190]) -> [PASS][140] [139]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11719/shard-tglb7/igt@gem_huc_copy@huc-copy.html [140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-tglb1/igt@gem_huc_copy@huc-copy.html * igt@gem_softpin@allocator-fork: - shard-iclb: [DMESG-WARN][141] ([i915#4391]) -> [PASS][142] [141]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11719/shard-iclb7/igt@gem_softpin@allocator-fork.html [142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-iclb7/igt@gem_softpin@allocator-fork.html * igt@gem_softpin@evict-single-offset: - shard-iclb: [FAIL][143] ([i915#4171]) -> [PASS][144] [143]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11719/shard-iclb3/igt@gem_softpin@evict-single-offset.html [144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-iclb6/igt@gem_softpin@evict-single-offset.html * igt@gen9_exec_parse@allowed-all: - shard-glk: [DMESG-WARN][145] ([i915#5566] / [i915#716]) -> [PASS][146] [145]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11719/shard-glk4/igt@gen9_exec_parse@allowed-all.html [146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-glk5/igt@gen9_exec_parse@allowed-all.html * igt@i915_pm_backlight@fade: - {shard-rkl}: [SKIP][147] ([i915#3012]) -> [PASS][148] [147]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11719/shard-rkl-5/igt@i915_pm_backlight@fade.html [148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-rkl-6/igt@i915_pm_backlight@fade.html * igt@i915_pm_dc@dc6-psr: - {shard-rkl}: [SKIP][149] ([i915#658]) -> [PASS][150] [149]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11719/shard-rkl-5/igt@i915_pm_dc@dc6-psr.html [150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-rkl-6/igt@i915_pm_dc@dc6-psr.html * igt@kms_color@pipe-a-ctm-blue-to-red: - {shard-rkl}: [SKIP][151] ([i915#1149] / [i915#1849] / [i915#4070] / [i915#4098]) -> [PASS][152] +2 similar issues [151]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11719/shard-rkl-5/igt@kms_color@pipe-a-ctm-blue-to-red.html [152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-rkl-6/igt@kms_color@pipe-a-ctm-blue-to-red.html * igt@kms_color@pipe-c-invalid-ctm-matrix-sizes: - {shard-rkl}: [SKIP][153] ([i915#4070]) -> [PASS][154] [153]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11719/shard-rkl-2/igt@kms_color@pipe-c-invalid-ctm-matrix-sizes.html [154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-rkl-5/igt@kms_color@pipe-c-invalid-ctm-matrix-sizes.html * igt@kms_cursor_crc@pipe-b-cursor-128x42-onscreen: - {shard-rkl}: [SKIP][155] ([fdo#112022] / [i915#4070]) -> [PASS][156] +4 similar issues [155]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11719/shard-rkl-5/igt@kms_cursor_crc@pipe-b-cursor-128x42-onscreen.html [156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-rkl-6/igt@kms_cursor_crc@pipe-b-cursor-128x42-onscreen.html * igt@kms_cursor_edge_walk@pipe-b-256x256-right-edge: - {shard-rkl}: [SKIP][157] ([i915#1849] / [i915#4070] / [i915#4098]) -> [PASS][158] +1 similar issue [157]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11719/shard-rkl-5/igt@kms_cursor_edge_walk@pipe-b-256x256-right-edge.html [158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-rkl-6/igt@kms_cursor_edge_walk@pipe-b-256x256-right-edge.html * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size: - {shard-rkl}: [SKIP][159] ([fdo#111825] / [i915#4070]) -> [PASS][160] [159]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11719/shard-rkl-5/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html [160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-rkl-6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html * igt@kms_draw_crc@draw-method-rgb565-pwrite-xtiled: - {shard-rkl}: [SKIP][161] ([fdo#111314] / [i915#4098] / [i915#4369]) -> [PASS][162] +3 similar issues [161]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11719/shard-rkl-5/igt@kms_draw_crc@draw-method-rgb565-pwrite-xtiled.html [162]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-rkl-6/igt@kms_draw_crc@draw-method-rgb565-pwrite-xtiled.html * igt@kms_fbcon_fbt@psr-suspend: - {shard-rkl}: [SKIP][163] ([fdo#110189] / [i915#3955]) -> [PASS][164] [163]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11719/shard-rkl-5/igt@kms_fbcon_fbt@psr-suspend.html [164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-rkl-6/igt@kms_fbcon_fbt@psr-suspend.html * igt@kms_flip@flip-vs-expired-vblank@a-hdmi-a2: - shard-glk: [FAIL][165] ([i915#79]) -> [PASS][166] [165]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11719/shard-glk1/igt@kms_flip@flip-vs-expired-vblank@a-hdmi-a2.html [166]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-glk9/igt@kms_flip@flip-vs-expired-vblank@a-hdmi-a2.html * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling: - {shard-rkl}: [SKIP][167] ([i915#3701]) -> [PASS][168] [167]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11719/shard-rkl-5/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling.html [168]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-rkl-6/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling.html * igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling: - shard-iclb: [SKIP][169] ([i915#3701]) -> [PASS][170] +1 similar issue [169]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11719/shard-iclb2/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling.html [170]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-iclb1/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-rte: - {shard-rkl}: [SKIP][171] ([i915#1849] / [i915#4098]) -> [PASS][172] +19 similar issues [171]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11719/shard-rkl-5/igt@kms_frontbuffer_tracking@fbcpsr-1p-rte.html [172]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-rkl-6/igt@kms_frontbuffer_tracking@fbcpsr-1p-rte.html * igt@kms_hdr@bpc-switch@pipe-a-dp-1: - shard-kbl: [FAIL][173] -> [PASS][174] [173]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11719/shard-kbl1/igt@kms_hdr@bpc-switch@pipe-a-dp-1.html [174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-kbl1/igt@kms_hdr@bpc-switch@pipe-a-dp-1.html * igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes: - shard-apl: [DMESG-WARN][175] ([i915#180]) -> [PASS][176] +2 similar issues [175]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11719/shard-apl2/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes.html [176]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-apl7/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes.html * igt@kms_plane@plane-panning-top-left@pipe-b-planes: - {shard-rkl}: [SKIP][177] ([i915#1849] / [i915#3558]) -> [PASS][178] +1 similar issue [177]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11719/shard-rkl-5/igt@kms_plane@plane-panning-top-left@pipe-b-planes.html [178]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-rkl-6/igt@kms_plane@plane-panning-top-left@pipe-b-planes.html * igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-a-edp-1: - shard-iclb: [SKIP][179] -> [PASS][180] +2 similar issues [179]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11719/shard-iclb2/igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-a-edp-1.html [180]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-iclb5/igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-a-edp-1.html * igt@kms_psr@cursor_render: - {shard-rkl}: [SKIP][181] ([i915#1072]) -> [PASS][182] +1 similar issue [181]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11719/shard-rkl-5/igt@kms_psr@cursor_render.html [182]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-rkl-6/igt@kms_psr@cursor_render.html * igt@kms_psr@psr2_cursor_mmap_cpu: - shard-iclb: [SKIP][183] ([fdo#109441]) -> [PASS][184] +2 similar issues [183]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11719/shard-iclb4/igt@kms_psr@psr2_cursor_mmap_cpu.html [184]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_cpu.html * igt@kms_vblank@pipe-a-wait-forked-busy-hang: - {shard-rkl}: [SKIP][185] ([i915#1845] / [i915#4098]) -> [PASS][186] +13 similar issues [185]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11719/shard-rkl-5/igt@kms_vblank@pipe-a-wait-forked-busy-hang.html [186]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-rkl-6/igt@kms_vblank@pipe-a-wait-forked-busy-hang.html * igt@perf@oa-exponents: - shard-glk: [INCOMPLETE][187] ([i915#5213]) -> [PASS][188] [187]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11719/shard-glk4/igt@perf@oa-exponents.html [188]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-glk8/igt@perf@oa-exponents.html * igt@perf@polling-parameterized: - {shard-rkl}: [FAIL][189] ([i915#5639]) -> [PASS][190] [189]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11719/shard-rkl-1/igt@perf@polling-parameterized.html [190]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-rkl-2/igt@perf@polling-parameterized.html #### Warnings #### * igt@gem_eio@unwedge-stress: - shard-tglb: [TIMEOUT][191] ([i915#3063]) -> [FAIL][192] ([i915#5784]) [191]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11719/shard-tglb7/igt@gem_eio@unwedge-stress.html [192]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-tglb2/igt@gem_eio@unwedge-stress.html * igt@gem_exec_balancer@fairslice: - shard-skl: [SKIP][193] ([fdo#109271]) -> [SKIP][194] ([fdo#109271] / [i915#1888]) [193]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11719/shard-skl10/igt@gem_exec_balancer@fairslice.html [194]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-skl7/igt@gem_exec_balancer@fairslice.html * igt@i915_pm_dc@dc3co-vpb-simulation: - shard-iclb: [SKIP][195] ([i915#658]) -> [SKIP][196] ([i915#588]) [195]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11719/shard-iclb4/igt@i915_pm_dc@dc3co-vpb-simulation.html [196]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-iclb2/igt@i915_pm_dc@dc3co-vpb-simulation.html * igt@kms_chamelium@hdmi-crc-nonplanar-formats: - shard-skl: [SKIP][197] ([fdo#109271] / [fdo#111827]) -> [SKIP][198] ([fdo#109271] / [fdo#111827] / [i915#1888]) [197]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11719/shard-skl10/igt@kms_chamelium@hdmi-crc-nonplanar-formats.html [198]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-skl7/igt@kms_chamelium@hdmi-crc-nonplanar-formats.html * igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-sf: - shard-iclb: [SKIP][199] ([i915#658]) -> [SKIP][200] ([i915#2920]) +1 similar issue [199]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11719/shard-iclb4/igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-sf.html [200]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-iclb2/igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-sf.html * igt@kms_psr2_sf@cursor-plane-update-sf: - shard-iclb: [SKIP][201] ([i915#2920]) -> [SKIP][202] ([fdo#111068] / [i915#658]) [201]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11719/shard-iclb2/igt@kms_psr2_sf@cursor-plane-update-sf.html [202]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-iclb5/igt@kms_psr2_sf@cursor-plane-update-sf.html * igt@kms_psr2_su@page_flip-p010: - shard-iclb: [FAIL][203] ([i915#5939]) -> [SKIP][204] ([fdo#109642] / [fdo#111068] / [i915#658]) [203]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11719/shard-iclb2/igt@kms_psr2_su@page_flip-p010.html [204]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-iclb1/igt@kms_psr2_su@page_flip-p010.html * igt@runner@aborted: - shard-apl: ([FAIL][205], [FAIL][206], [FAIL][207], [FAIL][208], [FAIL][209]) ([i915#180] / [i915#3002] / [i915#4312] / [i915#5257]) -> ([FAIL][210], [FAIL][211], [FAIL][212], [FAIL][213], [FAIL][214]) ([fdo#109271] / [i915#180] / [i915#3002] / [i915#4312] / [i915#5257]) [205]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11719/shard-apl1/igt@runner@aborted.html [206]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11719/shard-apl2/igt@runner@aborted.html [207]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11719/shard-apl2/igt@runner@aborted.html [208]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11719/shard-apl8/igt@runner@aborted.html [209]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11719/shard-apl8/igt@runner@aborted.html [210]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-apl6/igt@runner@aborted.html [211]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-apl8/igt@runner@aborted.html [212]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-apl4/igt@runner@aborted.html [213]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-apl1/igt@runner@aborted.html [214]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-apl6/igt@runner@aborted.html - shard-kbl: ([FAIL][215], [FAIL][216], [FAIL][217], [FAIL][218], [FAIL][219], [FAIL][220], [FAIL][221], [FAIL][222], [FAIL][223], [FAIL][224], [FAIL][225]) ([fdo#109271] / [i915#180] / [i915#3002] / [i915#4312] / [i915#5257]) -> ([FAIL][226], [FAIL][227], [FAIL][228], [FAIL][229], [FAIL][230], [FAIL][231], [FAIL][232], [FAIL][233], [FAIL][234], [FAIL][235], [FAIL][236]) ([i915#180] / [i915#3002] / [i915#4312] / [i915#5257]) [215]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11719/shard-kbl1/igt@runner@aborted.html [216]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11719/shard-kbl4/igt@runner@aborted.html [217]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11719/shard-kbl1/igt@runner@aborted.html [218]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11719/shard-kbl1/igt@runner@aborted.html [219]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11719/shard-kbl4/igt@runner@aborted.html [220]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11719/shard-kbl4/igt@runner@aborted.html [221]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11719/shard-kbl7/igt@runner@aborted.html [222]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11719/shard-kbl7/igt@runner@aborted.html [223]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11719/shard-kbl7/igt@runner@aborted.html [224]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11719/shard-kbl7/igt@runner@aborted.html [225]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11719/shard-kbl6/igt@runner@aborted.html [226]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-kbl4/igt@runner@aborted.html [227]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-kbl4/igt@runner@aborted.html [228]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-kbl6/igt@runner@aborted.html [229]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-kbl4/igt@runner@aborted.html [230]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-kbl7/igt@runner@aborted.html [231]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-kbl6/igt@runner@aborted.html [232]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-kbl6/igt@runner@aborted.html [233]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-kbl1/igt@runner@aborted.html [234]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-kbl7/igt@runner@aborted.html [235]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-kbl1/igt@runner@aborted.html [236]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/shard-kbl1/igt@runner@aborted.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375 [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274 [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278 [fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279 [fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280 [fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283 [fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284 [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285 [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289 [fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291 [fdo#109300]: https://bugs.freedesktop.org/show_bug.cgi?id=109300 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506 [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642 [fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189 [fdo#110542]: https://bugs.freedesktop.org/show_bug.cgi?id=110542 [fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723 [fdo#111066]: https://bugs.freedesktop.org/show_bug.cgi?id=111066 [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068 [fdo#111314]: https://bugs.freedesktop.org/show_bug.cgi?id=111314 [fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614 [fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615 [fdo#111644]: https://bugs.freedesktop.org/show_bug.cgi?id=111644 [fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [fdo#112022]: https://bugs.freedesktop.org/show_bug.cgi?id=112022 [fdo#112054]: https://bugs.freedesktop.org/show_bug.cgi?id=112054 [fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283 [i915#1063]: https://gitlab.freedesktop.org/drm/intel/issues/1063 [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072 [i915#1149]: https://gitlab.freedesktop.org/drm/intel/issues/1149 [i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155 [i915#132]: https://gitlab.freedesktop.org/drm/intel/issues/132 [i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397 [i915#1769]: https://gitlab.freedesktop.org/drm/intel/issues/1769 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825 [i915#1836]: https://gitlab.freedesktop.org/drm/intel/issues/1836 [i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839 [i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845 [i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849 [i915#1850]: https://gitlab.freedesktop.org/drm/intel/issues/1850 [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888 [i915#1902]: https://gitlab.freedesktop.org/drm/intel/issues/1902 [i915#1911]: https://gitlab.freedesktop.org/drm/intel/issues/1911 [i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122 [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190 [i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346 [i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437 [i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527 [i915#2530]: https://gitlab.freedesktop.org/drm/intel/issues/2530 [i915#2546]: https://gitlab.freedesktop.org/drm/intel/issues/2546 [i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280 [i915#284]: https://gitlab.freedesktop.org/drm/intel/issues/284 [i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842 [i915#2849]: https://gitlab.freedesktop.org/drm/intel/issues/2849 [i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856 [i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920 [i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994 [i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002 [i915#3012]: https://gitlab.freedesktop.org/drm/intel/issues/3012 [i915#3063]: https://gitlab.freedesktop.org/drm/intel/issues/3063 [i915#3070]: https://gitlab.freedesktop.org/drm/intel/issues/3070 [i915#3116]: https://gitlab.freedesktop.org/drm/intel/issues/3116 [i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281 [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282 [i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297 [i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299 [i915#3318]: https://gitlab.freedesktop.org/drm/intel/issues/3318 [i915#3319]: https://gitlab.freedesktop.org/drm/intel/issues/3319 [i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359 [i915#3371]: https://gitlab.freedesktop.org/drm/intel/issues/3371 [i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458 [i915#3469]: https://gitlab.freedesktop.org/drm/intel/issues/3469 [i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539 [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555 [i915#3558]: https://gitlab.freedesktop.org/drm/intel/issues/3558 [i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637 [i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638 [i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689 [i915#3701]: https://gitlab.freedesktop.org/drm/intel/issues/3701 [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708 [i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734 [i915#3743]: https://gitlab.freedesktop.org/drm/intel/issues/3743 [i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840 [i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886 [i915#3938]: https://gitlab.freedesktop.org/drm/intel/issues/3938 [i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955 [i915#4032]: https://gitlab.freedesktop.org/drm/intel/issues/4032 [i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070 [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077 [i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078 [i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098 [i915#4171]: https://gitlab.freedesktop.org/drm/intel/issues/4171 [i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212 [i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270 [i915#4278]: https://gitlab.freedesktop.org/drm/intel/issues/4278 [i915#4281]: https://gitlab.freedesktop.org/drm/intel/issues/4281 [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312 [i915#4369]: https://gitlab.freedesktop.org/drm/intel/issues/4369 [i915#4386]: https://gitlab.freedesktop.org/drm/intel/issues/4386 [i915#4391]: https://gitlab.freedesktop.org/drm/intel/issues/4391 [i915#4494]: https://gitlab.freedesktop.org/drm/intel/issues/4494 [i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525 [i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538 [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454 [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613 [i915#4771]: https://gitlab.freedesktop.org/drm/intel/issues/4771 [i915#4807]: https://gitlab.freedesktop.org/drm/intel/issues/4807 [i915#4833]: https://gitlab.freedesktop.org/drm/intel/issues/4833 [i915#4842]: https://gitlab.freedesktop.org/drm/intel/issues/4842 [i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852 [i915#4853]: https://gitlab.freedesktop.org/drm/intel/issues/4853 [i915#4859]: https://gitlab.freedesktop.org/drm/intel/issues/4859 [i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860 [i915#4881]: https://gitlab.freedesktop.org/drm/intel/issues/4881 [i915#4884]: https://gitlab.freedesktop.org/drm/intel/issues/4884 [i915#4893]: https://gitlab.freedesktop.org/drm/intel/issues/4893 [i915#4957]: https://gitlab.freedesktop.org/drm/intel/issues/4957 [i915#4991]: https://gitlab.freedesktop.org/drm/intel/issues/4991 [i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176 [i915#5213]: https://gitlab.freedesktop.org/drm/intel/issues/5213 [i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235 [i915#5257]: https://gitlab.freedesktop.org/drm/intel/issues/5257 [i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286 [i915#5287]: https://gitlab.freedesktop.org/drm/intel/issues/5287 [i915#5288]: https://gitlab.freedesktop.org/drm/intel/issues/5288 [i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289 [i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325 [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533 [i915#5439]: https://gitlab.freedesktop.org/drm/intel/issues/5439 [i915#5461]: https://gitlab.freedesktop.org/drm/intel/issues/5461 [i915#5498]: https://gitlab.freedesktop.org/drm/intel/issues/5498 [i915#5566]: https://gitlab.freedesktop.org/drm/intel/issues/5566 [i915#5639]: https://gitlab.freedesktop.org/drm/intel/issues/5639 [i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784 [i915#5843]: https://gitlab.freedesktop.org/drm/intel/issues/5843 [i915#588]: https://gitlab.freedesktop.org/drm/intel/issues/588 [i915#5939]: https://gitlab.freedesktop.org/drm/intel/issues/5939 [i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095 [i915#6139]: https://gitlab.freedesktop.org/drm/intel/issues/6139 [i915#6141]: https://gitlab.freedesktop.org/drm/intel/issues/6141 [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658 [i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716 [i915#768]: https://gitlab.freedesktop.org/drm/intel/issues/768 [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 Build changes ------------- * Linux: CI_DRM_11719 -> Patchwork_104645v1 CI-20190529: 20190529 CI_DRM_11719: 30f22faccf454263bc2a1c9212b8ab6efbb3425b @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6505: edb1a467fb622b23b927e28ff603fa43851fea97 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_104645v1: 30f22faccf454263bc2a1c9212b8ab6efbb3425b @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104645v1/index.html [-- Attachment #2: Type: text/html, Size: 58428 bytes --] ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/regs: split out intel audio register definitions 2022-06-02 9:45 [Intel-gfx] [PATCH] drm/i915/regs: split out intel audio register definitions Jani Nikula ` (3 preceding siblings ...) 2022-06-02 13:00 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork @ 2022-06-02 22:53 ` Matt Roper 2022-06-03 8:40 ` Jani Nikula 4 siblings, 1 reply; 7+ messages in thread From: Matt Roper @ 2022-06-02 22:53 UTC (permalink / raw) To: Jani Nikula; +Cc: intel-gfx On Thu, Jun 02, 2022 at 12:45:42PM +0300, Jani Nikula wrote: > Split out audio registers to a header of its own to reduce the size of > i915_reg.h. > > TODO: Remove direct audio register access from intel_ddi.c. However, > unification of audio get config is cumbersome due to the audio enable > bit being in the DP or HDMI registers on older platforms. > > Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> > --- > drivers/gpu/drm/i915/display/intel_audio.c | 1 + > .../gpu/drm/i915/display/intel_audio_regs.h | 160 ++++++++++++++++++ > drivers/gpu/drm/i915/display/intel_ddi.c | 1 + > drivers/gpu/drm/i915/i915_reg.h | 151 ----------------- > drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 2 + > 5 files changed, 164 insertions(+), 151 deletions(-) > create mode 100644 drivers/gpu/drm/i915/display/intel_audio_regs.h > > diff --git a/drivers/gpu/drm/i915/display/intel_audio.c b/drivers/gpu/drm/i915/display/intel_audio.c > index f0f0dfce27ce..6c9ee905f132 100644 > --- a/drivers/gpu/drm/i915/display/intel_audio.c > +++ b/drivers/gpu/drm/i915/display/intel_audio.c > @@ -30,6 +30,7 @@ > #include "i915_drv.h" > #include "intel_atomic.h" > #include "intel_audio.h" > +#include "intel_audio_regs.h" > #include "intel_cdclk.h" > #include "intel_crtc.h" > #include "intel_de.h" > diff --git a/drivers/gpu/drm/i915/display/intel_audio_regs.h b/drivers/gpu/drm/i915/display/intel_audio_regs.h > new file mode 100644 > index 000000000000..d1e5844e3484 > --- /dev/null > +++ b/drivers/gpu/drm/i915/display/intel_audio_regs.h > @@ -0,0 +1,160 @@ > +/* SPDX-License-Identifier: MIT */ > +/* > + * Copyright © 2022 Intel Corporation > + */ > + > +#ifndef __INTEL_AUDIO_REGS_H__ > +#define __INTEL_AUDIO_REGS_H__ > + > +#include "i915_reg_defs.h" > + > +#define G4X_AUD_VID_DID _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x62020) > +#define INTEL_AUDIO_DEVCL 0x808629FB > +#define INTEL_AUDIO_DEVBLC 0x80862801 > +#define INTEL_AUDIO_DEVCTG 0x80862802 > + > +#define G4X_AUD_CNTL_ST _MMIO(0x620B4) > +#define G4X_ELDV_DEVCL_DEVBLC (1 << 13) > +#define G4X_ELDV_DEVCTG (1 << 14) > +#define G4X_ELD_ADDR_MASK (0xf << 5) > +#define G4X_ELD_ACK (1 << 4) > +#define G4X_HDMIW_HDMIEDID _MMIO(0x6210C) > + > +#define _IBX_HDMIW_HDMIEDID_A 0xE2050 > +#define _IBX_HDMIW_HDMIEDID_B 0xE2150 > +#define IBX_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _IBX_HDMIW_HDMIEDID_A, \ > + _IBX_HDMIW_HDMIEDID_B) > +#define _IBX_AUD_CNTL_ST_A 0xE20B4 > +#define _IBX_AUD_CNTL_ST_B 0xE21B4 > +#define IBX_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _IBX_AUD_CNTL_ST_A, \ > + _IBX_AUD_CNTL_ST_B) > +#define IBX_ELD_BUFFER_SIZE_MASK (0x1f << 10) > +#define IBX_ELD_ADDRESS_MASK (0x1f << 5) > +#define IBX_ELD_ACK (1 << 4) > +#define IBX_AUD_CNTL_ST2 _MMIO(0xE20C0) > +#define IBX_CP_READY(port) ((1 << 1) << (((port) - 1) * 4)) > +#define IBX_ELD_VALID(port) ((1 << 0) << (((port) - 1) * 4)) > + > +#define _CPT_HDMIW_HDMIEDID_A 0xE5050 > +#define _CPT_HDMIW_HDMIEDID_B 0xE5150 > +#define CPT_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _CPT_HDMIW_HDMIEDID_A, _CPT_HDMIW_HDMIEDID_B) > +#define _CPT_AUD_CNTL_ST_A 0xE50B4 > +#define _CPT_AUD_CNTL_ST_B 0xE51B4 > +#define CPT_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _CPT_AUD_CNTL_ST_A, _CPT_AUD_CNTL_ST_B) > +#define CPT_AUD_CNTRL_ST2 _MMIO(0xE50C0) > + > +#define _VLV_HDMIW_HDMIEDID_A (VLV_DISPLAY_BASE + 0x62050) > +#define _VLV_HDMIW_HDMIEDID_B (VLV_DISPLAY_BASE + 0x62150) > +#define VLV_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _VLV_HDMIW_HDMIEDID_A, _VLV_HDMIW_HDMIEDID_B) > +#define _VLV_AUD_CNTL_ST_A (VLV_DISPLAY_BASE + 0x620B4) > +#define _VLV_AUD_CNTL_ST_B (VLV_DISPLAY_BASE + 0x621B4) > +#define VLV_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _VLV_AUD_CNTL_ST_A, _VLV_AUD_CNTL_ST_B) > +#define VLV_AUD_CNTL_ST2 _MMIO(VLV_DISPLAY_BASE + 0x620C0) > + > +#define _IBX_AUD_CONFIG_A 0xe2000 > +#define _IBX_AUD_CONFIG_B 0xe2100 > +#define IBX_AUD_CFG(pipe) _MMIO_PIPE(pipe, _IBX_AUD_CONFIG_A, _IBX_AUD_CONFIG_B) > +#define _CPT_AUD_CONFIG_A 0xe5000 > +#define _CPT_AUD_CONFIG_B 0xe5100 > +#define CPT_AUD_CFG(pipe) _MMIO_PIPE(pipe, _CPT_AUD_CONFIG_A, _CPT_AUD_CONFIG_B) > +#define _VLV_AUD_CONFIG_A (VLV_DISPLAY_BASE + 0x62000) > +#define _VLV_AUD_CONFIG_B (VLV_DISPLAY_BASE + 0x62100) > +#define VLV_AUD_CFG(pipe) _MMIO_PIPE(pipe, _VLV_AUD_CONFIG_A, _VLV_AUD_CONFIG_B) > + > +#define AUD_CONFIG_N_VALUE_INDEX (1 << 29) > +#define AUD_CONFIG_N_PROG_ENABLE (1 << 28) > +#define AUD_CONFIG_UPPER_N_SHIFT 20 > +#define AUD_CONFIG_UPPER_N_MASK (0xff << 20) > +#define AUD_CONFIG_LOWER_N_SHIFT 4 > +#define AUD_CONFIG_LOWER_N_MASK (0xfff << 4) > +#define AUD_CONFIG_N_MASK (AUD_CONFIG_UPPER_N_MASK | AUD_CONFIG_LOWER_N_MASK) > +#define AUD_CONFIG_N(n) \ > + (((((n) >> 12) & 0xff) << AUD_CONFIG_UPPER_N_SHIFT) | \ > + (((n) & 0xfff) << AUD_CONFIG_LOWER_N_SHIFT)) > +#define AUD_CONFIG_PIXEL_CLOCK_HDMI_SHIFT 16 > +#define AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK (0xf << 16) > +#define AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 (0 << 16) > +#define AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 (1 << 16) > +#define AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 (2 << 16) > +#define AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 (3 << 16) > +#define AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 (4 << 16) > +#define AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 (5 << 16) > +#define AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 (6 << 16) > +#define AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 (7 << 16) > +#define AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 (8 << 16) > +#define AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 (9 << 16) > +#define AUD_CONFIG_PIXEL_CLOCK_HDMI_296703 (10 << 16) > +#define AUD_CONFIG_PIXEL_CLOCK_HDMI_297000 (11 << 16) > +#define AUD_CONFIG_PIXEL_CLOCK_HDMI_593407 (12 << 16) > +#define AUD_CONFIG_PIXEL_CLOCK_HDMI_594000 (13 << 16) > +#define AUD_CONFIG_DISABLE_NCTS (1 << 3) > + > +#define _HSW_AUD_CONFIG_A 0x65000 > +#define _HSW_AUD_CONFIG_B 0x65100 > +#define HSW_AUD_CFG(trans) _MMIO_TRANS(trans, _HSW_AUD_CONFIG_A, _HSW_AUD_CONFIG_B) > + > +#define _HSW_AUD_MISC_CTRL_A 0x65010 > +#define _HSW_AUD_MISC_CTRL_B 0x65110 > +#define HSW_AUD_MISC_CTRL(trans) _MMIO_TRANS(trans, _HSW_AUD_MISC_CTRL_A, _HSW_AUD_MISC_CTRL_B) > + > +#define _HSW_AUD_M_CTS_ENABLE_A 0x65028 > +#define _HSW_AUD_M_CTS_ENABLE_B 0x65128 > +#define HSW_AUD_M_CTS_ENABLE(trans) _MMIO_TRANS(trans, _HSW_AUD_M_CTS_ENABLE_A, _HSW_AUD_M_CTS_ENABLE_B) > +#define AUD_M_CTS_M_VALUE_INDEX (1 << 21) > +#define AUD_M_CTS_M_PROG_ENABLE (1 << 20) > +#define AUD_CONFIG_M_MASK 0xfffff > + > +#define _HSW_AUD_DIP_ELD_CTRL_ST_A 0x650b4 > +#define _HSW_AUD_DIP_ELD_CTRL_ST_B 0x651b4 > +#define HSW_AUD_DIP_ELD_CTRL(trans) _MMIO_TRANS(trans, _HSW_AUD_DIP_ELD_CTRL_ST_A, _HSW_AUD_DIP_ELD_CTRL_ST_B) > + > +/* Audio Digital Converter */ > +#define _HSW_AUD_DIG_CNVT_1 0x65080 > +#define _HSW_AUD_DIG_CNVT_2 0x65180 > +#define AUD_DIG_CNVT(trans) _MMIO_TRANS(trans, _HSW_AUD_DIG_CNVT_1, _HSW_AUD_DIG_CNVT_2) > +#define DIP_PORT_SEL_MASK 0x3 > + > +#define _HSW_AUD_EDID_DATA_A 0x65050 > +#define _HSW_AUD_EDID_DATA_B 0x65150 > +#define HSW_AUD_EDID_DATA(trans) _MMIO_TRANS(trans, _HSW_AUD_EDID_DATA_A, _HSW_AUD_EDID_DATA_B) > + > +#define HSW_AUD_PIPE_CONV_CFG _MMIO(0x6507c) > +#define HSW_AUD_PIN_ELD_CP_VLD _MMIO(0x650c0) > +#define AUDIO_INACTIVE(trans) ((1 << 3) << ((trans) * 4)) > +#define AUDIO_OUTPUT_ENABLE(trans) ((1 << 2) << ((trans) * 4)) > +#define AUDIO_CP_READY(trans) ((1 << 1) << ((trans) * 4)) > +#define AUDIO_ELD_VALID(trans) ((1 << 0) << ((trans) * 4)) > + > +#define _AUD_TCA_DP_2DOT0_CTRL 0x650bc > +#define _AUD_TCB_DP_2DOT0_CTRL 0x651bc > +#define AUD_DP_2DOT0_CTRL(trans) _MMIO_TRANS(trans, _AUD_TCA_DP_2DOT0_CTRL, _AUD_TCB_DP_2DOT0_CTRL) > +#define AUD_ENABLE_SDP_SPLIT REG_BIT(31) > + > +#define HSW_AUD_CHICKENBIT _MMIO(0x65f10) > +#define SKL_AUD_CODEC_WAKE_SIGNAL (1 << 15) > + > +#define AUD_FREQ_CNTRL _MMIO(0x65900) > +#define AUD_PIN_BUF_CTL _MMIO(0x48414) > +#define AUD_PIN_BUF_ENABLE REG_BIT(31) > + > +#define AUD_TS_CDCLK_M _MMIO(0x65ea0) > +#define AUD_TS_CDCLK_M_EN REG_BIT(31) > +#define AUD_TS_CDCLK_N _MMIO(0x65ea4) > + > +/* Display Audio Config Reg */ > +#define AUD_CONFIG_BE _MMIO(0x65ef0) > +#define HBLANK_EARLY_ENABLE_ICL(pipe) (0x1 << (20 - (pipe))) > +#define HBLANK_EARLY_ENABLE_TGL(pipe) (0x1 << (24 + (pipe))) > +#define HBLANK_START_COUNT_MASK(pipe) (0x7 << (3 + ((pipe) * 6))) > +#define HBLANK_START_COUNT(pipe, val) (((val) & 0x7) << (3 + ((pipe)) * 6)) > +#define NUMBER_SAMPLES_PER_LINE_MASK(pipe) (0x3 << ((pipe) * 6)) > +#define NUMBER_SAMPLES_PER_LINE(pipe, val) (((val) & 0x3) << ((pipe) * 6)) > + > +#define HBLANK_START_COUNT_8 0 > +#define HBLANK_START_COUNT_16 1 > +#define HBLANK_START_COUNT_32 2 > +#define HBLANK_START_COUNT_64 3 > +#define HBLANK_START_COUNT_96 4 > +#define HBLANK_START_COUNT_128 5 > + > +#endif /* __INTEL_AUDIO_REGS_H__ */ > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c > index 915e8e3e8f38..c08e5407e170 100644 > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > @@ -32,6 +32,7 @@ > > #include "i915_drv.h" > #include "intel_audio.h" > +#include "intel_audio_regs.h" > #include "intel_backlight.h" > #include "intel_combo_phy.h" > #include "intel_combo_phy_regs.h" > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 0a5064e32284..672b1cdc06b9 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -6831,163 +6831,12 @@ > (((reg) & GEN7_L3CDERRST1_SUBBANK_MASK) >> 8) > #define GEN7_L3CDERRST1_ENABLE (1 << 7) > > -/* Audio */ > -#define G4X_AUD_VID_DID _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x62020) > -#define INTEL_AUDIO_DEVCL 0x808629FB > -#define INTEL_AUDIO_DEVBLC 0x80862801 > -#define INTEL_AUDIO_DEVCTG 0x80862802 > - > -#define G4X_AUD_CNTL_ST _MMIO(0x620B4) > -#define G4X_ELDV_DEVCL_DEVBLC (1 << 13) > -#define G4X_ELDV_DEVCTG (1 << 14) > -#define G4X_ELD_ADDR_MASK (0xf << 5) > -#define G4X_ELD_ACK (1 << 4) > -#define G4X_HDMIW_HDMIEDID _MMIO(0x6210C) > - > -#define _IBX_HDMIW_HDMIEDID_A 0xE2050 > -#define _IBX_HDMIW_HDMIEDID_B 0xE2150 > -#define IBX_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _IBX_HDMIW_HDMIEDID_A, \ > - _IBX_HDMIW_HDMIEDID_B) > -#define _IBX_AUD_CNTL_ST_A 0xE20B4 > -#define _IBX_AUD_CNTL_ST_B 0xE21B4 > -#define IBX_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _IBX_AUD_CNTL_ST_A, \ > - _IBX_AUD_CNTL_ST_B) > -#define IBX_ELD_BUFFER_SIZE_MASK (0x1f << 10) > -#define IBX_ELD_ADDRESS_MASK (0x1f << 5) > -#define IBX_ELD_ACK (1 << 4) > -#define IBX_AUD_CNTL_ST2 _MMIO(0xE20C0) > -#define IBX_CP_READY(port) ((1 << 1) << (((port) - 1) * 4)) > -#define IBX_ELD_VALID(port) ((1 << 0) << (((port) - 1) * 4)) > - > -#define _CPT_HDMIW_HDMIEDID_A 0xE5050 > -#define _CPT_HDMIW_HDMIEDID_B 0xE5150 > -#define CPT_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _CPT_HDMIW_HDMIEDID_A, _CPT_HDMIW_HDMIEDID_B) > -#define _CPT_AUD_CNTL_ST_A 0xE50B4 > -#define _CPT_AUD_CNTL_ST_B 0xE51B4 > -#define CPT_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _CPT_AUD_CNTL_ST_A, _CPT_AUD_CNTL_ST_B) > -#define CPT_AUD_CNTRL_ST2 _MMIO(0xE50C0) > - > -#define _VLV_HDMIW_HDMIEDID_A (VLV_DISPLAY_BASE + 0x62050) > -#define _VLV_HDMIW_HDMIEDID_B (VLV_DISPLAY_BASE + 0x62150) > -#define VLV_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _VLV_HDMIW_HDMIEDID_A, _VLV_HDMIW_HDMIEDID_B) > -#define _VLV_AUD_CNTL_ST_A (VLV_DISPLAY_BASE + 0x620B4) > -#define _VLV_AUD_CNTL_ST_B (VLV_DISPLAY_BASE + 0x621B4) > -#define VLV_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _VLV_AUD_CNTL_ST_A, _VLV_AUD_CNTL_ST_B) > -#define VLV_AUD_CNTL_ST2 _MMIO(VLV_DISPLAY_BASE + 0x620C0) > - > /* These are the 4 32-bit write offset registers for each stream > * output buffer. It determines the offset from the > * 3DSTATE_SO_BUFFERs that the next streamed vertex output goes to. > */ > #define GEN7_SO_WRITE_OFFSET(n) _MMIO(0x5280 + (n) * 4) > > -#define _IBX_AUD_CONFIG_A 0xe2000 > -#define _IBX_AUD_CONFIG_B 0xe2100 > -#define IBX_AUD_CFG(pipe) _MMIO_PIPE(pipe, _IBX_AUD_CONFIG_A, _IBX_AUD_CONFIG_B) > -#define _CPT_AUD_CONFIG_A 0xe5000 > -#define _CPT_AUD_CONFIG_B 0xe5100 > -#define CPT_AUD_CFG(pipe) _MMIO_PIPE(pipe, _CPT_AUD_CONFIG_A, _CPT_AUD_CONFIG_B) > -#define _VLV_AUD_CONFIG_A (VLV_DISPLAY_BASE + 0x62000) > -#define _VLV_AUD_CONFIG_B (VLV_DISPLAY_BASE + 0x62100) > -#define VLV_AUD_CFG(pipe) _MMIO_PIPE(pipe, _VLV_AUD_CONFIG_A, _VLV_AUD_CONFIG_B) > - > -#define AUD_CONFIG_N_VALUE_INDEX (1 << 29) > -#define AUD_CONFIG_N_PROG_ENABLE (1 << 28) > -#define AUD_CONFIG_UPPER_N_SHIFT 20 > -#define AUD_CONFIG_UPPER_N_MASK (0xff << 20) > -#define AUD_CONFIG_LOWER_N_SHIFT 4 > -#define AUD_CONFIG_LOWER_N_MASK (0xfff << 4) > -#define AUD_CONFIG_N_MASK (AUD_CONFIG_UPPER_N_MASK | AUD_CONFIG_LOWER_N_MASK) > -#define AUD_CONFIG_N(n) \ > - (((((n) >> 12) & 0xff) << AUD_CONFIG_UPPER_N_SHIFT) | \ > - (((n) & 0xfff) << AUD_CONFIG_LOWER_N_SHIFT)) > -#define AUD_CONFIG_PIXEL_CLOCK_HDMI_SHIFT 16 > -#define AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK (0xf << 16) > -#define AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 (0 << 16) > -#define AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 (1 << 16) > -#define AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 (2 << 16) > -#define AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 (3 << 16) > -#define AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 (4 << 16) > -#define AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 (5 << 16) > -#define AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 (6 << 16) > -#define AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 (7 << 16) > -#define AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 (8 << 16) > -#define AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 (9 << 16) > -#define AUD_CONFIG_PIXEL_CLOCK_HDMI_296703 (10 << 16) > -#define AUD_CONFIG_PIXEL_CLOCK_HDMI_297000 (11 << 16) > -#define AUD_CONFIG_PIXEL_CLOCK_HDMI_593407 (12 << 16) > -#define AUD_CONFIG_PIXEL_CLOCK_HDMI_594000 (13 << 16) > -#define AUD_CONFIG_DISABLE_NCTS (1 << 3) > - > -/* HSW Audio */ > -#define _HSW_AUD_CONFIG_A 0x65000 > -#define _HSW_AUD_CONFIG_B 0x65100 > -#define HSW_AUD_CFG(trans) _MMIO_TRANS(trans, _HSW_AUD_CONFIG_A, _HSW_AUD_CONFIG_B) > - > -#define _HSW_AUD_MISC_CTRL_A 0x65010 > -#define _HSW_AUD_MISC_CTRL_B 0x65110 > -#define HSW_AUD_MISC_CTRL(trans) _MMIO_TRANS(trans, _HSW_AUD_MISC_CTRL_A, _HSW_AUD_MISC_CTRL_B) > - > -#define _HSW_AUD_M_CTS_ENABLE_A 0x65028 > -#define _HSW_AUD_M_CTS_ENABLE_B 0x65128 > -#define HSW_AUD_M_CTS_ENABLE(trans) _MMIO_TRANS(trans, _HSW_AUD_M_CTS_ENABLE_A, _HSW_AUD_M_CTS_ENABLE_B) > -#define AUD_M_CTS_M_VALUE_INDEX (1 << 21) > -#define AUD_M_CTS_M_PROG_ENABLE (1 << 20) > -#define AUD_CONFIG_M_MASK 0xfffff > - > -#define _HSW_AUD_DIP_ELD_CTRL_ST_A 0x650b4 > -#define _HSW_AUD_DIP_ELD_CTRL_ST_B 0x651b4 > -#define HSW_AUD_DIP_ELD_CTRL(trans) _MMIO_TRANS(trans, _HSW_AUD_DIP_ELD_CTRL_ST_A, _HSW_AUD_DIP_ELD_CTRL_ST_B) > - > -/* Audio Digital Converter */ > -#define _HSW_AUD_DIG_CNVT_1 0x65080 > -#define _HSW_AUD_DIG_CNVT_2 0x65180 > -#define AUD_DIG_CNVT(trans) _MMIO_TRANS(trans, _HSW_AUD_DIG_CNVT_1, _HSW_AUD_DIG_CNVT_2) > -#define DIP_PORT_SEL_MASK 0x3 > - > -#define _HSW_AUD_EDID_DATA_A 0x65050 > -#define _HSW_AUD_EDID_DATA_B 0x65150 > -#define HSW_AUD_EDID_DATA(trans) _MMIO_TRANS(trans, _HSW_AUD_EDID_DATA_A, _HSW_AUD_EDID_DATA_B) > - > -#define HSW_AUD_PIPE_CONV_CFG _MMIO(0x6507c) > -#define HSW_AUD_PIN_ELD_CP_VLD _MMIO(0x650c0) > -#define AUDIO_INACTIVE(trans) ((1 << 3) << ((trans) * 4)) > -#define AUDIO_OUTPUT_ENABLE(trans) ((1 << 2) << ((trans) * 4)) > -#define AUDIO_CP_READY(trans) ((1 << 1) << ((trans) * 4)) > -#define AUDIO_ELD_VALID(trans) ((1 << 0) << ((trans) * 4)) > - > -#define _AUD_TCA_DP_2DOT0_CTRL 0x650bc > -#define _AUD_TCB_DP_2DOT0_CTRL 0x651bc > -#define AUD_DP_2DOT0_CTRL(trans) _MMIO_TRANS(trans, _AUD_TCA_DP_2DOT0_CTRL, _AUD_TCB_DP_2DOT0_CTRL) > -#define AUD_ENABLE_SDP_SPLIT REG_BIT(31) > - > -#define HSW_AUD_CHICKENBIT _MMIO(0x65f10) > -#define SKL_AUD_CODEC_WAKE_SIGNAL (1 << 15) > - > -#define AUD_FREQ_CNTRL _MMIO(0x65900) > -#define AUD_PIN_BUF_CTL _MMIO(0x48414) > -#define AUD_PIN_BUF_ENABLE REG_BIT(31) > - > -#define AUD_TS_CDCLK_M _MMIO(0x65ea0) > -#define AUD_TS_CDCLK_M_EN REG_BIT(31) > -#define AUD_TS_CDCLK_N _MMIO(0x65ea4) > - > -/* Display Audio Config Reg */ > -#define AUD_CONFIG_BE _MMIO(0x65ef0) > -#define HBLANK_EARLY_ENABLE_ICL(pipe) (0x1 << (20 - (pipe))) > -#define HBLANK_EARLY_ENABLE_TGL(pipe) (0x1 << (24 + (pipe))) > -#define HBLANK_START_COUNT_MASK(pipe) (0x7 << (3 + ((pipe) * 6))) > -#define HBLANK_START_COUNT(pipe, val) (((val) & 0x7) << (3 + ((pipe)) * 6)) > -#define NUMBER_SAMPLES_PER_LINE_MASK(pipe) (0x3 << ((pipe) * 6)) > -#define NUMBER_SAMPLES_PER_LINE(pipe, val) (((val) & 0x3) << ((pipe) * 6)) > - > -#define HBLANK_START_COUNT_8 0 > -#define HBLANK_START_COUNT_16 1 > -#define HBLANK_START_COUNT_32 2 > -#define HBLANK_START_COUNT_64 3 > -#define HBLANK_START_COUNT_96 4 > -#define HBLANK_START_COUNT_128 5 > - > /* > * HSW - ICL power wells > * > diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c > index 72dac1718f3e..157e166672d7 100644 > --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c > +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c > @@ -3,10 +3,12 @@ > * Copyright © 2020 Intel Corporation > */ > > +#include "display/intel_audio_regs.h" > #include "display/intel_dmc_regs.h" > #include "display/vlv_dsi_pll_regs.h" > #include "gt/intel_gt_regs.h" > #include "gvt/gvt.h" > + > #include "i915_drv.h" > #include "i915_pvinfo.h" > #include "i915_reg.h" > -- > 2.30.2 > -- Matt Roper Graphics Software Engineer VTT-OSGC Platform Enablement Intel Corporation ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/regs: split out intel audio register definitions 2022-06-02 22:53 ` [Intel-gfx] [PATCH] " Matt Roper @ 2022-06-03 8:40 ` Jani Nikula 0 siblings, 0 replies; 7+ messages in thread From: Jani Nikula @ 2022-06-03 8:40 UTC (permalink / raw) To: Matt Roper; +Cc: intel-gfx On Thu, 02 Jun 2022, Matt Roper <matthew.d.roper@intel.com> wrote: > On Thu, Jun 02, 2022 at 12:45:42PM +0300, Jani Nikula wrote: >> Split out audio registers to a header of its own to reduce the size of >> i915_reg.h. >> >> TODO: Remove direct audio register access from intel_ddi.c. However, >> unification of audio get config is cumbersome due to the audio enable >> bit being in the DP or HDMI registers on older platforms. >> >> Signed-off-by: Jani Nikula <jani.nikula@intel.com> > > Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Thanks, pushed to drm-intel-next. BR, Jani. > >> --- >> drivers/gpu/drm/i915/display/intel_audio.c | 1 + >> .../gpu/drm/i915/display/intel_audio_regs.h | 160 ++++++++++++++++++ >> drivers/gpu/drm/i915/display/intel_ddi.c | 1 + >> drivers/gpu/drm/i915/i915_reg.h | 151 ----------------- >> drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 2 + >> 5 files changed, 164 insertions(+), 151 deletions(-) >> create mode 100644 drivers/gpu/drm/i915/display/intel_audio_regs.h >> >> diff --git a/drivers/gpu/drm/i915/display/intel_audio.c b/drivers/gpu/drm/i915/display/intel_audio.c >> index f0f0dfce27ce..6c9ee905f132 100644 >> --- a/drivers/gpu/drm/i915/display/intel_audio.c >> +++ b/drivers/gpu/drm/i915/display/intel_audio.c >> @@ -30,6 +30,7 @@ >> #include "i915_drv.h" >> #include "intel_atomic.h" >> #include "intel_audio.h" >> +#include "intel_audio_regs.h" >> #include "intel_cdclk.h" >> #include "intel_crtc.h" >> #include "intel_de.h" >> diff --git a/drivers/gpu/drm/i915/display/intel_audio_regs.h b/drivers/gpu/drm/i915/display/intel_audio_regs.h >> new file mode 100644 >> index 000000000000..d1e5844e3484 >> --- /dev/null >> +++ b/drivers/gpu/drm/i915/display/intel_audio_regs.h >> @@ -0,0 +1,160 @@ >> +/* SPDX-License-Identifier: MIT */ >> +/* >> + * Copyright © 2022 Intel Corporation >> + */ >> + >> +#ifndef __INTEL_AUDIO_REGS_H__ >> +#define __INTEL_AUDIO_REGS_H__ >> + >> +#include "i915_reg_defs.h" >> + >> +#define G4X_AUD_VID_DID _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x62020) >> +#define INTEL_AUDIO_DEVCL 0x808629FB >> +#define INTEL_AUDIO_DEVBLC 0x80862801 >> +#define INTEL_AUDIO_DEVCTG 0x80862802 >> + >> +#define G4X_AUD_CNTL_ST _MMIO(0x620B4) >> +#define G4X_ELDV_DEVCL_DEVBLC (1 << 13) >> +#define G4X_ELDV_DEVCTG (1 << 14) >> +#define G4X_ELD_ADDR_MASK (0xf << 5) >> +#define G4X_ELD_ACK (1 << 4) >> +#define G4X_HDMIW_HDMIEDID _MMIO(0x6210C) >> + >> +#define _IBX_HDMIW_HDMIEDID_A 0xE2050 >> +#define _IBX_HDMIW_HDMIEDID_B 0xE2150 >> +#define IBX_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _IBX_HDMIW_HDMIEDID_A, \ >> + _IBX_HDMIW_HDMIEDID_B) >> +#define _IBX_AUD_CNTL_ST_A 0xE20B4 >> +#define _IBX_AUD_CNTL_ST_B 0xE21B4 >> +#define IBX_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _IBX_AUD_CNTL_ST_A, \ >> + _IBX_AUD_CNTL_ST_B) >> +#define IBX_ELD_BUFFER_SIZE_MASK (0x1f << 10) >> +#define IBX_ELD_ADDRESS_MASK (0x1f << 5) >> +#define IBX_ELD_ACK (1 << 4) >> +#define IBX_AUD_CNTL_ST2 _MMIO(0xE20C0) >> +#define IBX_CP_READY(port) ((1 << 1) << (((port) - 1) * 4)) >> +#define IBX_ELD_VALID(port) ((1 << 0) << (((port) - 1) * 4)) >> + >> +#define _CPT_HDMIW_HDMIEDID_A 0xE5050 >> +#define _CPT_HDMIW_HDMIEDID_B 0xE5150 >> +#define CPT_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _CPT_HDMIW_HDMIEDID_A, _CPT_HDMIW_HDMIEDID_B) >> +#define _CPT_AUD_CNTL_ST_A 0xE50B4 >> +#define _CPT_AUD_CNTL_ST_B 0xE51B4 >> +#define CPT_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _CPT_AUD_CNTL_ST_A, _CPT_AUD_CNTL_ST_B) >> +#define CPT_AUD_CNTRL_ST2 _MMIO(0xE50C0) >> + >> +#define _VLV_HDMIW_HDMIEDID_A (VLV_DISPLAY_BASE + 0x62050) >> +#define _VLV_HDMIW_HDMIEDID_B (VLV_DISPLAY_BASE + 0x62150) >> +#define VLV_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _VLV_HDMIW_HDMIEDID_A, _VLV_HDMIW_HDMIEDID_B) >> +#define _VLV_AUD_CNTL_ST_A (VLV_DISPLAY_BASE + 0x620B4) >> +#define _VLV_AUD_CNTL_ST_B (VLV_DISPLAY_BASE + 0x621B4) >> +#define VLV_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _VLV_AUD_CNTL_ST_A, _VLV_AUD_CNTL_ST_B) >> +#define VLV_AUD_CNTL_ST2 _MMIO(VLV_DISPLAY_BASE + 0x620C0) >> + >> +#define _IBX_AUD_CONFIG_A 0xe2000 >> +#define _IBX_AUD_CONFIG_B 0xe2100 >> +#define IBX_AUD_CFG(pipe) _MMIO_PIPE(pipe, _IBX_AUD_CONFIG_A, _IBX_AUD_CONFIG_B) >> +#define _CPT_AUD_CONFIG_A 0xe5000 >> +#define _CPT_AUD_CONFIG_B 0xe5100 >> +#define CPT_AUD_CFG(pipe) _MMIO_PIPE(pipe, _CPT_AUD_CONFIG_A, _CPT_AUD_CONFIG_B) >> +#define _VLV_AUD_CONFIG_A (VLV_DISPLAY_BASE + 0x62000) >> +#define _VLV_AUD_CONFIG_B (VLV_DISPLAY_BASE + 0x62100) >> +#define VLV_AUD_CFG(pipe) _MMIO_PIPE(pipe, _VLV_AUD_CONFIG_A, _VLV_AUD_CONFIG_B) >> + >> +#define AUD_CONFIG_N_VALUE_INDEX (1 << 29) >> +#define AUD_CONFIG_N_PROG_ENABLE (1 << 28) >> +#define AUD_CONFIG_UPPER_N_SHIFT 20 >> +#define AUD_CONFIG_UPPER_N_MASK (0xff << 20) >> +#define AUD_CONFIG_LOWER_N_SHIFT 4 >> +#define AUD_CONFIG_LOWER_N_MASK (0xfff << 4) >> +#define AUD_CONFIG_N_MASK (AUD_CONFIG_UPPER_N_MASK | AUD_CONFIG_LOWER_N_MASK) >> +#define AUD_CONFIG_N(n) \ >> + (((((n) >> 12) & 0xff) << AUD_CONFIG_UPPER_N_SHIFT) | \ >> + (((n) & 0xfff) << AUD_CONFIG_LOWER_N_SHIFT)) >> +#define AUD_CONFIG_PIXEL_CLOCK_HDMI_SHIFT 16 >> +#define AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK (0xf << 16) >> +#define AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 (0 << 16) >> +#define AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 (1 << 16) >> +#define AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 (2 << 16) >> +#define AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 (3 << 16) >> +#define AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 (4 << 16) >> +#define AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 (5 << 16) >> +#define AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 (6 << 16) >> +#define AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 (7 << 16) >> +#define AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 (8 << 16) >> +#define AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 (9 << 16) >> +#define AUD_CONFIG_PIXEL_CLOCK_HDMI_296703 (10 << 16) >> +#define AUD_CONFIG_PIXEL_CLOCK_HDMI_297000 (11 << 16) >> +#define AUD_CONFIG_PIXEL_CLOCK_HDMI_593407 (12 << 16) >> +#define AUD_CONFIG_PIXEL_CLOCK_HDMI_594000 (13 << 16) >> +#define AUD_CONFIG_DISABLE_NCTS (1 << 3) >> + >> +#define _HSW_AUD_CONFIG_A 0x65000 >> +#define _HSW_AUD_CONFIG_B 0x65100 >> +#define HSW_AUD_CFG(trans) _MMIO_TRANS(trans, _HSW_AUD_CONFIG_A, _HSW_AUD_CONFIG_B) >> + >> +#define _HSW_AUD_MISC_CTRL_A 0x65010 >> +#define _HSW_AUD_MISC_CTRL_B 0x65110 >> +#define HSW_AUD_MISC_CTRL(trans) _MMIO_TRANS(trans, _HSW_AUD_MISC_CTRL_A, _HSW_AUD_MISC_CTRL_B) >> + >> +#define _HSW_AUD_M_CTS_ENABLE_A 0x65028 >> +#define _HSW_AUD_M_CTS_ENABLE_B 0x65128 >> +#define HSW_AUD_M_CTS_ENABLE(trans) _MMIO_TRANS(trans, _HSW_AUD_M_CTS_ENABLE_A, _HSW_AUD_M_CTS_ENABLE_B) >> +#define AUD_M_CTS_M_VALUE_INDEX (1 << 21) >> +#define AUD_M_CTS_M_PROG_ENABLE (1 << 20) >> +#define AUD_CONFIG_M_MASK 0xfffff >> + >> +#define _HSW_AUD_DIP_ELD_CTRL_ST_A 0x650b4 >> +#define _HSW_AUD_DIP_ELD_CTRL_ST_B 0x651b4 >> +#define HSW_AUD_DIP_ELD_CTRL(trans) _MMIO_TRANS(trans, _HSW_AUD_DIP_ELD_CTRL_ST_A, _HSW_AUD_DIP_ELD_CTRL_ST_B) >> + >> +/* Audio Digital Converter */ >> +#define _HSW_AUD_DIG_CNVT_1 0x65080 >> +#define _HSW_AUD_DIG_CNVT_2 0x65180 >> +#define AUD_DIG_CNVT(trans) _MMIO_TRANS(trans, _HSW_AUD_DIG_CNVT_1, _HSW_AUD_DIG_CNVT_2) >> +#define DIP_PORT_SEL_MASK 0x3 >> + >> +#define _HSW_AUD_EDID_DATA_A 0x65050 >> +#define _HSW_AUD_EDID_DATA_B 0x65150 >> +#define HSW_AUD_EDID_DATA(trans) _MMIO_TRANS(trans, _HSW_AUD_EDID_DATA_A, _HSW_AUD_EDID_DATA_B) >> + >> +#define HSW_AUD_PIPE_CONV_CFG _MMIO(0x6507c) >> +#define HSW_AUD_PIN_ELD_CP_VLD _MMIO(0x650c0) >> +#define AUDIO_INACTIVE(trans) ((1 << 3) << ((trans) * 4)) >> +#define AUDIO_OUTPUT_ENABLE(trans) ((1 << 2) << ((trans) * 4)) >> +#define AUDIO_CP_READY(trans) ((1 << 1) << ((trans) * 4)) >> +#define AUDIO_ELD_VALID(trans) ((1 << 0) << ((trans) * 4)) >> + >> +#define _AUD_TCA_DP_2DOT0_CTRL 0x650bc >> +#define _AUD_TCB_DP_2DOT0_CTRL 0x651bc >> +#define AUD_DP_2DOT0_CTRL(trans) _MMIO_TRANS(trans, _AUD_TCA_DP_2DOT0_CTRL, _AUD_TCB_DP_2DOT0_CTRL) >> +#define AUD_ENABLE_SDP_SPLIT REG_BIT(31) >> + >> +#define HSW_AUD_CHICKENBIT _MMIO(0x65f10) >> +#define SKL_AUD_CODEC_WAKE_SIGNAL (1 << 15) >> + >> +#define AUD_FREQ_CNTRL _MMIO(0x65900) >> +#define AUD_PIN_BUF_CTL _MMIO(0x48414) >> +#define AUD_PIN_BUF_ENABLE REG_BIT(31) >> + >> +#define AUD_TS_CDCLK_M _MMIO(0x65ea0) >> +#define AUD_TS_CDCLK_M_EN REG_BIT(31) >> +#define AUD_TS_CDCLK_N _MMIO(0x65ea4) >> + >> +/* Display Audio Config Reg */ >> +#define AUD_CONFIG_BE _MMIO(0x65ef0) >> +#define HBLANK_EARLY_ENABLE_ICL(pipe) (0x1 << (20 - (pipe))) >> +#define HBLANK_EARLY_ENABLE_TGL(pipe) (0x1 << (24 + (pipe))) >> +#define HBLANK_START_COUNT_MASK(pipe) (0x7 << (3 + ((pipe) * 6))) >> +#define HBLANK_START_COUNT(pipe, val) (((val) & 0x7) << (3 + ((pipe)) * 6)) >> +#define NUMBER_SAMPLES_PER_LINE_MASK(pipe) (0x3 << ((pipe) * 6)) >> +#define NUMBER_SAMPLES_PER_LINE(pipe, val) (((val) & 0x3) << ((pipe) * 6)) >> + >> +#define HBLANK_START_COUNT_8 0 >> +#define HBLANK_START_COUNT_16 1 >> +#define HBLANK_START_COUNT_32 2 >> +#define HBLANK_START_COUNT_64 3 >> +#define HBLANK_START_COUNT_96 4 >> +#define HBLANK_START_COUNT_128 5 >> + >> +#endif /* __INTEL_AUDIO_REGS_H__ */ >> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c >> index 915e8e3e8f38..c08e5407e170 100644 >> --- a/drivers/gpu/drm/i915/display/intel_ddi.c >> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c >> @@ -32,6 +32,7 @@ >> >> #include "i915_drv.h" >> #include "intel_audio.h" >> +#include "intel_audio_regs.h" >> #include "intel_backlight.h" >> #include "intel_combo_phy.h" >> #include "intel_combo_phy_regs.h" >> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h >> index 0a5064e32284..672b1cdc06b9 100644 >> --- a/drivers/gpu/drm/i915/i915_reg.h >> +++ b/drivers/gpu/drm/i915/i915_reg.h >> @@ -6831,163 +6831,12 @@ >> (((reg) & GEN7_L3CDERRST1_SUBBANK_MASK) >> 8) >> #define GEN7_L3CDERRST1_ENABLE (1 << 7) >> >> -/* Audio */ >> -#define G4X_AUD_VID_DID _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x62020) >> -#define INTEL_AUDIO_DEVCL 0x808629FB >> -#define INTEL_AUDIO_DEVBLC 0x80862801 >> -#define INTEL_AUDIO_DEVCTG 0x80862802 >> - >> -#define G4X_AUD_CNTL_ST _MMIO(0x620B4) >> -#define G4X_ELDV_DEVCL_DEVBLC (1 << 13) >> -#define G4X_ELDV_DEVCTG (1 << 14) >> -#define G4X_ELD_ADDR_MASK (0xf << 5) >> -#define G4X_ELD_ACK (1 << 4) >> -#define G4X_HDMIW_HDMIEDID _MMIO(0x6210C) >> - >> -#define _IBX_HDMIW_HDMIEDID_A 0xE2050 >> -#define _IBX_HDMIW_HDMIEDID_B 0xE2150 >> -#define IBX_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _IBX_HDMIW_HDMIEDID_A, \ >> - _IBX_HDMIW_HDMIEDID_B) >> -#define _IBX_AUD_CNTL_ST_A 0xE20B4 >> -#define _IBX_AUD_CNTL_ST_B 0xE21B4 >> -#define IBX_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _IBX_AUD_CNTL_ST_A, \ >> - _IBX_AUD_CNTL_ST_B) >> -#define IBX_ELD_BUFFER_SIZE_MASK (0x1f << 10) >> -#define IBX_ELD_ADDRESS_MASK (0x1f << 5) >> -#define IBX_ELD_ACK (1 << 4) >> -#define IBX_AUD_CNTL_ST2 _MMIO(0xE20C0) >> -#define IBX_CP_READY(port) ((1 << 1) << (((port) - 1) * 4)) >> -#define IBX_ELD_VALID(port) ((1 << 0) << (((port) - 1) * 4)) >> - >> -#define _CPT_HDMIW_HDMIEDID_A 0xE5050 >> -#define _CPT_HDMIW_HDMIEDID_B 0xE5150 >> -#define CPT_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _CPT_HDMIW_HDMIEDID_A, _CPT_HDMIW_HDMIEDID_B) >> -#define _CPT_AUD_CNTL_ST_A 0xE50B4 >> -#define _CPT_AUD_CNTL_ST_B 0xE51B4 >> -#define CPT_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _CPT_AUD_CNTL_ST_A, _CPT_AUD_CNTL_ST_B) >> -#define CPT_AUD_CNTRL_ST2 _MMIO(0xE50C0) >> - >> -#define _VLV_HDMIW_HDMIEDID_A (VLV_DISPLAY_BASE + 0x62050) >> -#define _VLV_HDMIW_HDMIEDID_B (VLV_DISPLAY_BASE + 0x62150) >> -#define VLV_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _VLV_HDMIW_HDMIEDID_A, _VLV_HDMIW_HDMIEDID_B) >> -#define _VLV_AUD_CNTL_ST_A (VLV_DISPLAY_BASE + 0x620B4) >> -#define _VLV_AUD_CNTL_ST_B (VLV_DISPLAY_BASE + 0x621B4) >> -#define VLV_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _VLV_AUD_CNTL_ST_A, _VLV_AUD_CNTL_ST_B) >> -#define VLV_AUD_CNTL_ST2 _MMIO(VLV_DISPLAY_BASE + 0x620C0) >> - >> /* These are the 4 32-bit write offset registers for each stream >> * output buffer. It determines the offset from the >> * 3DSTATE_SO_BUFFERs that the next streamed vertex output goes to. >> */ >> #define GEN7_SO_WRITE_OFFSET(n) _MMIO(0x5280 + (n) * 4) >> >> -#define _IBX_AUD_CONFIG_A 0xe2000 >> -#define _IBX_AUD_CONFIG_B 0xe2100 >> -#define IBX_AUD_CFG(pipe) _MMIO_PIPE(pipe, _IBX_AUD_CONFIG_A, _IBX_AUD_CONFIG_B) >> -#define _CPT_AUD_CONFIG_A 0xe5000 >> -#define _CPT_AUD_CONFIG_B 0xe5100 >> -#define CPT_AUD_CFG(pipe) _MMIO_PIPE(pipe, _CPT_AUD_CONFIG_A, _CPT_AUD_CONFIG_B) >> -#define _VLV_AUD_CONFIG_A (VLV_DISPLAY_BASE + 0x62000) >> -#define _VLV_AUD_CONFIG_B (VLV_DISPLAY_BASE + 0x62100) >> -#define VLV_AUD_CFG(pipe) _MMIO_PIPE(pipe, _VLV_AUD_CONFIG_A, _VLV_AUD_CONFIG_B) >> - >> -#define AUD_CONFIG_N_VALUE_INDEX (1 << 29) >> -#define AUD_CONFIG_N_PROG_ENABLE (1 << 28) >> -#define AUD_CONFIG_UPPER_N_SHIFT 20 >> -#define AUD_CONFIG_UPPER_N_MASK (0xff << 20) >> -#define AUD_CONFIG_LOWER_N_SHIFT 4 >> -#define AUD_CONFIG_LOWER_N_MASK (0xfff << 4) >> -#define AUD_CONFIG_N_MASK (AUD_CONFIG_UPPER_N_MASK | AUD_CONFIG_LOWER_N_MASK) >> -#define AUD_CONFIG_N(n) \ >> - (((((n) >> 12) & 0xff) << AUD_CONFIG_UPPER_N_SHIFT) | \ >> - (((n) & 0xfff) << AUD_CONFIG_LOWER_N_SHIFT)) >> -#define AUD_CONFIG_PIXEL_CLOCK_HDMI_SHIFT 16 >> -#define AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK (0xf << 16) >> -#define AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 (0 << 16) >> -#define AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 (1 << 16) >> -#define AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 (2 << 16) >> -#define AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 (3 << 16) >> -#define AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 (4 << 16) >> -#define AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 (5 << 16) >> -#define AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 (6 << 16) >> -#define AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 (7 << 16) >> -#define AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 (8 << 16) >> -#define AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 (9 << 16) >> -#define AUD_CONFIG_PIXEL_CLOCK_HDMI_296703 (10 << 16) >> -#define AUD_CONFIG_PIXEL_CLOCK_HDMI_297000 (11 << 16) >> -#define AUD_CONFIG_PIXEL_CLOCK_HDMI_593407 (12 << 16) >> -#define AUD_CONFIG_PIXEL_CLOCK_HDMI_594000 (13 << 16) >> -#define AUD_CONFIG_DISABLE_NCTS (1 << 3) >> - >> -/* HSW Audio */ >> -#define _HSW_AUD_CONFIG_A 0x65000 >> -#define _HSW_AUD_CONFIG_B 0x65100 >> -#define HSW_AUD_CFG(trans) _MMIO_TRANS(trans, _HSW_AUD_CONFIG_A, _HSW_AUD_CONFIG_B) >> - >> -#define _HSW_AUD_MISC_CTRL_A 0x65010 >> -#define _HSW_AUD_MISC_CTRL_B 0x65110 >> -#define HSW_AUD_MISC_CTRL(trans) _MMIO_TRANS(trans, _HSW_AUD_MISC_CTRL_A, _HSW_AUD_MISC_CTRL_B) >> - >> -#define _HSW_AUD_M_CTS_ENABLE_A 0x65028 >> -#define _HSW_AUD_M_CTS_ENABLE_B 0x65128 >> -#define HSW_AUD_M_CTS_ENABLE(trans) _MMIO_TRANS(trans, _HSW_AUD_M_CTS_ENABLE_A, _HSW_AUD_M_CTS_ENABLE_B) >> -#define AUD_M_CTS_M_VALUE_INDEX (1 << 21) >> -#define AUD_M_CTS_M_PROG_ENABLE (1 << 20) >> -#define AUD_CONFIG_M_MASK 0xfffff >> - >> -#define _HSW_AUD_DIP_ELD_CTRL_ST_A 0x650b4 >> -#define _HSW_AUD_DIP_ELD_CTRL_ST_B 0x651b4 >> -#define HSW_AUD_DIP_ELD_CTRL(trans) _MMIO_TRANS(trans, _HSW_AUD_DIP_ELD_CTRL_ST_A, _HSW_AUD_DIP_ELD_CTRL_ST_B) >> - >> -/* Audio Digital Converter */ >> -#define _HSW_AUD_DIG_CNVT_1 0x65080 >> -#define _HSW_AUD_DIG_CNVT_2 0x65180 >> -#define AUD_DIG_CNVT(trans) _MMIO_TRANS(trans, _HSW_AUD_DIG_CNVT_1, _HSW_AUD_DIG_CNVT_2) >> -#define DIP_PORT_SEL_MASK 0x3 >> - >> -#define _HSW_AUD_EDID_DATA_A 0x65050 >> -#define _HSW_AUD_EDID_DATA_B 0x65150 >> -#define HSW_AUD_EDID_DATA(trans) _MMIO_TRANS(trans, _HSW_AUD_EDID_DATA_A, _HSW_AUD_EDID_DATA_B) >> - >> -#define HSW_AUD_PIPE_CONV_CFG _MMIO(0x6507c) >> -#define HSW_AUD_PIN_ELD_CP_VLD _MMIO(0x650c0) >> -#define AUDIO_INACTIVE(trans) ((1 << 3) << ((trans) * 4)) >> -#define AUDIO_OUTPUT_ENABLE(trans) ((1 << 2) << ((trans) * 4)) >> -#define AUDIO_CP_READY(trans) ((1 << 1) << ((trans) * 4)) >> -#define AUDIO_ELD_VALID(trans) ((1 << 0) << ((trans) * 4)) >> - >> -#define _AUD_TCA_DP_2DOT0_CTRL 0x650bc >> -#define _AUD_TCB_DP_2DOT0_CTRL 0x651bc >> -#define AUD_DP_2DOT0_CTRL(trans) _MMIO_TRANS(trans, _AUD_TCA_DP_2DOT0_CTRL, _AUD_TCB_DP_2DOT0_CTRL) >> -#define AUD_ENABLE_SDP_SPLIT REG_BIT(31) >> - >> -#define HSW_AUD_CHICKENBIT _MMIO(0x65f10) >> -#define SKL_AUD_CODEC_WAKE_SIGNAL (1 << 15) >> - >> -#define AUD_FREQ_CNTRL _MMIO(0x65900) >> -#define AUD_PIN_BUF_CTL _MMIO(0x48414) >> -#define AUD_PIN_BUF_ENABLE REG_BIT(31) >> - >> -#define AUD_TS_CDCLK_M _MMIO(0x65ea0) >> -#define AUD_TS_CDCLK_M_EN REG_BIT(31) >> -#define AUD_TS_CDCLK_N _MMIO(0x65ea4) >> - >> -/* Display Audio Config Reg */ >> -#define AUD_CONFIG_BE _MMIO(0x65ef0) >> -#define HBLANK_EARLY_ENABLE_ICL(pipe) (0x1 << (20 - (pipe))) >> -#define HBLANK_EARLY_ENABLE_TGL(pipe) (0x1 << (24 + (pipe))) >> -#define HBLANK_START_COUNT_MASK(pipe) (0x7 << (3 + ((pipe) * 6))) >> -#define HBLANK_START_COUNT(pipe, val) (((val) & 0x7) << (3 + ((pipe)) * 6)) >> -#define NUMBER_SAMPLES_PER_LINE_MASK(pipe) (0x3 << ((pipe) * 6)) >> -#define NUMBER_SAMPLES_PER_LINE(pipe, val) (((val) & 0x3) << ((pipe) * 6)) >> - >> -#define HBLANK_START_COUNT_8 0 >> -#define HBLANK_START_COUNT_16 1 >> -#define HBLANK_START_COUNT_32 2 >> -#define HBLANK_START_COUNT_64 3 >> -#define HBLANK_START_COUNT_96 4 >> -#define HBLANK_START_COUNT_128 5 >> - >> /* >> * HSW - ICL power wells >> * >> diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c >> index 72dac1718f3e..157e166672d7 100644 >> --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c >> +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c >> @@ -3,10 +3,12 @@ >> * Copyright © 2020 Intel Corporation >> */ >> >> +#include "display/intel_audio_regs.h" >> #include "display/intel_dmc_regs.h" >> #include "display/vlv_dsi_pll_regs.h" >> #include "gt/intel_gt_regs.h" >> #include "gvt/gvt.h" >> + >> #include "i915_drv.h" >> #include "i915_pvinfo.h" >> #include "i915_reg.h" >> -- >> 2.30.2 >> -- Jani Nikula, Intel Open Source Graphics Center ^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2022-06-03 8:40 UTC | newest] Thread overview: 7+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2022-06-02 9:45 [Intel-gfx] [PATCH] drm/i915/regs: split out intel audio register definitions Jani Nikula 2022-06-02 10:19 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork 2022-06-02 10:19 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork 2022-06-02 10:42 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2022-06-02 13:00 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork 2022-06-02 22:53 ` [Intel-gfx] [PATCH] " Matt Roper 2022-06-03 8:40 ` Jani Nikula
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