From: Robert Beckett <bob.beckett@collabora.com>
To: dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org,
Jani Nikula <jani.nikula@linux.intel.com>,
Joonas Lahtinen <joonas.lahtinen@linux.intel.com>,
Rodrigo Vivi <rodrigo.vivi@intel.com>,
Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>,
David Airlie <airlied@linux.ie>, Daniel Vetter <daniel@ffwll.ch>
Cc: "Thomas Hellström" <thomas.hellstrom@linux.intel.com>,
kernel@collabora.com, "Matthew Auld" <matthew.auld@intel.com>,
linux-kernel@vger.kernel.org
Subject: [Intel-gfx] [PATCH v2 4/8] drm/i915: allow volatile buffers to use ttm pool allocator
Date: Wed, 8 Jun 2022 20:51:27 +0000 [thread overview]
Message-ID: <20220608205132.438596-5-bob.beckett@collabora.com> (raw)
In-Reply-To: <20220608205132.438596-1-bob.beckett@collabora.com>
Internal/volatile buffers should not be shmem backed.
If a volatile buffer is requested, allow ttm to use the pool allocator
to provide volatile pages as backing.
Fix i915_ttm_shrink to handle !is_shmem volatile buffers by purging.
Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
---
drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
index 27d59639177f..8edce04a0509 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
@@ -309,7 +309,8 @@ static struct ttm_tt *i915_ttm_tt_create(struct ttm_buffer_object *bo,
page_flags |= TTM_TT_FLAG_ZERO_ALLOC;
caching = i915_ttm_select_tt_caching(obj);
- if (i915_gem_object_is_shrinkable(obj) && caching == ttm_cached) {
+ if (i915_gem_object_is_shrinkable(obj) && caching == ttm_cached &&
+ !i915_gem_object_is_volatile(obj)) {
page_flags |= TTM_TT_FLAG_EXTERNAL |
TTM_TT_FLAG_EXTERNAL_MAPPABLE;
i915_tt->is_shmem = true;
@@ -531,9 +532,9 @@ static int i915_ttm_shrink(struct drm_i915_gem_object *obj, unsigned int flags)
if (!bo->ttm || bo->resource->mem_type != TTM_PL_SYSTEM)
return 0;
- GEM_BUG_ON(!i915_tt->is_shmem);
+ GEM_BUG_ON(!i915_tt->is_shmem && obj->mm.madv != I915_MADV_DONTNEED);
- if (!i915_tt->filp)
+ if (i915_tt->is_shmem && !i915_tt->filp)
return 0;
ret = ttm_bo_wait_ctx(bo, &ctx);
--
2.25.1
next prev parent reply other threads:[~2022-06-08 20:53 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-08 20:51 [Intel-gfx] [PATCH v2 0/8] drm/i915: ttm for internal Robert Beckett
2022-06-08 20:51 ` [Intel-gfx] [PATCH v2 1/8] drm/i915/ttm: dont trample cache_level overrides during ttm move Robert Beckett
2022-06-08 20:51 ` [Intel-gfx] [PATCH v2 2/8] drm/i915: add gen6 ppgtt dummy creation function Robert Beckett
2022-06-08 20:51 ` [Intel-gfx] [PATCH v2 3/8] drm/i915: setup ggtt scratch page after memory regions Robert Beckett
2022-06-08 20:51 ` Robert Beckett [this message]
2022-06-08 20:51 ` [Intel-gfx] [PATCH v2 5/8] drm/i915: limit ttm to dma32 for i965G[M] Robert Beckett
2022-06-08 20:51 ` [Intel-gfx] [PATCH v2 6/8] drm/i915/gem: further fix mman selftest Robert Beckett
2022-06-08 20:51 ` [Intel-gfx] [PATCH v2 7/8] drm/i915/ttm: trust snooping when gen 6+ when deciding default cache_level Robert Beckett
2022-06-08 20:51 ` [Intel-gfx] [PATCH v2 8/8] drm/i915: internal buffers use ttm backend Robert Beckett
2022-06-08 22:30 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: ttm for internal Patchwork
2022-06-09 1:08 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
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