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* [Intel-gfx] [PATCH] drm/i915: Correct ss -> steering calculation for pre-Xe_HP platforms
@ 2022-07-12 22:05 Matt Roper
  2022-07-13  0:21 ` [Intel-gfx] ✓ Fi.CI.BAT: success for " Patchwork
                   ` (2 more replies)
  0 siblings, 3 replies; 6+ messages in thread
From: Matt Roper @ 2022-07-12 22:05 UTC (permalink / raw)
  To: intel-gfx; +Cc: dri-devel

Accidental use of a "SLICE" macro where a "SUBSLICE" macro was intended
causes the group ID for steering to be calculated incorrectly on
pre-Xe_HP platforms.

Fixes: 9a92732f040a ("drm/i915/gt: Add general DSS steering iterator to intel_gt_mcr")
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_gt_mcr.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
index f8c64ab9d3ca..e79405a45312 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
@@ -515,7 +515,7 @@ void intel_gt_mcr_get_ss_steering(struct intel_gt *gt, unsigned int dss,
 		*group = dss / GEN_DSS_PER_GSLICE;
 		*instance = dss % GEN_DSS_PER_GSLICE;
 	} else {
-		*group = dss / GEN_MAX_HSW_SLICES;
+		*group = dss / GEN_MAX_SS_PER_HSW_SLICE;
 		*instance = dss % GEN_MAX_SS_PER_HSW_SLICE;
 		return;
 	}
-- 
2.36.1


^ permalink raw reply related	[flat|nested] 6+ messages in thread

end of thread, other threads:[~2022-07-13 17:08 UTC | newest]

Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2022-07-12 22:05 [Intel-gfx] [PATCH] drm/i915: Correct ss -> steering calculation for pre-Xe_HP platforms Matt Roper
2022-07-13  0:21 ` [Intel-gfx] ✓ Fi.CI.BAT: success for " Patchwork
2022-07-13  3:50 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2022-07-13 16:26   ` Matt Roper
2022-07-13 17:07     ` Vudum, Lakshminarayana
2022-07-13 15:48 ` [Intel-gfx] [PATCH] " Lucas De Marchi

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