* [Intel-gfx] [PATCH v2 0/2] drm/i915: Media fuses future-proofing
@ 2022-09-09 23:18 Lucas De Marchi
2022-09-09 23:18 ` [Intel-gfx] [PATCH v2 1/2] drm/i915/gt: Use MEDIA_VER() when handling media fuses Lucas De Marchi
` (4 more replies)
0 siblings, 5 replies; 9+ messages in thread
From: Lucas De Marchi @ 2022-09-09 23:18 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi, dri-devel
Update fuse handling for media to future-proof it.
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
Lucas De Marchi (2):
drm/i915/gt: Use MEDIA_VER() when handling media fuses
drm/i915/gt: Extract function to apply media fuses
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 142 ++++++++++++++++--------------
1 file changed, 74 insertions(+), 68 deletions(-)
---
base-commit: ff8b32fbe64a79b380b1cca4232d30c0b29df069
change-id: 20220909-media-87cd0701e0d8
Best regards,
--
Lucas De Marchi <lucas.demarchi@intel.com>
^ permalink raw reply [flat|nested] 9+ messages in thread
* [Intel-gfx] [PATCH v2 1/2] drm/i915/gt: Use MEDIA_VER() when handling media fuses
2022-09-09 23:18 [Intel-gfx] [PATCH v2 0/2] drm/i915: Media fuses future-proofing Lucas De Marchi
@ 2022-09-09 23:18 ` Lucas De Marchi
2022-09-12 8:49 ` Andrzej Hajda
2022-09-09 23:18 ` [Intel-gfx] [PATCH v2 2/2] drm/i915/gt: Extract function to apply " Lucas De Marchi
` (3 subsequent siblings)
4 siblings, 1 reply; 9+ messages in thread
From: Lucas De Marchi @ 2022-09-09 23:18 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi, dri-devel
Check for media IP version instead of graphics since this is figuring
out the media engines' configuration. Currently the only platform with
non-matching graphics/media version is Meteor Lake: update the check in
gen11_vdbox_has_sfc() so it considers not only version 12, but also any
later version which then includes that platform.
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 6e0122b3dca2..b6602439224d 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -654,13 +654,12 @@ bool gen11_vdbox_has_sfc(struct intel_gt *gt,
*/
if ((gt->info.sfc_mask & BIT(physical_vdbox / 2)) == 0)
return false;
- else if (GRAPHICS_VER(i915) == 12)
+ else if (MEDIA_VER(i915) >= 12)
return (physical_vdbox % 2 == 0) ||
!(BIT(physical_vdbox - 1) & vdbox_mask);
- else if (GRAPHICS_VER(i915) == 11)
+ else if (MEDIA_VER(i915) == 11)
return logical_vdbox % 2 == 0;
- MISSING_CASE(GRAPHICS_VER(i915));
return false;
}
@@ -747,14 +746,14 @@ static intel_engine_mask_t init_engine_mask(struct intel_gt *gt)
* and bits have disable semantices.
*/
media_fuse = intel_uncore_read(uncore, GEN11_GT_VEBOX_VDBOX_DISABLE);
- if (GRAPHICS_VER_FULL(i915) < IP_VER(12, 50))
+ if (MEDIA_VER_FULL(i915) < IP_VER(12, 50))
media_fuse = ~media_fuse;
vdbox_mask = media_fuse & GEN11_GT_VDBOX_DISABLE_MASK;
vebox_mask = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >>
GEN11_GT_VEBOX_DISABLE_SHIFT;
- if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) {
+ if (MEDIA_VER_FULL(i915) >= IP_VER(12, 50)) {
fuse1 = intel_uncore_read(uncore, HSW_PAVP_FUSE1);
gt->info.sfc_mask = REG_FIELD_GET(XEHP_SFC_ENABLE_MASK, fuse1);
} else {
--
b4 0.10.0-dev-df873
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [Intel-gfx] [PATCH v2 2/2] drm/i915/gt: Extract function to apply media fuses
2022-09-09 23:18 [Intel-gfx] [PATCH v2 0/2] drm/i915: Media fuses future-proofing Lucas De Marchi
2022-09-09 23:18 ` [Intel-gfx] [PATCH v2 1/2] drm/i915/gt: Use MEDIA_VER() when handling media fuses Lucas De Marchi
@ 2022-09-09 23:18 ` Lucas De Marchi
2022-09-12 8:56 ` Andrzej Hajda
2022-09-10 0:16 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Media fuses future-proofing Patchwork
` (2 subsequent siblings)
4 siblings, 1 reply; 9+ messages in thread
From: Lucas De Marchi @ 2022-09-09 23:18 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi, dri-devel
Just like is done for compute and copy engines, extract a function to
handle media engines. While at it, be consistent on using or not the
uncore/gt/info variable aliases.
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index b6602439224d..814f83b5fe59 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -663,6 +663,74 @@ bool gen11_vdbox_has_sfc(struct intel_gt *gt,
return false;
}
+static void engine_mask_apply_media_fuses(struct intel_gt *gt)
+{
+ struct drm_i915_private *i915 = gt->i915;
+ unsigned int logical_vdbox = 0;
+ unsigned int i;
+ u32 media_fuse, fuse1;
+ u16 vdbox_mask;
+ u16 vebox_mask;
+
+ if (MEDIA_VER(gt->i915) < 11)
+ return;
+
+ /*
+ * On newer platforms the fusing register is called 'enable' and has
+ * enable semantics, while on older platforms it is called 'disable'
+ * and bits have disable semantices.
+ */
+ media_fuse = intel_uncore_read(gt->uncore, GEN11_GT_VEBOX_VDBOX_DISABLE);
+ if (MEDIA_VER_FULL(i915) < IP_VER(12, 50))
+ media_fuse = ~media_fuse;
+
+ vdbox_mask = media_fuse & GEN11_GT_VDBOX_DISABLE_MASK;
+ vebox_mask = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >>
+ GEN11_GT_VEBOX_DISABLE_SHIFT;
+
+ if (MEDIA_VER_FULL(i915) >= IP_VER(12, 50)) {
+ fuse1 = intel_uncore_read(gt->uncore, HSW_PAVP_FUSE1);
+ gt->info.sfc_mask = REG_FIELD_GET(XEHP_SFC_ENABLE_MASK, fuse1);
+ } else {
+ gt->info.sfc_mask = ~0;
+ }
+
+ for (i = 0; i < I915_MAX_VCS; i++) {
+ if (!HAS_ENGINE(gt, _VCS(i))) {
+ vdbox_mask &= ~BIT(i);
+ continue;
+ }
+
+ if (!(BIT(i) & vdbox_mask)) {
+ gt->info.engine_mask &= ~BIT(_VCS(i));
+ drm_dbg(&i915->drm, "vcs%u fused off\n", i);
+ continue;
+ }
+
+ if (gen11_vdbox_has_sfc(gt, i, logical_vdbox, vdbox_mask))
+ gt->info.vdbox_sfc_access |= BIT(i);
+ logical_vdbox++;
+ }
+ drm_dbg(&i915->drm, "vdbox enable: %04x, instances: %04lx\n",
+ vdbox_mask, VDBOX_MASK(gt));
+ GEM_BUG_ON(vdbox_mask != VDBOX_MASK(gt));
+
+ for (i = 0; i < I915_MAX_VECS; i++) {
+ if (!HAS_ENGINE(gt, _VECS(i))) {
+ vebox_mask &= ~BIT(i);
+ continue;
+ }
+
+ if (!(BIT(i) & vebox_mask)) {
+ gt->info.engine_mask &= ~BIT(_VECS(i));
+ drm_dbg(&i915->drm, "vecs%u fused off\n", i);
+ }
+ }
+ drm_dbg(&i915->drm, "vebox enable: %04x, instances: %04lx\n",
+ vebox_mask, VEBOX_MASK(gt));
+ GEM_BUG_ON(vebox_mask != VEBOX_MASK(gt));
+}
+
static void engine_mask_apply_compute_fuses(struct intel_gt *gt)
{
struct drm_i915_private *i915 = gt->i915;
@@ -671,6 +739,9 @@ static void engine_mask_apply_compute_fuses(struct intel_gt *gt)
unsigned long ccs_mask;
unsigned int i;
+ if (GRAPHICS_VER(i915) < 11)
+ return;
+
if (hweight32(CCS_MASK(gt)) <= 1)
return;
@@ -726,75 +797,11 @@ static void engine_mask_apply_copy_fuses(struct intel_gt *gt)
*/
static intel_engine_mask_t init_engine_mask(struct intel_gt *gt)
{
- struct drm_i915_private *i915 = gt->i915;
struct intel_gt_info *info = >->info;
- struct intel_uncore *uncore = gt->uncore;
- unsigned int logical_vdbox = 0;
- unsigned int i;
- u32 media_fuse, fuse1;
- u16 vdbox_mask;
- u16 vebox_mask;
GEM_BUG_ON(!info->engine_mask);
- if (GRAPHICS_VER(i915) < 11)
- return info->engine_mask;
-
- /*
- * On newer platforms the fusing register is called 'enable' and has
- * enable semantics, while on older platforms it is called 'disable'
- * and bits have disable semantices.
- */
- media_fuse = intel_uncore_read(uncore, GEN11_GT_VEBOX_VDBOX_DISABLE);
- if (MEDIA_VER_FULL(i915) < IP_VER(12, 50))
- media_fuse = ~media_fuse;
-
- vdbox_mask = media_fuse & GEN11_GT_VDBOX_DISABLE_MASK;
- vebox_mask = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >>
- GEN11_GT_VEBOX_DISABLE_SHIFT;
-
- if (MEDIA_VER_FULL(i915) >= IP_VER(12, 50)) {
- fuse1 = intel_uncore_read(uncore, HSW_PAVP_FUSE1);
- gt->info.sfc_mask = REG_FIELD_GET(XEHP_SFC_ENABLE_MASK, fuse1);
- } else {
- gt->info.sfc_mask = ~0;
- }
-
- for (i = 0; i < I915_MAX_VCS; i++) {
- if (!HAS_ENGINE(gt, _VCS(i))) {
- vdbox_mask &= ~BIT(i);
- continue;
- }
-
- if (!(BIT(i) & vdbox_mask)) {
- info->engine_mask &= ~BIT(_VCS(i));
- drm_dbg(&i915->drm, "vcs%u fused off\n", i);
- continue;
- }
-
- if (gen11_vdbox_has_sfc(gt, i, logical_vdbox, vdbox_mask))
- gt->info.vdbox_sfc_access |= BIT(i);
- logical_vdbox++;
- }
- drm_dbg(&i915->drm, "vdbox enable: %04x, instances: %04lx\n",
- vdbox_mask, VDBOX_MASK(gt));
- GEM_BUG_ON(vdbox_mask != VDBOX_MASK(gt));
-
- for (i = 0; i < I915_MAX_VECS; i++) {
- if (!HAS_ENGINE(gt, _VECS(i))) {
- vebox_mask &= ~BIT(i);
- continue;
- }
-
- if (!(BIT(i) & vebox_mask)) {
- info->engine_mask &= ~BIT(_VECS(i));
- drm_dbg(&i915->drm, "vecs%u fused off\n", i);
- }
- }
- drm_dbg(&i915->drm, "vebox enable: %04x, instances: %04lx\n",
- vebox_mask, VEBOX_MASK(gt));
- GEM_BUG_ON(vebox_mask != VEBOX_MASK(gt));
-
+ engine_mask_apply_media_fuses(gt);
engine_mask_apply_compute_fuses(gt);
engine_mask_apply_copy_fuses(gt);
--
b4 0.10.0-dev-df873
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Media fuses future-proofing
2022-09-09 23:18 [Intel-gfx] [PATCH v2 0/2] drm/i915: Media fuses future-proofing Lucas De Marchi
2022-09-09 23:18 ` [Intel-gfx] [PATCH v2 1/2] drm/i915/gt: Use MEDIA_VER() when handling media fuses Lucas De Marchi
2022-09-09 23:18 ` [Intel-gfx] [PATCH v2 2/2] drm/i915/gt: Extract function to apply " Lucas De Marchi
@ 2022-09-10 0:16 ` Patchwork
2022-09-10 6:44 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2022-09-12 16:14 ` [Intel-gfx] [PATCH v2 0/2] " Lucas De Marchi
4 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2022-09-10 0:16 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 6263 bytes --]
== Series Details ==
Series: drm/i915: Media fuses future-proofing
URL : https://patchwork.freedesktop.org/series/108391/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12112 -> Patchwork_108391v1
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108391v1/index.html
Participating hosts (37 -> 38)
------------------------------
Additional (2): fi-kbl-soraka fi-hsw-4770
Missing (1): fi-bdw-samus
Known issues
------------
Here are the changes found in Patchwork_108391v1 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_pm_backlight@basic-brightness:
- fi-hsw-4770: NOTRUN -> [SKIP][1] ([fdo#109271] / [i915#3012])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108391v1/fi-hsw-4770/igt@i915_pm_backlight@basic-brightness.html
* igt@i915_selftest@live@hangcheck:
- fi-hsw-g3258: [PASS][2] -> [INCOMPLETE][3] ([i915#3303] / [i915#4785])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12112/fi-hsw-g3258/igt@i915_selftest@live@hangcheck.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108391v1/fi-hsw-g3258/igt@i915_selftest@live@hangcheck.html
* igt@i915_selftest@live@requests:
- fi-pnv-d510: [PASS][4] -> [DMESG-FAIL][5] ([i915#4528])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12112/fi-pnv-d510/igt@i915_selftest@live@requests.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108391v1/fi-pnv-d510/igt@i915_selftest@live@requests.html
* igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- fi-hsw-4770: NOTRUN -> [SKIP][6] ([fdo#109271]) +9 similar issues
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108391v1/fi-hsw-4770/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html
* igt@kms_chamelium@dp-crc-fast:
- fi-hsw-4770: NOTRUN -> [SKIP][7] ([fdo#109271] / [fdo#111827]) +8 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108391v1/fi-hsw-4770/igt@kms_chamelium@dp-crc-fast.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions:
- fi-bsw-kefka: [PASS][8] -> [FAIL][9] ([i915#6298])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12112/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108391v1/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions.html
* igt@kms_psr@sprite_plane_onoff:
- fi-hsw-4770: NOTRUN -> [SKIP][10] ([fdo#109271] / [i915#1072]) +3 similar issues
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108391v1/fi-hsw-4770/igt@kms_psr@sprite_plane_onoff.html
* igt@runner@aborted:
- fi-kbl-soraka: NOTRUN -> [FAIL][11] ([i915#6219])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108391v1/fi-kbl-soraka/igt@runner@aborted.html
- fi-hsw-g3258: NOTRUN -> [FAIL][12] ([fdo#109271] / [i915#4312] / [i915#6246])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108391v1/fi-hsw-g3258/igt@runner@aborted.html
#### Possible fixes ####
* igt@i915_pm_rpm@module-reload:
- {bat-rpls-2}: [DMESG-WARN][13] ([i915#5537]) -> [PASS][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12112/bat-rpls-2/igt@i915_pm_rpm@module-reload.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108391v1/bat-rpls-2/igt@i915_pm_rpm@module-reload.html
* igt@i915_selftest@live@gem_contexts:
- {bat-dg2-8}: [INCOMPLETE][15] ([i915#6523]) -> [PASS][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12112/bat-dg2-8/igt@i915_selftest@live@gem_contexts.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108391v1/bat-dg2-8/igt@i915_selftest@live@gem_contexts.html
* igt@i915_selftest@live@reset:
- {bat-rpls-1}: [DMESG-FAIL][17] ([i915#4983]) -> [PASS][18]
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12112/bat-rpls-1/igt@i915_selftest@live@reset.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108391v1/bat-rpls-1/igt@i915_selftest@live@reset.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#3012]: https://gitlab.freedesktop.org/drm/intel/issues/3012
[i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4528]: https://gitlab.freedesktop.org/drm/intel/issues/4528
[i915#4785]: https://gitlab.freedesktop.org/drm/intel/issues/4785
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#5537]: https://gitlab.freedesktop.org/drm/intel/issues/5537
[i915#6219]: https://gitlab.freedesktop.org/drm/intel/issues/6219
[i915#6246]: https://gitlab.freedesktop.org/drm/intel/issues/6246
[i915#6257]: https://gitlab.freedesktop.org/drm/intel/issues/6257
[i915#6298]: https://gitlab.freedesktop.org/drm/intel/issues/6298
[i915#6523]: https://gitlab.freedesktop.org/drm/intel/issues/6523
[i915#6645]: https://gitlab.freedesktop.org/drm/intel/issues/6645
Build changes
-------------
* Linux: CI_DRM_12112 -> Patchwork_108391v1
CI-20190529: 20190529
CI_DRM_12112: ff8b32fbe64a79b380b1cca4232d30c0b29df069 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6650: f7aff600ab16d6405f0704b1743d2b7909715752 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_108391v1: ff8b32fbe64a79b380b1cca4232d30c0b29df069 @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
47b6387b7a4d drm/i915/gt: Extract function to apply media fuses
eba609641cd0 drm/i915/gt: Use MEDIA_VER() when handling media fuses
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108391v1/index.html
[-- Attachment #2: Type: text/html, Size: 7228 bytes --]
^ permalink raw reply [flat|nested] 9+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Media fuses future-proofing
2022-09-09 23:18 [Intel-gfx] [PATCH v2 0/2] drm/i915: Media fuses future-proofing Lucas De Marchi
` (2 preceding siblings ...)
2022-09-10 0:16 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Media fuses future-proofing Patchwork
@ 2022-09-10 6:44 ` Patchwork
2022-09-12 16:14 ` [Intel-gfx] [PATCH v2 0/2] " Lucas De Marchi
4 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2022-09-10 6:44 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 24564 bytes --]
== Series Details ==
Series: drm/i915: Media fuses future-proofing
URL : https://patchwork.freedesktop.org/series/108391/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12112_full -> Patchwork_108391v1_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_108391v1_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_108391v1_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (11 -> 10)
------------------------------
Missing (1): shard-rkl
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_108391v1_full:
### IGT changes ###
#### Possible regressions ####
* igt@i915_pm_rpm@i2c:
- shard-iclb: [PASS][1] -> [SKIP][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12112/shard-iclb5/igt@i915_pm_rpm@i2c.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108391v1/shard-iclb8/igt@i915_pm_rpm@i2c.html
Known issues
------------
Here are the changes found in Patchwork_108391v1_full that come from known issues:
### CI changes ###
#### Issues hit ####
* boot:
- shard-glk: ([PASS][3], [PASS][4], [PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25], [PASS][26], [PASS][27]) -> ([PASS][28], [PASS][29], [PASS][30], [PASS][31], [PASS][32], [FAIL][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49], [PASS][50], [PASS][51], [PASS][52]) ([i915#4392])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12112/shard-glk3/boot.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12112/shard-glk9/boot.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12112/shard-glk9/boot.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12112/shard-glk9/boot.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12112/shard-glk8/boot.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12112/shard-glk1/boot.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12112/shard-glk1/boot.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12112/shard-glk8/boot.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12112/shard-glk8/boot.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12112/shard-glk1/boot.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12112/shard-glk7/boot.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12112/shard-glk7/boot.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12112/shard-glk7/boot.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12112/shard-glk7/boot.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12112/shard-glk6/boot.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12112/shard-glk6/boot.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12112/shard-glk6/boot.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12112/shard-glk2/boot.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12112/shard-glk2/boot.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12112/shard-glk5/boot.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12112/shard-glk5/boot.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12112/shard-glk3/boot.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12112/shard-glk5/boot.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12112/shard-glk3/boot.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12112/shard-glk3/boot.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108391v1/shard-glk9/boot.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108391v1/shard-glk9/boot.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108391v1/shard-glk9/boot.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108391v1/shard-glk8/boot.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108391v1/shard-glk8/boot.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108391v1/shard-glk8/boot.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108391v1/shard-glk8/boot.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108391v1/shard-glk7/boot.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108391v1/shard-glk7/boot.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108391v1/shard-glk7/boot.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108391v1/shard-glk6/boot.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108391v1/shard-glk6/boot.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108391v1/shard-glk6/boot.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108391v1/shard-glk6/boot.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108391v1/shard-glk5/boot.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108391v1/shard-glk5/boot.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108391v1/shard-glk5/boot.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108391v1/shard-glk3/boot.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108391v1/shard-glk3/boot.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108391v1/shard-glk2/boot.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108391v1/shard-glk2/boot.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108391v1/shard-glk2/boot.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108391v1/shard-glk1/boot.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108391v1/shard-glk1/boot.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108391v1/shard-glk1/boot.html
### IGT changes ###
#### Issues hit ####
* igt@gem_eio@unwedge-stress:
- shard-iclb: [PASS][53] -> [TIMEOUT][54] ([i915#3070])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12112/shard-iclb3/igt@gem_eio@unwedge-stress.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108391v1/shard-iclb4/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_balancer@parallel-bb-first:
- shard-iclb: [PASS][55] -> [SKIP][56] ([i915#4525]) +2 similar issues
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12112/shard-iclb2/igt@gem_exec_balancer@parallel-bb-first.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108391v1/shard-iclb3/igt@gem_exec_balancer@parallel-bb-first.html
* igt@gem_lmem_swapping@heavy-random:
- shard-apl: NOTRUN -> [SKIP][57] ([fdo#109271] / [i915#4613])
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108391v1/shard-apl7/igt@gem_lmem_swapping@heavy-random.html
* igt@gem_userptr_blits@vma-merge:
- shard-apl: NOTRUN -> [FAIL][58] ([i915#3318])
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108391v1/shard-apl7/igt@gem_userptr_blits@vma-merge.html
* igt@i915_selftest@perf@region:
- shard-iclb: [PASS][59] -> [DMESG-WARN][60] ([i915#2867])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12112/shard-iclb5/igt@i915_selftest@perf@region.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108391v1/shard-iclb8/igt@i915_selftest@perf@region.html
* igt@kms_big_fb@x-tiled-64bpp-rotate-90:
- shard-glk: NOTRUN -> [SKIP][61] ([fdo#109271]) +43 similar issues
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108391v1/shard-glk8/igt@kms_big_fb@x-tiled-64bpp-rotate-90.html
* igt@kms_ccs@pipe-a-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc:
- shard-apl: NOTRUN -> [SKIP][62] ([fdo#109271] / [i915#3886]) +2 similar issues
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108391v1/shard-apl7/igt@kms_ccs@pipe-a-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc:
- shard-glk: NOTRUN -> [SKIP][63] ([fdo#109271] / [i915#3886]) +4 similar issues
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108391v1/shard-glk8/igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_chamelium@common-hpd-after-suspend:
- shard-apl: NOTRUN -> [SKIP][64] ([fdo#109271] / [fdo#111827]) +3 similar issues
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108391v1/shard-apl7/igt@kms_chamelium@common-hpd-after-suspend.html
* igt@kms_chamelium@hdmi-hpd:
- shard-glk: NOTRUN -> [SKIP][65] ([fdo#109271] / [fdo#111827]) +1 similar issue
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108391v1/shard-glk2/igt@kms_chamelium@hdmi-hpd.html
* igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions-varying-size:
- shard-glk: [PASS][66] -> [FAIL][67] ([i915#2346]) +1 similar issue
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12112/shard-glk1/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions-varying-size.html
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108391v1/shard-glk1/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions-varying-size.html
* igt@kms_flip@flip-vs-suspend-interruptible@c-dp1:
- shard-apl: [PASS][68] -> [DMESG-WARN][69] ([i915#180]) +1 similar issue
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12112/shard-apl4/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108391v1/shard-apl8/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html
* igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling@pipe-a-valid-mode:
- shard-iclb: NOTRUN -> [SKIP][70] ([i915#2672]) +5 similar issues
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108391v1/shard-iclb7/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling@pipe-a-valid-mode.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-fullscreen:
- shard-apl: NOTRUN -> [SKIP][71] ([fdo#109271]) +54 similar issues
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108391v1/shard-apl7/igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-fullscreen.html
* igt@kms_psr@psr2_primary_blt:
- shard-iclb: [PASS][72] -> [SKIP][73] ([fdo#109441])
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12112/shard-iclb2/igt@kms_psr@psr2_primary_blt.html
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108391v1/shard-iclb7/igt@kms_psr@psr2_primary_blt.html
* igt@kms_vblank@pipe-d-wait-idle:
- shard-apl: NOTRUN -> [SKIP][74] ([fdo#109271] / [i915#533])
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108391v1/shard-apl7/igt@kms_vblank@pipe-d-wait-idle.html
* igt@sysfs_clients@sema-25:
- shard-glk: NOTRUN -> [SKIP][75] ([fdo#109271] / [i915#2994])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108391v1/shard-glk8/igt@sysfs_clients@sema-25.html
#### Possible fixes ####
* igt@gem_ctx_exec@basic-nohangcheck:
- shard-tglb: [FAIL][76] ([i915#6268]) -> [PASS][77]
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12112/shard-tglb2/igt@gem_ctx_exec@basic-nohangcheck.html
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108391v1/shard-tglb5/igt@gem_ctx_exec@basic-nohangcheck.html
* igt@gem_eio@in-flight-contexts-immediate:
- shard-tglb: [TIMEOUT][78] ([i915#3063]) -> [PASS][79]
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12112/shard-tglb3/igt@gem_eio@in-flight-contexts-immediate.html
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108391v1/shard-tglb7/igt@gem_eio@in-flight-contexts-immediate.html
* igt@gem_eio@kms:
- shard-tglb: [FAIL][80] ([i915#5784]) -> [PASS][81] +1 similar issue
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12112/shard-tglb1/igt@gem_eio@kms.html
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108391v1/shard-tglb6/igt@gem_eio@kms.html
* igt@gem_exec_balancer@parallel-keep-in-fence:
- shard-iclb: [SKIP][82] ([i915#4525]) -> [PASS][83]
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12112/shard-iclb6/igt@gem_exec_balancer@parallel-keep-in-fence.html
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108391v1/shard-iclb4/igt@gem_exec_balancer@parallel-keep-in-fence.html
* igt@gem_exec_endless@dispatch@vcs1:
- shard-tglb: [INCOMPLETE][84] ([i915#3778]) -> [PASS][85]
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12112/shard-tglb7/igt@gem_exec_endless@dispatch@vcs1.html
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108391v1/shard-tglb6/igt@gem_exec_endless@dispatch@vcs1.html
* igt@gem_exec_fair@basic-flow@rcs0:
- shard-tglb: [FAIL][86] ([i915#2842]) -> [PASS][87]
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12112/shard-tglb1/igt@gem_exec_fair@basic-flow@rcs0.html
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108391v1/shard-tglb1/igt@gem_exec_fair@basic-flow@rcs0.html
* igt@gem_exec_fair@basic-pace@vecs0:
- shard-iclb: [FAIL][88] ([i915#2842]) -> [PASS][89]
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12112/shard-iclb5/igt@gem_exec_fair@basic-pace@vecs0.html
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108391v1/shard-iclb8/igt@gem_exec_fair@basic-pace@vecs0.html
* igt@gen9_exec_parse@allowed-single:
- shard-glk: [DMESG-WARN][90] ([i915#5566] / [i915#716]) -> [PASS][91]
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12112/shard-glk7/igt@gen9_exec_parse@allowed-single.html
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108391v1/shard-glk8/igt@gen9_exec_parse@allowed-single.html
* igt@i915_pm_dc@dc6-dpms:
- {shard-tglu}: [FAIL][92] ([i915#3989] / [i915#454]) -> [PASS][93]
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12112/shard-tglu-3/igt@i915_pm_dc@dc6-dpms.html
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108391v1/shard-tglu-2/igt@i915_pm_dc@dc6-dpms.html
* igt@i915_pm_rps@engine-order:
- shard-apl: [FAIL][94] ([i915#6537]) -> [PASS][95]
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12112/shard-apl6/igt@i915_pm_rps@engine-order.html
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108391v1/shard-apl2/igt@i915_pm_rps@engine-order.html
* igt@kms_cursor_crc@cursor-suspend@pipe-c-dp-1:
- shard-apl: [DMESG-WARN][96] ([i915#180]) -> [PASS][97] +1 similar issue
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12112/shard-apl8/igt@kms_cursor_crc@cursor-suspend@pipe-c-dp-1.html
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108391v1/shard-apl7/igt@kms_cursor_crc@cursor-suspend@pipe-c-dp-1.html
* igt@kms_flip_scaled_crc@flip-64bpp-linear-to-32bpp-linear-downscaling@pipe-a-default-mode:
- shard-iclb: [SKIP][98] ([i915#3555]) -> [PASS][99]
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12112/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-linear-to-32bpp-linear-downscaling@pipe-a-default-mode.html
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108391v1/shard-iclb3/igt@kms_flip_scaled_crc@flip-64bpp-linear-to-32bpp-linear-downscaling@pipe-a-default-mode.html
* igt@kms_psr@psr2_no_drrs:
- shard-iclb: [SKIP][100] ([fdo#109441]) -> [PASS][101] +2 similar issues
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12112/shard-iclb6/igt@kms_psr@psr2_no_drrs.html
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108391v1/shard-iclb2/igt@kms_psr@psr2_no_drrs.html
#### Warnings ####
* igt@gem_exec_balancer@parallel-ordering:
- shard-iclb: [FAIL][102] ([i915#6117]) -> [SKIP][103] ([i915#4525])
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12112/shard-iclb4/igt@gem_exec_balancer@parallel-ordering.html
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108391v1/shard-iclb6/igt@gem_exec_balancer@parallel-ordering.html
* igt@kms_psr2_sf@overlay-plane-move-continuous-sf:
- shard-iclb: [SKIP][104] ([i915#2920]) -> [SKIP][105] ([i915#658])
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12112/shard-iclb2/igt@kms_psr2_sf@overlay-plane-move-continuous-sf.html
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108391v1/shard-iclb3/igt@kms_psr2_sf@overlay-plane-move-continuous-sf.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[fdo#109302]: https://bugs.freedesktop.org/show_bug.cgi?id=109302
[fdo#109303]: https://bugs.freedesktop.org/show_bug.cgi?id=109303
[fdo#109307]: https://bugs.freedesktop.org/show_bug.cgi?id=109307
[fdo#109312]: https://bugs.freedesktop.org/show_bug.cgi?id=109312
[fdo#109313]: https://bugs.freedesktop.org/show_bug.cgi?id=109313
[fdo#109314]: https://bugs.freedesktop.org/show_bug.cgi?id=109314
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#110542]: https://bugs.freedesktop.org/show_bug.cgi?id=110542
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111644]: https://bugs.freedesktop.org/show_bug.cgi?id=111644
[fdo#111656]: https://bugs.freedesktop.org/show_bug.cgi?id=111656
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[fdo#112054]: https://bugs.freedesktop.org/show_bug.cgi?id=112054
[fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283
[i915#1063]: https://gitlab.freedesktop.org/drm/intel/issues/1063
[i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
[i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
[i915#1902]: https://gitlab.freedesktop.org/drm/intel/issues/1902
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
[i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
[i915#2530]: https://gitlab.freedesktop.org/drm/intel/issues/2530
[i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
[i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280
[i915#284]: https://gitlab.freedesktop.org/drm/intel/issues/284
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
[i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867
[i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
[i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994
[i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002
[i915#3063]: https://gitlab.freedesktop.org/drm/intel/issues/3063
[i915#3070]: https://gitlab.freedesktop.org/drm/intel/issues/3070
[i915#3116]: https://gitlab.freedesktop.org/drm/intel/issues/3116
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299
[i915#3318]: https://gitlab.freedesktop.org/drm/intel/issues/3318
[i915#3323]: https://gitlab.freedesktop.org/drm/intel/issues/3323
[i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
[i915#3528]: https://gitlab.freedesktop.org/drm/intel/issues/3528
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3742]: https://gitlab.freedesktop.org/drm/intel/issues/3742
[i915#3778]: https://gitlab.freedesktop.org/drm/intel/issues/3778
[i915#3804]: https://gitlab.freedesktop.org/drm/intel/issues/3804
[i915#3825]: https://gitlab.freedesktop.org/drm/intel/issues/3825
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#3966]: https://gitlab.freedesktop.org/drm/intel/issues/3966
[i915#3987]: https://gitlab.freedesktop.org/drm/intel/issues/3987
[i915#3989]: https://gitlab.freedesktop.org/drm/intel/issues/3989
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#426]: https://gitlab.freedesktop.org/drm/intel/issues/426
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#4281]: https://gitlab.freedesktop.org/drm/intel/issues/4281
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4392]: https://gitlab.freedesktop.org/drm/intel/issues/4392
[i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525
[i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4991]: https://gitlab.freedesktop.org/drm/intel/issues/4991
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5182]: https://gitlab.freedesktop.org/drm/intel/issues/5182
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5257]: https://gitlab.freedesktop.org/drm/intel/issues/5257
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
[i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#5439]: https://gitlab.freedesktop.org/drm/intel/issues/5439
[i915#5566]: https://gitlab.freedesktop.org/drm/intel/issues/5566
[i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784
[i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
[i915#6117]: https://gitlab.freedesktop.org/drm/intel/issues/6117
[i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268
[i915#6335]: https://gitlab.freedesktop.org/drm/intel/issues/6335
[i915#6433]: https://gitlab.freedesktop.org/drm/intel/issues/6433
[i915#6537]: https://gitlab.freedesktop.org/drm/intel/issues/6537
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#6599]: https://gitlab.freedesktop.org/drm/intel/issues/6599
[i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
Build changes
-------------
* Linux: CI_DRM_12112 -> Patchwork_108391v1
CI-20190529: 20190529
CI_DRM_12112: ff8b32fbe64a79b380b1cca4232d30c0b29df069 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6650: f7aff600ab16d6405f0704b1743d2b7909715752 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_108391v1: ff8b32fbe64a79b380b1cca4232d30c0b29df069 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108391v1/index.html
[-- Attachment #2: Type: text/html, Size: 22471 bytes --]
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [Intel-gfx] [PATCH v2 1/2] drm/i915/gt: Use MEDIA_VER() when handling media fuses
2022-09-09 23:18 ` [Intel-gfx] [PATCH v2 1/2] drm/i915/gt: Use MEDIA_VER() when handling media fuses Lucas De Marchi
@ 2022-09-12 8:49 ` Andrzej Hajda
0 siblings, 0 replies; 9+ messages in thread
From: Andrzej Hajda @ 2022-09-12 8:49 UTC (permalink / raw)
To: Lucas De Marchi, intel-gfx; +Cc: dri-devel
On 10.09.2022 01:18, Lucas De Marchi wrote:
> Check for media IP version instead of graphics since this is figuring
> out the media engines' configuration. Currently the only platform with
> non-matching graphics/media version is Meteor Lake: update the check in
> gen11_vdbox_has_sfc() so it considers not only version 12, but also any
> later version which then includes that platform.
>
> Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com>
Regards
Andrzej
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> index 6e0122b3dca2..b6602439224d 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> @@ -654,13 +654,12 @@ bool gen11_vdbox_has_sfc(struct intel_gt *gt,
> */
> if ((gt->info.sfc_mask & BIT(physical_vdbox / 2)) == 0)
> return false;
> - else if (GRAPHICS_VER(i915) == 12)
> + else if (MEDIA_VER(i915) >= 12)
> return (physical_vdbox % 2 == 0) ||
> !(BIT(physical_vdbox - 1) & vdbox_mask);
> - else if (GRAPHICS_VER(i915) == 11)
> + else if (MEDIA_VER(i915) == 11)
> return logical_vdbox % 2 == 0;
>
> - MISSING_CASE(GRAPHICS_VER(i915));
> return false;
> }
>
> @@ -747,14 +746,14 @@ static intel_engine_mask_t init_engine_mask(struct intel_gt *gt)
> * and bits have disable semantices.
> */
> media_fuse = intel_uncore_read(uncore, GEN11_GT_VEBOX_VDBOX_DISABLE);
> - if (GRAPHICS_VER_FULL(i915) < IP_VER(12, 50))
> + if (MEDIA_VER_FULL(i915) < IP_VER(12, 50))
> media_fuse = ~media_fuse;
>
> vdbox_mask = media_fuse & GEN11_GT_VDBOX_DISABLE_MASK;
> vebox_mask = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >>
> GEN11_GT_VEBOX_DISABLE_SHIFT;
>
> - if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) {
> + if (MEDIA_VER_FULL(i915) >= IP_VER(12, 50)) {
> fuse1 = intel_uncore_read(uncore, HSW_PAVP_FUSE1);
> gt->info.sfc_mask = REG_FIELD_GET(XEHP_SFC_ENABLE_MASK, fuse1);
> } else {
>
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [Intel-gfx] [PATCH v2 2/2] drm/i915/gt: Extract function to apply media fuses
2022-09-09 23:18 ` [Intel-gfx] [PATCH v2 2/2] drm/i915/gt: Extract function to apply " Lucas De Marchi
@ 2022-09-12 8:56 ` Andrzej Hajda
2022-09-12 15:32 ` Lucas De Marchi
0 siblings, 1 reply; 9+ messages in thread
From: Andrzej Hajda @ 2022-09-12 8:56 UTC (permalink / raw)
To: Lucas De Marchi, intel-gfx; +Cc: dri-devel
On 10.09.2022 01:18, Lucas De Marchi wrote:
> Just like is done for compute and copy engines, extract a function to
> handle media engines. While at it, be consistent on using or not the
> uncore/gt/info variable aliases.
>
> Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> index b6602439224d..814f83b5fe59 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> @@ -663,6 +663,74 @@ bool gen11_vdbox_has_sfc(struct intel_gt *gt,
> return false;
> }
>
> +static void engine_mask_apply_media_fuses(struct intel_gt *gt)
> +{
> + struct drm_i915_private *i915 = gt->i915;
> + unsigned int logical_vdbox = 0;
> + unsigned int i;
> + u32 media_fuse, fuse1;
> + u16 vdbox_mask;
> + u16 vebox_mask;
> +
> + if (MEDIA_VER(gt->i915) < 11)
> + return;
> +
> + /*
> + * On newer platforms the fusing register is called 'enable' and has
> + * enable semantics, while on older platforms it is called 'disable'
> + * and bits have disable semantices.
> + */
> + media_fuse = intel_uncore_read(gt->uncore, GEN11_GT_VEBOX_VDBOX_DISABLE);
> + if (MEDIA_VER_FULL(i915) < IP_VER(12, 50))
> + media_fuse = ~media_fuse;
> +
> + vdbox_mask = media_fuse & GEN11_GT_VDBOX_DISABLE_MASK;
> + vebox_mask = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >>
> + GEN11_GT_VEBOX_DISABLE_SHIFT;
> +
> + if (MEDIA_VER_FULL(i915) >= IP_VER(12, 50)) {
> + fuse1 = intel_uncore_read(gt->uncore, HSW_PAVP_FUSE1);
> + gt->info.sfc_mask = REG_FIELD_GET(XEHP_SFC_ENABLE_MASK, fuse1);
> + } else {
> + gt->info.sfc_mask = ~0;
> + }
> +
> + for (i = 0; i < I915_MAX_VCS; i++) {
> + if (!HAS_ENGINE(gt, _VCS(i))) {
> + vdbox_mask &= ~BIT(i);
> + continue;
> + }
> +
> + if (!(BIT(i) & vdbox_mask)) {
> + gt->info.engine_mask &= ~BIT(_VCS(i));
> + drm_dbg(&i915->drm, "vcs%u fused off\n", i);
> + continue;
> + }
> +
> + if (gen11_vdbox_has_sfc(gt, i, logical_vdbox, vdbox_mask))
> + gt->info.vdbox_sfc_access |= BIT(i);
> + logical_vdbox++;
> + }
> + drm_dbg(&i915->drm, "vdbox enable: %04x, instances: %04lx\n",
> + vdbox_mask, VDBOX_MASK(gt));
> + GEM_BUG_ON(vdbox_mask != VDBOX_MASK(gt));
> +
> + for (i = 0; i < I915_MAX_VECS; i++) {
> + if (!HAS_ENGINE(gt, _VECS(i))) {
> + vebox_mask &= ~BIT(i);
> + continue;
> + }
> +
> + if (!(BIT(i) & vebox_mask)) {
> + gt->info.engine_mask &= ~BIT(_VECS(i));
> + drm_dbg(&i915->drm, "vecs%u fused off\n", i);
> + }
> + }
> + drm_dbg(&i915->drm, "vebox enable: %04x, instances: %04lx\n",
> + vebox_mask, VEBOX_MASK(gt));
> + GEM_BUG_ON(vebox_mask != VEBOX_MASK(gt));
> +}
> +
> static void engine_mask_apply_compute_fuses(struct intel_gt *gt)
> {
> struct drm_i915_private *i915 = gt->i915;
> @@ -671,6 +739,9 @@ static void engine_mask_apply_compute_fuses(struct intel_gt *gt)
> unsigned long ccs_mask;
> unsigned int i;
>
> + if (GRAPHICS_VER(i915) < 11)
> + return;
> +
Why there is no similar sentinel in case of engine_mask_apply_copy_fuses?
Beside this:
Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com>
Regards
Andrzej
> if (hweight32(CCS_MASK(gt)) <= 1)
> return;
>
> @@ -726,75 +797,11 @@ static void engine_mask_apply_copy_fuses(struct intel_gt *gt)
> */
> static intel_engine_mask_t init_engine_mask(struct intel_gt *gt)
> {
> - struct drm_i915_private *i915 = gt->i915;
> struct intel_gt_info *info = >->info;
> - struct intel_uncore *uncore = gt->uncore;
> - unsigned int logical_vdbox = 0;
> - unsigned int i;
> - u32 media_fuse, fuse1;
> - u16 vdbox_mask;
> - u16 vebox_mask;
>
> GEM_BUG_ON(!info->engine_mask);
>
> - if (GRAPHICS_VER(i915) < 11)
> - return info->engine_mask;
> -
> - /*
> - * On newer platforms the fusing register is called 'enable' and has
> - * enable semantics, while on older platforms it is called 'disable'
> - * and bits have disable semantices.
> - */
> - media_fuse = intel_uncore_read(uncore, GEN11_GT_VEBOX_VDBOX_DISABLE);
> - if (MEDIA_VER_FULL(i915) < IP_VER(12, 50))
> - media_fuse = ~media_fuse;
> -
> - vdbox_mask = media_fuse & GEN11_GT_VDBOX_DISABLE_MASK;
> - vebox_mask = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >>
> - GEN11_GT_VEBOX_DISABLE_SHIFT;
> -
> - if (MEDIA_VER_FULL(i915) >= IP_VER(12, 50)) {
> - fuse1 = intel_uncore_read(uncore, HSW_PAVP_FUSE1);
> - gt->info.sfc_mask = REG_FIELD_GET(XEHP_SFC_ENABLE_MASK, fuse1);
> - } else {
> - gt->info.sfc_mask = ~0;
> - }
> -
> - for (i = 0; i < I915_MAX_VCS; i++) {
> - if (!HAS_ENGINE(gt, _VCS(i))) {
> - vdbox_mask &= ~BIT(i);
> - continue;
> - }
> -
> - if (!(BIT(i) & vdbox_mask)) {
> - info->engine_mask &= ~BIT(_VCS(i));
> - drm_dbg(&i915->drm, "vcs%u fused off\n", i);
> - continue;
> - }
> -
> - if (gen11_vdbox_has_sfc(gt, i, logical_vdbox, vdbox_mask))
> - gt->info.vdbox_sfc_access |= BIT(i);
> - logical_vdbox++;
> - }
> - drm_dbg(&i915->drm, "vdbox enable: %04x, instances: %04lx\n",
> - vdbox_mask, VDBOX_MASK(gt));
> - GEM_BUG_ON(vdbox_mask != VDBOX_MASK(gt));
> -
> - for (i = 0; i < I915_MAX_VECS; i++) {
> - if (!HAS_ENGINE(gt, _VECS(i))) {
> - vebox_mask &= ~BIT(i);
> - continue;
> - }
> -
> - if (!(BIT(i) & vebox_mask)) {
> - info->engine_mask &= ~BIT(_VECS(i));
> - drm_dbg(&i915->drm, "vecs%u fused off\n", i);
> - }
> - }
> - drm_dbg(&i915->drm, "vebox enable: %04x, instances: %04lx\n",
> - vebox_mask, VEBOX_MASK(gt));
> - GEM_BUG_ON(vebox_mask != VEBOX_MASK(gt));
> -
> + engine_mask_apply_media_fuses(gt);
> engine_mask_apply_compute_fuses(gt);
> engine_mask_apply_copy_fuses(gt);
>
>
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [Intel-gfx] [PATCH v2 2/2] drm/i915/gt: Extract function to apply media fuses
2022-09-12 8:56 ` Andrzej Hajda
@ 2022-09-12 15:32 ` Lucas De Marchi
0 siblings, 0 replies; 9+ messages in thread
From: Lucas De Marchi @ 2022-09-12 15:32 UTC (permalink / raw)
To: Andrzej Hajda; +Cc: intel-gfx, dri-devel
On Mon, Sep 12, 2022 at 10:56:16AM +0200, Andrzej Hajda wrote:
>On 10.09.2022 01:18, Lucas De Marchi wrote:
>>Just like is done for compute and copy engines, extract a function to
>>handle media engines. While at it, be consistent on using or not the
>>uncore/gt/info variable aliases.
>>
>>Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
>>Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>>
>>diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
>>index b6602439224d..814f83b5fe59 100644
>>--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
>>+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
>>@@ -663,6 +663,74 @@ bool gen11_vdbox_has_sfc(struct intel_gt *gt,
>> return false;
>> }
>>+static void engine_mask_apply_media_fuses(struct intel_gt *gt)
>>+{
>>+ struct drm_i915_private *i915 = gt->i915;
>>+ unsigned int logical_vdbox = 0;
>>+ unsigned int i;
>>+ u32 media_fuse, fuse1;
>>+ u16 vdbox_mask;
>>+ u16 vebox_mask;
>>+
>>+ if (MEDIA_VER(gt->i915) < 11)
>>+ return;
>>+
>>+ /*
>>+ * On newer platforms the fusing register is called 'enable' and has
>>+ * enable semantics, while on older platforms it is called 'disable'
>>+ * and bits have disable semantices.
>>+ */
>>+ media_fuse = intel_uncore_read(gt->uncore, GEN11_GT_VEBOX_VDBOX_DISABLE);
>>+ if (MEDIA_VER_FULL(i915) < IP_VER(12, 50))
>>+ media_fuse = ~media_fuse;
>>+
>>+ vdbox_mask = media_fuse & GEN11_GT_VDBOX_DISABLE_MASK;
>>+ vebox_mask = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >>
>>+ GEN11_GT_VEBOX_DISABLE_SHIFT;
>>+
>>+ if (MEDIA_VER_FULL(i915) >= IP_VER(12, 50)) {
>>+ fuse1 = intel_uncore_read(gt->uncore, HSW_PAVP_FUSE1);
>>+ gt->info.sfc_mask = REG_FIELD_GET(XEHP_SFC_ENABLE_MASK, fuse1);
>>+ } else {
>>+ gt->info.sfc_mask = ~0;
>>+ }
>>+
>>+ for (i = 0; i < I915_MAX_VCS; i++) {
>>+ if (!HAS_ENGINE(gt, _VCS(i))) {
>>+ vdbox_mask &= ~BIT(i);
>>+ continue;
>>+ }
>>+
>>+ if (!(BIT(i) & vdbox_mask)) {
>>+ gt->info.engine_mask &= ~BIT(_VCS(i));
>>+ drm_dbg(&i915->drm, "vcs%u fused off\n", i);
>>+ continue;
>>+ }
>>+
>>+ if (gen11_vdbox_has_sfc(gt, i, logical_vdbox, vdbox_mask))
>>+ gt->info.vdbox_sfc_access |= BIT(i);
>>+ logical_vdbox++;
>>+ }
>>+ drm_dbg(&i915->drm, "vdbox enable: %04x, instances: %04lx\n",
>>+ vdbox_mask, VDBOX_MASK(gt));
>>+ GEM_BUG_ON(vdbox_mask != VDBOX_MASK(gt));
>>+
>>+ for (i = 0; i < I915_MAX_VECS; i++) {
>>+ if (!HAS_ENGINE(gt, _VECS(i))) {
>>+ vebox_mask &= ~BIT(i);
>>+ continue;
>>+ }
>>+
>>+ if (!(BIT(i) & vebox_mask)) {
>>+ gt->info.engine_mask &= ~BIT(_VECS(i));
>>+ drm_dbg(&i915->drm, "vecs%u fused off\n", i);
>>+ }
>>+ }
>>+ drm_dbg(&i915->drm, "vebox enable: %04x, instances: %04lx\n",
>>+ vebox_mask, VEBOX_MASK(gt));
>>+ GEM_BUG_ON(vebox_mask != VEBOX_MASK(gt));
>>+}
>>+
>> static void engine_mask_apply_compute_fuses(struct intel_gt *gt)
>> {
>> struct drm_i915_private *i915 = gt->i915;
>>@@ -671,6 +739,9 @@ static void engine_mask_apply_compute_fuses(struct intel_gt *gt)
>> unsigned long ccs_mask;
>> unsigned int i;
>>+ if (GRAPHICS_VER(i915) < 11)
>>+ return;
>>+
>
>Why there is no similar sentinel in case of engine_mask_apply_copy_fuses?
>Beside this:
>Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com>
I noticed it too while doing these patches. I have a pending one for
that, but it seems I failed to send it on Friday.
drm/i915: Skip applying copy engine fuses
Support for reading the fuses to check what are the Link Copy engines
was added in commit ad5f74f34201 ("drm/i915/pvc: read fuses for link
copy engines"). However they were added unconditionally because the
FUSE3 register is present since graphics version 10.
However the bitfield with meml3 fuses only exists since graphics version
12. Moreover, Link Copy engines are currently only available in PVC.
Tying additional copy engines to the meml3 fuses is not correct for
other platforms.
Make sure there is a check for `12.60 <= ver < 12.70`. Later platforms
may extend this function later if it's needed to fuse off copy engines.
Currently it's harmless as the Link Copy engines are still not exported:
info->engine_mask only has BCS0 set and the register is only read for
platforms that do have it.
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 6e0122b3dca2..ac5ff17888cd 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -694,6 +694,10 @@ static void engine_mask_apply_copy_fuses(struct intel_gt *gt)
unsigned long meml3_mask;
unsigned long quad;
+ if (!(GRAPHICS_VER_FULL(i915) >= IP_VER(12, 60) &&
+ GRAPHICS_VER_FULL(i915) < IP_VER(12, 70)))
+ return;
+
meml3_mask = intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3);
meml3_mask = REG_FIELD_GET(GEN12_MEML3_EN_MASK, meml3_mask);
^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [Intel-gfx] [PATCH v2 0/2] drm/i915: Media fuses future-proofing
2022-09-09 23:18 [Intel-gfx] [PATCH v2 0/2] drm/i915: Media fuses future-proofing Lucas De Marchi
` (3 preceding siblings ...)
2022-09-10 6:44 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
@ 2022-09-12 16:14 ` Lucas De Marchi
4 siblings, 0 replies; 9+ messages in thread
From: Lucas De Marchi @ 2022-09-12 16:14 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
On Fri, Sep 09, 2022 at 04:18:14PM -0700, Lucas De Marchi wrote:
>Update fuse handling for media to future-proof it.
>
>Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Thanks Matt Roper and Andrzej for the review. Applied.
Lucas De Marchi
^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2022-09-12 16:14 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz follow: Atom feed
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2022-09-09 23:18 [Intel-gfx] [PATCH v2 0/2] drm/i915: Media fuses future-proofing Lucas De Marchi
2022-09-09 23:18 ` [Intel-gfx] [PATCH v2 1/2] drm/i915/gt: Use MEDIA_VER() when handling media fuses Lucas De Marchi
2022-09-12 8:49 ` Andrzej Hajda
2022-09-09 23:18 ` [Intel-gfx] [PATCH v2 2/2] drm/i915/gt: Extract function to apply " Lucas De Marchi
2022-09-12 8:56 ` Andrzej Hajda
2022-09-12 15:32 ` Lucas De Marchi
2022-09-10 0:16 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Media fuses future-proofing Patchwork
2022-09-10 6:44 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2022-09-12 16:14 ` [Intel-gfx] [PATCH v2 0/2] " Lucas De Marchi
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