* [Intel-gfx] [PATCH v3] drm/i915/psr: Fix PSR_IMR/IIR field handling
@ 2022-09-27 11:09 Jouni Högander
2022-09-27 17:31 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/psr: Fix PSR_IMR/IIR field handling (rev3) Patchwork
` (3 more replies)
0 siblings, 4 replies; 6+ messages in thread
From: Jouni Högander @ 2022-09-27 11:09 UTC (permalink / raw)
To: intel-gfx
Current PSR code is supposed to use TRANSCODER_EDP to force 0 shift for
bits in PSR_IMR/IIR registers:
/*
* gen12+ has registers relative to transcoder and one per transcoder
* using the same bit definition: handle it as TRANSCODER_EDP to force
* 0 shift in bit definition
*/
At the time of writing the code assumption "TRANSCODER_EDP == 0" was made.
This is not the case and all fields in PSR_IMR and PSR_IIR are shifted
incorrectly if DISPLAY_VER >= 12.
Fix this by adding separate register field defines for >=12 and add bit
getter functions to keep code readability.
v3:
- Add separate register field defines (José)
- Add bit getter functions (José)
v2:
- Improve commit message (José)
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
---
drivers/gpu/drm/i915/display/intel_psr.c | 84 ++++++++++++++----------
drivers/gpu/drm/i915/i915_reg.h | 16 +++--
2 files changed, 62 insertions(+), 38 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 9def8d9fade6..d7b08a7da9e9 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -116,34 +116,56 @@ static bool psr2_global_enabled(struct intel_dp *intel_dp)
}
}
+static u32 psr_irq_psr_error_bit_get(struct intel_dp *intel_dp)
+{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+
+ return DISPLAY_VER(dev_priv) >= 12 ? TGL_EDP_PSR_ERROR :
+ EDP_PSR_ERROR(intel_dp->psr.transcoder);
+}
+
+static u32 psr_irq_post_exit_bit_get(struct intel_dp *intel_dp)
+{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+
+ return DISPLAY_VER(dev_priv) >= 12 ? TGL_EDP_PSR_POST_EXIT :
+ EDP_PSR_POST_EXIT(intel_dp->psr.transcoder);
+}
+
+static u32 psr_irq_pre_entry_bit_get(struct intel_dp *intel_dp)
+{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+
+ return DISPLAY_VER(dev_priv) >= 12 ? TGL_EDP_PSR_PRE_ENTRY :
+ EDP_PSR_PRE_ENTRY(intel_dp->psr.transcoder);
+}
+
+static u32 psr_irq_mask_get(struct intel_dp *intel_dp)
+{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+
+ return DISPLAY_VER(dev_priv) >= 12 ? TGL_EDP_PSR_MASK :
+ EDP_PSR_MASK(intel_dp->psr.transcoder);
+}
+
static void psr_irq_control(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- enum transcoder trans_shift;
i915_reg_t imr_reg;
u32 mask, val;
- /*
- * gen12+ has registers relative to transcoder and one per transcoder
- * using the same bit definition: handle it as TRANSCODER_EDP to force
- * 0 shift in bit definition
- */
- if (DISPLAY_VER(dev_priv) >= 12) {
- trans_shift = 0;
+ if (DISPLAY_VER(dev_priv) >= 12)
imr_reg = TRANS_PSR_IMR(intel_dp->psr.transcoder);
- } else {
- trans_shift = intel_dp->psr.transcoder;
+ else
imr_reg = EDP_PSR_IMR;
- }
- mask = EDP_PSR_ERROR(trans_shift);
+ mask = psr_irq_psr_error_bit_get(intel_dp);
if (intel_dp->psr.debug & I915_PSR_DEBUG_IRQ)
- mask |= EDP_PSR_POST_EXIT(trans_shift) |
- EDP_PSR_PRE_ENTRY(trans_shift);
+ mask |= psr_irq_post_exit_bit_get(intel_dp) |
+ psr_irq_pre_entry_bit_get(intel_dp);
- /* Warning: it is masking/setting reserved bits too */
val = intel_de_read(dev_priv, imr_reg);
- val &= ~EDP_PSR_TRANS_MASK(trans_shift);
+ val &= ~psr_irq_mask_get(intel_dp);
val |= ~mask;
intel_de_write(dev_priv, imr_reg, val);
}
@@ -191,25 +213,21 @@ void intel_psr_irq_handler(struct intel_dp *intel_dp, u32 psr_iir)
enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
ktime_t time_ns = ktime_get();
- enum transcoder trans_shift;
i915_reg_t imr_reg;
- if (DISPLAY_VER(dev_priv) >= 12) {
- trans_shift = 0;
+ if (DISPLAY_VER(dev_priv) >= 12)
imr_reg = TRANS_PSR_IMR(intel_dp->psr.transcoder);
- } else {
- trans_shift = intel_dp->psr.transcoder;
+ else
imr_reg = EDP_PSR_IMR;
- }
- if (psr_iir & EDP_PSR_PRE_ENTRY(trans_shift)) {
+ if (psr_iir & psr_irq_pre_entry_bit_get(intel_dp)) {
intel_dp->psr.last_entry_attempt = time_ns;
drm_dbg_kms(&dev_priv->drm,
"[transcoder %s] PSR entry attempt in 2 vblanks\n",
transcoder_name(cpu_transcoder));
}
- if (psr_iir & EDP_PSR_POST_EXIT(trans_shift)) {
+ if (psr_iir & psr_irq_post_exit_bit_get(intel_dp)) {
intel_dp->psr.last_exit = time_ns;
drm_dbg_kms(&dev_priv->drm,
"[transcoder %s] PSR exit completed\n",
@@ -226,7 +244,7 @@ void intel_psr_irq_handler(struct intel_dp *intel_dp, u32 psr_iir)
}
}
- if (psr_iir & EDP_PSR_ERROR(trans_shift)) {
+ if (psr_iir & psr_irq_psr_error_bit_get(intel_dp)) {
u32 val;
drm_warn(&dev_priv->drm, "[transcoder %s] PSR aux error\n",
@@ -243,7 +261,7 @@ void intel_psr_irq_handler(struct intel_dp *intel_dp, u32 psr_iir)
* or unset irq_aux_error.
*/
val = intel_de_read(dev_priv, imr_reg);
- val |= EDP_PSR_ERROR(trans_shift);
+ val |= psr_irq_psr_error_bit_get(intel_dp);
intel_de_write(dev_priv, imr_reg, val);
schedule_work(&intel_dp->psr.work);
@@ -1194,14 +1212,12 @@ static bool psr_interrupt_error_check(struct intel_dp *intel_dp)
* first time that PSR HW tries to activate so lets keep PSR disabled
* to avoid any rendering problems.
*/
- if (DISPLAY_VER(dev_priv) >= 12) {
+ if (DISPLAY_VER(dev_priv) >= 12)
val = intel_de_read(dev_priv,
TRANS_PSR_IIR(intel_dp->psr.transcoder));
- val &= EDP_PSR_ERROR(0);
- } else {
+ else
val = intel_de_read(dev_priv, EDP_PSR_IIR);
- val &= EDP_PSR_ERROR(intel_dp->psr.transcoder);
- }
+ val &= psr_irq_psr_error_bit_get(intel_dp);
if (val) {
intel_dp->psr.sink_not_reliable = true;
drm_dbg_kms(&dev_priv->drm,
@@ -2158,9 +2174,9 @@ static void intel_psr_work(struct work_struct *work)
/*
* We have to make sure PSR is ready for re-enable
- * otherwise it keeps disabled until next full enable/disable cycle.
- * PSR might take some time to get fully disabled
- * and be ready for re-enable.
+ * otherwise it keeps disabled until next full enable/disable
+ * cycle. PSR might take some time to get fully disabled and
+ * be ready for re-enable.
*/
if (!__psr_wait_for_idle_locked(intel_dp))
goto unlock;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5003a5ffbc6a..3c103aeaa2e4 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2168,10 +2168,18 @@
#define TRANS_PSR_IIR(tran) _MMIO_TRANS2(tran, _PSR_IIR_A)
#define _EDP_PSR_TRANS_SHIFT(trans) ((trans) == TRANSCODER_EDP ? \
0 : ((trans) - TRANSCODER_A + 1) * 8)
-#define EDP_PSR_TRANS_MASK(trans) (0x7 << _EDP_PSR_TRANS_SHIFT(trans))
-#define EDP_PSR_ERROR(trans) (0x4 << _EDP_PSR_TRANS_SHIFT(trans))
-#define EDP_PSR_POST_EXIT(trans) (0x2 << _EDP_PSR_TRANS_SHIFT(trans))
-#define EDP_PSR_PRE_ENTRY(trans) (0x1 << _EDP_PSR_TRANS_SHIFT(trans))
+#define TGL_EDP_PSR_MASK (0x7)
+#define TGL_EDP_PSR_ERROR (1 << 2)
+#define TGL_EDP_PSR_POST_EXIT (1 << 1)
+#define TGL_EDP_PSR_PRE_ENTRY (1 << 0)
+#define EDP_PSR_MASK(trans) (TGL_EDP_PSR_MASK << \
+ _EDP_PSR_TRANS_SHIFT(trans))
+#define EDP_PSR_ERROR(trans) (TGL_EDP_PSR_ERROR << \
+ _EDP_PSR_TRANS_SHIFT(trans))
+#define EDP_PSR_POST_EXIT(trans) (TGL_EDP_PSR_POST_EXIT << \
+ _EDP_PSR_TRANS_SHIFT(trans))
+#define EDP_PSR_PRE_ENTRY(trans) (TGL_EDP_PSR_PRE_ENTRY << \
+ _EDP_PSR_TRANS_SHIFT(trans))
#define _SRD_AUX_DATA_A 0x60814
#define _SRD_AUX_DATA_EDP 0x6f814
--
2.34.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/psr: Fix PSR_IMR/IIR field handling (rev3)
2022-09-27 11:09 [Intel-gfx] [PATCH v3] drm/i915/psr: Fix PSR_IMR/IIR field handling Jouni Högander
@ 2022-09-27 17:31 ` Patchwork
2022-09-27 17:54 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
` (2 subsequent siblings)
3 siblings, 0 replies; 6+ messages in thread
From: Patchwork @ 2022-09-27 17:31 UTC (permalink / raw)
To: Jouni Högander; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/psr: Fix PSR_IMR/IIR field handling (rev3)
URL : https://patchwork.freedesktop.org/series/108811/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 6+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/psr: Fix PSR_IMR/IIR field handling (rev3)
2022-09-27 11:09 [Intel-gfx] [PATCH v3] drm/i915/psr: Fix PSR_IMR/IIR field handling Jouni Högander
2022-09-27 17:31 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/psr: Fix PSR_IMR/IIR field handling (rev3) Patchwork
@ 2022-09-27 17:54 ` Patchwork
2022-09-28 7:29 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2022-09-29 13:16 ` [Intel-gfx] [PATCH v3] drm/i915/psr: Fix PSR_IMR/IIR field handling Souza, Jose
3 siblings, 0 replies; 6+ messages in thread
From: Patchwork @ 2022-09-27 17:54 UTC (permalink / raw)
To: Jouni Högander; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 4926 bytes --]
== Series Details ==
Series: drm/i915/psr: Fix PSR_IMR/IIR field handling (rev3)
URL : https://patchwork.freedesktop.org/series/108811/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12191 -> Patchwork_108811v3
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v3/index.html
Participating hosts (45 -> 43)
------------------------------
Missing (2): fi-hsw-4770 fi-bdw-samus
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_108811v3:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_pipe_crc_basic@suspend-read-crc@pipe-b-dp-2:
- {bat-dg2-11}: [PASS][1] -> [FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12191/bat-dg2-11/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-b-dp-2.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v3/bat-dg2-11/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-b-dp-2.html
Known issues
------------
Here are the changes found in Patchwork_108811v3 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-bsw-nick: NOTRUN -> [SKIP][3] ([fdo#109271] / [fdo#111827])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v3/fi-bsw-nick/igt@kms_chamelium@common-hpd-after-suspend.html
- fi-rkl-11600: NOTRUN -> [SKIP][4] ([fdo#111827])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v3/fi-rkl-11600/igt@kms_chamelium@common-hpd-after-suspend.html
* igt@kms_pipe_crc_basic@suspend-read-crc:
- fi-bsw-nick: NOTRUN -> [SKIP][5] ([fdo#109271])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v3/fi-bsw-nick/igt@kms_pipe_crc_basic@suspend-read-crc.html
#### Possible fixes ####
* igt@i915_selftest@live@execlists:
- fi-bsw-nick: [INCOMPLETE][6] -> [PASS][7]
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12191/fi-bsw-nick/igt@i915_selftest@live@execlists.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v3/fi-bsw-nick/igt@i915_selftest@live@execlists.html
* igt@i915_selftest@live@reset:
- {bat-rpls-1}: [DMESG-FAIL][8] ([i915#4983]) -> [PASS][9]
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12191/bat-rpls-1/igt@i915_selftest@live@reset.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v3/bat-rpls-1/igt@i915_selftest@live@reset.html
* igt@i915_suspend@basic-s3-without-i915:
- fi-rkl-11600: [INCOMPLETE][10] ([i915#5982]) -> [PASS][11]
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12191/fi-rkl-11600/igt@i915_suspend@basic-s3-without-i915.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v3/fi-rkl-11600/igt@i915_suspend@basic-s3-without-i915.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions-varying-size:
- fi-bsw-kefka: [FAIL][12] ([i915#6298]) -> [PASS][13]
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12191/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions-varying-size.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v3/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions-varying-size.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867
[i915#4258]: https://gitlab.freedesktop.org/drm/intel/issues/4258
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#5153]: https://gitlab.freedesktop.org/drm/intel/issues/5153
[i915#5982]: https://gitlab.freedesktop.org/drm/intel/issues/5982
[i915#6298]: https://gitlab.freedesktop.org/drm/intel/issues/6298
Build changes
-------------
* Linux: CI_DRM_12191 -> Patchwork_108811v3
CI-20190529: 20190529
CI_DRM_12191: b16161a277e2e302cf488cda83f48d6d1a3052f4 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6665: aecdb7ff269899b13b127bfa595d091af9781d94 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_108811v3: b16161a277e2e302cf488cda83f48d6d1a3052f4 @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
9e397e03ddac drm/i915/psr: Fix PSR_IMR/IIR field handling
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v3/index.html
[-- Attachment #2: Type: text/html, Size: 5594 bytes --]
^ permalink raw reply [flat|nested] 6+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/psr: Fix PSR_IMR/IIR field handling (rev3)
2022-09-27 11:09 [Intel-gfx] [PATCH v3] drm/i915/psr: Fix PSR_IMR/IIR field handling Jouni Högander
2022-09-27 17:31 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/psr: Fix PSR_IMR/IIR field handling (rev3) Patchwork
2022-09-27 17:54 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2022-09-28 7:29 ` Patchwork
2022-09-29 13:16 ` [Intel-gfx] [PATCH v3] drm/i915/psr: Fix PSR_IMR/IIR field handling Souza, Jose
3 siblings, 0 replies; 6+ messages in thread
From: Patchwork @ 2022-09-28 7:29 UTC (permalink / raw)
To: Jouni Högander; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 25977 bytes --]
== Series Details ==
Series: drm/i915/psr: Fix PSR_IMR/IIR field handling (rev3)
URL : https://patchwork.freedesktop.org/series/108811/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12191_full -> Patchwork_108811v3_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_108811v3_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_108811v3_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (9 -> 11)
------------------------------
Additional (2): shard-rkl shard-tglu
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_108811v3_full:
### IGT changes ###
#### Possible regressions ####
* igt@gem_exec_whisper@basic-queues-priority-all:
- shard-iclb: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12191/shard-iclb1/igt@gem_exec_whisper@basic-queues-priority-all.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v3/shard-iclb7/igt@gem_exec_whisper@basic-queues-priority-all.html
Known issues
------------
Here are the changes found in Patchwork_108811v3_full that come from known issues:
### CI changes ###
### IGT changes ###
#### Issues hit ####
* igt@feature_discovery@psr2:
- shard-iclb: [PASS][3] -> [SKIP][4] ([i915#658])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12191/shard-iclb2/igt@feature_discovery@psr2.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v3/shard-iclb1/igt@feature_discovery@psr2.html
* igt@gem_eio@reset-stress:
- shard-tglb: [PASS][5] -> [FAIL][6] ([i915#5784])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12191/shard-tglb8/igt@gem_eio@reset-stress.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v3/shard-tglb8/igt@gem_eio@reset-stress.html
* igt@gem_exec_balancer@parallel-bb-first:
- shard-iclb: [PASS][7] -> [SKIP][8] ([i915#4525]) +2 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12191/shard-iclb1/igt@gem_exec_balancer@parallel-bb-first.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v3/shard-iclb5/igt@gem_exec_balancer@parallel-bb-first.html
* igt@gem_exec_fair@basic-deadline:
- shard-glk: [PASS][9] -> [FAIL][10] ([i915#2846])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12191/shard-glk9/igt@gem_exec_fair@basic-deadline.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v3/shard-glk5/igt@gem_exec_fair@basic-deadline.html
* igt@gem_exec_fair@basic-flow@rcs0:
- shard-tglb: [PASS][11] -> [FAIL][12] ([i915#2842])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12191/shard-tglb3/igt@gem_exec_fair@basic-flow@rcs0.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v3/shard-tglb7/igt@gem_exec_fair@basic-flow@rcs0.html
* igt@gem_exec_fair@basic-none@vcs1:
- shard-iclb: NOTRUN -> [FAIL][13] ([i915#2842])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v3/shard-iclb4/igt@gem_exec_fair@basic-none@vcs1.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-iclb: [PASS][14] -> [FAIL][15] ([i915#2842])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12191/shard-iclb7/igt@gem_exec_fair@basic-throttle@rcs0.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v3/shard-iclb7/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@gem_lmem_swapping@parallel-multi:
- shard-tglb: NOTRUN -> [SKIP][16] ([i915#4613])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v3/shard-tglb2/igt@gem_lmem_swapping@parallel-multi.html
* igt@gem_userptr_blits@input-checking:
- shard-tglb: NOTRUN -> [DMESG-WARN][17] ([i915#4991])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v3/shard-tglb2/igt@gem_userptr_blits@input-checking.html
* igt@gem_workarounds@suspend-resume:
- shard-apl: [PASS][18] -> [DMESG-WARN][19] ([i915#180]) +1 similar issue
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12191/shard-apl1/igt@gem_workarounds@suspend-resume.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v3/shard-apl1/igt@gem_workarounds@suspend-resume.html
* igt@gen9_exec_parse@bb-chained:
- shard-tglb: NOTRUN -> [SKIP][20] ([i915#2527] / [i915#2856])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v3/shard-tglb2/igt@gen9_exec_parse@bb-chained.html
* igt@i915_pm_rc6_residency@media-rc6-accuracy:
- shard-tglb: NOTRUN -> [SKIP][21] ([fdo#109289])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v3/shard-tglb2/igt@i915_pm_rc6_residency@media-rc6-accuracy.html
* igt@kms_async_flips@alternate-sync-async-flip@pipe-a-hdmi-a-1:
- shard-glk: [PASS][22] -> [FAIL][23] ([i915#2521])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12191/shard-glk1/igt@kms_async_flips@alternate-sync-async-flip@pipe-a-hdmi-a-1.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v3/shard-glk9/igt@kms_async_flips@alternate-sync-async-flip@pipe-a-hdmi-a-1.html
* igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-async-flip:
- shard-tglb: NOTRUN -> [SKIP][24] ([i915#5286])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v3/shard-tglb2/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180:
- shard-tglb: NOTRUN -> [SKIP][25] ([fdo#111615])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v3/shard-tglb2/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180.html
* igt@kms_ccs@pipe-a-crc-primary-basic-4_tiled_dg2_mc_ccs:
- shard-tglb: NOTRUN -> [SKIP][26] ([i915#3689] / [i915#6095])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v3/shard-tglb2/igt@kms_ccs@pipe-a-crc-primary-basic-4_tiled_dg2_mc_ccs.html
* igt@kms_ccs@pipe-b-ccs-on-another-bo-y_tiled_gen12_mc_ccs:
- shard-tglb: NOTRUN -> [SKIP][27] ([i915#3689] / [i915#3886]) +1 similar issue
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v3/shard-tglb2/igt@kms_ccs@pipe-b-ccs-on-another-bo-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-c-random-ccs-data-4_tiled_dg2_rc_ccs_cc:
- shard-tglb: NOTRUN -> [SKIP][28] ([i915#6095]) +2 similar issues
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v3/shard-tglb2/igt@kms_ccs@pipe-c-random-ccs-data-4_tiled_dg2_rc_ccs_cc.html
* igt@kms_ccs@pipe-c-random-ccs-data-y_tiled_gen12_mc_ccs:
- shard-apl: NOTRUN -> [SKIP][29] ([fdo#109271] / [i915#3886]) +1 similar issue
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v3/shard-apl2/igt@kms_ccs@pipe-c-random-ccs-data-y_tiled_gen12_mc_ccs.html
* igt@kms_chamelium@dp-crc-single:
- shard-tglb: NOTRUN -> [SKIP][30] ([fdo#109284] / [fdo#111827]) +1 similar issue
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v3/shard-tglb2/igt@kms_chamelium@dp-crc-single.html
* igt@kms_cursor_crc@cursor-random-32x10:
- shard-tglb: NOTRUN -> [SKIP][31] ([i915#3555]) +2 similar issues
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v3/shard-tglb2/igt@kms_cursor_crc@cursor-random-32x10.html
* igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic:
- shard-tglb: NOTRUN -> [SKIP][32] ([fdo#109274] / [fdo#111825])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v3/shard-tglb2/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic.html
* igt@kms_cursor_legacy@flip-vs-cursor-crc-atomic:
- shard-snb: [PASS][33] -> [SKIP][34] ([fdo#109271]) +1 similar issue
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12191/shard-snb5/igt@kms_cursor_legacy@flip-vs-cursor-crc-atomic.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v3/shard-snb7/igt@kms_cursor_legacy@flip-vs-cursor-crc-atomic.html
* igt@kms_flip@2x-absolute-wf_vblank:
- shard-tglb: NOTRUN -> [SKIP][35] ([fdo#109274] / [fdo#111825] / [i915#3637] / [i915#3966])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v3/shard-tglb2/igt@kms_flip@2x-absolute-wf_vblank.html
* igt@kms_flip@2x-plain-flip:
- shard-tglb: NOTRUN -> [SKIP][36] ([fdo#109274] / [fdo#111825] / [i915#3637])
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v3/shard-tglb2/igt@kms_flip@2x-plain-flip.html
* igt@kms_flip@flip-vs-expired-vblank@b-hdmi-a1:
- shard-glk: [PASS][37] -> [FAIL][38] ([i915#79])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12191/shard-glk7/igt@kms_flip@flip-vs-expired-vblank@b-hdmi-a1.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v3/shard-glk7/igt@kms_flip@flip-vs-expired-vblank@b-hdmi-a1.html
* igt@kms_flip@flip-vs-suspend-interruptible@a-dp1:
- shard-apl: NOTRUN -> [DMESG-WARN][39] ([i915#180])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v3/shard-apl2/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
* igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling@pipe-a-default-mode:
- shard-iclb: NOTRUN -> [SKIP][40] ([i915#2672]) +1 similar issue
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v3/shard-iclb3/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-downscaling@pipe-a-valid-mode:
- shard-tglb: NOTRUN -> [SKIP][41] ([i915#2587] / [i915#2672])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v3/shard-tglb2/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-downscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling@pipe-a-default-mode:
- shard-iclb: [PASS][42] -> [SKIP][43] ([i915#3555])
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12191/shard-iclb3/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling@pipe-a-default-mode.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v3/shard-iclb2/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-upscaling@pipe-a-valid-mode:
- shard-iclb: NOTRUN -> [SKIP][44] ([i915#2587] / [i915#2672]) +1 similar issue
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v3/shard-iclb1/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-upscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-downscaling@pipe-a-default-mode:
- shard-iclb: NOTRUN -> [SKIP][45] ([i915#3555])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v3/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-downscaling@pipe-a-default-mode.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-fullscreen:
- shard-tglb: NOTRUN -> [SKIP][46] ([i915#6497]) +1 similar issue
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v3/shard-tglb2/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-fullscreen.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-blt:
- shard-tglb: NOTRUN -> [SKIP][47] ([fdo#109280] / [fdo#111825]) +5 similar issues
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v3/shard-tglb2/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-pwrite:
- shard-apl: NOTRUN -> [SKIP][48] ([fdo#109271]) +20 similar issues
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v3/shard-apl2/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-pwrite.html
* igt@kms_invalid_mode@clock-too-high@edp-1-pipe-d:
- shard-tglb: NOTRUN -> [SKIP][49] ([i915#6403]) +3 similar issues
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v3/shard-tglb2/igt@kms_invalid_mode@clock-too-high@edp-1-pipe-d.html
* igt@kms_pipe_crc_basic@hang-read-crc@pipe-a-vga-1:
- shard-snb: [PASS][50] -> [INCOMPLETE][51] ([i915#6952])
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12191/shard-snb2/igt@kms_pipe_crc_basic@hang-read-crc@pipe-a-vga-1.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v3/shard-snb4/igt@kms_pipe_crc_basic@hang-read-crc@pipe-a-vga-1.html
* igt@kms_psr@psr2_dpms:
- shard-iclb: [PASS][52] -> [SKIP][53] ([fdo#109441])
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12191/shard-iclb2/igt@kms_psr@psr2_dpms.html
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v3/shard-iclb8/igt@kms_psr@psr2_dpms.html
* igt@kms_psr@psr2_sprite_render:
- shard-tglb: NOTRUN -> [FAIL][54] ([i915#132] / [i915#3467]) +1 similar issue
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v3/shard-tglb2/igt@kms_psr@psr2_sprite_render.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180:
- shard-tglb: NOTRUN -> [SKIP][55] ([fdo#111615] / [i915#5289])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v3/shard-tglb2/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180.html
* igt@perf@polling-parameterized:
- shard-iclb: [PASS][56] -> [FAIL][57] ([i915#5639])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12191/shard-iclb6/igt@perf@polling-parameterized.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v3/shard-iclb4/igt@perf@polling-parameterized.html
* igt@sysfs_clients@sema-50:
- shard-tglb: NOTRUN -> [SKIP][58] ([i915#2994])
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v3/shard-tglb2/igt@sysfs_clients@sema-50.html
#### Possible fixes ####
* igt@drm_import_export@flink:
- shard-tglb: [INCOMPLETE][59] -> [PASS][60]
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12191/shard-tglb5/igt@drm_import_export@flink.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v3/shard-tglb2/igt@drm_import_export@flink.html
* igt@gem_eio@in-flight-contexts-1us:
- shard-iclb: [TIMEOUT][61] ([i915#3070]) -> [PASS][62]
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12191/shard-iclb2/igt@gem_eio@in-flight-contexts-1us.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v3/shard-iclb8/igt@gem_eio@in-flight-contexts-1us.html
* igt@gem_exec_balancer@parallel-keep-in-fence:
- shard-iclb: [SKIP][63] ([i915#4525]) -> [PASS][64] +1 similar issue
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12191/shard-iclb6/igt@gem_exec_balancer@parallel-keep-in-fence.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v3/shard-iclb4/igt@gem_exec_balancer@parallel-keep-in-fence.html
* igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-apl: [FAIL][65] ([i915#2842]) -> [PASS][66]
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12191/shard-apl7/igt@gem_exec_fair@basic-none-solo@rcs0.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v3/shard-apl3/igt@gem_exec_fair@basic-none-solo@rcs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: [FAIL][67] ([i915#2842]) -> [PASS][68]
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12191/shard-glk8/igt@gem_exec_fair@basic-pace-share@rcs0.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v3/shard-glk9/igt@gem_exec_fair@basic-pace-share@rcs0.html
- shard-tglb: [FAIL][69] ([i915#2842]) -> [PASS][70]
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12191/shard-tglb2/igt@gem_exec_fair@basic-pace-share@rcs0.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v3/shard-tglb3/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_mmap_offset@clear@smem0:
- shard-snb: [FAIL][71] -> [PASS][72]
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12191/shard-snb2/igt@gem_mmap_offset@clear@smem0.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v3/shard-snb4/igt@gem_mmap_offset@clear@smem0.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180:
- shard-glk: [DMESG-FAIL][73] ([i915#118] / [i915#1888]) -> [PASS][74]
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12191/shard-glk1/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v3/shard-glk7/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180.html
* igt@kms_flip@flip-vs-expired-vblank@c-hdmi-a1:
- shard-glk: [FAIL][75] ([i915#79]) -> [PASS][76]
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12191/shard-glk7/igt@kms_flip@flip-vs-expired-vblank@c-hdmi-a1.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v3/shard-glk7/igt@kms_flip@flip-vs-expired-vblank@c-hdmi-a1.html
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-c-edp-1:
- shard-iclb: [SKIP][77] ([i915#5235]) -> [PASS][78] +2 similar issues
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12191/shard-iclb2/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-c-edp-1.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v3/shard-iclb1/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-c-edp-1.html
* igt@kms_psr@psr2_sprite_plane_move:
- shard-iclb: [SKIP][79] ([fdo#109441]) -> [PASS][80] +1 similar issue
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12191/shard-iclb3/igt@kms_psr@psr2_sprite_plane_move.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v3/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html
* igt@kms_psr_stress_test@flip-primary-invalidate-overlay:
- shard-tglb: [SKIP][81] ([i915#5519]) -> [PASS][82]
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12191/shard-tglb7/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v3/shard-tglb1/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
* igt@perf_pmu@rc6-suspend:
- shard-apl: [DMESG-WARN][83] ([i915#180]) -> [PASS][84]
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12191/shard-apl1/igt@perf_pmu@rc6-suspend.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v3/shard-apl2/igt@perf_pmu@rc6-suspend.html
#### Warnings ####
* igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area:
- shard-iclb: [SKIP][85] ([fdo#111068] / [i915#658]) -> [SKIP][86] ([i915#2920])
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12191/shard-iclb5/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v3/shard-iclb2/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area:
- shard-iclb: [SKIP][87] ([i915#2920]) -> [SKIP][88] ([fdo#111068] / [i915#658])
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12191/shard-iclb2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v3/shard-iclb1/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area.html
* igt@kms_psr2_su@page_flip-p010:
- shard-iclb: [SKIP][89] ([fdo#109642] / [fdo#111068] / [i915#658]) -> [FAIL][90] ([i915#5939])
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12191/shard-iclb4/igt@kms_psr2_su@page_flip-p010.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v3/shard-iclb2/igt@kms_psr2_su@page_flip-p010.html
* igt@kms_rotation_crc@sprite-rotation-90-pos-100-0:
- shard-glk: [FAIL][91] -> [FAIL][92] ([i915#5852])
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12191/shard-glk7/igt@kms_rotation_crc@sprite-rotation-90-pos-100-0.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v3/shard-glk9/igt@kms_rotation_crc@sprite-rotation-90-pos-100-0.html
* igt@runner@aborted:
- shard-apl: ([FAIL][93], [FAIL][94], [FAIL][95]) ([i915#3002] / [i915#4312]) -> ([FAIL][96], [FAIL][97], [FAIL][98], [FAIL][99], [FAIL][100]) ([fdo#109271] / [i915#180] / [i915#3002] / [i915#4312])
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12191/shard-apl1/igt@runner@aborted.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12191/shard-apl3/igt@runner@aborted.html
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12191/shard-apl7/igt@runner@aborted.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v3/shard-apl6/igt@runner@aborted.html
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v3/shard-apl8/igt@runner@aborted.html
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v3/shard-apl1/igt@runner@aborted.html
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v3/shard-apl8/igt@runner@aborted.html
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v3/shard-apl2/igt@runner@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
[i915#132]: https://gitlab.freedesktop.org/drm/intel/issues/132
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
[i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521
[i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
[i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2846]: https://gitlab.freedesktop.org/drm/intel/issues/2846
[i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
[i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
[i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994
[i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002
[i915#3070]: https://gitlab.freedesktop.org/drm/intel/issues/3070
[i915#3467]: https://gitlab.freedesktop.org/drm/intel/issues/3467
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#3966]: https://gitlab.freedesktop.org/drm/intel/issues/3966
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4991]: https://gitlab.freedesktop.org/drm/intel/issues/4991
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
[i915#5519]: https://gitlab.freedesktop.org/drm/intel/issues/5519
[i915#5639]: https://gitlab.freedesktop.org/drm/intel/issues/5639
[i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784
[i915#5852]: https://gitlab.freedesktop.org/drm/intel/issues/5852
[i915#5939]: https://gitlab.freedesktop.org/drm/intel/issues/5939
[i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
[i915#6403]: https://gitlab.freedesktop.org/drm/intel/issues/6403
[i915#6497]: https://gitlab.freedesktop.org/drm/intel/issues/6497
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#6928]: https://gitlab.freedesktop.org/drm/intel/issues/6928
[i915#6952]: https://gitlab.freedesktop.org/drm/intel/issues/6952
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
Build changes
-------------
* Linux: CI_DRM_12191 -> Patchwork_108811v3
CI-20190529: 20190529
CI_DRM_12191: b16161a277e2e302cf488cda83f48d6d1a3052f4 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6665: aecdb7ff269899b13b127bfa595d091af9781d94 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_108811v3: b16161a277e2e302cf488cda83f48d6d1a3052f4 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v3/index.html
[-- Attachment #2: Type: text/html, Size: 30903 bytes --]
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [Intel-gfx] [PATCH v3] drm/i915/psr: Fix PSR_IMR/IIR field handling
2022-09-27 11:09 [Intel-gfx] [PATCH v3] drm/i915/psr: Fix PSR_IMR/IIR field handling Jouni Högander
` (2 preceding siblings ...)
2022-09-28 7:29 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
@ 2022-09-29 13:16 ` Souza, Jose
2022-09-29 13:18 ` Souza, Jose
3 siblings, 1 reply; 6+ messages in thread
From: Souza, Jose @ 2022-09-29 13:16 UTC (permalink / raw)
To: intel-gfx@lists.freedesktop.org, Hogander, Jouni
On Tue, 2022-09-27 at 14:09 +0300, Jouni Högander wrote:
> Current PSR code is supposed to use TRANSCODER_EDP to force 0 shift for
> bits in PSR_IMR/IIR registers:
>
> /*
> * gen12+ has registers relative to transcoder and one per transcoder
> * using the same bit definition: handle it as TRANSCODER_EDP to force
> * 0 shift in bit definition
> */
>
> At the time of writing the code assumption "TRANSCODER_EDP == 0" was made.
> This is not the case and all fields in PSR_IMR and PSR_IIR are shifted
> incorrectly if DISPLAY_VER >= 12.
>
> Fix this by adding separate register field defines for >=12 and add bit
> getter functions to keep code readability.
>
> v3:
> - Add separate register field defines (José)
> - Add bit getter functions (José)
> v2:
> - Improve commit message (José)
>
> Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_psr.c | 84 ++++++++++++++----------
> drivers/gpu/drm/i915/i915_reg.h | 16 +++--
> 2 files changed, 62 insertions(+), 38 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 9def8d9fade6..d7b08a7da9e9 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -116,34 +116,56 @@ static bool psr2_global_enabled(struct intel_dp *intel_dp)
> }
> }
>
> +static u32 psr_irq_psr_error_bit_get(struct intel_dp *intel_dp)
> +{
> + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> +
> + return DISPLAY_VER(dev_priv) >= 12 ? TGL_EDP_PSR_ERROR :
> + EDP_PSR_ERROR(intel_dp->psr.transcoder);
Drop the "_EDP", just go with TGL_PSR_ERROR... there is no reference to EDP or any transcoder in TGL+ it is one register per transcoder.
> +}
> +
> +static u32 psr_irq_post_exit_bit_get(struct intel_dp *intel_dp)
> +{
> + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> +
> + return DISPLAY_VER(dev_priv) >= 12 ? TGL_EDP_PSR_POST_EXIT :
> + EDP_PSR_POST_EXIT(intel_dp->psr.transcoder);
> +}
> +
> +static u32 psr_irq_pre_entry_bit_get(struct intel_dp *intel_dp)
> +{
> + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> +
> + return DISPLAY_VER(dev_priv) >= 12 ? TGL_EDP_PSR_PRE_ENTRY :
> + EDP_PSR_PRE_ENTRY(intel_dp->psr.transcoder);
> +}
> +
> +static u32 psr_irq_mask_get(struct intel_dp *intel_dp)
> +{
> + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> +
> + return DISPLAY_VER(dev_priv) >= 12 ? TGL_EDP_PSR_MASK :
> + EDP_PSR_MASK(intel_dp->psr.transcoder);
> +}
> +
> static void psr_irq_control(struct intel_dp *intel_dp)
> {
> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> - enum transcoder trans_shift;
> i915_reg_t imr_reg;
> u32 mask, val;
>
> - /*
> - * gen12+ has registers relative to transcoder and one per transcoder
> - * using the same bit definition: handle it as TRANSCODER_EDP to force
> - * 0 shift in bit definition
> - */
> - if (DISPLAY_VER(dev_priv) >= 12) {
> - trans_shift = 0;
> + if (DISPLAY_VER(dev_priv) >= 12)
> imr_reg = TRANS_PSR_IMR(intel_dp->psr.transcoder);
> - } else {
> - trans_shift = intel_dp->psr.transcoder;
> + else
> imr_reg = EDP_PSR_IMR;
> - }
>
> - mask = EDP_PSR_ERROR(trans_shift);
> + mask = psr_irq_psr_error_bit_get(intel_dp);
> if (intel_dp->psr.debug & I915_PSR_DEBUG_IRQ)
> - mask |= EDP_PSR_POST_EXIT(trans_shift) |
> - EDP_PSR_PRE_ENTRY(trans_shift);
> + mask |= psr_irq_post_exit_bit_get(intel_dp) |
> + psr_irq_pre_entry_bit_get(intel_dp);
>
> - /* Warning: it is masking/setting reserved bits too */
> val = intel_de_read(dev_priv, imr_reg);
> - val &= ~EDP_PSR_TRANS_MASK(trans_shift);
> + val &= ~psr_irq_mask_get(intel_dp);
> val |= ~mask;
> intel_de_write(dev_priv, imr_reg, val);
> }
> @@ -191,25 +213,21 @@ void intel_psr_irq_handler(struct intel_dp *intel_dp, u32 psr_iir)
> enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> ktime_t time_ns = ktime_get();
> - enum transcoder trans_shift;
> i915_reg_t imr_reg;
>
> - if (DISPLAY_VER(dev_priv) >= 12) {
> - trans_shift = 0;
> + if (DISPLAY_VER(dev_priv) >= 12)
> imr_reg = TRANS_PSR_IMR(intel_dp->psr.transcoder);
> - } else {
> - trans_shift = intel_dp->psr.transcoder;
> + else
> imr_reg = EDP_PSR_IMR;
> - }
>
> - if (psr_iir & EDP_PSR_PRE_ENTRY(trans_shift)) {
> + if (psr_iir & psr_irq_pre_entry_bit_get(intel_dp)) {
> intel_dp->psr.last_entry_attempt = time_ns;
> drm_dbg_kms(&dev_priv->drm,
> "[transcoder %s] PSR entry attempt in 2 vblanks\n",
> transcoder_name(cpu_transcoder));
> }
>
> - if (psr_iir & EDP_PSR_POST_EXIT(trans_shift)) {
> + if (psr_iir & psr_irq_post_exit_bit_get(intel_dp)) {
> intel_dp->psr.last_exit = time_ns;
> drm_dbg_kms(&dev_priv->drm,
> "[transcoder %s] PSR exit completed\n",
> @@ -226,7 +244,7 @@ void intel_psr_irq_handler(struct intel_dp *intel_dp, u32 psr_iir)
> }
> }
>
> - if (psr_iir & EDP_PSR_ERROR(trans_shift)) {
> + if (psr_iir & psr_irq_psr_error_bit_get(intel_dp)) {
> u32 val;
>
> drm_warn(&dev_priv->drm, "[transcoder %s] PSR aux error\n",
> @@ -243,7 +261,7 @@ void intel_psr_irq_handler(struct intel_dp *intel_dp, u32 psr_iir)
> * or unset irq_aux_error.
> */
> val = intel_de_read(dev_priv, imr_reg);
> - val |= EDP_PSR_ERROR(trans_shift);
> + val |= psr_irq_psr_error_bit_get(intel_dp);
> intel_de_write(dev_priv, imr_reg, val);
>
> schedule_work(&intel_dp->psr.work);
> @@ -1194,14 +1212,12 @@ static bool psr_interrupt_error_check(struct intel_dp *intel_dp)
> * first time that PSR HW tries to activate so lets keep PSR disabled
> * to avoid any rendering problems.
> */
> - if (DISPLAY_VER(dev_priv) >= 12) {
> + if (DISPLAY_VER(dev_priv) >= 12)
> val = intel_de_read(dev_priv,
> TRANS_PSR_IIR(intel_dp->psr.transcoder));
> - val &= EDP_PSR_ERROR(0);
> - } else {
> + else
> val = intel_de_read(dev_priv, EDP_PSR_IIR);
> - val &= EDP_PSR_ERROR(intel_dp->psr.transcoder);
> - }
> + val &= psr_irq_psr_error_bit_get(intel_dp);
> if (val) {
> intel_dp->psr.sink_not_reliable = true;
> drm_dbg_kms(&dev_priv->drm,
> @@ -2158,9 +2174,9 @@ static void intel_psr_work(struct work_struct *work)
>
> /*
> * We have to make sure PSR is ready for re-enable
> - * otherwise it keeps disabled until next full enable/disable cycle.
> - * PSR might take some time to get fully disabled
> - * and be ready for re-enable.
> + * otherwise it keeps disabled until next full enable/disable
> + * cycle. PSR might take some time to get fully disabled and
> + * be ready for re-enable.
Non-related change.
> */
> if (!__psr_wait_for_idle_locked(intel_dp))
> goto unlock;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 5003a5ffbc6a..3c103aeaa2e4 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2168,10 +2168,18 @@
> #define TRANS_PSR_IIR(tran) _MMIO_TRANS2(tran, _PSR_IIR_A)
> #define _EDP_PSR_TRANS_SHIFT(trans) ((trans) == TRANSCODER_EDP ? \
> 0 : ((trans) - TRANSCODER_A + 1) * 8)
> -#define EDP_PSR_TRANS_MASK(trans) (0x7 << _EDP_PSR_TRANS_SHIFT(trans))
> -#define EDP_PSR_ERROR(trans) (0x4 << _EDP_PSR_TRANS_SHIFT(trans))
> -#define EDP_PSR_POST_EXIT(trans) (0x2 << _EDP_PSR_TRANS_SHIFT(trans))
> -#define EDP_PSR_PRE_ENTRY(trans) (0x1 << _EDP_PSR_TRANS_SHIFT(trans))
> +#define TGL_EDP_PSR_MASK (0x7)
> +#define TGL_EDP_PSR_ERROR (1 << 2)
> +#define TGL_EDP_PSR_POST_EXIT (1 << 1)
> +#define TGL_EDP_PSR_PRE_ENTRY (1 << 0)
For new stuff REG_BIT() should be used.
> +#define EDP_PSR_MASK(trans) (TGL_EDP_PSR_MASK << \
> + _EDP_PSR_TRANS_SHIFT(trans))
> +#define EDP_PSR_ERROR(trans) (TGL_EDP_PSR_ERROR << \
> + _EDP_PSR_TRANS_SHIFT(trans))
> +#define EDP_PSR_POST_EXIT(trans) (TGL_EDP_PSR_POST_EXIT << \
> + _EDP_PSR_TRANS_SHIFT(trans))
> +#define EDP_PSR_PRE_ENTRY(trans) (TGL_EDP_PSR_PRE_ENTRY << \
> + _EDP_PSR_TRANS_SHIFT(trans))
>
> #define _SRD_AUX_DATA_A 0x60814
> #define _SRD_AUX_DATA_EDP 0x6f814
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [Intel-gfx] [PATCH v3] drm/i915/psr: Fix PSR_IMR/IIR field handling
2022-09-29 13:16 ` [Intel-gfx] [PATCH v3] drm/i915/psr: Fix PSR_IMR/IIR field handling Souza, Jose
@ 2022-09-29 13:18 ` Souza, Jose
0 siblings, 0 replies; 6+ messages in thread
From: Souza, Jose @ 2022-09-29 13:18 UTC (permalink / raw)
To: intel-gfx@lists.freedesktop.org, Hogander, Jouni
On Thu, 2022-09-29 at 06:16 -0700, José Roberto de Souza wrote:
> On Tue, 2022-09-27 at 14:09 +0300, Jouni Högander wrote:
> > Current PSR code is supposed to use TRANSCODER_EDP to force 0 shift for
> > bits in PSR_IMR/IIR registers:
> >
> > /*
> > * gen12+ has registers relative to transcoder and one per transcoder
> > * using the same bit definition: handle it as TRANSCODER_EDP to force
> > * 0 shift in bit definition
> > */
> >
> > At the time of writing the code assumption "TRANSCODER_EDP == 0" was made.
> > This is not the case and all fields in PSR_IMR and PSR_IIR are shifted
> > incorrectly if DISPLAY_VER >= 12.
> >
> > Fix this by adding separate register field defines for >=12 and add bit
> > getter functions to keep code readability.
> >
> > v3:
> > - Add separate register field defines (José)
> > - Add bit getter functions (José)
> > v2:
> > - Improve commit message (José)
Also missing the Fixes tag, so this gets backported to stable kernels.
> >
> > Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_psr.c | 84 ++++++++++++++----------
> > drivers/gpu/drm/i915/i915_reg.h | 16 +++--
> > 2 files changed, 62 insertions(+), 38 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> > index 9def8d9fade6..d7b08a7da9e9 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > @@ -116,34 +116,56 @@ static bool psr2_global_enabled(struct intel_dp *intel_dp)
> > }
> > }
> >
> > +static u32 psr_irq_psr_error_bit_get(struct intel_dp *intel_dp)
> > +{
> > + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > +
> > + return DISPLAY_VER(dev_priv) >= 12 ? TGL_EDP_PSR_ERROR :
> > + EDP_PSR_ERROR(intel_dp->psr.transcoder);
>
> Drop the "_EDP", just go with TGL_PSR_ERROR... there is no reference to EDP or any transcoder in TGL+ it is one register per transcoder.
>
> > +}
> > +
> > +static u32 psr_irq_post_exit_bit_get(struct intel_dp *intel_dp)
> > +{
> > + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > +
> > + return DISPLAY_VER(dev_priv) >= 12 ? TGL_EDP_PSR_POST_EXIT :
> > + EDP_PSR_POST_EXIT(intel_dp->psr.transcoder);
> > +}
> > +
> > +static u32 psr_irq_pre_entry_bit_get(struct intel_dp *intel_dp)
> > +{
> > + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > +
> > + return DISPLAY_VER(dev_priv) >= 12 ? TGL_EDP_PSR_PRE_ENTRY :
> > + EDP_PSR_PRE_ENTRY(intel_dp->psr.transcoder);
> > +}
> > +
> > +static u32 psr_irq_mask_get(struct intel_dp *intel_dp)
> > +{
> > + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > +
> > + return DISPLAY_VER(dev_priv) >= 12 ? TGL_EDP_PSR_MASK :
> > + EDP_PSR_MASK(intel_dp->psr.transcoder);
> > +}
> > +
> > static void psr_irq_control(struct intel_dp *intel_dp)
> > {
> > struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > - enum transcoder trans_shift;
> > i915_reg_t imr_reg;
> > u32 mask, val;
> >
> > - /*
> > - * gen12+ has registers relative to transcoder and one per transcoder
> > - * using the same bit definition: handle it as TRANSCODER_EDP to force
> > - * 0 shift in bit definition
> > - */
> > - if (DISPLAY_VER(dev_priv) >= 12) {
> > - trans_shift = 0;
> > + if (DISPLAY_VER(dev_priv) >= 12)
> > imr_reg = TRANS_PSR_IMR(intel_dp->psr.transcoder);
> > - } else {
> > - trans_shift = intel_dp->psr.transcoder;
> > + else
> > imr_reg = EDP_PSR_IMR;
> > - }
> >
> > - mask = EDP_PSR_ERROR(trans_shift);
> > + mask = psr_irq_psr_error_bit_get(intel_dp);
> > if (intel_dp->psr.debug & I915_PSR_DEBUG_IRQ)
> > - mask |= EDP_PSR_POST_EXIT(trans_shift) |
> > - EDP_PSR_PRE_ENTRY(trans_shift);
> > + mask |= psr_irq_post_exit_bit_get(intel_dp) |
> > + psr_irq_pre_entry_bit_get(intel_dp);
> >
> > - /* Warning: it is masking/setting reserved bits too */
> > val = intel_de_read(dev_priv, imr_reg);
> > - val &= ~EDP_PSR_TRANS_MASK(trans_shift);
> > + val &= ~psr_irq_mask_get(intel_dp);
> > val |= ~mask;
> > intel_de_write(dev_priv, imr_reg, val);
> > }
> > @@ -191,25 +213,21 @@ void intel_psr_irq_handler(struct intel_dp *intel_dp, u32 psr_iir)
> > enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
> > struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > ktime_t time_ns = ktime_get();
> > - enum transcoder trans_shift;
> > i915_reg_t imr_reg;
> >
> > - if (DISPLAY_VER(dev_priv) >= 12) {
> > - trans_shift = 0;
> > + if (DISPLAY_VER(dev_priv) >= 12)
> > imr_reg = TRANS_PSR_IMR(intel_dp->psr.transcoder);
> > - } else {
> > - trans_shift = intel_dp->psr.transcoder;
> > + else
> > imr_reg = EDP_PSR_IMR;
> > - }
> >
> > - if (psr_iir & EDP_PSR_PRE_ENTRY(trans_shift)) {
> > + if (psr_iir & psr_irq_pre_entry_bit_get(intel_dp)) {
> > intel_dp->psr.last_entry_attempt = time_ns;
> > drm_dbg_kms(&dev_priv->drm,
> > "[transcoder %s] PSR entry attempt in 2 vblanks\n",
> > transcoder_name(cpu_transcoder));
> > }
> >
> > - if (psr_iir & EDP_PSR_POST_EXIT(trans_shift)) {
> > + if (psr_iir & psr_irq_post_exit_bit_get(intel_dp)) {
> > intel_dp->psr.last_exit = time_ns;
> > drm_dbg_kms(&dev_priv->drm,
> > "[transcoder %s] PSR exit completed\n",
> > @@ -226,7 +244,7 @@ void intel_psr_irq_handler(struct intel_dp *intel_dp, u32 psr_iir)
> > }
> > }
> >
> > - if (psr_iir & EDP_PSR_ERROR(trans_shift)) {
> > + if (psr_iir & psr_irq_psr_error_bit_get(intel_dp)) {
> > u32 val;
> >
> > drm_warn(&dev_priv->drm, "[transcoder %s] PSR aux error\n",
> > @@ -243,7 +261,7 @@ void intel_psr_irq_handler(struct intel_dp *intel_dp, u32 psr_iir)
> > * or unset irq_aux_error.
> > */
> > val = intel_de_read(dev_priv, imr_reg);
> > - val |= EDP_PSR_ERROR(trans_shift);
> > + val |= psr_irq_psr_error_bit_get(intel_dp);
> > intel_de_write(dev_priv, imr_reg, val);
> >
> > schedule_work(&intel_dp->psr.work);
> > @@ -1194,14 +1212,12 @@ static bool psr_interrupt_error_check(struct intel_dp *intel_dp)
> > * first time that PSR HW tries to activate so lets keep PSR disabled
> > * to avoid any rendering problems.
> > */
> > - if (DISPLAY_VER(dev_priv) >= 12) {
> > + if (DISPLAY_VER(dev_priv) >= 12)
> > val = intel_de_read(dev_priv,
> > TRANS_PSR_IIR(intel_dp->psr.transcoder));
> > - val &= EDP_PSR_ERROR(0);
> > - } else {
> > + else
> > val = intel_de_read(dev_priv, EDP_PSR_IIR);
> > - val &= EDP_PSR_ERROR(intel_dp->psr.transcoder);
> > - }
> > + val &= psr_irq_psr_error_bit_get(intel_dp);
> > if (val) {
> > intel_dp->psr.sink_not_reliable = true;
> > drm_dbg_kms(&dev_priv->drm,
> > @@ -2158,9 +2174,9 @@ static void intel_psr_work(struct work_struct *work)
> >
> > /*
> > * We have to make sure PSR is ready for re-enable
> > - * otherwise it keeps disabled until next full enable/disable cycle.
> > - * PSR might take some time to get fully disabled
> > - * and be ready for re-enable.
> > + * otherwise it keeps disabled until next full enable/disable
> > + * cycle. PSR might take some time to get fully disabled and
> > + * be ready for re-enable.
>
> Non-related change.
>
> > */
> > if (!__psr_wait_for_idle_locked(intel_dp))
> > goto unlock;
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 5003a5ffbc6a..3c103aeaa2e4 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -2168,10 +2168,18 @@
> > #define TRANS_PSR_IIR(tran) _MMIO_TRANS2(tran, _PSR_IIR_A)
> > #define _EDP_PSR_TRANS_SHIFT(trans) ((trans) == TRANSCODER_EDP ? \
> > 0 : ((trans) - TRANSCODER_A + 1) * 8)
> > -#define EDP_PSR_TRANS_MASK(trans) (0x7 << _EDP_PSR_TRANS_SHIFT(trans))
> > -#define EDP_PSR_ERROR(trans) (0x4 << _EDP_PSR_TRANS_SHIFT(trans))
> > -#define EDP_PSR_POST_EXIT(trans) (0x2 << _EDP_PSR_TRANS_SHIFT(trans))
> > -#define EDP_PSR_PRE_ENTRY(trans) (0x1 << _EDP_PSR_TRANS_SHIFT(trans))
> > +#define TGL_EDP_PSR_MASK (0x7)
> > +#define TGL_EDP_PSR_ERROR (1 << 2)
> > +#define TGL_EDP_PSR_POST_EXIT (1 << 1)
> > +#define TGL_EDP_PSR_PRE_ENTRY (1 << 0)
>
> For new stuff REG_BIT() should be used.
>
> > +#define EDP_PSR_MASK(trans) (TGL_EDP_PSR_MASK << \
> > + _EDP_PSR_TRANS_SHIFT(trans))
> > +#define EDP_PSR_ERROR(trans) (TGL_EDP_PSR_ERROR << \
> > + _EDP_PSR_TRANS_SHIFT(trans))
> > +#define EDP_PSR_POST_EXIT(trans) (TGL_EDP_PSR_POST_EXIT << \
> > + _EDP_PSR_TRANS_SHIFT(trans))
> > +#define EDP_PSR_PRE_ENTRY(trans) (TGL_EDP_PSR_PRE_ENTRY << \
> > + _EDP_PSR_TRANS_SHIFT(trans))
> >
> > #define _SRD_AUX_DATA_A 0x60814
> > #define _SRD_AUX_DATA_EDP 0x6f814
>
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2022-09-29 13:18 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
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2022-09-27 11:09 [Intel-gfx] [PATCH v3] drm/i915/psr: Fix PSR_IMR/IIR field handling Jouni Högander
2022-09-27 17:31 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/psr: Fix PSR_IMR/IIR field handling (rev3) Patchwork
2022-09-27 17:54 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-09-28 7:29 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2022-09-29 13:16 ` [Intel-gfx] [PATCH v3] drm/i915/psr: Fix PSR_IMR/IIR field handling Souza, Jose
2022-09-29 13:18 ` Souza, Jose
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