* [Intel-gfx] [PATCH v3 0/4] drm/i915/tgl+: Fix race conditions during DKL PHY accesses
@ 2022-10-25 10:26 Imre Deak
2022-10-25 10:26 ` [Intel-gfx] [PATCH v3 1/4] drm/i915/tgl+: Add locking around DKL PHY register accesses Imre Deak
` (10 more replies)
0 siblings, 11 replies; 16+ messages in thread
From: Imre Deak @ 2022-10-25 10:26 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula
This is v3 of [1] fixing checkpatch issues and adding the Acked-bys.
[1] https://lore.kernel.org/intel-gfx/20221020160022.1823365-1-imre.deak@intel.com/T/#md92b51e5698295844f5436b479fdd473bf430882
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Imre Deak (4):
drm/i915/tgl+: Add locking around DKL PHY register accesses
drm/i915: Rename intel_tc_phy_regs.h to intel_mg_phy_regs.h
drm/i915/tgl+: Move DKL PHY register definitions to
intel_dkl_phy_regs.h
drm/i915/tgl+: Sanitize DKL PHY register definitions
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/display/intel_ddi.c | 71 +++---
.../gpu/drm/i915/display/intel_display_core.h | 8 +
.../i915/display/intel_display_power_well.c | 8 +-
drivers/gpu/drm/i915/display/intel_dkl_phy.c | 106 +++++++++
drivers/gpu/drm/i915/display/intel_dkl_phy.h | 24 +++
.../gpu/drm/i915/display/intel_dkl_phy_regs.h | 204 ++++++++++++++++++
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 62 +++---
...ntel_tc_phy_regs.h => intel_mg_phy_regs.h} | 6 +-
drivers/gpu/drm/i915/display/intel_tc.c | 3 +-
drivers/gpu/drm/i915/i915_driver.c | 1 +
drivers/gpu/drm/i915/i915_reg.h | 176 ---------------
12 files changed, 412 insertions(+), 258 deletions(-)
create mode 100644 drivers/gpu/drm/i915/display/intel_dkl_phy.c
create mode 100644 drivers/gpu/drm/i915/display/intel_dkl_phy.h
create mode 100644 drivers/gpu/drm/i915/display/intel_dkl_phy_regs.h
rename drivers/gpu/drm/i915/display/{intel_tc_phy_regs.h => intel_mg_phy_regs.h} (99%)
--
2.37.1
^ permalink raw reply [flat|nested] 16+ messages in thread* [Intel-gfx] [PATCH v3 1/4] drm/i915/tgl+: Add locking around DKL PHY register accesses 2022-10-25 10:26 [Intel-gfx] [PATCH v3 0/4] drm/i915/tgl+: Fix race conditions during DKL PHY accesses Imre Deak @ 2022-10-25 10:26 ` Imre Deak 2022-10-25 11:44 ` [Intel-gfx] [PATCH v4 " Imre Deak 2022-10-25 10:26 ` [Intel-gfx] [PATCH v3 2/4] drm/i915: Rename intel_tc_phy_regs.h to intel_mg_phy_regs.h Imre Deak ` (9 subsequent siblings) 10 siblings, 1 reply; 16+ messages in thread From: Imre Deak @ 2022-10-25 10:26 UTC (permalink / raw) To: intel-gfx; +Cc: Jani Nikula, stable Accessing the TypeC DKL PHY registers during modeset-commit, -verification, DP link-retraining and AUX power well toggling is racy due to these code paths being concurrent and the PHY register bank selection register (HIP_INDEX_REG) being shared between PHY instances (aka TC ports) and the bank selection being not atomic wrt. the actual PHY register access. Add the required locking around each PHY register bank selection-> register access sequence. Kudos to Ville for noticing the race conditions. v2: - Add the DKL PHY register accessors to intel_dkl_phy.[ch]. (Jani) - Make the DKL_REG_TC_PORT macro independent of PHY internals. - Move initing the DKL PHY lock to a more logical place. v3: - Fix parameter reuse in the DKL_REG_TC_PORT definition. - Document the usage of phy_lock. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Cc: <stable@vger.kernel.org> # v5.5+ Acked-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> --- drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/display/intel_ddi.c | 68 +++++------ .../gpu/drm/i915/display/intel_display_core.h | 8 ++ .../i915/display/intel_display_power_well.c | 7 +- drivers/gpu/drm/i915/display/intel_dkl_phy.c | 109 ++++++++++++++++++ drivers/gpu/drm/i915/display/intel_dkl_phy.h | 24 ++++ drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 59 +++++----- drivers/gpu/drm/i915/i915_driver.c | 1 + drivers/gpu/drm/i915/i915_reg.h | 3 + 9 files changed, 204 insertions(+), 76 deletions(-) create mode 100644 drivers/gpu/drm/i915/display/intel_dkl_phy.c create mode 100644 drivers/gpu/drm/i915/display/intel_dkl_phy.h diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile index 2535593ab379e..51704b54317cf 100644 --- a/drivers/gpu/drm/i915/Makefile +++ b/drivers/gpu/drm/i915/Makefile @@ -285,6 +285,7 @@ i915-y += \ display/intel_ddi.o \ display/intel_ddi_buf_trans.o \ display/intel_display_trace.o \ + display/intel_dkl_phy.o \ display/intel_dp.o \ display/intel_dp_aux.o \ display/intel_dp_aux_backlight.o \ diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 971356237eca3..7708ccbbdeb75 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -43,6 +43,7 @@ #include "intel_de.h" #include "intel_display_power.h" #include "intel_display_types.h" +#include "intel_dkl_phy.h" #include "intel_dp.h" #include "intel_dp_link_training.h" #include "intel_dp_mst.h" @@ -1262,33 +1263,30 @@ static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder, for (ln = 0; ln < 2; ln++) { int level; - intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), - HIP_INDEX_VAL(tc_port, ln)); - - intel_de_write(dev_priv, DKL_TX_PMD_LANE_SUS(tc_port), 0); + intel_dkl_phy_write(dev_priv, DKL_TX_PMD_LANE_SUS(tc_port), ln, 0); level = intel_ddi_level(encoder, crtc_state, 2*ln+0); - intel_de_rmw(dev_priv, DKL_TX_DPCNTL0(tc_port), - DKL_TX_PRESHOOT_COEFF_MASK | - DKL_TX_DE_EMPAHSIS_COEFF_MASK | - DKL_TX_VSWING_CONTROL_MASK, - DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot) | - DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) | - DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing)); + intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL0(tc_port), ln, + DKL_TX_PRESHOOT_COEFF_MASK | + DKL_TX_DE_EMPAHSIS_COEFF_MASK | + DKL_TX_VSWING_CONTROL_MASK, + DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot) | + DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) | + DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing)); level = intel_ddi_level(encoder, crtc_state, 2*ln+1); - intel_de_rmw(dev_priv, DKL_TX_DPCNTL1(tc_port), - DKL_TX_PRESHOOT_COEFF_MASK | - DKL_TX_DE_EMPAHSIS_COEFF_MASK | - DKL_TX_VSWING_CONTROL_MASK, - DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot) | - DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) | - DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing)); + intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL1(tc_port), ln, + DKL_TX_PRESHOOT_COEFF_MASK | + DKL_TX_DE_EMPAHSIS_COEFF_MASK | + DKL_TX_VSWING_CONTROL_MASK, + DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot) | + DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) | + DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing)); - intel_de_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port), - DKL_TX_DP20BITMODE, 0); + intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port), ln, + DKL_TX_DP20BITMODE, 0); if (IS_ALDERLAKE_P(dev_priv)) { u32 val; @@ -1306,10 +1304,10 @@ static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder, val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(0); } - intel_de_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port), - DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK | - DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK, - val); + intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port), ln, + DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK | + DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK, + val); } } } @@ -2019,12 +2017,8 @@ icl_program_mg_dp_mode(struct intel_digital_port *dig_port, return; if (DISPLAY_VER(dev_priv) >= 12) { - intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), - HIP_INDEX_VAL(tc_port, 0x0)); - ln0 = intel_de_read(dev_priv, DKL_DP_MODE(tc_port)); - intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), - HIP_INDEX_VAL(tc_port, 0x1)); - ln1 = intel_de_read(dev_priv, DKL_DP_MODE(tc_port)); + ln0 = intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port), 0); + ln1 = intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port), 1); } else { ln0 = intel_de_read(dev_priv, MG_DP_MODE(0, tc_port)); ln1 = intel_de_read(dev_priv, MG_DP_MODE(1, tc_port)); @@ -2085,12 +2079,8 @@ icl_program_mg_dp_mode(struct intel_digital_port *dig_port, } if (DISPLAY_VER(dev_priv) >= 12) { - intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), - HIP_INDEX_VAL(tc_port, 0x0)); - intel_de_write(dev_priv, DKL_DP_MODE(tc_port), ln0); - intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), - HIP_INDEX_VAL(tc_port, 0x1)); - intel_de_write(dev_priv, DKL_DP_MODE(tc_port), ln1); + intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port), 0, ln0); + intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port), 1, ln1); } else { intel_de_write(dev_priv, MG_DP_MODE(0, tc_port), ln0); intel_de_write(dev_priv, MG_DP_MODE(1, tc_port), ln1); @@ -3094,10 +3084,8 @@ static void adlp_tbt_to_dp_alt_switch_wa(struct intel_encoder *encoder) enum tc_port tc_port = intel_port_to_tc(i915, encoder->port); int ln; - for (ln = 0; ln < 2; ln++) { - intel_de_write(i915, HIP_INDEX_REG(tc_port), HIP_INDEX_VAL(tc_port, ln)); - intel_de_rmw(i915, DKL_PCS_DW5(tc_port), DKL_PCS_DW5_CORE_SOFTRESET, 0); - } + for (ln = 0; ln < 2; ln++) + intel_dkl_phy_rmw(i915, DKL_PCS_DW5(tc_port), ln, DKL_PCS_DW5_CORE_SOFTRESET, 0); } static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp, diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h index 96cf994b0ad1f..9b51148e8ba56 100644 --- a/drivers/gpu/drm/i915/display/intel_display_core.h +++ b/drivers/gpu/drm/i915/display/intel_display_core.h @@ -315,6 +315,14 @@ struct intel_display { struct intel_global_obj obj; } dbuf; + struct { + /* + * dkl.phy_lock protects against concurrent access of the + * Dekel TypeC PHYs. + */ + spinlock_t phy_lock; + } dkl; + struct { /* VLV/CHV/BXT/GLK DSI MMIO register base address */ u32 mmio_base; diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c index df7ee4969ef17..1d18eee562534 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c @@ -12,6 +12,7 @@ #include "intel_de.h" #include "intel_display_power_well.h" #include "intel_display_types.h" +#include "intel_dkl_phy.h" #include "intel_dmc.h" #include "intel_dpio_phy.h" #include "intel_dpll.h" @@ -529,11 +530,9 @@ icl_tc_phy_aux_power_well_enable(struct drm_i915_private *dev_priv, enum tc_port tc_port; tc_port = TGL_AUX_PW_TO_TC_PORT(i915_power_well_instance(power_well)->hsw.idx); - intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), - HIP_INDEX_VAL(tc_port, 0x2)); - if (intel_de_wait_for_set(dev_priv, DKL_CMN_UC_DW_27(tc_port), - DKL_CMN_UC_DW27_UC_HEALTH, 1)) + if (wait_for(intel_dkl_phy_read(dev_priv, DKL_CMN_UC_DW_27(tc_port), 2) & + DKL_CMN_UC_DW27_UC_HEALTH, 1)) drm_warn(&dev_priv->drm, "Timeout waiting TC uC health\n"); } diff --git a/drivers/gpu/drm/i915/display/intel_dkl_phy.c b/drivers/gpu/drm/i915/display/intel_dkl_phy.c new file mode 100644 index 0000000000000..710b030c7ed54 --- /dev/null +++ b/drivers/gpu/drm/i915/display/intel_dkl_phy.c @@ -0,0 +1,109 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright © 2022 Intel Corporation + */ + +#include "i915_drv.h" +#include "i915_reg.h" + +#include "intel_de.h" +#include "intel_display.h" +#include "intel_dkl_phy.h" + +static void +dkl_phy_set_hip_idx(struct drm_i915_private *i915, i915_reg_t reg, int idx) +{ + enum tc_port tc_port = DKL_REG_TC_PORT(reg); + + drm_WARN_ON(&i915->drm, tc_port < TC_PORT_1 || tc_port >= I915_MAX_TC_PORTS); + + intel_de_write(i915, + HIP_INDEX_REG(tc_port), + HIP_INDEX_VAL(tc_port, idx)); +} + +/** + * intel_dkl_phy_read - read a Dekel PHY register + * @i915: i915 device instance + * @reg: Dekel PHY register + * @ln: lane instance of @reg + * + * Read the @reg Dekel PHY register. + * + * Returns the read value. + */ +u32 +intel_dkl_phy_read(struct drm_i915_private *i915, i915_reg_t reg, int ln) +{ + u32 val; + + spin_lock(&i915->display.dkl.phy_lock); + + dkl_phy_set_hip_idx(i915, reg, ln); + val = intel_de_read(i915, reg); + + spin_unlock(&i915->display.dkl.phy_lock); + + return val; +} + +/** + * intel_dkl_phy_write - write a Dekel PHY register + * @i915: i915 device instance + * @reg: Dekel PHY register + * @ln: lane instance of @reg + * @val: value to write + * + * Write @val to the @reg Dekel PHY register. + */ +void +intel_dkl_phy_write(struct drm_i915_private *i915, i915_reg_t reg, int ln, u32 val) +{ + spin_lock(&i915->display.dkl.phy_lock); + + dkl_phy_set_hip_idx(i915, reg, ln); + intel_de_write(i915, reg, val); + + spin_unlock(&i915->display.dkl.phy_lock); +} + +/** + * intel_dkl_phy_rmw - read-modify-write a Dekel PHY register + * @i915: i915 device instance + * @reg: Dekel PHY register + * @ln: lane instance of @reg + * @clear: mask to clear + * @set: mask to set + * + * Read the @reg Dekel PHY register, clearing then setting the @clear/@set bits in it, and writing + * this value back to the register if the value differs from the read one. + */ +void +intel_dkl_phy_rmw(struct drm_i915_private *i915, i915_reg_t reg, int ln, u32 clear, u32 set) +{ + spin_lock(&i915->display.dkl.phy_lock); + + dkl_phy_set_hip_idx(i915, reg, ln); + intel_de_rmw(i915, reg, clear, set); + + spin_unlock(&i915->display.dkl.phy_lock); +} + +/** + * intel_dkl_phy_posting_read - do a posting read from a Dekel PHY register + * @i915: i915 device instance + * @reg: Dekel PHY register + * @ln: lane instance of @reg + * + * Read the @reg Dekel PHY register without returning the read value. + */ +void +intel_dkl_phy_posting_read(struct drm_i915_private *i915, i915_reg_t reg, int ln) +{ + spin_lock(&i915->display.dkl.phy_lock); + + dkl_phy_set_hip_idx(i915, reg, ln); + intel_de_posting_read(i915, reg); + + spin_unlock(&i915->display.dkl.phy_lock); +} diff --git a/drivers/gpu/drm/i915/display/intel_dkl_phy.h b/drivers/gpu/drm/i915/display/intel_dkl_phy.h new file mode 100644 index 0000000000000..260ad121a0b18 --- /dev/null +++ b/drivers/gpu/drm/i915/display/intel_dkl_phy.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright © 2022 Intel Corporation + */ + +#ifndef __INTEL_DKL_PHY_H__ +#define __INTEL_DKL_PHY_H__ + +#include <linux/types.h> + +#include "i915_reg_defs.h" + +struct drm_i915_private; + +u32 +intel_dkl_phy_read(struct drm_i915_private *i915, i915_reg_t reg, int ln); +void +intel_dkl_phy_write(struct drm_i915_private *i915, i915_reg_t reg, int ln, u32 val); +void +intel_dkl_phy_rmw(struct drm_i915_private *i915, i915_reg_t reg, int ln, u32 clear, u32 set); +void +intel_dkl_phy_posting_read(struct drm_i915_private *i915, i915_reg_t reg, int ln); + +#endif /* __INTEL_DKL_PHY_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c index b63600d8ebeb0..8bbc2b5e50ed9 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c @@ -25,6 +25,7 @@ #include "intel_de.h" #include "intel_display_types.h" +#include "intel_dkl_phy.h" #include "intel_dpio_phy.h" #include "intel_dpll.h" #include "intel_dpll_mgr.h" @@ -3486,15 +3487,12 @@ static bool dkl_pll_get_hw_state(struct drm_i915_private *dev_priv, * All registers read here have the same HIP_INDEX_REG even though * they are on different building blocks */ - intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), - HIP_INDEX_VAL(tc_port, 0x2)); - - hw_state->mg_refclkin_ctl = intel_de_read(dev_priv, - DKL_REFCLKIN_CTL(tc_port)); + hw_state->mg_refclkin_ctl = intel_dkl_phy_read(dev_priv, + DKL_REFCLKIN_CTL(tc_port), 2); hw_state->mg_refclkin_ctl &= MG_REFCLKIN_CTL_OD_2_MUX_MASK; hw_state->mg_clktop2_hsclkctl = - intel_de_read(dev_priv, DKL_CLKTOP2_HSCLKCTL(tc_port)); + intel_dkl_phy_read(dev_priv, DKL_CLKTOP2_HSCLKCTL(tc_port), 2); hw_state->mg_clktop2_hsclkctl &= MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK | MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK | @@ -3502,32 +3500,32 @@ static bool dkl_pll_get_hw_state(struct drm_i915_private *dev_priv, MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK; hw_state->mg_clktop2_coreclkctl1 = - intel_de_read(dev_priv, DKL_CLKTOP2_CORECLKCTL1(tc_port)); + intel_dkl_phy_read(dev_priv, DKL_CLKTOP2_CORECLKCTL1(tc_port), 2); hw_state->mg_clktop2_coreclkctl1 &= MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK; - hw_state->mg_pll_div0 = intel_de_read(dev_priv, DKL_PLL_DIV0(tc_port)); + hw_state->mg_pll_div0 = intel_dkl_phy_read(dev_priv, DKL_PLL_DIV0(tc_port), 2); val = DKL_PLL_DIV0_MASK; if (dev_priv->display.vbt.override_afc_startup) val |= DKL_PLL_DIV0_AFC_STARTUP_MASK; hw_state->mg_pll_div0 &= val; - hw_state->mg_pll_div1 = intel_de_read(dev_priv, DKL_PLL_DIV1(tc_port)); + hw_state->mg_pll_div1 = intel_dkl_phy_read(dev_priv, DKL_PLL_DIV1(tc_port), 2); hw_state->mg_pll_div1 &= (DKL_PLL_DIV1_IREF_TRIM_MASK | DKL_PLL_DIV1_TDC_TARGET_CNT_MASK); - hw_state->mg_pll_ssc = intel_de_read(dev_priv, DKL_PLL_SSC(tc_port)); + hw_state->mg_pll_ssc = intel_dkl_phy_read(dev_priv, DKL_PLL_SSC(tc_port), 2); hw_state->mg_pll_ssc &= (DKL_PLL_SSC_IREF_NDIV_RATIO_MASK | DKL_PLL_SSC_STEP_LEN_MASK | DKL_PLL_SSC_STEP_NUM_MASK | DKL_PLL_SSC_EN); - hw_state->mg_pll_bias = intel_de_read(dev_priv, DKL_PLL_BIAS(tc_port)); + hw_state->mg_pll_bias = intel_dkl_phy_read(dev_priv, DKL_PLL_BIAS(tc_port), 2); hw_state->mg_pll_bias &= (DKL_PLL_BIAS_FRAC_EN_H | DKL_PLL_BIAS_FBDIV_FRAC_MASK); hw_state->mg_pll_tdc_coldst_bias = - intel_de_read(dev_priv, DKL_PLL_TDC_COLDST_BIAS(tc_port)); + intel_dkl_phy_read(dev_priv, DKL_PLL_TDC_COLDST_BIAS(tc_port), 2); hw_state->mg_pll_tdc_coldst_bias &= (DKL_PLL_TDC_SSC_STEP_SIZE_MASK | DKL_PLL_TDC_FEED_FWD_GAIN_MASK); @@ -3715,61 +3713,58 @@ static void dkl_pll_write(struct drm_i915_private *dev_priv, * All registers programmed here have the same HIP_INDEX_REG even * though on different building block */ - intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), - HIP_INDEX_VAL(tc_port, 0x2)); - /* All the registers are RMW */ - val = intel_de_read(dev_priv, DKL_REFCLKIN_CTL(tc_port)); + val = intel_dkl_phy_read(dev_priv, DKL_REFCLKIN_CTL(tc_port), 2); val &= ~MG_REFCLKIN_CTL_OD_2_MUX_MASK; val |= hw_state->mg_refclkin_ctl; - intel_de_write(dev_priv, DKL_REFCLKIN_CTL(tc_port), val); + intel_dkl_phy_write(dev_priv, DKL_REFCLKIN_CTL(tc_port), 2, val); - val = intel_de_read(dev_priv, DKL_CLKTOP2_CORECLKCTL1(tc_port)); + val = intel_dkl_phy_read(dev_priv, DKL_CLKTOP2_CORECLKCTL1(tc_port), 2); val &= ~MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK; val |= hw_state->mg_clktop2_coreclkctl1; - intel_de_write(dev_priv, DKL_CLKTOP2_CORECLKCTL1(tc_port), val); + intel_dkl_phy_write(dev_priv, DKL_CLKTOP2_CORECLKCTL1(tc_port), 2, val); - val = intel_de_read(dev_priv, DKL_CLKTOP2_HSCLKCTL(tc_port)); + val = intel_dkl_phy_read(dev_priv, DKL_CLKTOP2_HSCLKCTL(tc_port), 2); val &= ~(MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK | MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK | MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK | MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK); val |= hw_state->mg_clktop2_hsclkctl; - intel_de_write(dev_priv, DKL_CLKTOP2_HSCLKCTL(tc_port), val); + intel_dkl_phy_write(dev_priv, DKL_CLKTOP2_HSCLKCTL(tc_port), 2, val); val = DKL_PLL_DIV0_MASK; if (dev_priv->display.vbt.override_afc_startup) val |= DKL_PLL_DIV0_AFC_STARTUP_MASK; - intel_de_rmw(dev_priv, DKL_PLL_DIV0(tc_port), val, - hw_state->mg_pll_div0); + intel_dkl_phy_rmw(dev_priv, DKL_PLL_DIV0(tc_port), 2, val, + hw_state->mg_pll_div0); - val = intel_de_read(dev_priv, DKL_PLL_DIV1(tc_port)); + val = intel_dkl_phy_read(dev_priv, DKL_PLL_DIV1(tc_port), 2); val &= ~(DKL_PLL_DIV1_IREF_TRIM_MASK | DKL_PLL_DIV1_TDC_TARGET_CNT_MASK); val |= hw_state->mg_pll_div1; - intel_de_write(dev_priv, DKL_PLL_DIV1(tc_port), val); + intel_dkl_phy_write(dev_priv, DKL_PLL_DIV1(tc_port), 2, val); - val = intel_de_read(dev_priv, DKL_PLL_SSC(tc_port)); + val = intel_dkl_phy_read(dev_priv, DKL_PLL_SSC(tc_port), 2); val &= ~(DKL_PLL_SSC_IREF_NDIV_RATIO_MASK | DKL_PLL_SSC_STEP_LEN_MASK | DKL_PLL_SSC_STEP_NUM_MASK | DKL_PLL_SSC_EN); val |= hw_state->mg_pll_ssc; - intel_de_write(dev_priv, DKL_PLL_SSC(tc_port), val); + intel_dkl_phy_write(dev_priv, DKL_PLL_SSC(tc_port), 2, val); - val = intel_de_read(dev_priv, DKL_PLL_BIAS(tc_port)); + val = intel_dkl_phy_read(dev_priv, DKL_PLL_BIAS(tc_port), 2); val &= ~(DKL_PLL_BIAS_FRAC_EN_H | DKL_PLL_BIAS_FBDIV_FRAC_MASK); val |= hw_state->mg_pll_bias; - intel_de_write(dev_priv, DKL_PLL_BIAS(tc_port), val); + intel_dkl_phy_write(dev_priv, DKL_PLL_BIAS(tc_port), 2, val); - val = intel_de_read(dev_priv, DKL_PLL_TDC_COLDST_BIAS(tc_port)); + val = intel_dkl_phy_read(dev_priv, DKL_PLL_TDC_COLDST_BIAS(tc_port), 2); val &= ~(DKL_PLL_TDC_SSC_STEP_SIZE_MASK | DKL_PLL_TDC_FEED_FWD_GAIN_MASK); val |= hw_state->mg_pll_tdc_coldst_bias; - intel_de_write(dev_priv, DKL_PLL_TDC_COLDST_BIAS(tc_port), val); + intel_dkl_phy_write(dev_priv, DKL_PLL_TDC_COLDST_BIAS(tc_port), 2, val); - intel_de_posting_read(dev_priv, DKL_PLL_TDC_COLDST_BIAS(tc_port)); + intel_dkl_phy_posting_read(dev_priv, DKL_PLL_TDC_COLDST_BIAS(tc_port), 2); } static void icl_pll_power_enable(struct drm_i915_private *dev_priv, diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c index ffff49868dc51..c3d43f9b1e45d 100644 --- a/drivers/gpu/drm/i915/i915_driver.c +++ b/drivers/gpu/drm/i915/i915_driver.c @@ -355,6 +355,7 @@ static int i915_driver_early_probe(struct drm_i915_private *dev_priv) mutex_init(&dev_priv->display.wm.wm_mutex); mutex_init(&dev_priv->display.pps.mutex); mutex_init(&dev_priv->display.hdcp.comp_mutex); + spin_lock_init(&dev_priv->display.dkl.phy_lock); i915_memcpy_init_early(dev_priv); intel_runtime_pm_init_early(&dev_priv->runtime_pm); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 99a8535193957..231345887cbb3 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -7442,6 +7442,9 @@ enum skl_power_gate { #define _DKL_PHY5_BASE 0x16C000 #define _DKL_PHY6_BASE 0x16D000 +#define DKL_REG_TC_PORT(__reg) \ + (((__reg).reg - _DKL_PHY1_BASE) / (TC_PORT_1 + _DKL_PHY2_BASE - _DKL_PHY1_BASE)) + /* DEKEL PHY MMIO Address = Phy base + (internal address & ~index_mask) */ #define _DKL_PCS_DW5 0x14 #define DKL_PCS_DW5(tc_port) _MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \ -- 2.37.1 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [Intel-gfx] [PATCH v4 1/4] drm/i915/tgl+: Add locking around DKL PHY register accesses 2022-10-25 10:26 ` [Intel-gfx] [PATCH v3 1/4] drm/i915/tgl+: Add locking around DKL PHY register accesses Imre Deak @ 2022-10-25 11:44 ` Imre Deak 0 siblings, 0 replies; 16+ messages in thread From: Imre Deak @ 2022-10-25 11:44 UTC (permalink / raw) To: intel-gfx; +Cc: Jani Nikula, stable Accessing the TypeC DKL PHY registers during modeset-commit, -verification, DP link-retraining and AUX power well toggling is racy due to these code paths being concurrent and the PHY register bank selection register (HIP_INDEX_REG) being shared between PHY instances (aka TC ports) and the bank selection being not atomic wrt. the actual PHY register access. Add the required locking around each PHY register bank selection-> register access sequence. Kudos to Ville for noticing the race conditions. v2: - Add the DKL PHY register accessors to intel_dkl_phy.[ch]. (Jani) - Make the DKL_REG_TC_PORT macro independent of PHY internals. - Move initing the DKL PHY lock to a more logical place. v3: - Fix parameter reuse in the DKL_REG_TC_PORT definition. - Document the usage of phy_lock. v4: - Fix adding TC_PORT_1 offset in the DKL_REG_TC_PORT definition. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Cc: <stable@vger.kernel.org> # v5.5+ Acked-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> --- drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/display/intel_ddi.c | 68 +++++------ .../gpu/drm/i915/display/intel_display_core.h | 8 ++ .../i915/display/intel_display_power_well.c | 7 +- drivers/gpu/drm/i915/display/intel_dkl_phy.c | 109 ++++++++++++++++++ drivers/gpu/drm/i915/display/intel_dkl_phy.h | 24 ++++ drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 59 +++++----- drivers/gpu/drm/i915/i915_driver.c | 1 + drivers/gpu/drm/i915/i915_reg.h | 3 + 9 files changed, 204 insertions(+), 76 deletions(-) create mode 100644 drivers/gpu/drm/i915/display/intel_dkl_phy.c create mode 100644 drivers/gpu/drm/i915/display/intel_dkl_phy.h diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile index 2535593ab379e..51704b54317cf 100644 --- a/drivers/gpu/drm/i915/Makefile +++ b/drivers/gpu/drm/i915/Makefile @@ -285,6 +285,7 @@ i915-y += \ display/intel_ddi.o \ display/intel_ddi_buf_trans.o \ display/intel_display_trace.o \ + display/intel_dkl_phy.o \ display/intel_dp.o \ display/intel_dp_aux.o \ display/intel_dp_aux_backlight.o \ diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 971356237eca3..7708ccbbdeb75 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -43,6 +43,7 @@ #include "intel_de.h" #include "intel_display_power.h" #include "intel_display_types.h" +#include "intel_dkl_phy.h" #include "intel_dp.h" #include "intel_dp_link_training.h" #include "intel_dp_mst.h" @@ -1262,33 +1263,30 @@ static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder, for (ln = 0; ln < 2; ln++) { int level; - intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), - HIP_INDEX_VAL(tc_port, ln)); - - intel_de_write(dev_priv, DKL_TX_PMD_LANE_SUS(tc_port), 0); + intel_dkl_phy_write(dev_priv, DKL_TX_PMD_LANE_SUS(tc_port), ln, 0); level = intel_ddi_level(encoder, crtc_state, 2*ln+0); - intel_de_rmw(dev_priv, DKL_TX_DPCNTL0(tc_port), - DKL_TX_PRESHOOT_COEFF_MASK | - DKL_TX_DE_EMPAHSIS_COEFF_MASK | - DKL_TX_VSWING_CONTROL_MASK, - DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot) | - DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) | - DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing)); + intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL0(tc_port), ln, + DKL_TX_PRESHOOT_COEFF_MASK | + DKL_TX_DE_EMPAHSIS_COEFF_MASK | + DKL_TX_VSWING_CONTROL_MASK, + DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot) | + DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) | + DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing)); level = intel_ddi_level(encoder, crtc_state, 2*ln+1); - intel_de_rmw(dev_priv, DKL_TX_DPCNTL1(tc_port), - DKL_TX_PRESHOOT_COEFF_MASK | - DKL_TX_DE_EMPAHSIS_COEFF_MASK | - DKL_TX_VSWING_CONTROL_MASK, - DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot) | - DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) | - DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing)); + intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL1(tc_port), ln, + DKL_TX_PRESHOOT_COEFF_MASK | + DKL_TX_DE_EMPAHSIS_COEFF_MASK | + DKL_TX_VSWING_CONTROL_MASK, + DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot) | + DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) | + DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing)); - intel_de_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port), - DKL_TX_DP20BITMODE, 0); + intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port), ln, + DKL_TX_DP20BITMODE, 0); if (IS_ALDERLAKE_P(dev_priv)) { u32 val; @@ -1306,10 +1304,10 @@ static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder, val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(0); } - intel_de_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port), - DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK | - DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK, - val); + intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port), ln, + DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK | + DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK, + val); } } } @@ -2019,12 +2017,8 @@ icl_program_mg_dp_mode(struct intel_digital_port *dig_port, return; if (DISPLAY_VER(dev_priv) >= 12) { - intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), - HIP_INDEX_VAL(tc_port, 0x0)); - ln0 = intel_de_read(dev_priv, DKL_DP_MODE(tc_port)); - intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), - HIP_INDEX_VAL(tc_port, 0x1)); - ln1 = intel_de_read(dev_priv, DKL_DP_MODE(tc_port)); + ln0 = intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port), 0); + ln1 = intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port), 1); } else { ln0 = intel_de_read(dev_priv, MG_DP_MODE(0, tc_port)); ln1 = intel_de_read(dev_priv, MG_DP_MODE(1, tc_port)); @@ -2085,12 +2079,8 @@ icl_program_mg_dp_mode(struct intel_digital_port *dig_port, } if (DISPLAY_VER(dev_priv) >= 12) { - intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), - HIP_INDEX_VAL(tc_port, 0x0)); - intel_de_write(dev_priv, DKL_DP_MODE(tc_port), ln0); - intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), - HIP_INDEX_VAL(tc_port, 0x1)); - intel_de_write(dev_priv, DKL_DP_MODE(tc_port), ln1); + intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port), 0, ln0); + intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port), 1, ln1); } else { intel_de_write(dev_priv, MG_DP_MODE(0, tc_port), ln0); intel_de_write(dev_priv, MG_DP_MODE(1, tc_port), ln1); @@ -3094,10 +3084,8 @@ static void adlp_tbt_to_dp_alt_switch_wa(struct intel_encoder *encoder) enum tc_port tc_port = intel_port_to_tc(i915, encoder->port); int ln; - for (ln = 0; ln < 2; ln++) { - intel_de_write(i915, HIP_INDEX_REG(tc_port), HIP_INDEX_VAL(tc_port, ln)); - intel_de_rmw(i915, DKL_PCS_DW5(tc_port), DKL_PCS_DW5_CORE_SOFTRESET, 0); - } + for (ln = 0; ln < 2; ln++) + intel_dkl_phy_rmw(i915, DKL_PCS_DW5(tc_port), ln, DKL_PCS_DW5_CORE_SOFTRESET, 0); } static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp, diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h index 96cf994b0ad1f..9b51148e8ba56 100644 --- a/drivers/gpu/drm/i915/display/intel_display_core.h +++ b/drivers/gpu/drm/i915/display/intel_display_core.h @@ -315,6 +315,14 @@ struct intel_display { struct intel_global_obj obj; } dbuf; + struct { + /* + * dkl.phy_lock protects against concurrent access of the + * Dekel TypeC PHYs. + */ + spinlock_t phy_lock; + } dkl; + struct { /* VLV/CHV/BXT/GLK DSI MMIO register base address */ u32 mmio_base; diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c index df7ee4969ef17..1d18eee562534 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c @@ -12,6 +12,7 @@ #include "intel_de.h" #include "intel_display_power_well.h" #include "intel_display_types.h" +#include "intel_dkl_phy.h" #include "intel_dmc.h" #include "intel_dpio_phy.h" #include "intel_dpll.h" @@ -529,11 +530,9 @@ icl_tc_phy_aux_power_well_enable(struct drm_i915_private *dev_priv, enum tc_port tc_port; tc_port = TGL_AUX_PW_TO_TC_PORT(i915_power_well_instance(power_well)->hsw.idx); - intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), - HIP_INDEX_VAL(tc_port, 0x2)); - if (intel_de_wait_for_set(dev_priv, DKL_CMN_UC_DW_27(tc_port), - DKL_CMN_UC_DW27_UC_HEALTH, 1)) + if (wait_for(intel_dkl_phy_read(dev_priv, DKL_CMN_UC_DW_27(tc_port), 2) & + DKL_CMN_UC_DW27_UC_HEALTH, 1)) drm_warn(&dev_priv->drm, "Timeout waiting TC uC health\n"); } diff --git a/drivers/gpu/drm/i915/display/intel_dkl_phy.c b/drivers/gpu/drm/i915/display/intel_dkl_phy.c new file mode 100644 index 0000000000000..710b030c7ed54 --- /dev/null +++ b/drivers/gpu/drm/i915/display/intel_dkl_phy.c @@ -0,0 +1,109 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright © 2022 Intel Corporation + */ + +#include "i915_drv.h" +#include "i915_reg.h" + +#include "intel_de.h" +#include "intel_display.h" +#include "intel_dkl_phy.h" + +static void +dkl_phy_set_hip_idx(struct drm_i915_private *i915, i915_reg_t reg, int idx) +{ + enum tc_port tc_port = DKL_REG_TC_PORT(reg); + + drm_WARN_ON(&i915->drm, tc_port < TC_PORT_1 || tc_port >= I915_MAX_TC_PORTS); + + intel_de_write(i915, + HIP_INDEX_REG(tc_port), + HIP_INDEX_VAL(tc_port, idx)); +} + +/** + * intel_dkl_phy_read - read a Dekel PHY register + * @i915: i915 device instance + * @reg: Dekel PHY register + * @ln: lane instance of @reg + * + * Read the @reg Dekel PHY register. + * + * Returns the read value. + */ +u32 +intel_dkl_phy_read(struct drm_i915_private *i915, i915_reg_t reg, int ln) +{ + u32 val; + + spin_lock(&i915->display.dkl.phy_lock); + + dkl_phy_set_hip_idx(i915, reg, ln); + val = intel_de_read(i915, reg); + + spin_unlock(&i915->display.dkl.phy_lock); + + return val; +} + +/** + * intel_dkl_phy_write - write a Dekel PHY register + * @i915: i915 device instance + * @reg: Dekel PHY register + * @ln: lane instance of @reg + * @val: value to write + * + * Write @val to the @reg Dekel PHY register. + */ +void +intel_dkl_phy_write(struct drm_i915_private *i915, i915_reg_t reg, int ln, u32 val) +{ + spin_lock(&i915->display.dkl.phy_lock); + + dkl_phy_set_hip_idx(i915, reg, ln); + intel_de_write(i915, reg, val); + + spin_unlock(&i915->display.dkl.phy_lock); +} + +/** + * intel_dkl_phy_rmw - read-modify-write a Dekel PHY register + * @i915: i915 device instance + * @reg: Dekel PHY register + * @ln: lane instance of @reg + * @clear: mask to clear + * @set: mask to set + * + * Read the @reg Dekel PHY register, clearing then setting the @clear/@set bits in it, and writing + * this value back to the register if the value differs from the read one. + */ +void +intel_dkl_phy_rmw(struct drm_i915_private *i915, i915_reg_t reg, int ln, u32 clear, u32 set) +{ + spin_lock(&i915->display.dkl.phy_lock); + + dkl_phy_set_hip_idx(i915, reg, ln); + intel_de_rmw(i915, reg, clear, set); + + spin_unlock(&i915->display.dkl.phy_lock); +} + +/** + * intel_dkl_phy_posting_read - do a posting read from a Dekel PHY register + * @i915: i915 device instance + * @reg: Dekel PHY register + * @ln: lane instance of @reg + * + * Read the @reg Dekel PHY register without returning the read value. + */ +void +intel_dkl_phy_posting_read(struct drm_i915_private *i915, i915_reg_t reg, int ln) +{ + spin_lock(&i915->display.dkl.phy_lock); + + dkl_phy_set_hip_idx(i915, reg, ln); + intel_de_posting_read(i915, reg); + + spin_unlock(&i915->display.dkl.phy_lock); +} diff --git a/drivers/gpu/drm/i915/display/intel_dkl_phy.h b/drivers/gpu/drm/i915/display/intel_dkl_phy.h new file mode 100644 index 0000000000000..260ad121a0b18 --- /dev/null +++ b/drivers/gpu/drm/i915/display/intel_dkl_phy.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright © 2022 Intel Corporation + */ + +#ifndef __INTEL_DKL_PHY_H__ +#define __INTEL_DKL_PHY_H__ + +#include <linux/types.h> + +#include "i915_reg_defs.h" + +struct drm_i915_private; + +u32 +intel_dkl_phy_read(struct drm_i915_private *i915, i915_reg_t reg, int ln); +void +intel_dkl_phy_write(struct drm_i915_private *i915, i915_reg_t reg, int ln, u32 val); +void +intel_dkl_phy_rmw(struct drm_i915_private *i915, i915_reg_t reg, int ln, u32 clear, u32 set); +void +intel_dkl_phy_posting_read(struct drm_i915_private *i915, i915_reg_t reg, int ln); + +#endif /* __INTEL_DKL_PHY_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c index b63600d8ebeb0..8bbc2b5e50ed9 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c @@ -25,6 +25,7 @@ #include "intel_de.h" #include "intel_display_types.h" +#include "intel_dkl_phy.h" #include "intel_dpio_phy.h" #include "intel_dpll.h" #include "intel_dpll_mgr.h" @@ -3486,15 +3487,12 @@ static bool dkl_pll_get_hw_state(struct drm_i915_private *dev_priv, * All registers read here have the same HIP_INDEX_REG even though * they are on different building blocks */ - intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), - HIP_INDEX_VAL(tc_port, 0x2)); - - hw_state->mg_refclkin_ctl = intel_de_read(dev_priv, - DKL_REFCLKIN_CTL(tc_port)); + hw_state->mg_refclkin_ctl = intel_dkl_phy_read(dev_priv, + DKL_REFCLKIN_CTL(tc_port), 2); hw_state->mg_refclkin_ctl &= MG_REFCLKIN_CTL_OD_2_MUX_MASK; hw_state->mg_clktop2_hsclkctl = - intel_de_read(dev_priv, DKL_CLKTOP2_HSCLKCTL(tc_port)); + intel_dkl_phy_read(dev_priv, DKL_CLKTOP2_HSCLKCTL(tc_port), 2); hw_state->mg_clktop2_hsclkctl &= MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK | MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK | @@ -3502,32 +3500,32 @@ static bool dkl_pll_get_hw_state(struct drm_i915_private *dev_priv, MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK; hw_state->mg_clktop2_coreclkctl1 = - intel_de_read(dev_priv, DKL_CLKTOP2_CORECLKCTL1(tc_port)); + intel_dkl_phy_read(dev_priv, DKL_CLKTOP2_CORECLKCTL1(tc_port), 2); hw_state->mg_clktop2_coreclkctl1 &= MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK; - hw_state->mg_pll_div0 = intel_de_read(dev_priv, DKL_PLL_DIV0(tc_port)); + hw_state->mg_pll_div0 = intel_dkl_phy_read(dev_priv, DKL_PLL_DIV0(tc_port), 2); val = DKL_PLL_DIV0_MASK; if (dev_priv->display.vbt.override_afc_startup) val |= DKL_PLL_DIV0_AFC_STARTUP_MASK; hw_state->mg_pll_div0 &= val; - hw_state->mg_pll_div1 = intel_de_read(dev_priv, DKL_PLL_DIV1(tc_port)); + hw_state->mg_pll_div1 = intel_dkl_phy_read(dev_priv, DKL_PLL_DIV1(tc_port), 2); hw_state->mg_pll_div1 &= (DKL_PLL_DIV1_IREF_TRIM_MASK | DKL_PLL_DIV1_TDC_TARGET_CNT_MASK); - hw_state->mg_pll_ssc = intel_de_read(dev_priv, DKL_PLL_SSC(tc_port)); + hw_state->mg_pll_ssc = intel_dkl_phy_read(dev_priv, DKL_PLL_SSC(tc_port), 2); hw_state->mg_pll_ssc &= (DKL_PLL_SSC_IREF_NDIV_RATIO_MASK | DKL_PLL_SSC_STEP_LEN_MASK | DKL_PLL_SSC_STEP_NUM_MASK | DKL_PLL_SSC_EN); - hw_state->mg_pll_bias = intel_de_read(dev_priv, DKL_PLL_BIAS(tc_port)); + hw_state->mg_pll_bias = intel_dkl_phy_read(dev_priv, DKL_PLL_BIAS(tc_port), 2); hw_state->mg_pll_bias &= (DKL_PLL_BIAS_FRAC_EN_H | DKL_PLL_BIAS_FBDIV_FRAC_MASK); hw_state->mg_pll_tdc_coldst_bias = - intel_de_read(dev_priv, DKL_PLL_TDC_COLDST_BIAS(tc_port)); + intel_dkl_phy_read(dev_priv, DKL_PLL_TDC_COLDST_BIAS(tc_port), 2); hw_state->mg_pll_tdc_coldst_bias &= (DKL_PLL_TDC_SSC_STEP_SIZE_MASK | DKL_PLL_TDC_FEED_FWD_GAIN_MASK); @@ -3715,61 +3713,58 @@ static void dkl_pll_write(struct drm_i915_private *dev_priv, * All registers programmed here have the same HIP_INDEX_REG even * though on different building block */ - intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), - HIP_INDEX_VAL(tc_port, 0x2)); - /* All the registers are RMW */ - val = intel_de_read(dev_priv, DKL_REFCLKIN_CTL(tc_port)); + val = intel_dkl_phy_read(dev_priv, DKL_REFCLKIN_CTL(tc_port), 2); val &= ~MG_REFCLKIN_CTL_OD_2_MUX_MASK; val |= hw_state->mg_refclkin_ctl; - intel_de_write(dev_priv, DKL_REFCLKIN_CTL(tc_port), val); + intel_dkl_phy_write(dev_priv, DKL_REFCLKIN_CTL(tc_port), 2, val); - val = intel_de_read(dev_priv, DKL_CLKTOP2_CORECLKCTL1(tc_port)); + val = intel_dkl_phy_read(dev_priv, DKL_CLKTOP2_CORECLKCTL1(tc_port), 2); val &= ~MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK; val |= hw_state->mg_clktop2_coreclkctl1; - intel_de_write(dev_priv, DKL_CLKTOP2_CORECLKCTL1(tc_port), val); + intel_dkl_phy_write(dev_priv, DKL_CLKTOP2_CORECLKCTL1(tc_port), 2, val); - val = intel_de_read(dev_priv, DKL_CLKTOP2_HSCLKCTL(tc_port)); + val = intel_dkl_phy_read(dev_priv, DKL_CLKTOP2_HSCLKCTL(tc_port), 2); val &= ~(MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK | MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK | MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK | MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK); val |= hw_state->mg_clktop2_hsclkctl; - intel_de_write(dev_priv, DKL_CLKTOP2_HSCLKCTL(tc_port), val); + intel_dkl_phy_write(dev_priv, DKL_CLKTOP2_HSCLKCTL(tc_port), 2, val); val = DKL_PLL_DIV0_MASK; if (dev_priv->display.vbt.override_afc_startup) val |= DKL_PLL_DIV0_AFC_STARTUP_MASK; - intel_de_rmw(dev_priv, DKL_PLL_DIV0(tc_port), val, - hw_state->mg_pll_div0); + intel_dkl_phy_rmw(dev_priv, DKL_PLL_DIV0(tc_port), 2, val, + hw_state->mg_pll_div0); - val = intel_de_read(dev_priv, DKL_PLL_DIV1(tc_port)); + val = intel_dkl_phy_read(dev_priv, DKL_PLL_DIV1(tc_port), 2); val &= ~(DKL_PLL_DIV1_IREF_TRIM_MASK | DKL_PLL_DIV1_TDC_TARGET_CNT_MASK); val |= hw_state->mg_pll_div1; - intel_de_write(dev_priv, DKL_PLL_DIV1(tc_port), val); + intel_dkl_phy_write(dev_priv, DKL_PLL_DIV1(tc_port), 2, val); - val = intel_de_read(dev_priv, DKL_PLL_SSC(tc_port)); + val = intel_dkl_phy_read(dev_priv, DKL_PLL_SSC(tc_port), 2); val &= ~(DKL_PLL_SSC_IREF_NDIV_RATIO_MASK | DKL_PLL_SSC_STEP_LEN_MASK | DKL_PLL_SSC_STEP_NUM_MASK | DKL_PLL_SSC_EN); val |= hw_state->mg_pll_ssc; - intel_de_write(dev_priv, DKL_PLL_SSC(tc_port), val); + intel_dkl_phy_write(dev_priv, DKL_PLL_SSC(tc_port), 2, val); - val = intel_de_read(dev_priv, DKL_PLL_BIAS(tc_port)); + val = intel_dkl_phy_read(dev_priv, DKL_PLL_BIAS(tc_port), 2); val &= ~(DKL_PLL_BIAS_FRAC_EN_H | DKL_PLL_BIAS_FBDIV_FRAC_MASK); val |= hw_state->mg_pll_bias; - intel_de_write(dev_priv, DKL_PLL_BIAS(tc_port), val); + intel_dkl_phy_write(dev_priv, DKL_PLL_BIAS(tc_port), 2, val); - val = intel_de_read(dev_priv, DKL_PLL_TDC_COLDST_BIAS(tc_port)); + val = intel_dkl_phy_read(dev_priv, DKL_PLL_TDC_COLDST_BIAS(tc_port), 2); val &= ~(DKL_PLL_TDC_SSC_STEP_SIZE_MASK | DKL_PLL_TDC_FEED_FWD_GAIN_MASK); val |= hw_state->mg_pll_tdc_coldst_bias; - intel_de_write(dev_priv, DKL_PLL_TDC_COLDST_BIAS(tc_port), val); + intel_dkl_phy_write(dev_priv, DKL_PLL_TDC_COLDST_BIAS(tc_port), 2, val); - intel_de_posting_read(dev_priv, DKL_PLL_TDC_COLDST_BIAS(tc_port)); + intel_dkl_phy_posting_read(dev_priv, DKL_PLL_TDC_COLDST_BIAS(tc_port), 2); } static void icl_pll_power_enable(struct drm_i915_private *dev_priv, diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c index ffff49868dc51..c3d43f9b1e45d 100644 --- a/drivers/gpu/drm/i915/i915_driver.c +++ b/drivers/gpu/drm/i915/i915_driver.c @@ -355,6 +355,7 @@ static int i915_driver_early_probe(struct drm_i915_private *dev_priv) mutex_init(&dev_priv->display.wm.wm_mutex); mutex_init(&dev_priv->display.pps.mutex); mutex_init(&dev_priv->display.hdcp.comp_mutex); + spin_lock_init(&dev_priv->display.dkl.phy_lock); i915_memcpy_init_early(dev_priv); intel_runtime_pm_init_early(&dev_priv->runtime_pm); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 99a8535193957..52e49687ddb5d 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -7442,6 +7442,9 @@ enum skl_power_gate { #define _DKL_PHY5_BASE 0x16C000 #define _DKL_PHY6_BASE 0x16D000 +#define DKL_REG_TC_PORT(__reg) \ + (TC_PORT_1 + ((__reg).reg - _DKL_PHY1_BASE) / (_DKL_PHY2_BASE - _DKL_PHY1_BASE)) + /* DEKEL PHY MMIO Address = Phy base + (internal address & ~index_mask) */ #define _DKL_PCS_DW5 0x14 #define DKL_PCS_DW5(tc_port) _MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \ -- 2.37.1 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [Intel-gfx] [PATCH v3 2/4] drm/i915: Rename intel_tc_phy_regs.h to intel_mg_phy_regs.h 2022-10-25 10:26 [Intel-gfx] [PATCH v3 0/4] drm/i915/tgl+: Fix race conditions during DKL PHY accesses Imre Deak 2022-10-25 10:26 ` [Intel-gfx] [PATCH v3 1/4] drm/i915/tgl+: Add locking around DKL PHY register accesses Imre Deak @ 2022-10-25 10:26 ` Imre Deak 2022-10-25 10:26 ` [Intel-gfx] [PATCH v3 3/4] drm/i915/tgl+: Move DKL PHY register definitions to intel_dkl_phy_regs.h Imre Deak ` (8 subsequent siblings) 10 siblings, 0 replies; 16+ messages in thread From: Imre Deak @ 2022-10-25 10:26 UTC (permalink / raw) To: intel-gfx; +Cc: Jani Nikula An upcoming patch moves the DKL PHY register definitions to intel_dkl_phy_regs.h, so for consistency rename intel_tc_phy_regs.h containing only MG PHY register definitions to intel_mg_phy_regs.h. Suggested-by: Jani Nikula <jani.nikula@intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Acked-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> --- drivers/gpu/drm/i915/display/intel_ddi.c | 2 +- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 2 +- .../display/{intel_tc_phy_regs.h => intel_mg_phy_regs.h} | 6 +++--- drivers/gpu/drm/i915/display/intel_tc.c | 2 +- 4 files changed, 6 insertions(+), 6 deletions(-) rename drivers/gpu/drm/i915/display/{intel_tc_phy_regs.h => intel_mg_phy_regs.h} (99%) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 7708ccbbdeb75..37272c6e4269d 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -56,13 +56,13 @@ #include "intel_hdmi.h" #include "intel_hotplug.h" #include "intel_lspcon.h" +#include "intel_mg_phy_regs.h" #include "intel_pps.h" #include "intel_psr.h" #include "intel_quirks.h" #include "intel_snps_phy.h" #include "intel_sprite.h" #include "intel_tc.h" -#include "intel_tc_phy_regs.h" #include "intel_vdsc.h" #include "intel_vrr.h" #include "skl_scaler.h" diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c index 8bbc2b5e50ed9..eb4decd8c68bf 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c @@ -29,9 +29,9 @@ #include "intel_dpio_phy.h" #include "intel_dpll.h" #include "intel_dpll_mgr.h" +#include "intel_mg_phy_regs.h" #include "intel_pch_refclk.h" #include "intel_tc.h" -#include "intel_tc_phy_regs.h" /** * DOC: Display PLLs diff --git a/drivers/gpu/drm/i915/display/intel_tc_phy_regs.h b/drivers/gpu/drm/i915/display/intel_mg_phy_regs.h similarity index 99% rename from drivers/gpu/drm/i915/display/intel_tc_phy_regs.h rename to drivers/gpu/drm/i915/display/intel_mg_phy_regs.h index 5a545086f9599..07978f8d5fb74 100644 --- a/drivers/gpu/drm/i915/display/intel_tc_phy_regs.h +++ b/drivers/gpu/drm/i915/display/intel_mg_phy_regs.h @@ -3,8 +3,8 @@ * Copyright © 2022 Intel Corporation */ -#ifndef __INTEL_TC_PHY_REGS__ -#define __INTEL_TC_PHY_REGS__ +#ifndef __INTEL_MG_PHY_REGS__ +#define __INTEL_MG_PHY_REGS__ #include "i915_reg_defs.h" @@ -277,4 +277,4 @@ _MG_PLL_TDC_COLDST_BIAS_PORT1, \ _MG_PLL_TDC_COLDST_BIAS_PORT2) -#endif /* __INTEL_TC_PHY_REGS__ */ +#endif /* __INTEL_MG_PHY_REGS__ */ diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c index 8cecd41ed0033..351709725cd04 100644 --- a/drivers/gpu/drm/i915/display/intel_tc.c +++ b/drivers/gpu/drm/i915/display/intel_tc.c @@ -9,8 +9,8 @@ #include "intel_display_power_map.h" #include "intel_display_types.h" #include "intel_dp_mst.h" +#include "intel_mg_phy_regs.h" #include "intel_tc.h" -#include "intel_tc_phy_regs.h" static const char *tc_port_mode_name(enum tc_port_mode mode) { -- 2.37.1 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [Intel-gfx] [PATCH v3 3/4] drm/i915/tgl+: Move DKL PHY register definitions to intel_dkl_phy_regs.h 2022-10-25 10:26 [Intel-gfx] [PATCH v3 0/4] drm/i915/tgl+: Fix race conditions during DKL PHY accesses Imre Deak 2022-10-25 10:26 ` [Intel-gfx] [PATCH v3 1/4] drm/i915/tgl+: Add locking around DKL PHY register accesses Imre Deak 2022-10-25 10:26 ` [Intel-gfx] [PATCH v3 2/4] drm/i915: Rename intel_tc_phy_regs.h to intel_mg_phy_regs.h Imre Deak @ 2022-10-25 10:26 ` Imre Deak 2022-10-25 11:44 ` [Intel-gfx] [PATCH v4 " Imre Deak 2022-10-25 10:26 ` [Intel-gfx] [PATCH v3 4/4] drm/i915/tgl+: Sanitize DKL PHY register definitions Imre Deak ` (7 subsequent siblings) 10 siblings, 1 reply; 16+ messages in thread From: Imre Deak @ 2022-10-25 10:26 UTC (permalink / raw) To: intel-gfx; +Cc: Jani Nikula Move the TypeC DKL PHY register definitions to intel_dkl_phy_regs.h. No functional changes. v2: - Move the definitions to a new intel_dkl_phy_regs.h file. (Jani). Cc: Jani Nikula <jani.nikula@intel.com> Acked-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> --- drivers/gpu/drm/i915/display/intel_ddi.c | 1 + .../i915/display/intel_display_power_well.c | 1 + drivers/gpu/drm/i915/display/intel_dkl_phy.c | 1 + .../gpu/drm/i915/display/intel_dkl_phy_regs.h | 193 ++++++++++++++++++ drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 1 + drivers/gpu/drm/i915/display/intel_tc.c | 1 + drivers/gpu/drm/i915/i915_reg.h | 179 ---------------- 7 files changed, 198 insertions(+), 179 deletions(-) create mode 100644 drivers/gpu/drm/i915/display/intel_dkl_phy_regs.h diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 37272c6e4269d..54142ca3e6947 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -44,6 +44,7 @@ #include "intel_display_power.h" #include "intel_display_types.h" #include "intel_dkl_phy.h" +#include "intel_dkl_phy_regs.h" #include "intel_dp.h" #include "intel_dp_link_training.h" #include "intel_dp_mst.h" diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c index 1d18eee562534..86974c515206e 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c @@ -13,6 +13,7 @@ #include "intel_display_power_well.h" #include "intel_display_types.h" #include "intel_dkl_phy.h" +#include "intel_dkl_phy_regs.h" #include "intel_dmc.h" #include "intel_dpio_phy.h" #include "intel_dpll.h" diff --git a/drivers/gpu/drm/i915/display/intel_dkl_phy.c b/drivers/gpu/drm/i915/display/intel_dkl_phy.c index 710b030c7ed54..01781293ffdcf 100644 --- a/drivers/gpu/drm/i915/display/intel_dkl_phy.c +++ b/drivers/gpu/drm/i915/display/intel_dkl_phy.c @@ -9,6 +9,7 @@ #include "intel_de.h" #include "intel_display.h" #include "intel_dkl_phy.h" +#include "intel_dkl_phy_regs.h" static void dkl_phy_set_hip_idx(struct drm_i915_private *i915, i915_reg_t reg, int idx) diff --git a/drivers/gpu/drm/i915/display/intel_dkl_phy_regs.h b/drivers/gpu/drm/i915/display/intel_dkl_phy_regs.h new file mode 100644 index 0000000000000..189201278f590 --- /dev/null +++ b/drivers/gpu/drm/i915/display/intel_dkl_phy_regs.h @@ -0,0 +1,193 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright © 2022 Intel Corporation + */ + +#ifndef __INTEL_DKL_PHY_REGS__ +#define __INTEL_DKL_PHY_REGS__ + +#define _DKL_PHY1_BASE 0x168000 +#define _DKL_PHY2_BASE 0x169000 +#define _DKL_PHY3_BASE 0x16A000 +#define _DKL_PHY4_BASE 0x16B000 +#define _DKL_PHY5_BASE 0x16C000 +#define _DKL_PHY6_BASE 0x16D000 + +#define DKL_REG_TC_PORT(__reg) \ + (((__reg).reg - _DKL_PHY1_BASE) / (TC_PORT_1 + _DKL_PHY2_BASE - _DKL_PHY1_BASE)) + +/* DEKEL PHY MMIO Address = Phy base + (internal address & ~index_mask) */ +#define _DKL_PCS_DW5 0x14 +#define DKL_PCS_DW5(tc_port) _MMIO(_PORT(tc_port, \ + _DKL_PHY1_BASE, \ + _DKL_PHY2_BASE) + \ + _DKL_PCS_DW5) +#define DKL_PCS_DW5_CORE_SOFTRESET REG_BIT(11) + +#define _DKL_PLL_DIV0 0x200 +#define DKL_PLL_DIV0(tc_port) _MMIO(_PORT(tc_port, \ + _DKL_PHY1_BASE, \ + _DKL_PHY2_BASE) + \ + _DKL_PLL_DIV0) +#define DKL_PLL_DIV0_AFC_STARTUP_MASK REG_GENMASK(27, 25) +#define DKL_PLL_DIV0_AFC_STARTUP(val) REG_FIELD_PREP(DKL_PLL_DIV0_AFC_STARTUP_MASK, (val)) +#define DKL_PLL_DIV0_INTEG_COEFF(x) ((x) << 16) +#define DKL_PLL_DIV0_INTEG_COEFF_MASK (0x1F << 16) +#define DKL_PLL_DIV0_PROP_COEFF(x) ((x) << 12) +#define DKL_PLL_DIV0_PROP_COEFF_MASK (0xF << 12) +#define DKL_PLL_DIV0_FBPREDIV_SHIFT (8) +#define DKL_PLL_DIV0_FBPREDIV(x) ((x) << DKL_PLL_DIV0_FBPREDIV_SHIFT) +#define DKL_PLL_DIV0_FBPREDIV_MASK (0xF << DKL_PLL_DIV0_FBPREDIV_SHIFT) +#define DKL_PLL_DIV0_FBDIV_INT(x) ((x) << 0) +#define DKL_PLL_DIV0_FBDIV_INT_MASK (0xFF << 0) +#define DKL_PLL_DIV0_MASK (DKL_PLL_DIV0_INTEG_COEFF_MASK | \ + DKL_PLL_DIV0_PROP_COEFF_MASK | \ + DKL_PLL_DIV0_FBPREDIV_MASK | \ + DKL_PLL_DIV0_FBDIV_INT_MASK) + +#define _DKL_PLL_DIV1 0x204 +#define DKL_PLL_DIV1(tc_port) _MMIO(_PORT(tc_port, \ + _DKL_PHY1_BASE, \ + _DKL_PHY2_BASE) + \ + _DKL_PLL_DIV1) +#define DKL_PLL_DIV1_IREF_TRIM(x) ((x) << 16) +#define DKL_PLL_DIV1_IREF_TRIM_MASK (0x1F << 16) +#define DKL_PLL_DIV1_TDC_TARGET_CNT(x) ((x) << 0) +#define DKL_PLL_DIV1_TDC_TARGET_CNT_MASK (0xFF << 0) + +#define _DKL_PLL_SSC 0x210 +#define DKL_PLL_SSC(tc_port) _MMIO(_PORT(tc_port, \ + _DKL_PHY1_BASE, \ + _DKL_PHY2_BASE) + \ + _DKL_PLL_SSC) +#define DKL_PLL_SSC_IREF_NDIV_RATIO(x) ((x) << 29) +#define DKL_PLL_SSC_IREF_NDIV_RATIO_MASK (0x7 << 29) +#define DKL_PLL_SSC_STEP_LEN(x) ((x) << 16) +#define DKL_PLL_SSC_STEP_LEN_MASK (0xFF << 16) +#define DKL_PLL_SSC_STEP_NUM(x) ((x) << 11) +#define DKL_PLL_SSC_STEP_NUM_MASK (0x7 << 11) +#define DKL_PLL_SSC_EN (1 << 9) + +#define _DKL_PLL_BIAS 0x214 +#define DKL_PLL_BIAS(tc_port) _MMIO(_PORT(tc_port, \ + _DKL_PHY1_BASE, \ + _DKL_PHY2_BASE) + \ + _DKL_PLL_BIAS) +#define DKL_PLL_BIAS_FRAC_EN_H (1 << 30) +#define DKL_PLL_BIAS_FBDIV_SHIFT (8) +#define DKL_PLL_BIAS_FBDIV_FRAC(x) ((x) << DKL_PLL_BIAS_FBDIV_SHIFT) +#define DKL_PLL_BIAS_FBDIV_FRAC_MASK (0x3FFFFF << DKL_PLL_BIAS_FBDIV_SHIFT) + +#define _DKL_PLL_TDC_COLDST_BIAS 0x218 +#define DKL_PLL_TDC_COLDST_BIAS(tc_port) _MMIO(_PORT(tc_port, \ + _DKL_PHY1_BASE, \ + _DKL_PHY2_BASE) + \ + _DKL_PLL_TDC_COLDST_BIAS) +#define DKL_PLL_TDC_SSC_STEP_SIZE(x) ((x) << 8) +#define DKL_PLL_TDC_SSC_STEP_SIZE_MASK (0xFF << 8) +#define DKL_PLL_TDC_FEED_FWD_GAIN(x) ((x) << 0) +#define DKL_PLL_TDC_FEED_FWD_GAIN_MASK (0xFF << 0) + +#define _DKL_REFCLKIN_CTL 0x12C +#define DKL_REFCLKIN_CTL(tc_port) _MMIO(_PORT(tc_port, \ + _DKL_PHY1_BASE, \ + _DKL_PHY2_BASE) + \ + _DKL_REFCLKIN_CTL) +/* Bits are the same as MG_REFCLKIN_CTL */ + +#define _DKL_CLKTOP2_HSCLKCTL 0xD4 +#define DKL_CLKTOP2_HSCLKCTL(tc_port) _MMIO(_PORT(tc_port, \ + _DKL_PHY1_BASE, \ + _DKL_PHY2_BASE) + \ + _DKL_CLKTOP2_HSCLKCTL) +/* Bits are the same as MG_CLKTOP2_HSCLKCTL */ + +#define _DKL_CLKTOP2_CORECLKCTL1 0xD8 +#define DKL_CLKTOP2_CORECLKCTL1(tc_port) _MMIO(_PORT(tc_port, \ + _DKL_PHY1_BASE, \ + _DKL_PHY2_BASE) + \ + _DKL_CLKTOP2_CORECLKCTL1) +/* Bits are the same as MG_CLKTOP2_CORECLKCTL1 */ + +#define _DKL_TX_DPCNTL0 0x2C0 +#define DKL_TX_DPCNTL0(tc_port) _MMIO(_PORT(tc_port, \ + _DKL_PHY1_BASE, \ + _DKL_PHY2_BASE) + \ + _DKL_TX_DPCNTL0) +#define DKL_TX_PRESHOOT_COEFF(x) ((x) << 13) +#define DKL_TX_PRESHOOT_COEFF_MASK (0x1f << 13) +#define DKL_TX_DE_EMPHASIS_COEFF(x) ((x) << 8) +#define DKL_TX_DE_EMPAHSIS_COEFF_MASK (0x1f << 8) +#define DKL_TX_VSWING_CONTROL(x) ((x) << 0) +#define DKL_TX_VSWING_CONTROL_MASK (0x7 << 0) + +#define _DKL_TX_DPCNTL1 0x2C4 +#define DKL_TX_DPCNTL1(tc_port) _MMIO(_PORT(tc_port, \ + _DKL_PHY1_BASE, \ + _DKL_PHY2_BASE) + \ + _DKL_TX_DPCNTL1) +/* Bits are the same as DKL_TX_DPCNTRL0 */ + +#define _DKL_TX_DPCNTL2 0x2C8 +#define DKL_TX_DPCNTL2(tc_port) _MMIO(_PORT(tc_port, \ + _DKL_PHY1_BASE, \ + _DKL_PHY2_BASE) + \ + _DKL_TX_DPCNTL2) +#define DKL_TX_DP20BITMODE REG_BIT(2) +#define DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK REG_GENMASK(4, 3) +#define DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(val) REG_FIELD_PREP(DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK, (val)) +#define DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK REG_GENMASK(6, 5) +#define DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(val) REG_FIELD_PREP(DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK, (val)) + +#define _DKL_TX_FW_CALIB 0x2F8 +#define DKL_TX_FW_CALIB(tc_port) _MMIO(_PORT(tc_port, \ + _DKL_PHY1_BASE, \ + _DKL_PHY2_BASE) + \ + _DKL_TX_FW_CALIB) +#define DKL_TX_CFG_DISABLE_WAIT_INIT (1 << 7) + +#define _DKL_TX_PMD_LANE_SUS 0xD00 +#define DKL_TX_PMD_LANE_SUS(tc_port) _MMIO(_PORT(tc_port, \ + _DKL_PHY1_BASE, \ + _DKL_PHY2_BASE) + \ + _DKL_TX_PMD_LANE_SUS) + +#define _DKL_TX_DW17 0xDC4 +#define DKL_TX_DW17(tc_port) _MMIO(_PORT(tc_port, \ + _DKL_PHY1_BASE, \ + _DKL_PHY2_BASE) + \ + _DKL_TX_DW17) + +#define _DKL_TX_DW18 0xDC8 +#define DKL_TX_DW18(tc_port) _MMIO(_PORT(tc_port, \ + _DKL_PHY1_BASE, \ + _DKL_PHY2_BASE) + \ + _DKL_TX_DW18) + +#define _DKL_DP_MODE 0xA0 +#define DKL_DP_MODE(tc_port) _MMIO(_PORT(tc_port, \ + _DKL_PHY1_BASE, \ + _DKL_PHY2_BASE) + \ + _DKL_DP_MODE) + +#define _DKL_CMN_UC_DW27 0x36C +#define DKL_CMN_UC_DW_27(tc_port) _MMIO(_PORT(tc_port, \ + _DKL_PHY1_BASE, \ + _DKL_PHY2_BASE) + \ + _DKL_CMN_UC_DW27) +#define DKL_CMN_UC_DW27_UC_HEALTH (0x1 << 15) + +/* + * Each Dekel PHY is addressed through a 4KB aperture. Each PHY has more than + * 4KB of register space, so a separate index is programmed in HIP_INDEX_REG0 + * or HIP_INDEX_REG1, based on the port number, to set the upper 2 address + * bits that point the 4KB window into the full PHY register space. + */ +#define _HIP_INDEX_REG0 0x1010A0 +#define _HIP_INDEX_REG1 0x1010A4 +#define HIP_INDEX_REG(tc_port) _MMIO((tc_port) < 4 ? _HIP_INDEX_REG0 \ + : _HIP_INDEX_REG1) +#define _HIP_INDEX_SHIFT(tc_port) (8 * ((tc_port) % 4)) +#define HIP_INDEX_VAL(tc_port, val) ((val) << _HIP_INDEX_SHIFT(tc_port)) + +#endif /* __INTEL_DKL_PHY_REGS__ */ diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c index eb4decd8c68bf..bb7c8aef89526 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c @@ -26,6 +26,7 @@ #include "intel_de.h" #include "intel_display_types.h" #include "intel_dkl_phy.h" +#include "intel_dkl_phy_regs.h" #include "intel_dpio_phy.h" #include "intel_dpll.h" #include "intel_dpll_mgr.h" diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c index 351709725cd04..70624b4b2d38c 100644 --- a/drivers/gpu/drm/i915/display/intel_tc.c +++ b/drivers/gpu/drm/i915/display/intel_tc.c @@ -8,6 +8,7 @@ #include "intel_display.h" #include "intel_display_power_map.h" #include "intel_display_types.h" +#include "intel_dkl_phy_regs.h" #include "intel_dp_mst.h" #include "intel_mg_phy_regs.h" #include "intel_tc.h" diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 231345887cbb3..1c0da50c0dc73 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -7435,185 +7435,6 @@ enum skl_power_gate { _ADLS_DPLL4_CFGCR1, \ _ADLS_DPLL3_CFGCR1) -#define _DKL_PHY1_BASE 0x168000 -#define _DKL_PHY2_BASE 0x169000 -#define _DKL_PHY3_BASE 0x16A000 -#define _DKL_PHY4_BASE 0x16B000 -#define _DKL_PHY5_BASE 0x16C000 -#define _DKL_PHY6_BASE 0x16D000 - -#define DKL_REG_TC_PORT(__reg) \ - (((__reg).reg - _DKL_PHY1_BASE) / (TC_PORT_1 + _DKL_PHY2_BASE - _DKL_PHY1_BASE)) - -/* DEKEL PHY MMIO Address = Phy base + (internal address & ~index_mask) */ -#define _DKL_PCS_DW5 0x14 -#define DKL_PCS_DW5(tc_port) _MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \ - _DKL_PHY2_BASE) + \ - _DKL_PCS_DW5) -#define DKL_PCS_DW5_CORE_SOFTRESET REG_BIT(11) - -#define _DKL_PLL_DIV0 0x200 -#define DKL_PLL_DIV0_AFC_STARTUP_MASK REG_GENMASK(27, 25) -#define DKL_PLL_DIV0_AFC_STARTUP(val) REG_FIELD_PREP(DKL_PLL_DIV0_AFC_STARTUP_MASK, (val)) -#define DKL_PLL_DIV0_INTEG_COEFF(x) ((x) << 16) -#define DKL_PLL_DIV0_INTEG_COEFF_MASK (0x1F << 16) -#define DKL_PLL_DIV0_PROP_COEFF(x) ((x) << 12) -#define DKL_PLL_DIV0_PROP_COEFF_MASK (0xF << 12) -#define DKL_PLL_DIV0_FBPREDIV_SHIFT (8) -#define DKL_PLL_DIV0_FBPREDIV(x) ((x) << DKL_PLL_DIV0_FBPREDIV_SHIFT) -#define DKL_PLL_DIV0_FBPREDIV_MASK (0xF << DKL_PLL_DIV0_FBPREDIV_SHIFT) -#define DKL_PLL_DIV0_FBDIV_INT(x) ((x) << 0) -#define DKL_PLL_DIV0_FBDIV_INT_MASK (0xFF << 0) -#define DKL_PLL_DIV0_MASK (DKL_PLL_DIV0_INTEG_COEFF_MASK | \ - DKL_PLL_DIV0_PROP_COEFF_MASK | \ - DKL_PLL_DIV0_FBPREDIV_MASK | \ - DKL_PLL_DIV0_FBDIV_INT_MASK) -#define DKL_PLL_DIV0(tc_port) _MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \ - _DKL_PHY2_BASE) + \ - _DKL_PLL_DIV0) - -#define _DKL_PLL_DIV1 0x204 -#define DKL_PLL_DIV1_IREF_TRIM(x) ((x) << 16) -#define DKL_PLL_DIV1_IREF_TRIM_MASK (0x1F << 16) -#define DKL_PLL_DIV1_TDC_TARGET_CNT(x) ((x) << 0) -#define DKL_PLL_DIV1_TDC_TARGET_CNT_MASK (0xFF << 0) -#define DKL_PLL_DIV1(tc_port) _MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \ - _DKL_PHY2_BASE) + \ - _DKL_PLL_DIV1) - -#define _DKL_PLL_SSC 0x210 -#define DKL_PLL_SSC_IREF_NDIV_RATIO(x) ((x) << 29) -#define DKL_PLL_SSC_IREF_NDIV_RATIO_MASK (0x7 << 29) -#define DKL_PLL_SSC_STEP_LEN(x) ((x) << 16) -#define DKL_PLL_SSC_STEP_LEN_MASK (0xFF << 16) -#define DKL_PLL_SSC_STEP_NUM(x) ((x) << 11) -#define DKL_PLL_SSC_STEP_NUM_MASK (0x7 << 11) -#define DKL_PLL_SSC_EN (1 << 9) -#define DKL_PLL_SSC(tc_port) _MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \ - _DKL_PHY2_BASE) + \ - _DKL_PLL_SSC) - -#define _DKL_PLL_BIAS 0x214 -#define DKL_PLL_BIAS_FRAC_EN_H (1 << 30) -#define DKL_PLL_BIAS_FBDIV_SHIFT (8) -#define DKL_PLL_BIAS_FBDIV_FRAC(x) ((x) << DKL_PLL_BIAS_FBDIV_SHIFT) -#define DKL_PLL_BIAS_FBDIV_FRAC_MASK (0x3FFFFF << DKL_PLL_BIAS_FBDIV_SHIFT) -#define DKL_PLL_BIAS(tc_port) _MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \ - _DKL_PHY2_BASE) + \ - _DKL_PLL_BIAS) - -#define _DKL_PLL_TDC_COLDST_BIAS 0x218 -#define DKL_PLL_TDC_SSC_STEP_SIZE(x) ((x) << 8) -#define DKL_PLL_TDC_SSC_STEP_SIZE_MASK (0xFF << 8) -#define DKL_PLL_TDC_FEED_FWD_GAIN(x) ((x) << 0) -#define DKL_PLL_TDC_FEED_FWD_GAIN_MASK (0xFF << 0) -#define DKL_PLL_TDC_COLDST_BIAS(tc_port) _MMIO(_PORT(tc_port, \ - _DKL_PHY1_BASE, \ - _DKL_PHY2_BASE) + \ - _DKL_PLL_TDC_COLDST_BIAS) - -#define _DKL_REFCLKIN_CTL 0x12C -/* Bits are the same as MG_REFCLKIN_CTL */ -#define DKL_REFCLKIN_CTL(tc_port) _MMIO(_PORT(tc_port, \ - _DKL_PHY1_BASE, \ - _DKL_PHY2_BASE) + \ - _DKL_REFCLKIN_CTL) - -#define _DKL_CLKTOP2_HSCLKCTL 0xD4 -/* Bits are the same as MG_CLKTOP2_HSCLKCTL */ -#define DKL_CLKTOP2_HSCLKCTL(tc_port) _MMIO(_PORT(tc_port, \ - _DKL_PHY1_BASE, \ - _DKL_PHY2_BASE) + \ - _DKL_CLKTOP2_HSCLKCTL) - -#define _DKL_CLKTOP2_CORECLKCTL1 0xD8 -/* Bits are the same as MG_CLKTOP2_CORECLKCTL1 */ -#define DKL_CLKTOP2_CORECLKCTL1(tc_port) _MMIO(_PORT(tc_port, \ - _DKL_PHY1_BASE, \ - _DKL_PHY2_BASE) + \ - _DKL_CLKTOP2_CORECLKCTL1) - -#define _DKL_TX_DPCNTL0 0x2C0 -#define DKL_TX_PRESHOOT_COEFF(x) ((x) << 13) -#define DKL_TX_PRESHOOT_COEFF_MASK (0x1f << 13) -#define DKL_TX_DE_EMPHASIS_COEFF(x) ((x) << 8) -#define DKL_TX_DE_EMPAHSIS_COEFF_MASK (0x1f << 8) -#define DKL_TX_VSWING_CONTROL(x) ((x) << 0) -#define DKL_TX_VSWING_CONTROL_MASK (0x7 << 0) -#define DKL_TX_DPCNTL0(tc_port) _MMIO(_PORT(tc_port, \ - _DKL_PHY1_BASE, \ - _DKL_PHY2_BASE) + \ - _DKL_TX_DPCNTL0) - -#define _DKL_TX_DPCNTL1 0x2C4 -/* Bits are the same as DKL_TX_DPCNTRL0 */ -#define DKL_TX_DPCNTL1(tc_port) _MMIO(_PORT(tc_port, \ - _DKL_PHY1_BASE, \ - _DKL_PHY2_BASE) + \ - _DKL_TX_DPCNTL1) - -#define _DKL_TX_DPCNTL2 0x2C8 -#define DKL_TX_DP20BITMODE REG_BIT(2) -#define DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK REG_GENMASK(4, 3) -#define DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(val) REG_FIELD_PREP(DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK, (val)) -#define DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK REG_GENMASK(6, 5) -#define DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(val) REG_FIELD_PREP(DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK, (val)) -#define DKL_TX_DPCNTL2(tc_port) _MMIO(_PORT(tc_port, \ - _DKL_PHY1_BASE, \ - _DKL_PHY2_BASE) + \ - _DKL_TX_DPCNTL2) - -#define _DKL_TX_FW_CALIB 0x2F8 -#define DKL_TX_CFG_DISABLE_WAIT_INIT (1 << 7) -#define DKL_TX_FW_CALIB(tc_port) _MMIO(_PORT(tc_port, \ - _DKL_PHY1_BASE, \ - _DKL_PHY2_BASE) + \ - _DKL_TX_FW_CALIB) - -#define _DKL_TX_PMD_LANE_SUS 0xD00 -#define DKL_TX_PMD_LANE_SUS(tc_port) _MMIO(_PORT(tc_port, \ - _DKL_PHY1_BASE, \ - _DKL_PHY2_BASE) + \ - _DKL_TX_PMD_LANE_SUS) - -#define _DKL_TX_DW17 0xDC4 -#define DKL_TX_DW17(tc_port) _MMIO(_PORT(tc_port, \ - _DKL_PHY1_BASE, \ - _DKL_PHY2_BASE) + \ - _DKL_TX_DW17) - -#define _DKL_TX_DW18 0xDC8 -#define DKL_TX_DW18(tc_port) _MMIO(_PORT(tc_port, \ - _DKL_PHY1_BASE, \ - _DKL_PHY2_BASE) + \ - _DKL_TX_DW18) - -#define _DKL_DP_MODE 0xA0 -#define DKL_DP_MODE(tc_port) _MMIO(_PORT(tc_port, \ - _DKL_PHY1_BASE, \ - _DKL_PHY2_BASE) + \ - _DKL_DP_MODE) - -#define _DKL_CMN_UC_DW27 0x36C -#define DKL_CMN_UC_DW27_UC_HEALTH (0x1 << 15) -#define DKL_CMN_UC_DW_27(tc_port) _MMIO(_PORT(tc_port, \ - _DKL_PHY1_BASE, \ - _DKL_PHY2_BASE) + \ - _DKL_CMN_UC_DW27) - -/* - * Each Dekel PHY is addressed through a 4KB aperture. Each PHY has more than - * 4KB of register space, so a separate index is programmed in HIP_INDEX_REG0 - * or HIP_INDEX_REG1, based on the port number, to set the upper 2 address - * bits that point the 4KB window into the full PHY register space. - */ -#define _HIP_INDEX_REG0 0x1010A0 -#define _HIP_INDEX_REG1 0x1010A4 -#define HIP_INDEX_REG(tc_port) _MMIO((tc_port) < 4 ? _HIP_INDEX_REG0 \ - : _HIP_INDEX_REG1) -#define _HIP_INDEX_SHIFT(tc_port) (8 * ((tc_port) % 4)) -#define HIP_INDEX_VAL(tc_port, val) ((val) << _HIP_INDEX_SHIFT(tc_port)) - /* BXT display engine PLL */ #define BXT_DE_PLL_CTL _MMIO(0x6d000) #define BXT_DE_PLL_RATIO(x) (x) /* {60,65,100} * 19.2MHz */ -- 2.37.1 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [Intel-gfx] [PATCH v4 3/4] drm/i915/tgl+: Move DKL PHY register definitions to intel_dkl_phy_regs.h 2022-10-25 10:26 ` [Intel-gfx] [PATCH v3 3/4] drm/i915/tgl+: Move DKL PHY register definitions to intel_dkl_phy_regs.h Imre Deak @ 2022-10-25 11:44 ` Imre Deak 0 siblings, 0 replies; 16+ messages in thread From: Imre Deak @ 2022-10-25 11:44 UTC (permalink / raw) To: intel-gfx; +Cc: Jani Nikula Move the TypeC DKL PHY register definitions to intel_dkl_phy_regs.h. No functional changes. v2: - Move the definitions to a new intel_dkl_phy_regs.h file. (Jani). v3: - Rebase on latest patchset version. Cc: Jani Nikula <jani.nikula@intel.com> Acked-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> --- drivers/gpu/drm/i915/display/intel_ddi.c | 1 + .../i915/display/intel_display_power_well.c | 1 + drivers/gpu/drm/i915/display/intel_dkl_phy.c | 1 + .../gpu/drm/i915/display/intel_dkl_phy_regs.h | 193 ++++++++++++++++++ drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 1 + drivers/gpu/drm/i915/display/intel_tc.c | 1 + drivers/gpu/drm/i915/i915_reg.h | 179 ---------------- 7 files changed, 198 insertions(+), 179 deletions(-) create mode 100644 drivers/gpu/drm/i915/display/intel_dkl_phy_regs.h diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 37272c6e4269d..54142ca3e6947 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -44,6 +44,7 @@ #include "intel_display_power.h" #include "intel_display_types.h" #include "intel_dkl_phy.h" +#include "intel_dkl_phy_regs.h" #include "intel_dp.h" #include "intel_dp_link_training.h" #include "intel_dp_mst.h" diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c index 1d18eee562534..86974c515206e 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c @@ -13,6 +13,7 @@ #include "intel_display_power_well.h" #include "intel_display_types.h" #include "intel_dkl_phy.h" +#include "intel_dkl_phy_regs.h" #include "intel_dmc.h" #include "intel_dpio_phy.h" #include "intel_dpll.h" diff --git a/drivers/gpu/drm/i915/display/intel_dkl_phy.c b/drivers/gpu/drm/i915/display/intel_dkl_phy.c index 710b030c7ed54..01781293ffdcf 100644 --- a/drivers/gpu/drm/i915/display/intel_dkl_phy.c +++ b/drivers/gpu/drm/i915/display/intel_dkl_phy.c @@ -9,6 +9,7 @@ #include "intel_de.h" #include "intel_display.h" #include "intel_dkl_phy.h" +#include "intel_dkl_phy_regs.h" static void dkl_phy_set_hip_idx(struct drm_i915_private *i915, i915_reg_t reg, int idx) diff --git a/drivers/gpu/drm/i915/display/intel_dkl_phy_regs.h b/drivers/gpu/drm/i915/display/intel_dkl_phy_regs.h new file mode 100644 index 0000000000000..7d0f3aab7f5c6 --- /dev/null +++ b/drivers/gpu/drm/i915/display/intel_dkl_phy_regs.h @@ -0,0 +1,193 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright © 2022 Intel Corporation + */ + +#ifndef __INTEL_DKL_PHY_REGS__ +#define __INTEL_DKL_PHY_REGS__ + +#define _DKL_PHY1_BASE 0x168000 +#define _DKL_PHY2_BASE 0x169000 +#define _DKL_PHY3_BASE 0x16A000 +#define _DKL_PHY4_BASE 0x16B000 +#define _DKL_PHY5_BASE 0x16C000 +#define _DKL_PHY6_BASE 0x16D000 + +#define DKL_REG_TC_PORT(__reg) \ + (TC_PORT_1 + ((__reg).reg - _DKL_PHY1_BASE) / (_DKL_PHY2_BASE - _DKL_PHY1_BASE)) + +/* DEKEL PHY MMIO Address = Phy base + (internal address & ~index_mask) */ +#define _DKL_PCS_DW5 0x14 +#define DKL_PCS_DW5(tc_port) _MMIO(_PORT(tc_port, \ + _DKL_PHY1_BASE, \ + _DKL_PHY2_BASE) + \ + _DKL_PCS_DW5) +#define DKL_PCS_DW5_CORE_SOFTRESET REG_BIT(11) + +#define _DKL_PLL_DIV0 0x200 +#define DKL_PLL_DIV0(tc_port) _MMIO(_PORT(tc_port, \ + _DKL_PHY1_BASE, \ + _DKL_PHY2_BASE) + \ + _DKL_PLL_DIV0) +#define DKL_PLL_DIV0_AFC_STARTUP_MASK REG_GENMASK(27, 25) +#define DKL_PLL_DIV0_AFC_STARTUP(val) REG_FIELD_PREP(DKL_PLL_DIV0_AFC_STARTUP_MASK, (val)) +#define DKL_PLL_DIV0_INTEG_COEFF(x) ((x) << 16) +#define DKL_PLL_DIV0_INTEG_COEFF_MASK (0x1F << 16) +#define DKL_PLL_DIV0_PROP_COEFF(x) ((x) << 12) +#define DKL_PLL_DIV0_PROP_COEFF_MASK (0xF << 12) +#define DKL_PLL_DIV0_FBPREDIV_SHIFT (8) +#define DKL_PLL_DIV0_FBPREDIV(x) ((x) << DKL_PLL_DIV0_FBPREDIV_SHIFT) +#define DKL_PLL_DIV0_FBPREDIV_MASK (0xF << DKL_PLL_DIV0_FBPREDIV_SHIFT) +#define DKL_PLL_DIV0_FBDIV_INT(x) ((x) << 0) +#define DKL_PLL_DIV0_FBDIV_INT_MASK (0xFF << 0) +#define DKL_PLL_DIV0_MASK (DKL_PLL_DIV0_INTEG_COEFF_MASK | \ + DKL_PLL_DIV0_PROP_COEFF_MASK | \ + DKL_PLL_DIV0_FBPREDIV_MASK | \ + DKL_PLL_DIV0_FBDIV_INT_MASK) + +#define _DKL_PLL_DIV1 0x204 +#define DKL_PLL_DIV1(tc_port) _MMIO(_PORT(tc_port, \ + _DKL_PHY1_BASE, \ + _DKL_PHY2_BASE) + \ + _DKL_PLL_DIV1) +#define DKL_PLL_DIV1_IREF_TRIM(x) ((x) << 16) +#define DKL_PLL_DIV1_IREF_TRIM_MASK (0x1F << 16) +#define DKL_PLL_DIV1_TDC_TARGET_CNT(x) ((x) << 0) +#define DKL_PLL_DIV1_TDC_TARGET_CNT_MASK (0xFF << 0) + +#define _DKL_PLL_SSC 0x210 +#define DKL_PLL_SSC(tc_port) _MMIO(_PORT(tc_port, \ + _DKL_PHY1_BASE, \ + _DKL_PHY2_BASE) + \ + _DKL_PLL_SSC) +#define DKL_PLL_SSC_IREF_NDIV_RATIO(x) ((x) << 29) +#define DKL_PLL_SSC_IREF_NDIV_RATIO_MASK (0x7 << 29) +#define DKL_PLL_SSC_STEP_LEN(x) ((x) << 16) +#define DKL_PLL_SSC_STEP_LEN_MASK (0xFF << 16) +#define DKL_PLL_SSC_STEP_NUM(x) ((x) << 11) +#define DKL_PLL_SSC_STEP_NUM_MASK (0x7 << 11) +#define DKL_PLL_SSC_EN (1 << 9) + +#define _DKL_PLL_BIAS 0x214 +#define DKL_PLL_BIAS(tc_port) _MMIO(_PORT(tc_port, \ + _DKL_PHY1_BASE, \ + _DKL_PHY2_BASE) + \ + _DKL_PLL_BIAS) +#define DKL_PLL_BIAS_FRAC_EN_H (1 << 30) +#define DKL_PLL_BIAS_FBDIV_SHIFT (8) +#define DKL_PLL_BIAS_FBDIV_FRAC(x) ((x) << DKL_PLL_BIAS_FBDIV_SHIFT) +#define DKL_PLL_BIAS_FBDIV_FRAC_MASK (0x3FFFFF << DKL_PLL_BIAS_FBDIV_SHIFT) + +#define _DKL_PLL_TDC_COLDST_BIAS 0x218 +#define DKL_PLL_TDC_COLDST_BIAS(tc_port) _MMIO(_PORT(tc_port, \ + _DKL_PHY1_BASE, \ + _DKL_PHY2_BASE) + \ + _DKL_PLL_TDC_COLDST_BIAS) +#define DKL_PLL_TDC_SSC_STEP_SIZE(x) ((x) << 8) +#define DKL_PLL_TDC_SSC_STEP_SIZE_MASK (0xFF << 8) +#define DKL_PLL_TDC_FEED_FWD_GAIN(x) ((x) << 0) +#define DKL_PLL_TDC_FEED_FWD_GAIN_MASK (0xFF << 0) + +#define _DKL_REFCLKIN_CTL 0x12C +#define DKL_REFCLKIN_CTL(tc_port) _MMIO(_PORT(tc_port, \ + _DKL_PHY1_BASE, \ + _DKL_PHY2_BASE) + \ + _DKL_REFCLKIN_CTL) +/* Bits are the same as MG_REFCLKIN_CTL */ + +#define _DKL_CLKTOP2_HSCLKCTL 0xD4 +#define DKL_CLKTOP2_HSCLKCTL(tc_port) _MMIO(_PORT(tc_port, \ + _DKL_PHY1_BASE, \ + _DKL_PHY2_BASE) + \ + _DKL_CLKTOP2_HSCLKCTL) +/* Bits are the same as MG_CLKTOP2_HSCLKCTL */ + +#define _DKL_CLKTOP2_CORECLKCTL1 0xD8 +#define DKL_CLKTOP2_CORECLKCTL1(tc_port) _MMIO(_PORT(tc_port, \ + _DKL_PHY1_BASE, \ + _DKL_PHY2_BASE) + \ + _DKL_CLKTOP2_CORECLKCTL1) +/* Bits are the same as MG_CLKTOP2_CORECLKCTL1 */ + +#define _DKL_TX_DPCNTL0 0x2C0 +#define DKL_TX_DPCNTL0(tc_port) _MMIO(_PORT(tc_port, \ + _DKL_PHY1_BASE, \ + _DKL_PHY2_BASE) + \ + _DKL_TX_DPCNTL0) +#define DKL_TX_PRESHOOT_COEFF(x) ((x) << 13) +#define DKL_TX_PRESHOOT_COEFF_MASK (0x1f << 13) +#define DKL_TX_DE_EMPHASIS_COEFF(x) ((x) << 8) +#define DKL_TX_DE_EMPAHSIS_COEFF_MASK (0x1f << 8) +#define DKL_TX_VSWING_CONTROL(x) ((x) << 0) +#define DKL_TX_VSWING_CONTROL_MASK (0x7 << 0) + +#define _DKL_TX_DPCNTL1 0x2C4 +#define DKL_TX_DPCNTL1(tc_port) _MMIO(_PORT(tc_port, \ + _DKL_PHY1_BASE, \ + _DKL_PHY2_BASE) + \ + _DKL_TX_DPCNTL1) +/* Bits are the same as DKL_TX_DPCNTRL0 */ + +#define _DKL_TX_DPCNTL2 0x2C8 +#define DKL_TX_DPCNTL2(tc_port) _MMIO(_PORT(tc_port, \ + _DKL_PHY1_BASE, \ + _DKL_PHY2_BASE) + \ + _DKL_TX_DPCNTL2) +#define DKL_TX_DP20BITMODE REG_BIT(2) +#define DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK REG_GENMASK(4, 3) +#define DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(val) REG_FIELD_PREP(DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK, (val)) +#define DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK REG_GENMASK(6, 5) +#define DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(val) REG_FIELD_PREP(DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK, (val)) + +#define _DKL_TX_FW_CALIB 0x2F8 +#define DKL_TX_FW_CALIB(tc_port) _MMIO(_PORT(tc_port, \ + _DKL_PHY1_BASE, \ + _DKL_PHY2_BASE) + \ + _DKL_TX_FW_CALIB) +#define DKL_TX_CFG_DISABLE_WAIT_INIT (1 << 7) + +#define _DKL_TX_PMD_LANE_SUS 0xD00 +#define DKL_TX_PMD_LANE_SUS(tc_port) _MMIO(_PORT(tc_port, \ + _DKL_PHY1_BASE, \ + _DKL_PHY2_BASE) + \ + _DKL_TX_PMD_LANE_SUS) + +#define _DKL_TX_DW17 0xDC4 +#define DKL_TX_DW17(tc_port) _MMIO(_PORT(tc_port, \ + _DKL_PHY1_BASE, \ + _DKL_PHY2_BASE) + \ + _DKL_TX_DW17) + +#define _DKL_TX_DW18 0xDC8 +#define DKL_TX_DW18(tc_port) _MMIO(_PORT(tc_port, \ + _DKL_PHY1_BASE, \ + _DKL_PHY2_BASE) + \ + _DKL_TX_DW18) + +#define _DKL_DP_MODE 0xA0 +#define DKL_DP_MODE(tc_port) _MMIO(_PORT(tc_port, \ + _DKL_PHY1_BASE, \ + _DKL_PHY2_BASE) + \ + _DKL_DP_MODE) + +#define _DKL_CMN_UC_DW27 0x36C +#define DKL_CMN_UC_DW_27(tc_port) _MMIO(_PORT(tc_port, \ + _DKL_PHY1_BASE, \ + _DKL_PHY2_BASE) + \ + _DKL_CMN_UC_DW27) +#define DKL_CMN_UC_DW27_UC_HEALTH (0x1 << 15) + +/* + * Each Dekel PHY is addressed through a 4KB aperture. Each PHY has more than + * 4KB of register space, so a separate index is programmed in HIP_INDEX_REG0 + * or HIP_INDEX_REG1, based on the port number, to set the upper 2 address + * bits that point the 4KB window into the full PHY register space. + */ +#define _HIP_INDEX_REG0 0x1010A0 +#define _HIP_INDEX_REG1 0x1010A4 +#define HIP_INDEX_REG(tc_port) _MMIO((tc_port) < 4 ? _HIP_INDEX_REG0 \ + : _HIP_INDEX_REG1) +#define _HIP_INDEX_SHIFT(tc_port) (8 * ((tc_port) % 4)) +#define HIP_INDEX_VAL(tc_port, val) ((val) << _HIP_INDEX_SHIFT(tc_port)) + +#endif /* __INTEL_DKL_PHY_REGS__ */ diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c index eb4decd8c68bf..bb7c8aef89526 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c @@ -26,6 +26,7 @@ #include "intel_de.h" #include "intel_display_types.h" #include "intel_dkl_phy.h" +#include "intel_dkl_phy_regs.h" #include "intel_dpio_phy.h" #include "intel_dpll.h" #include "intel_dpll_mgr.h" diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c index 351709725cd04..70624b4b2d38c 100644 --- a/drivers/gpu/drm/i915/display/intel_tc.c +++ b/drivers/gpu/drm/i915/display/intel_tc.c @@ -8,6 +8,7 @@ #include "intel_display.h" #include "intel_display_power_map.h" #include "intel_display_types.h" +#include "intel_dkl_phy_regs.h" #include "intel_dp_mst.h" #include "intel_mg_phy_regs.h" #include "intel_tc.h" diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 52e49687ddb5d..1c0da50c0dc73 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -7435,185 +7435,6 @@ enum skl_power_gate { _ADLS_DPLL4_CFGCR1, \ _ADLS_DPLL3_CFGCR1) -#define _DKL_PHY1_BASE 0x168000 -#define _DKL_PHY2_BASE 0x169000 -#define _DKL_PHY3_BASE 0x16A000 -#define _DKL_PHY4_BASE 0x16B000 -#define _DKL_PHY5_BASE 0x16C000 -#define _DKL_PHY6_BASE 0x16D000 - -#define DKL_REG_TC_PORT(__reg) \ - (TC_PORT_1 + ((__reg).reg - _DKL_PHY1_BASE) / (_DKL_PHY2_BASE - _DKL_PHY1_BASE)) - -/* DEKEL PHY MMIO Address = Phy base + (internal address & ~index_mask) */ -#define _DKL_PCS_DW5 0x14 -#define DKL_PCS_DW5(tc_port) _MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \ - _DKL_PHY2_BASE) + \ - _DKL_PCS_DW5) -#define DKL_PCS_DW5_CORE_SOFTRESET REG_BIT(11) - -#define _DKL_PLL_DIV0 0x200 -#define DKL_PLL_DIV0_AFC_STARTUP_MASK REG_GENMASK(27, 25) -#define DKL_PLL_DIV0_AFC_STARTUP(val) REG_FIELD_PREP(DKL_PLL_DIV0_AFC_STARTUP_MASK, (val)) -#define DKL_PLL_DIV0_INTEG_COEFF(x) ((x) << 16) -#define DKL_PLL_DIV0_INTEG_COEFF_MASK (0x1F << 16) -#define DKL_PLL_DIV0_PROP_COEFF(x) ((x) << 12) -#define DKL_PLL_DIV0_PROP_COEFF_MASK (0xF << 12) -#define DKL_PLL_DIV0_FBPREDIV_SHIFT (8) -#define DKL_PLL_DIV0_FBPREDIV(x) ((x) << DKL_PLL_DIV0_FBPREDIV_SHIFT) -#define DKL_PLL_DIV0_FBPREDIV_MASK (0xF << DKL_PLL_DIV0_FBPREDIV_SHIFT) -#define DKL_PLL_DIV0_FBDIV_INT(x) ((x) << 0) -#define DKL_PLL_DIV0_FBDIV_INT_MASK (0xFF << 0) -#define DKL_PLL_DIV0_MASK (DKL_PLL_DIV0_INTEG_COEFF_MASK | \ - DKL_PLL_DIV0_PROP_COEFF_MASK | \ - DKL_PLL_DIV0_FBPREDIV_MASK | \ - DKL_PLL_DIV0_FBDIV_INT_MASK) -#define DKL_PLL_DIV0(tc_port) _MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \ - _DKL_PHY2_BASE) + \ - _DKL_PLL_DIV0) - -#define _DKL_PLL_DIV1 0x204 -#define DKL_PLL_DIV1_IREF_TRIM(x) ((x) << 16) -#define DKL_PLL_DIV1_IREF_TRIM_MASK (0x1F << 16) -#define DKL_PLL_DIV1_TDC_TARGET_CNT(x) ((x) << 0) -#define DKL_PLL_DIV1_TDC_TARGET_CNT_MASK (0xFF << 0) -#define DKL_PLL_DIV1(tc_port) _MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \ - _DKL_PHY2_BASE) + \ - _DKL_PLL_DIV1) - -#define _DKL_PLL_SSC 0x210 -#define DKL_PLL_SSC_IREF_NDIV_RATIO(x) ((x) << 29) -#define DKL_PLL_SSC_IREF_NDIV_RATIO_MASK (0x7 << 29) -#define DKL_PLL_SSC_STEP_LEN(x) ((x) << 16) -#define DKL_PLL_SSC_STEP_LEN_MASK (0xFF << 16) -#define DKL_PLL_SSC_STEP_NUM(x) ((x) << 11) -#define DKL_PLL_SSC_STEP_NUM_MASK (0x7 << 11) -#define DKL_PLL_SSC_EN (1 << 9) -#define DKL_PLL_SSC(tc_port) _MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \ - _DKL_PHY2_BASE) + \ - _DKL_PLL_SSC) - -#define _DKL_PLL_BIAS 0x214 -#define DKL_PLL_BIAS_FRAC_EN_H (1 << 30) -#define DKL_PLL_BIAS_FBDIV_SHIFT (8) -#define DKL_PLL_BIAS_FBDIV_FRAC(x) ((x) << DKL_PLL_BIAS_FBDIV_SHIFT) -#define DKL_PLL_BIAS_FBDIV_FRAC_MASK (0x3FFFFF << DKL_PLL_BIAS_FBDIV_SHIFT) -#define DKL_PLL_BIAS(tc_port) _MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \ - _DKL_PHY2_BASE) + \ - _DKL_PLL_BIAS) - -#define _DKL_PLL_TDC_COLDST_BIAS 0x218 -#define DKL_PLL_TDC_SSC_STEP_SIZE(x) ((x) << 8) -#define DKL_PLL_TDC_SSC_STEP_SIZE_MASK (0xFF << 8) -#define DKL_PLL_TDC_FEED_FWD_GAIN(x) ((x) << 0) -#define DKL_PLL_TDC_FEED_FWD_GAIN_MASK (0xFF << 0) -#define DKL_PLL_TDC_COLDST_BIAS(tc_port) _MMIO(_PORT(tc_port, \ - _DKL_PHY1_BASE, \ - _DKL_PHY2_BASE) + \ - _DKL_PLL_TDC_COLDST_BIAS) - -#define _DKL_REFCLKIN_CTL 0x12C -/* Bits are the same as MG_REFCLKIN_CTL */ -#define DKL_REFCLKIN_CTL(tc_port) _MMIO(_PORT(tc_port, \ - _DKL_PHY1_BASE, \ - _DKL_PHY2_BASE) + \ - _DKL_REFCLKIN_CTL) - -#define _DKL_CLKTOP2_HSCLKCTL 0xD4 -/* Bits are the same as MG_CLKTOP2_HSCLKCTL */ -#define DKL_CLKTOP2_HSCLKCTL(tc_port) _MMIO(_PORT(tc_port, \ - _DKL_PHY1_BASE, \ - _DKL_PHY2_BASE) + \ - _DKL_CLKTOP2_HSCLKCTL) - -#define _DKL_CLKTOP2_CORECLKCTL1 0xD8 -/* Bits are the same as MG_CLKTOP2_CORECLKCTL1 */ -#define DKL_CLKTOP2_CORECLKCTL1(tc_port) _MMIO(_PORT(tc_port, \ - _DKL_PHY1_BASE, \ - _DKL_PHY2_BASE) + \ - _DKL_CLKTOP2_CORECLKCTL1) - -#define _DKL_TX_DPCNTL0 0x2C0 -#define DKL_TX_PRESHOOT_COEFF(x) ((x) << 13) -#define DKL_TX_PRESHOOT_COEFF_MASK (0x1f << 13) -#define DKL_TX_DE_EMPHASIS_COEFF(x) ((x) << 8) -#define DKL_TX_DE_EMPAHSIS_COEFF_MASK (0x1f << 8) -#define DKL_TX_VSWING_CONTROL(x) ((x) << 0) -#define DKL_TX_VSWING_CONTROL_MASK (0x7 << 0) -#define DKL_TX_DPCNTL0(tc_port) _MMIO(_PORT(tc_port, \ - _DKL_PHY1_BASE, \ - _DKL_PHY2_BASE) + \ - _DKL_TX_DPCNTL0) - -#define _DKL_TX_DPCNTL1 0x2C4 -/* Bits are the same as DKL_TX_DPCNTRL0 */ -#define DKL_TX_DPCNTL1(tc_port) _MMIO(_PORT(tc_port, \ - _DKL_PHY1_BASE, \ - _DKL_PHY2_BASE) + \ - _DKL_TX_DPCNTL1) - -#define _DKL_TX_DPCNTL2 0x2C8 -#define DKL_TX_DP20BITMODE REG_BIT(2) -#define DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK REG_GENMASK(4, 3) -#define DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(val) REG_FIELD_PREP(DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK, (val)) -#define DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK REG_GENMASK(6, 5) -#define DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(val) REG_FIELD_PREP(DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK, (val)) -#define DKL_TX_DPCNTL2(tc_port) _MMIO(_PORT(tc_port, \ - _DKL_PHY1_BASE, \ - _DKL_PHY2_BASE) + \ - _DKL_TX_DPCNTL2) - -#define _DKL_TX_FW_CALIB 0x2F8 -#define DKL_TX_CFG_DISABLE_WAIT_INIT (1 << 7) -#define DKL_TX_FW_CALIB(tc_port) _MMIO(_PORT(tc_port, \ - _DKL_PHY1_BASE, \ - _DKL_PHY2_BASE) + \ - _DKL_TX_FW_CALIB) - -#define _DKL_TX_PMD_LANE_SUS 0xD00 -#define DKL_TX_PMD_LANE_SUS(tc_port) _MMIO(_PORT(tc_port, \ - _DKL_PHY1_BASE, \ - _DKL_PHY2_BASE) + \ - _DKL_TX_PMD_LANE_SUS) - -#define _DKL_TX_DW17 0xDC4 -#define DKL_TX_DW17(tc_port) _MMIO(_PORT(tc_port, \ - _DKL_PHY1_BASE, \ - _DKL_PHY2_BASE) + \ - _DKL_TX_DW17) - -#define _DKL_TX_DW18 0xDC8 -#define DKL_TX_DW18(tc_port) _MMIO(_PORT(tc_port, \ - _DKL_PHY1_BASE, \ - _DKL_PHY2_BASE) + \ - _DKL_TX_DW18) - -#define _DKL_DP_MODE 0xA0 -#define DKL_DP_MODE(tc_port) _MMIO(_PORT(tc_port, \ - _DKL_PHY1_BASE, \ - _DKL_PHY2_BASE) + \ - _DKL_DP_MODE) - -#define _DKL_CMN_UC_DW27 0x36C -#define DKL_CMN_UC_DW27_UC_HEALTH (0x1 << 15) -#define DKL_CMN_UC_DW_27(tc_port) _MMIO(_PORT(tc_port, \ - _DKL_PHY1_BASE, \ - _DKL_PHY2_BASE) + \ - _DKL_CMN_UC_DW27) - -/* - * Each Dekel PHY is addressed through a 4KB aperture. Each PHY has more than - * 4KB of register space, so a separate index is programmed in HIP_INDEX_REG0 - * or HIP_INDEX_REG1, based on the port number, to set the upper 2 address - * bits that point the 4KB window into the full PHY register space. - */ -#define _HIP_INDEX_REG0 0x1010A0 -#define _HIP_INDEX_REG1 0x1010A4 -#define HIP_INDEX_REG(tc_port) _MMIO((tc_port) < 4 ? _HIP_INDEX_REG0 \ - : _HIP_INDEX_REG1) -#define _HIP_INDEX_SHIFT(tc_port) (8 * ((tc_port) % 4)) -#define HIP_INDEX_VAL(tc_port, val) ((val) << _HIP_INDEX_SHIFT(tc_port)) - /* BXT display engine PLL */ #define BXT_DE_PLL_CTL _MMIO(0x6d000) #define BXT_DE_PLL_RATIO(x) (x) /* {60,65,100} * 19.2MHz */ -- 2.37.1 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [Intel-gfx] [PATCH v3 4/4] drm/i915/tgl+: Sanitize DKL PHY register definitions 2022-10-25 10:26 [Intel-gfx] [PATCH v3 0/4] drm/i915/tgl+: Fix race conditions during DKL PHY accesses Imre Deak ` (2 preceding siblings ...) 2022-10-25 10:26 ` [Intel-gfx] [PATCH v3 3/4] drm/i915/tgl+: Move DKL PHY register definitions to intel_dkl_phy_regs.h Imre Deak @ 2022-10-25 10:26 ` Imre Deak 2022-10-25 11:44 ` [Intel-gfx] [PATCH v4 " Imre Deak 2022-10-25 13:06 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/tgl+: Fix race conditions during DKL PHY accesses (rev5) Patchwork ` (6 subsequent siblings) 10 siblings, 1 reply; 16+ messages in thread From: Imre Deak @ 2022-10-25 10:26 UTC (permalink / raw) To: intel-gfx; +Cc: Jani Nikula Not all Dekel PHY registers have a lane instance, so having to specify this when using them is awkward. It makes more sense to define each PHY register with its full internal PHY offset where bits 15:12 is the lane for lane-instanced PHY registers and just a register bank index for other PHY registers. This way lane-instanced registers can be referred to with the (tc_port, lane) parameters, while other registers just with a tc_port parameter. An additional benefit of this change is to prevent passing a Dekel register to a generic MMIO access function or vice versa. v2: - Fix parameter reuse in the DKL_REG_MMIO definition. Cc: Jani Nikula <jani.nikula@intel.com> Acked-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> --- drivers/gpu/drm/i915/display/intel_ddi.c | 20 +- .../i915/display/intel_display_power_well.c | 2 +- drivers/gpu/drm/i915/display/intel_dkl_phy.c | 32 ++- drivers/gpu/drm/i915/display/intel_dkl_phy.h | 10 +- .../gpu/drm/i915/display/intel_dkl_phy_regs.h | 191 +++++++++--------- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 48 ++--- 6 files changed, 155 insertions(+), 148 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 54142ca3e6947..e95bde5cf060e 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -1264,11 +1264,11 @@ static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder, for (ln = 0; ln < 2; ln++) { int level; - intel_dkl_phy_write(dev_priv, DKL_TX_PMD_LANE_SUS(tc_port), ln, 0); + intel_dkl_phy_write(dev_priv, DKL_TX_PMD_LANE_SUS(tc_port, ln), 0); level = intel_ddi_level(encoder, crtc_state, 2*ln+0); - intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL0(tc_port), ln, + intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL0(tc_port, ln), DKL_TX_PRESHOOT_COEFF_MASK | DKL_TX_DE_EMPAHSIS_COEFF_MASK | DKL_TX_VSWING_CONTROL_MASK, @@ -1278,7 +1278,7 @@ static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder, level = intel_ddi_level(encoder, crtc_state, 2*ln+1); - intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL1(tc_port), ln, + intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL1(tc_port, ln), DKL_TX_PRESHOOT_COEFF_MASK | DKL_TX_DE_EMPAHSIS_COEFF_MASK | DKL_TX_VSWING_CONTROL_MASK, @@ -1286,7 +1286,7 @@ static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder, DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) | DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing)); - intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port), ln, + intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port, ln), DKL_TX_DP20BITMODE, 0); if (IS_ALDERLAKE_P(dev_priv)) { @@ -1305,7 +1305,7 @@ static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder, val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(0); } - intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port), ln, + intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port, ln), DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK | DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK, val); @@ -2018,8 +2018,8 @@ icl_program_mg_dp_mode(struct intel_digital_port *dig_port, return; if (DISPLAY_VER(dev_priv) >= 12) { - ln0 = intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port), 0); - ln1 = intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port), 1); + ln0 = intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port, 0)); + ln1 = intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port, 1)); } else { ln0 = intel_de_read(dev_priv, MG_DP_MODE(0, tc_port)); ln1 = intel_de_read(dev_priv, MG_DP_MODE(1, tc_port)); @@ -2080,8 +2080,8 @@ icl_program_mg_dp_mode(struct intel_digital_port *dig_port, } if (DISPLAY_VER(dev_priv) >= 12) { - intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port), 0, ln0); - intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port), 1, ln1); + intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 0), ln0); + intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 1), ln1); } else { intel_de_write(dev_priv, MG_DP_MODE(0, tc_port), ln0); intel_de_write(dev_priv, MG_DP_MODE(1, tc_port), ln1); @@ -3086,7 +3086,7 @@ static void adlp_tbt_to_dp_alt_switch_wa(struct intel_encoder *encoder) int ln; for (ln = 0; ln < 2; ln++) - intel_dkl_phy_rmw(i915, DKL_PCS_DW5(tc_port), ln, DKL_PCS_DW5_CORE_SOFTRESET, 0); + intel_dkl_phy_rmw(i915, DKL_PCS_DW5(tc_port, ln), DKL_PCS_DW5_CORE_SOFTRESET, 0); } static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp, diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c index 86974c515206e..8710dd41ffd4c 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c @@ -532,7 +532,7 @@ icl_tc_phy_aux_power_well_enable(struct drm_i915_private *dev_priv, tc_port = TGL_AUX_PW_TO_TC_PORT(i915_power_well_instance(power_well)->hsw.idx); - if (wait_for(intel_dkl_phy_read(dev_priv, DKL_CMN_UC_DW_27(tc_port), 2) & + if (wait_for(intel_dkl_phy_read(dev_priv, DKL_CMN_UC_DW_27(tc_port)) & DKL_CMN_UC_DW27_UC_HEALTH, 1)) drm_warn(&dev_priv->drm, "Timeout waiting TC uC health\n"); diff --git a/drivers/gpu/drm/i915/display/intel_dkl_phy.c b/drivers/gpu/drm/i915/display/intel_dkl_phy.c index 01781293ffdcf..57cc3edba0163 100644 --- a/drivers/gpu/drm/i915/display/intel_dkl_phy.c +++ b/drivers/gpu/drm/i915/display/intel_dkl_phy.c @@ -12,7 +12,7 @@ #include "intel_dkl_phy_regs.h" static void -dkl_phy_set_hip_idx(struct drm_i915_private *i915, i915_reg_t reg, int idx) +dkl_phy_set_hip_idx(struct drm_i915_private *i915, struct intel_dkl_phy_reg reg) { enum tc_port tc_port = DKL_REG_TC_PORT(reg); @@ -20,28 +20,27 @@ dkl_phy_set_hip_idx(struct drm_i915_private *i915, i915_reg_t reg, int idx) intel_de_write(i915, HIP_INDEX_REG(tc_port), - HIP_INDEX_VAL(tc_port, idx)); + HIP_INDEX_VAL(tc_port, reg.bank_idx)); } /** * intel_dkl_phy_read - read a Dekel PHY register * @i915: i915 device instance * @reg: Dekel PHY register - * @ln: lane instance of @reg * * Read the @reg Dekel PHY register. * * Returns the read value. */ u32 -intel_dkl_phy_read(struct drm_i915_private *i915, i915_reg_t reg, int ln) +intel_dkl_phy_read(struct drm_i915_private *i915, struct intel_dkl_phy_reg reg) { u32 val; spin_lock(&i915->display.dkl.phy_lock); - dkl_phy_set_hip_idx(i915, reg, ln); - val = intel_de_read(i915, reg); + dkl_phy_set_hip_idx(i915, reg); + val = intel_de_read(i915, DKL_REG_MMIO(reg)); spin_unlock(&i915->display.dkl.phy_lock); @@ -52,18 +51,17 @@ intel_dkl_phy_read(struct drm_i915_private *i915, i915_reg_t reg, int ln) * intel_dkl_phy_write - write a Dekel PHY register * @i915: i915 device instance * @reg: Dekel PHY register - * @ln: lane instance of @reg * @val: value to write * * Write @val to the @reg Dekel PHY register. */ void -intel_dkl_phy_write(struct drm_i915_private *i915, i915_reg_t reg, int ln, u32 val) +intel_dkl_phy_write(struct drm_i915_private *i915, struct intel_dkl_phy_reg reg, u32 val) { spin_lock(&i915->display.dkl.phy_lock); - dkl_phy_set_hip_idx(i915, reg, ln); - intel_de_write(i915, reg, val); + dkl_phy_set_hip_idx(i915, reg); + intel_de_write(i915, DKL_REG_MMIO(reg), val); spin_unlock(&i915->display.dkl.phy_lock); } @@ -72,7 +70,6 @@ intel_dkl_phy_write(struct drm_i915_private *i915, i915_reg_t reg, int ln, u32 v * intel_dkl_phy_rmw - read-modify-write a Dekel PHY register * @i915: i915 device instance * @reg: Dekel PHY register - * @ln: lane instance of @reg * @clear: mask to clear * @set: mask to set * @@ -80,12 +77,12 @@ intel_dkl_phy_write(struct drm_i915_private *i915, i915_reg_t reg, int ln, u32 v * this value back to the register if the value differs from the read one. */ void -intel_dkl_phy_rmw(struct drm_i915_private *i915, i915_reg_t reg, int ln, u32 clear, u32 set) +intel_dkl_phy_rmw(struct drm_i915_private *i915, struct intel_dkl_phy_reg reg, u32 clear, u32 set) { spin_lock(&i915->display.dkl.phy_lock); - dkl_phy_set_hip_idx(i915, reg, ln); - intel_de_rmw(i915, reg, clear, set); + dkl_phy_set_hip_idx(i915, reg); + intel_de_rmw(i915, DKL_REG_MMIO(reg), clear, set); spin_unlock(&i915->display.dkl.phy_lock); } @@ -94,17 +91,16 @@ intel_dkl_phy_rmw(struct drm_i915_private *i915, i915_reg_t reg, int ln, u32 cle * intel_dkl_phy_posting_read - do a posting read from a Dekel PHY register * @i915: i915 device instance * @reg: Dekel PHY register - * @ln: lane instance of @reg * * Read the @reg Dekel PHY register without returning the read value. */ void -intel_dkl_phy_posting_read(struct drm_i915_private *i915, i915_reg_t reg, int ln) +intel_dkl_phy_posting_read(struct drm_i915_private *i915, struct intel_dkl_phy_reg reg) { spin_lock(&i915->display.dkl.phy_lock); - dkl_phy_set_hip_idx(i915, reg, ln); - intel_de_posting_read(i915, reg); + dkl_phy_set_hip_idx(i915, reg); + intel_de_posting_read(i915, DKL_REG_MMIO(reg)); spin_unlock(&i915->display.dkl.phy_lock); } diff --git a/drivers/gpu/drm/i915/display/intel_dkl_phy.h b/drivers/gpu/drm/i915/display/intel_dkl_phy.h index 260ad121a0b18..570ee36f9386f 100644 --- a/drivers/gpu/drm/i915/display/intel_dkl_phy.h +++ b/drivers/gpu/drm/i915/display/intel_dkl_phy.h @@ -8,17 +8,17 @@ #include <linux/types.h> -#include "i915_reg_defs.h" +#include "intel_dkl_phy_regs.h" struct drm_i915_private; u32 -intel_dkl_phy_read(struct drm_i915_private *i915, i915_reg_t reg, int ln); +intel_dkl_phy_read(struct drm_i915_private *i915, struct intel_dkl_phy_reg reg); void -intel_dkl_phy_write(struct drm_i915_private *i915, i915_reg_t reg, int ln, u32 val); +intel_dkl_phy_write(struct drm_i915_private *i915, struct intel_dkl_phy_reg reg, u32 val); void -intel_dkl_phy_rmw(struct drm_i915_private *i915, i915_reg_t reg, int ln, u32 clear, u32 set); +intel_dkl_phy_rmw(struct drm_i915_private *i915, struct intel_dkl_phy_reg reg, u32 clear, u32 set); void -intel_dkl_phy_posting_read(struct drm_i915_private *i915, i915_reg_t reg, int ln); +intel_dkl_phy_posting_read(struct drm_i915_private *i915, struct intel_dkl_phy_reg reg); #endif /* __INTEL_DKL_PHY_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_dkl_phy_regs.h b/drivers/gpu/drm/i915/display/intel_dkl_phy_regs.h index 189201278f590..ab6f676f356ae 100644 --- a/drivers/gpu/drm/i915/display/intel_dkl_phy_regs.h +++ b/drivers/gpu/drm/i915/display/intel_dkl_phy_regs.h @@ -6,6 +6,13 @@ #ifndef __INTEL_DKL_PHY_REGS__ #define __INTEL_DKL_PHY_REGS__ +#include <linux/types.h> + +struct intel_dkl_phy_reg { + u32 reg:24; + u32 bank_idx:4; +}; + #define _DKL_PHY1_BASE 0x168000 #define _DKL_PHY2_BASE 0x169000 #define _DKL_PHY3_BASE 0x16A000 @@ -17,18 +24,38 @@ (((__reg).reg - _DKL_PHY1_BASE) / (TC_PORT_1 + _DKL_PHY2_BASE - _DKL_PHY1_BASE)) /* DEKEL PHY MMIO Address = Phy base + (internal address & ~index_mask) */ -#define _DKL_PCS_DW5 0x14 -#define DKL_PCS_DW5(tc_port) _MMIO(_PORT(tc_port, \ - _DKL_PHY1_BASE, \ - _DKL_PHY2_BASE) + \ - _DKL_PCS_DW5) +#define DKL_REG_MMIO(__reg) _MMIO((__reg).reg) + +#define _DKL_REG_PHY_BASE(tc_port) _PORT(tc_port, \ + _DKL_PHY1_BASE, \ + _DKL_PHY2_BASE) + +#define _DKL_BANK_SHIFT 12 +#define _DKL_REG_BANK_OFFSET(phy_offset) \ + ((phy_offset) & ((1 << _DKL_BANK_SHIFT) - 1)) +#define _DKL_REG_BANK_IDX(phy_offset) \ + (((phy_offset) >> _DKL_BANK_SHIFT) & 0xf) + +#define _DKL_REG(tc_port, phy_offset) \ + ((const struct intel_dkl_phy_reg) { \ + .reg = _DKL_REG_PHY_BASE(tc_port) + \ + _DKL_REG_BANK_OFFSET(phy_offset), \ + .bank_idx = _DKL_REG_BANK_IDX(phy_offset), \ + }) + +#define _DKL_REG_LN(tc_port, ln_idx, ln0_offs, ln1_offs) \ + _DKL_REG(tc_port, (ln0_offs) + (ln_idx) * ((ln1_offs) - (ln0_offs))) + +#define _DKL_PCS_DW5_LN0 0x0014 +#define _DKL_PCS_DW5_LN1 0x1014 +#define DKL_PCS_DW5(tc_port, ln) _DKL_REG_LN(tc_port, ln, \ + _DKL_PCS_DW5_LN0, \ + _DKL_PCS_DW5_LN1) #define DKL_PCS_DW5_CORE_SOFTRESET REG_BIT(11) -#define _DKL_PLL_DIV0 0x200 -#define DKL_PLL_DIV0(tc_port) _MMIO(_PORT(tc_port, \ - _DKL_PHY1_BASE, \ - _DKL_PHY2_BASE) + \ - _DKL_PLL_DIV0) +#define _DKL_PLL_DIV0 0x2200 +#define DKL_PLL_DIV0(tc_port) _DKL_REG(tc_port, \ + _DKL_PLL_DIV0) #define DKL_PLL_DIV0_AFC_STARTUP_MASK REG_GENMASK(27, 25) #define DKL_PLL_DIV0_AFC_STARTUP(val) REG_FIELD_PREP(DKL_PLL_DIV0_AFC_STARTUP_MASK, (val)) #define DKL_PLL_DIV0_INTEG_COEFF(x) ((x) << 16) @@ -45,21 +72,17 @@ DKL_PLL_DIV0_FBPREDIV_MASK | \ DKL_PLL_DIV0_FBDIV_INT_MASK) -#define _DKL_PLL_DIV1 0x204 -#define DKL_PLL_DIV1(tc_port) _MMIO(_PORT(tc_port, \ - _DKL_PHY1_BASE, \ - _DKL_PHY2_BASE) + \ - _DKL_PLL_DIV1) +#define _DKL_PLL_DIV1 0x2204 +#define DKL_PLL_DIV1(tc_port) _DKL_REG(tc_port, \ + _DKL_PLL_DIV1) #define DKL_PLL_DIV1_IREF_TRIM(x) ((x) << 16) #define DKL_PLL_DIV1_IREF_TRIM_MASK (0x1F << 16) #define DKL_PLL_DIV1_TDC_TARGET_CNT(x) ((x) << 0) #define DKL_PLL_DIV1_TDC_TARGET_CNT_MASK (0xFF << 0) -#define _DKL_PLL_SSC 0x210 -#define DKL_PLL_SSC(tc_port) _MMIO(_PORT(tc_port, \ - _DKL_PHY1_BASE, \ - _DKL_PHY2_BASE) + \ - _DKL_PLL_SSC) +#define _DKL_PLL_SSC 0x2210 +#define DKL_PLL_SSC(tc_port) _DKL_REG(tc_port, \ + _DKL_PLL_SSC) #define DKL_PLL_SSC_IREF_NDIV_RATIO(x) ((x) << 29) #define DKL_PLL_SSC_IREF_NDIV_RATIO_MASK (0x7 << 29) #define DKL_PLL_SSC_STEP_LEN(x) ((x) << 16) @@ -68,52 +91,42 @@ #define DKL_PLL_SSC_STEP_NUM_MASK (0x7 << 11) #define DKL_PLL_SSC_EN (1 << 9) -#define _DKL_PLL_BIAS 0x214 -#define DKL_PLL_BIAS(tc_port) _MMIO(_PORT(tc_port, \ - _DKL_PHY1_BASE, \ - _DKL_PHY2_BASE) + \ - _DKL_PLL_BIAS) +#define _DKL_PLL_BIAS 0x2214 +#define DKL_PLL_BIAS(tc_port) _DKL_REG(tc_port, \ + _DKL_PLL_BIAS) #define DKL_PLL_BIAS_FRAC_EN_H (1 << 30) #define DKL_PLL_BIAS_FBDIV_SHIFT (8) #define DKL_PLL_BIAS_FBDIV_FRAC(x) ((x) << DKL_PLL_BIAS_FBDIV_SHIFT) #define DKL_PLL_BIAS_FBDIV_FRAC_MASK (0x3FFFFF << DKL_PLL_BIAS_FBDIV_SHIFT) -#define _DKL_PLL_TDC_COLDST_BIAS 0x218 -#define DKL_PLL_TDC_COLDST_BIAS(tc_port) _MMIO(_PORT(tc_port, \ - _DKL_PHY1_BASE, \ - _DKL_PHY2_BASE) + \ - _DKL_PLL_TDC_COLDST_BIAS) +#define _DKL_PLL_TDC_COLDST_BIAS 0x2218 +#define DKL_PLL_TDC_COLDST_BIAS(tc_port) _DKL_REG(tc_port, \ + _DKL_PLL_TDC_COLDST_BIAS) #define DKL_PLL_TDC_SSC_STEP_SIZE(x) ((x) << 8) #define DKL_PLL_TDC_SSC_STEP_SIZE_MASK (0xFF << 8) #define DKL_PLL_TDC_FEED_FWD_GAIN(x) ((x) << 0) #define DKL_PLL_TDC_FEED_FWD_GAIN_MASK (0xFF << 0) -#define _DKL_REFCLKIN_CTL 0x12C -#define DKL_REFCLKIN_CTL(tc_port) _MMIO(_PORT(tc_port, \ - _DKL_PHY1_BASE, \ - _DKL_PHY2_BASE) + \ - _DKL_REFCLKIN_CTL) +#define _DKL_REFCLKIN_CTL 0x212C +#define DKL_REFCLKIN_CTL(tc_port) _DKL_REG(tc_port, \ + _DKL_REFCLKIN_CTL) /* Bits are the same as MG_REFCLKIN_CTL */ -#define _DKL_CLKTOP2_HSCLKCTL 0xD4 -#define DKL_CLKTOP2_HSCLKCTL(tc_port) _MMIO(_PORT(tc_port, \ - _DKL_PHY1_BASE, \ - _DKL_PHY2_BASE) + \ - _DKL_CLKTOP2_HSCLKCTL) +#define _DKL_CLKTOP2_HSCLKCTL 0x20D4 +#define DKL_CLKTOP2_HSCLKCTL(rc_port) _DKL_REG(tc_port, \ + _DKL_CLKTOP2_HSCLKCTL) /* Bits are the same as MG_CLKTOP2_HSCLKCTL */ -#define _DKL_CLKTOP2_CORECLKCTL1 0xD8 -#define DKL_CLKTOP2_CORECLKCTL1(tc_port) _MMIO(_PORT(tc_port, \ - _DKL_PHY1_BASE, \ - _DKL_PHY2_BASE) + \ - _DKL_CLKTOP2_CORECLKCTL1) +#define _DKL_CLKTOP2_CORECLKCTL1 0x20D8 +#define DKL_CLKTOP2_CORECLKCTL1(tc_port) _DKL_REG(tc_port, \ + _DKL_CLKTOP2_CORECLKCTL1) /* Bits are the same as MG_CLKTOP2_CORECLKCTL1 */ -#define _DKL_TX_DPCNTL0 0x2C0 -#define DKL_TX_DPCNTL0(tc_port) _MMIO(_PORT(tc_port, \ - _DKL_PHY1_BASE, \ - _DKL_PHY2_BASE) + \ - _DKL_TX_DPCNTL0) +#define _DKL_TX_DPCNTL0_LN0 0x02C0 +#define _DKL_TX_DPCNTL0_LN1 0x12C0 +#define DKL_TX_DPCNTL0(tc_port, ln) _DKL_REG_LN(tc_port, ln, \ + _DKL_TX_DPCNTL0_LN0, \ + _DKL_TX_DPCNTL0_LN1) #define DKL_TX_PRESHOOT_COEFF(x) ((x) << 13) #define DKL_TX_PRESHOOT_COEFF_MASK (0x1f << 13) #define DKL_TX_DE_EMPHASIS_COEFF(x) ((x) << 8) @@ -121,60 +134,58 @@ #define DKL_TX_VSWING_CONTROL(x) ((x) << 0) #define DKL_TX_VSWING_CONTROL_MASK (0x7 << 0) -#define _DKL_TX_DPCNTL1 0x2C4 -#define DKL_TX_DPCNTL1(tc_port) _MMIO(_PORT(tc_port, \ - _DKL_PHY1_BASE, \ - _DKL_PHY2_BASE) + \ - _DKL_TX_DPCNTL1) +#define _DKL_TX_DPCNTL1_LN0 0x02C4 +#define _DKL_TX_DPCNTL1_LN1 0x12C4 +#define DKL_TX_DPCNTL1(tc_port, ln) _DKL_REG_LN(tc_port, ln, \ + _DKL_TX_DPCNTL1_LN0, \ + _DKL_TX_DPCNTL1_LN1) /* Bits are the same as DKL_TX_DPCNTRL0 */ -#define _DKL_TX_DPCNTL2 0x2C8 -#define DKL_TX_DPCNTL2(tc_port) _MMIO(_PORT(tc_port, \ - _DKL_PHY1_BASE, \ - _DKL_PHY2_BASE) + \ - _DKL_TX_DPCNTL2) +#define _DKL_TX_DPCNTL2_LN0 0x02C8 +#define _DKL_TX_DPCNTL2_LN1 0x12C8 +#define DKL_TX_DPCNTL2(tc_port, ln) _DKL_REG_LN(tc_port, ln, \ + _DKL_TX_DPCNTL2_LN0, \ + _DKL_TX_DPCNTL2_LN1) #define DKL_TX_DP20BITMODE REG_BIT(2) #define DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK REG_GENMASK(4, 3) #define DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(val) REG_FIELD_PREP(DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK, (val)) #define DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK REG_GENMASK(6, 5) #define DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(val) REG_FIELD_PREP(DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK, (val)) -#define _DKL_TX_FW_CALIB 0x2F8 -#define DKL_TX_FW_CALIB(tc_port) _MMIO(_PORT(tc_port, \ - _DKL_PHY1_BASE, \ - _DKL_PHY2_BASE) + \ - _DKL_TX_FW_CALIB) +#define _DKL_TX_FW_CALIB_LN0 0x02F8 +#define _DKL_TX_FW_CALIB_LN1 0x12F8 +#define DKL_TX_FW_CALIB(tc_port, ln) _DKL_REG_LN(tc_port, ln, \ + _DKL_TX_FW_CALIB_LN0, \ + _DKL_TX_FW_CALIB_LN1) #define DKL_TX_CFG_DISABLE_WAIT_INIT (1 << 7) -#define _DKL_TX_PMD_LANE_SUS 0xD00 -#define DKL_TX_PMD_LANE_SUS(tc_port) _MMIO(_PORT(tc_port, \ - _DKL_PHY1_BASE, \ - _DKL_PHY2_BASE) + \ - _DKL_TX_PMD_LANE_SUS) +#define _DKL_TX_PMD_LANE_SUS_LN0 0x0D00 +#define _DKL_TX_PMD_LANE_SUS_LN1 0x1D00 +#define DKL_TX_PMD_LANE_SUS(tc_port, ln) _DKL_REG_LN(tc_port, ln, \ + _DKL_TX_PMD_LANE_SUS_LN0, \ + _DKL_TX_PMD_LANE_SUS_LN1) -#define _DKL_TX_DW17 0xDC4 -#define DKL_TX_DW17(tc_port) _MMIO(_PORT(tc_port, \ - _DKL_PHY1_BASE, \ - _DKL_PHY2_BASE) + \ - _DKL_TX_DW17) +#define _DKL_TX_DW17_LN0 0x0DC4 +#define _DKL_TX_DW17_LN1 0x1DC4 +#define DKL_TX_DW17(tc_port, ln) _DKL_REG_LN(tc_port, ln, \ + _DKL_TX_DW17_LN0, \ + _DKL_TX_DW17_LN1) -#define _DKL_TX_DW18 0xDC8 -#define DKL_TX_DW18(tc_port) _MMIO(_PORT(tc_port, \ - _DKL_PHY1_BASE, \ - _DKL_PHY2_BASE) + \ - _DKL_TX_DW18) +#define _DKL_TX_DW18_LN0 0x0DC8 +#define _DKL_TX_DW18_LN1 0x1DC8 +#define DKL_TX_DW18(tc_port, ln) _DKL_REG_LN(tc_port, ln, \ + _DKL_TX_DW18_LN0, \ + _DKL_TX_DW18_LN1) -#define _DKL_DP_MODE 0xA0 -#define DKL_DP_MODE(tc_port) _MMIO(_PORT(tc_port, \ - _DKL_PHY1_BASE, \ - _DKL_PHY2_BASE) + \ - _DKL_DP_MODE) +#define _DKL_DP_MODE_LN0 0x00A0 +#define _DKL_DP_MODE_LN1 0x10A0 +#define DKL_DP_MODE(tc_port, ln) _DKL_REG_LN(tc_port, ln, \ + _DKL_DP_MODE_LN0, \ + _DKL_DP_MODE_LN1) -#define _DKL_CMN_UC_DW27 0x36C -#define DKL_CMN_UC_DW_27(tc_port) _MMIO(_PORT(tc_port, \ - _DKL_PHY1_BASE, \ - _DKL_PHY2_BASE) + \ - _DKL_CMN_UC_DW27) +#define _DKL_CMN_UC_DW27 0x236C +#define DKL_CMN_UC_DW_27(tc_port) _DKL_REG(tc_port, \ + _DKL_CMN_UC_DW27) #define DKL_CMN_UC_DW27_UC_HEALTH (0x1 << 15) /* diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c index bb7c8aef89526..7c6c094a0a01d 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c @@ -3489,11 +3489,11 @@ static bool dkl_pll_get_hw_state(struct drm_i915_private *dev_priv, * they are on different building blocks */ hw_state->mg_refclkin_ctl = intel_dkl_phy_read(dev_priv, - DKL_REFCLKIN_CTL(tc_port), 2); + DKL_REFCLKIN_CTL(tc_port)); hw_state->mg_refclkin_ctl &= MG_REFCLKIN_CTL_OD_2_MUX_MASK; hw_state->mg_clktop2_hsclkctl = - intel_dkl_phy_read(dev_priv, DKL_CLKTOP2_HSCLKCTL(tc_port), 2); + intel_dkl_phy_read(dev_priv, DKL_CLKTOP2_HSCLKCTL(tc_port)); hw_state->mg_clktop2_hsclkctl &= MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK | MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK | @@ -3501,32 +3501,32 @@ static bool dkl_pll_get_hw_state(struct drm_i915_private *dev_priv, MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK; hw_state->mg_clktop2_coreclkctl1 = - intel_dkl_phy_read(dev_priv, DKL_CLKTOP2_CORECLKCTL1(tc_port), 2); + intel_dkl_phy_read(dev_priv, DKL_CLKTOP2_CORECLKCTL1(tc_port)); hw_state->mg_clktop2_coreclkctl1 &= MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK; - hw_state->mg_pll_div0 = intel_dkl_phy_read(dev_priv, DKL_PLL_DIV0(tc_port), 2); + hw_state->mg_pll_div0 = intel_dkl_phy_read(dev_priv, DKL_PLL_DIV0(tc_port)); val = DKL_PLL_DIV0_MASK; if (dev_priv->display.vbt.override_afc_startup) val |= DKL_PLL_DIV0_AFC_STARTUP_MASK; hw_state->mg_pll_div0 &= val; - hw_state->mg_pll_div1 = intel_dkl_phy_read(dev_priv, DKL_PLL_DIV1(tc_port), 2); + hw_state->mg_pll_div1 = intel_dkl_phy_read(dev_priv, DKL_PLL_DIV1(tc_port)); hw_state->mg_pll_div1 &= (DKL_PLL_DIV1_IREF_TRIM_MASK | DKL_PLL_DIV1_TDC_TARGET_CNT_MASK); - hw_state->mg_pll_ssc = intel_dkl_phy_read(dev_priv, DKL_PLL_SSC(tc_port), 2); + hw_state->mg_pll_ssc = intel_dkl_phy_read(dev_priv, DKL_PLL_SSC(tc_port)); hw_state->mg_pll_ssc &= (DKL_PLL_SSC_IREF_NDIV_RATIO_MASK | DKL_PLL_SSC_STEP_LEN_MASK | DKL_PLL_SSC_STEP_NUM_MASK | DKL_PLL_SSC_EN); - hw_state->mg_pll_bias = intel_dkl_phy_read(dev_priv, DKL_PLL_BIAS(tc_port), 2); + hw_state->mg_pll_bias = intel_dkl_phy_read(dev_priv, DKL_PLL_BIAS(tc_port)); hw_state->mg_pll_bias &= (DKL_PLL_BIAS_FRAC_EN_H | DKL_PLL_BIAS_FBDIV_FRAC_MASK); hw_state->mg_pll_tdc_coldst_bias = - intel_dkl_phy_read(dev_priv, DKL_PLL_TDC_COLDST_BIAS(tc_port), 2); + intel_dkl_phy_read(dev_priv, DKL_PLL_TDC_COLDST_BIAS(tc_port)); hw_state->mg_pll_tdc_coldst_bias &= (DKL_PLL_TDC_SSC_STEP_SIZE_MASK | DKL_PLL_TDC_FEED_FWD_GAIN_MASK); @@ -3715,57 +3715,57 @@ static void dkl_pll_write(struct drm_i915_private *dev_priv, * though on different building block */ /* All the registers are RMW */ - val = intel_dkl_phy_read(dev_priv, DKL_REFCLKIN_CTL(tc_port), 2); + val = intel_dkl_phy_read(dev_priv, DKL_REFCLKIN_CTL(tc_port)); val &= ~MG_REFCLKIN_CTL_OD_2_MUX_MASK; val |= hw_state->mg_refclkin_ctl; - intel_dkl_phy_write(dev_priv, DKL_REFCLKIN_CTL(tc_port), 2, val); + intel_dkl_phy_write(dev_priv, DKL_REFCLKIN_CTL(tc_port), val); - val = intel_dkl_phy_read(dev_priv, DKL_CLKTOP2_CORECLKCTL1(tc_port), 2); + val = intel_dkl_phy_read(dev_priv, DKL_CLKTOP2_CORECLKCTL1(tc_port)); val &= ~MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK; val |= hw_state->mg_clktop2_coreclkctl1; - intel_dkl_phy_write(dev_priv, DKL_CLKTOP2_CORECLKCTL1(tc_port), 2, val); + intel_dkl_phy_write(dev_priv, DKL_CLKTOP2_CORECLKCTL1(tc_port), val); - val = intel_dkl_phy_read(dev_priv, DKL_CLKTOP2_HSCLKCTL(tc_port), 2); + val = intel_dkl_phy_read(dev_priv, DKL_CLKTOP2_HSCLKCTL(tc_port)); val &= ~(MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK | MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK | MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK | MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK); val |= hw_state->mg_clktop2_hsclkctl; - intel_dkl_phy_write(dev_priv, DKL_CLKTOP2_HSCLKCTL(tc_port), 2, val); + intel_dkl_phy_write(dev_priv, DKL_CLKTOP2_HSCLKCTL(tc_port), val); val = DKL_PLL_DIV0_MASK; if (dev_priv->display.vbt.override_afc_startup) val |= DKL_PLL_DIV0_AFC_STARTUP_MASK; - intel_dkl_phy_rmw(dev_priv, DKL_PLL_DIV0(tc_port), 2, val, + intel_dkl_phy_rmw(dev_priv, DKL_PLL_DIV0(tc_port), val, hw_state->mg_pll_div0); - val = intel_dkl_phy_read(dev_priv, DKL_PLL_DIV1(tc_port), 2); + val = intel_dkl_phy_read(dev_priv, DKL_PLL_DIV1(tc_port)); val &= ~(DKL_PLL_DIV1_IREF_TRIM_MASK | DKL_PLL_DIV1_TDC_TARGET_CNT_MASK); val |= hw_state->mg_pll_div1; - intel_dkl_phy_write(dev_priv, DKL_PLL_DIV1(tc_port), 2, val); + intel_dkl_phy_write(dev_priv, DKL_PLL_DIV1(tc_port), val); - val = intel_dkl_phy_read(dev_priv, DKL_PLL_SSC(tc_port), 2); + val = intel_dkl_phy_read(dev_priv, DKL_PLL_SSC(tc_port)); val &= ~(DKL_PLL_SSC_IREF_NDIV_RATIO_MASK | DKL_PLL_SSC_STEP_LEN_MASK | DKL_PLL_SSC_STEP_NUM_MASK | DKL_PLL_SSC_EN); val |= hw_state->mg_pll_ssc; - intel_dkl_phy_write(dev_priv, DKL_PLL_SSC(tc_port), 2, val); + intel_dkl_phy_write(dev_priv, DKL_PLL_SSC(tc_port), val); - val = intel_dkl_phy_read(dev_priv, DKL_PLL_BIAS(tc_port), 2); + val = intel_dkl_phy_read(dev_priv, DKL_PLL_BIAS(tc_port)); val &= ~(DKL_PLL_BIAS_FRAC_EN_H | DKL_PLL_BIAS_FBDIV_FRAC_MASK); val |= hw_state->mg_pll_bias; - intel_dkl_phy_write(dev_priv, DKL_PLL_BIAS(tc_port), 2, val); + intel_dkl_phy_write(dev_priv, DKL_PLL_BIAS(tc_port), val); - val = intel_dkl_phy_read(dev_priv, DKL_PLL_TDC_COLDST_BIAS(tc_port), 2); + val = intel_dkl_phy_read(dev_priv, DKL_PLL_TDC_COLDST_BIAS(tc_port)); val &= ~(DKL_PLL_TDC_SSC_STEP_SIZE_MASK | DKL_PLL_TDC_FEED_FWD_GAIN_MASK); val |= hw_state->mg_pll_tdc_coldst_bias; - intel_dkl_phy_write(dev_priv, DKL_PLL_TDC_COLDST_BIAS(tc_port), 2, val); + intel_dkl_phy_write(dev_priv, DKL_PLL_TDC_COLDST_BIAS(tc_port), val); - intel_dkl_phy_posting_read(dev_priv, DKL_PLL_TDC_COLDST_BIAS(tc_port), 2); + intel_dkl_phy_posting_read(dev_priv, DKL_PLL_TDC_COLDST_BIAS(tc_port)); } static void icl_pll_power_enable(struct drm_i915_private *dev_priv, -- 2.37.1 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [Intel-gfx] [PATCH v4 4/4] drm/i915/tgl+: Sanitize DKL PHY register definitions 2022-10-25 10:26 ` [Intel-gfx] [PATCH v3 4/4] drm/i915/tgl+: Sanitize DKL PHY register definitions Imre Deak @ 2022-10-25 11:44 ` Imre Deak 0 siblings, 0 replies; 16+ messages in thread From: Imre Deak @ 2022-10-25 11:44 UTC (permalink / raw) To: intel-gfx; +Cc: Jani Nikula Not all Dekel PHY registers have a lane instance, so having to specify this when using them is awkward. It makes more sense to define each PHY register with its full internal PHY offset where bits 15:12 is the lane for lane-instanced PHY registers and just a register bank index for other PHY registers. This way lane-instanced registers can be referred to with the (tc_port, lane) parameters, while other registers just with a tc_port parameter. An additional benefit of this change is to prevent passing a Dekel register to a generic MMIO access function or vice versa. v2: - Fix parameter reuse in the DKL_REG_MMIO definition. v3: - Rebase on latest patchset version. Cc: Jani Nikula <jani.nikula@intel.com> Acked-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> --- drivers/gpu/drm/i915/display/intel_ddi.c | 20 +- .../i915/display/intel_display_power_well.c | 2 +- drivers/gpu/drm/i915/display/intel_dkl_phy.c | 32 ++- drivers/gpu/drm/i915/display/intel_dkl_phy.h | 10 +- .../gpu/drm/i915/display/intel_dkl_phy_regs.h | 191 +++++++++--------- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 48 ++--- 6 files changed, 155 insertions(+), 148 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 54142ca3e6947..e95bde5cf060e 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -1264,11 +1264,11 @@ static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder, for (ln = 0; ln < 2; ln++) { int level; - intel_dkl_phy_write(dev_priv, DKL_TX_PMD_LANE_SUS(tc_port), ln, 0); + intel_dkl_phy_write(dev_priv, DKL_TX_PMD_LANE_SUS(tc_port, ln), 0); level = intel_ddi_level(encoder, crtc_state, 2*ln+0); - intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL0(tc_port), ln, + intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL0(tc_port, ln), DKL_TX_PRESHOOT_COEFF_MASK | DKL_TX_DE_EMPAHSIS_COEFF_MASK | DKL_TX_VSWING_CONTROL_MASK, @@ -1278,7 +1278,7 @@ static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder, level = intel_ddi_level(encoder, crtc_state, 2*ln+1); - intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL1(tc_port), ln, + intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL1(tc_port, ln), DKL_TX_PRESHOOT_COEFF_MASK | DKL_TX_DE_EMPAHSIS_COEFF_MASK | DKL_TX_VSWING_CONTROL_MASK, @@ -1286,7 +1286,7 @@ static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder, DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) | DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing)); - intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port), ln, + intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port, ln), DKL_TX_DP20BITMODE, 0); if (IS_ALDERLAKE_P(dev_priv)) { @@ -1305,7 +1305,7 @@ static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder, val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(0); } - intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port), ln, + intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port, ln), DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK | DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK, val); @@ -2018,8 +2018,8 @@ icl_program_mg_dp_mode(struct intel_digital_port *dig_port, return; if (DISPLAY_VER(dev_priv) >= 12) { - ln0 = intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port), 0); - ln1 = intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port), 1); + ln0 = intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port, 0)); + ln1 = intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port, 1)); } else { ln0 = intel_de_read(dev_priv, MG_DP_MODE(0, tc_port)); ln1 = intel_de_read(dev_priv, MG_DP_MODE(1, tc_port)); @@ -2080,8 +2080,8 @@ icl_program_mg_dp_mode(struct intel_digital_port *dig_port, } if (DISPLAY_VER(dev_priv) >= 12) { - intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port), 0, ln0); - intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port), 1, ln1); + intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 0), ln0); + intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 1), ln1); } else { intel_de_write(dev_priv, MG_DP_MODE(0, tc_port), ln0); intel_de_write(dev_priv, MG_DP_MODE(1, tc_port), ln1); @@ -3086,7 +3086,7 @@ static void adlp_tbt_to_dp_alt_switch_wa(struct intel_encoder *encoder) int ln; for (ln = 0; ln < 2; ln++) - intel_dkl_phy_rmw(i915, DKL_PCS_DW5(tc_port), ln, DKL_PCS_DW5_CORE_SOFTRESET, 0); + intel_dkl_phy_rmw(i915, DKL_PCS_DW5(tc_port, ln), DKL_PCS_DW5_CORE_SOFTRESET, 0); } static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp, diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c index 86974c515206e..8710dd41ffd4c 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c @@ -532,7 +532,7 @@ icl_tc_phy_aux_power_well_enable(struct drm_i915_private *dev_priv, tc_port = TGL_AUX_PW_TO_TC_PORT(i915_power_well_instance(power_well)->hsw.idx); - if (wait_for(intel_dkl_phy_read(dev_priv, DKL_CMN_UC_DW_27(tc_port), 2) & + if (wait_for(intel_dkl_phy_read(dev_priv, DKL_CMN_UC_DW_27(tc_port)) & DKL_CMN_UC_DW27_UC_HEALTH, 1)) drm_warn(&dev_priv->drm, "Timeout waiting TC uC health\n"); diff --git a/drivers/gpu/drm/i915/display/intel_dkl_phy.c b/drivers/gpu/drm/i915/display/intel_dkl_phy.c index 01781293ffdcf..57cc3edba0163 100644 --- a/drivers/gpu/drm/i915/display/intel_dkl_phy.c +++ b/drivers/gpu/drm/i915/display/intel_dkl_phy.c @@ -12,7 +12,7 @@ #include "intel_dkl_phy_regs.h" static void -dkl_phy_set_hip_idx(struct drm_i915_private *i915, i915_reg_t reg, int idx) +dkl_phy_set_hip_idx(struct drm_i915_private *i915, struct intel_dkl_phy_reg reg) { enum tc_port tc_port = DKL_REG_TC_PORT(reg); @@ -20,28 +20,27 @@ dkl_phy_set_hip_idx(struct drm_i915_private *i915, i915_reg_t reg, int idx) intel_de_write(i915, HIP_INDEX_REG(tc_port), - HIP_INDEX_VAL(tc_port, idx)); + HIP_INDEX_VAL(tc_port, reg.bank_idx)); } /** * intel_dkl_phy_read - read a Dekel PHY register * @i915: i915 device instance * @reg: Dekel PHY register - * @ln: lane instance of @reg * * Read the @reg Dekel PHY register. * * Returns the read value. */ u32 -intel_dkl_phy_read(struct drm_i915_private *i915, i915_reg_t reg, int ln) +intel_dkl_phy_read(struct drm_i915_private *i915, struct intel_dkl_phy_reg reg) { u32 val; spin_lock(&i915->display.dkl.phy_lock); - dkl_phy_set_hip_idx(i915, reg, ln); - val = intel_de_read(i915, reg); + dkl_phy_set_hip_idx(i915, reg); + val = intel_de_read(i915, DKL_REG_MMIO(reg)); spin_unlock(&i915->display.dkl.phy_lock); @@ -52,18 +51,17 @@ intel_dkl_phy_read(struct drm_i915_private *i915, i915_reg_t reg, int ln) * intel_dkl_phy_write - write a Dekel PHY register * @i915: i915 device instance * @reg: Dekel PHY register - * @ln: lane instance of @reg * @val: value to write * * Write @val to the @reg Dekel PHY register. */ void -intel_dkl_phy_write(struct drm_i915_private *i915, i915_reg_t reg, int ln, u32 val) +intel_dkl_phy_write(struct drm_i915_private *i915, struct intel_dkl_phy_reg reg, u32 val) { spin_lock(&i915->display.dkl.phy_lock); - dkl_phy_set_hip_idx(i915, reg, ln); - intel_de_write(i915, reg, val); + dkl_phy_set_hip_idx(i915, reg); + intel_de_write(i915, DKL_REG_MMIO(reg), val); spin_unlock(&i915->display.dkl.phy_lock); } @@ -72,7 +70,6 @@ intel_dkl_phy_write(struct drm_i915_private *i915, i915_reg_t reg, int ln, u32 v * intel_dkl_phy_rmw - read-modify-write a Dekel PHY register * @i915: i915 device instance * @reg: Dekel PHY register - * @ln: lane instance of @reg * @clear: mask to clear * @set: mask to set * @@ -80,12 +77,12 @@ intel_dkl_phy_write(struct drm_i915_private *i915, i915_reg_t reg, int ln, u32 v * this value back to the register if the value differs from the read one. */ void -intel_dkl_phy_rmw(struct drm_i915_private *i915, i915_reg_t reg, int ln, u32 clear, u32 set) +intel_dkl_phy_rmw(struct drm_i915_private *i915, struct intel_dkl_phy_reg reg, u32 clear, u32 set) { spin_lock(&i915->display.dkl.phy_lock); - dkl_phy_set_hip_idx(i915, reg, ln); - intel_de_rmw(i915, reg, clear, set); + dkl_phy_set_hip_idx(i915, reg); + intel_de_rmw(i915, DKL_REG_MMIO(reg), clear, set); spin_unlock(&i915->display.dkl.phy_lock); } @@ -94,17 +91,16 @@ intel_dkl_phy_rmw(struct drm_i915_private *i915, i915_reg_t reg, int ln, u32 cle * intel_dkl_phy_posting_read - do a posting read from a Dekel PHY register * @i915: i915 device instance * @reg: Dekel PHY register - * @ln: lane instance of @reg * * Read the @reg Dekel PHY register without returning the read value. */ void -intel_dkl_phy_posting_read(struct drm_i915_private *i915, i915_reg_t reg, int ln) +intel_dkl_phy_posting_read(struct drm_i915_private *i915, struct intel_dkl_phy_reg reg) { spin_lock(&i915->display.dkl.phy_lock); - dkl_phy_set_hip_idx(i915, reg, ln); - intel_de_posting_read(i915, reg); + dkl_phy_set_hip_idx(i915, reg); + intel_de_posting_read(i915, DKL_REG_MMIO(reg)); spin_unlock(&i915->display.dkl.phy_lock); } diff --git a/drivers/gpu/drm/i915/display/intel_dkl_phy.h b/drivers/gpu/drm/i915/display/intel_dkl_phy.h index 260ad121a0b18..570ee36f9386f 100644 --- a/drivers/gpu/drm/i915/display/intel_dkl_phy.h +++ b/drivers/gpu/drm/i915/display/intel_dkl_phy.h @@ -8,17 +8,17 @@ #include <linux/types.h> -#include "i915_reg_defs.h" +#include "intel_dkl_phy_regs.h" struct drm_i915_private; u32 -intel_dkl_phy_read(struct drm_i915_private *i915, i915_reg_t reg, int ln); +intel_dkl_phy_read(struct drm_i915_private *i915, struct intel_dkl_phy_reg reg); void -intel_dkl_phy_write(struct drm_i915_private *i915, i915_reg_t reg, int ln, u32 val); +intel_dkl_phy_write(struct drm_i915_private *i915, struct intel_dkl_phy_reg reg, u32 val); void -intel_dkl_phy_rmw(struct drm_i915_private *i915, i915_reg_t reg, int ln, u32 clear, u32 set); +intel_dkl_phy_rmw(struct drm_i915_private *i915, struct intel_dkl_phy_reg reg, u32 clear, u32 set); void -intel_dkl_phy_posting_read(struct drm_i915_private *i915, i915_reg_t reg, int ln); +intel_dkl_phy_posting_read(struct drm_i915_private *i915, struct intel_dkl_phy_reg reg); #endif /* __INTEL_DKL_PHY_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_dkl_phy_regs.h b/drivers/gpu/drm/i915/display/intel_dkl_phy_regs.h index 7d0f3aab7f5c6..56085b32956d8 100644 --- a/drivers/gpu/drm/i915/display/intel_dkl_phy_regs.h +++ b/drivers/gpu/drm/i915/display/intel_dkl_phy_regs.h @@ -6,6 +6,13 @@ #ifndef __INTEL_DKL_PHY_REGS__ #define __INTEL_DKL_PHY_REGS__ +#include <linux/types.h> + +struct intel_dkl_phy_reg { + u32 reg:24; + u32 bank_idx:4; +}; + #define _DKL_PHY1_BASE 0x168000 #define _DKL_PHY2_BASE 0x169000 #define _DKL_PHY3_BASE 0x16A000 @@ -17,18 +24,38 @@ (TC_PORT_1 + ((__reg).reg - _DKL_PHY1_BASE) / (_DKL_PHY2_BASE - _DKL_PHY1_BASE)) /* DEKEL PHY MMIO Address = Phy base + (internal address & ~index_mask) */ -#define _DKL_PCS_DW5 0x14 -#define DKL_PCS_DW5(tc_port) _MMIO(_PORT(tc_port, \ - _DKL_PHY1_BASE, \ - _DKL_PHY2_BASE) + \ - _DKL_PCS_DW5) +#define DKL_REG_MMIO(__reg) _MMIO((__reg).reg) + +#define _DKL_REG_PHY_BASE(tc_port) _PORT(tc_port, \ + _DKL_PHY1_BASE, \ + _DKL_PHY2_BASE) + +#define _DKL_BANK_SHIFT 12 +#define _DKL_REG_BANK_OFFSET(phy_offset) \ + ((phy_offset) & ((1 << _DKL_BANK_SHIFT) - 1)) +#define _DKL_REG_BANK_IDX(phy_offset) \ + (((phy_offset) >> _DKL_BANK_SHIFT) & 0xf) + +#define _DKL_REG(tc_port, phy_offset) \ + ((const struct intel_dkl_phy_reg) { \ + .reg = _DKL_REG_PHY_BASE(tc_port) + \ + _DKL_REG_BANK_OFFSET(phy_offset), \ + .bank_idx = _DKL_REG_BANK_IDX(phy_offset), \ + }) + +#define _DKL_REG_LN(tc_port, ln_idx, ln0_offs, ln1_offs) \ + _DKL_REG(tc_port, (ln0_offs) + (ln_idx) * ((ln1_offs) - (ln0_offs))) + +#define _DKL_PCS_DW5_LN0 0x0014 +#define _DKL_PCS_DW5_LN1 0x1014 +#define DKL_PCS_DW5(tc_port, ln) _DKL_REG_LN(tc_port, ln, \ + _DKL_PCS_DW5_LN0, \ + _DKL_PCS_DW5_LN1) #define DKL_PCS_DW5_CORE_SOFTRESET REG_BIT(11) -#define _DKL_PLL_DIV0 0x200 -#define DKL_PLL_DIV0(tc_port) _MMIO(_PORT(tc_port, \ - _DKL_PHY1_BASE, \ - _DKL_PHY2_BASE) + \ - _DKL_PLL_DIV0) +#define _DKL_PLL_DIV0 0x2200 +#define DKL_PLL_DIV0(tc_port) _DKL_REG(tc_port, \ + _DKL_PLL_DIV0) #define DKL_PLL_DIV0_AFC_STARTUP_MASK REG_GENMASK(27, 25) #define DKL_PLL_DIV0_AFC_STARTUP(val) REG_FIELD_PREP(DKL_PLL_DIV0_AFC_STARTUP_MASK, (val)) #define DKL_PLL_DIV0_INTEG_COEFF(x) ((x) << 16) @@ -45,21 +72,17 @@ DKL_PLL_DIV0_FBPREDIV_MASK | \ DKL_PLL_DIV0_FBDIV_INT_MASK) -#define _DKL_PLL_DIV1 0x204 -#define DKL_PLL_DIV1(tc_port) _MMIO(_PORT(tc_port, \ - _DKL_PHY1_BASE, \ - _DKL_PHY2_BASE) + \ - _DKL_PLL_DIV1) +#define _DKL_PLL_DIV1 0x2204 +#define DKL_PLL_DIV1(tc_port) _DKL_REG(tc_port, \ + _DKL_PLL_DIV1) #define DKL_PLL_DIV1_IREF_TRIM(x) ((x) << 16) #define DKL_PLL_DIV1_IREF_TRIM_MASK (0x1F << 16) #define DKL_PLL_DIV1_TDC_TARGET_CNT(x) ((x) << 0) #define DKL_PLL_DIV1_TDC_TARGET_CNT_MASK (0xFF << 0) -#define _DKL_PLL_SSC 0x210 -#define DKL_PLL_SSC(tc_port) _MMIO(_PORT(tc_port, \ - _DKL_PHY1_BASE, \ - _DKL_PHY2_BASE) + \ - _DKL_PLL_SSC) +#define _DKL_PLL_SSC 0x2210 +#define DKL_PLL_SSC(tc_port) _DKL_REG(tc_port, \ + _DKL_PLL_SSC) #define DKL_PLL_SSC_IREF_NDIV_RATIO(x) ((x) << 29) #define DKL_PLL_SSC_IREF_NDIV_RATIO_MASK (0x7 << 29) #define DKL_PLL_SSC_STEP_LEN(x) ((x) << 16) @@ -68,52 +91,42 @@ #define DKL_PLL_SSC_STEP_NUM_MASK (0x7 << 11) #define DKL_PLL_SSC_EN (1 << 9) -#define _DKL_PLL_BIAS 0x214 -#define DKL_PLL_BIAS(tc_port) _MMIO(_PORT(tc_port, \ - _DKL_PHY1_BASE, \ - _DKL_PHY2_BASE) + \ - _DKL_PLL_BIAS) +#define _DKL_PLL_BIAS 0x2214 +#define DKL_PLL_BIAS(tc_port) _DKL_REG(tc_port, \ + _DKL_PLL_BIAS) #define DKL_PLL_BIAS_FRAC_EN_H (1 << 30) #define DKL_PLL_BIAS_FBDIV_SHIFT (8) #define DKL_PLL_BIAS_FBDIV_FRAC(x) ((x) << DKL_PLL_BIAS_FBDIV_SHIFT) #define DKL_PLL_BIAS_FBDIV_FRAC_MASK (0x3FFFFF << DKL_PLL_BIAS_FBDIV_SHIFT) -#define _DKL_PLL_TDC_COLDST_BIAS 0x218 -#define DKL_PLL_TDC_COLDST_BIAS(tc_port) _MMIO(_PORT(tc_port, \ - _DKL_PHY1_BASE, \ - _DKL_PHY2_BASE) + \ - _DKL_PLL_TDC_COLDST_BIAS) +#define _DKL_PLL_TDC_COLDST_BIAS 0x2218 +#define DKL_PLL_TDC_COLDST_BIAS(tc_port) _DKL_REG(tc_port, \ + _DKL_PLL_TDC_COLDST_BIAS) #define DKL_PLL_TDC_SSC_STEP_SIZE(x) ((x) << 8) #define DKL_PLL_TDC_SSC_STEP_SIZE_MASK (0xFF << 8) #define DKL_PLL_TDC_FEED_FWD_GAIN(x) ((x) << 0) #define DKL_PLL_TDC_FEED_FWD_GAIN_MASK (0xFF << 0) -#define _DKL_REFCLKIN_CTL 0x12C -#define DKL_REFCLKIN_CTL(tc_port) _MMIO(_PORT(tc_port, \ - _DKL_PHY1_BASE, \ - _DKL_PHY2_BASE) + \ - _DKL_REFCLKIN_CTL) +#define _DKL_REFCLKIN_CTL 0x212C +#define DKL_REFCLKIN_CTL(tc_port) _DKL_REG(tc_port, \ + _DKL_REFCLKIN_CTL) /* Bits are the same as MG_REFCLKIN_CTL */ -#define _DKL_CLKTOP2_HSCLKCTL 0xD4 -#define DKL_CLKTOP2_HSCLKCTL(tc_port) _MMIO(_PORT(tc_port, \ - _DKL_PHY1_BASE, \ - _DKL_PHY2_BASE) + \ - _DKL_CLKTOP2_HSCLKCTL) +#define _DKL_CLKTOP2_HSCLKCTL 0x20D4 +#define DKL_CLKTOP2_HSCLKCTL(rc_port) _DKL_REG(tc_port, \ + _DKL_CLKTOP2_HSCLKCTL) /* Bits are the same as MG_CLKTOP2_HSCLKCTL */ -#define _DKL_CLKTOP2_CORECLKCTL1 0xD8 -#define DKL_CLKTOP2_CORECLKCTL1(tc_port) _MMIO(_PORT(tc_port, \ - _DKL_PHY1_BASE, \ - _DKL_PHY2_BASE) + \ - _DKL_CLKTOP2_CORECLKCTL1) +#define _DKL_CLKTOP2_CORECLKCTL1 0x20D8 +#define DKL_CLKTOP2_CORECLKCTL1(tc_port) _DKL_REG(tc_port, \ + _DKL_CLKTOP2_CORECLKCTL1) /* Bits are the same as MG_CLKTOP2_CORECLKCTL1 */ -#define _DKL_TX_DPCNTL0 0x2C0 -#define DKL_TX_DPCNTL0(tc_port) _MMIO(_PORT(tc_port, \ - _DKL_PHY1_BASE, \ - _DKL_PHY2_BASE) + \ - _DKL_TX_DPCNTL0) +#define _DKL_TX_DPCNTL0_LN0 0x02C0 +#define _DKL_TX_DPCNTL0_LN1 0x12C0 +#define DKL_TX_DPCNTL0(tc_port, ln) _DKL_REG_LN(tc_port, ln, \ + _DKL_TX_DPCNTL0_LN0, \ + _DKL_TX_DPCNTL0_LN1) #define DKL_TX_PRESHOOT_COEFF(x) ((x) << 13) #define DKL_TX_PRESHOOT_COEFF_MASK (0x1f << 13) #define DKL_TX_DE_EMPHASIS_COEFF(x) ((x) << 8) @@ -121,60 +134,58 @@ #define DKL_TX_VSWING_CONTROL(x) ((x) << 0) #define DKL_TX_VSWING_CONTROL_MASK (0x7 << 0) -#define _DKL_TX_DPCNTL1 0x2C4 -#define DKL_TX_DPCNTL1(tc_port) _MMIO(_PORT(tc_port, \ - _DKL_PHY1_BASE, \ - _DKL_PHY2_BASE) + \ - _DKL_TX_DPCNTL1) +#define _DKL_TX_DPCNTL1_LN0 0x02C4 +#define _DKL_TX_DPCNTL1_LN1 0x12C4 +#define DKL_TX_DPCNTL1(tc_port, ln) _DKL_REG_LN(tc_port, ln, \ + _DKL_TX_DPCNTL1_LN0, \ + _DKL_TX_DPCNTL1_LN1) /* Bits are the same as DKL_TX_DPCNTRL0 */ -#define _DKL_TX_DPCNTL2 0x2C8 -#define DKL_TX_DPCNTL2(tc_port) _MMIO(_PORT(tc_port, \ - _DKL_PHY1_BASE, \ - _DKL_PHY2_BASE) + \ - _DKL_TX_DPCNTL2) +#define _DKL_TX_DPCNTL2_LN0 0x02C8 +#define _DKL_TX_DPCNTL2_LN1 0x12C8 +#define DKL_TX_DPCNTL2(tc_port, ln) _DKL_REG_LN(tc_port, ln, \ + _DKL_TX_DPCNTL2_LN0, \ + _DKL_TX_DPCNTL2_LN1) #define DKL_TX_DP20BITMODE REG_BIT(2) #define DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK REG_GENMASK(4, 3) #define DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(val) REG_FIELD_PREP(DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK, (val)) #define DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK REG_GENMASK(6, 5) #define DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(val) REG_FIELD_PREP(DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK, (val)) -#define _DKL_TX_FW_CALIB 0x2F8 -#define DKL_TX_FW_CALIB(tc_port) _MMIO(_PORT(tc_port, \ - _DKL_PHY1_BASE, \ - _DKL_PHY2_BASE) + \ - _DKL_TX_FW_CALIB) +#define _DKL_TX_FW_CALIB_LN0 0x02F8 +#define _DKL_TX_FW_CALIB_LN1 0x12F8 +#define DKL_TX_FW_CALIB(tc_port, ln) _DKL_REG_LN(tc_port, ln, \ + _DKL_TX_FW_CALIB_LN0, \ + _DKL_TX_FW_CALIB_LN1) #define DKL_TX_CFG_DISABLE_WAIT_INIT (1 << 7) -#define _DKL_TX_PMD_LANE_SUS 0xD00 -#define DKL_TX_PMD_LANE_SUS(tc_port) _MMIO(_PORT(tc_port, \ - _DKL_PHY1_BASE, \ - _DKL_PHY2_BASE) + \ - _DKL_TX_PMD_LANE_SUS) +#define _DKL_TX_PMD_LANE_SUS_LN0 0x0D00 +#define _DKL_TX_PMD_LANE_SUS_LN1 0x1D00 +#define DKL_TX_PMD_LANE_SUS(tc_port, ln) _DKL_REG_LN(tc_port, ln, \ + _DKL_TX_PMD_LANE_SUS_LN0, \ + _DKL_TX_PMD_LANE_SUS_LN1) -#define _DKL_TX_DW17 0xDC4 -#define DKL_TX_DW17(tc_port) _MMIO(_PORT(tc_port, \ - _DKL_PHY1_BASE, \ - _DKL_PHY2_BASE) + \ - _DKL_TX_DW17) +#define _DKL_TX_DW17_LN0 0x0DC4 +#define _DKL_TX_DW17_LN1 0x1DC4 +#define DKL_TX_DW17(tc_port, ln) _DKL_REG_LN(tc_port, ln, \ + _DKL_TX_DW17_LN0, \ + _DKL_TX_DW17_LN1) -#define _DKL_TX_DW18 0xDC8 -#define DKL_TX_DW18(tc_port) _MMIO(_PORT(tc_port, \ - _DKL_PHY1_BASE, \ - _DKL_PHY2_BASE) + \ - _DKL_TX_DW18) +#define _DKL_TX_DW18_LN0 0x0DC8 +#define _DKL_TX_DW18_LN1 0x1DC8 +#define DKL_TX_DW18(tc_port, ln) _DKL_REG_LN(tc_port, ln, \ + _DKL_TX_DW18_LN0, \ + _DKL_TX_DW18_LN1) -#define _DKL_DP_MODE 0xA0 -#define DKL_DP_MODE(tc_port) _MMIO(_PORT(tc_port, \ - _DKL_PHY1_BASE, \ - _DKL_PHY2_BASE) + \ - _DKL_DP_MODE) +#define _DKL_DP_MODE_LN0 0x00A0 +#define _DKL_DP_MODE_LN1 0x10A0 +#define DKL_DP_MODE(tc_port, ln) _DKL_REG_LN(tc_port, ln, \ + _DKL_DP_MODE_LN0, \ + _DKL_DP_MODE_LN1) -#define _DKL_CMN_UC_DW27 0x36C -#define DKL_CMN_UC_DW_27(tc_port) _MMIO(_PORT(tc_port, \ - _DKL_PHY1_BASE, \ - _DKL_PHY2_BASE) + \ - _DKL_CMN_UC_DW27) +#define _DKL_CMN_UC_DW27 0x236C +#define DKL_CMN_UC_DW_27(tc_port) _DKL_REG(tc_port, \ + _DKL_CMN_UC_DW27) #define DKL_CMN_UC_DW27_UC_HEALTH (0x1 << 15) /* diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c index bb7c8aef89526..7c6c094a0a01d 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c @@ -3489,11 +3489,11 @@ static bool dkl_pll_get_hw_state(struct drm_i915_private *dev_priv, * they are on different building blocks */ hw_state->mg_refclkin_ctl = intel_dkl_phy_read(dev_priv, - DKL_REFCLKIN_CTL(tc_port), 2); + DKL_REFCLKIN_CTL(tc_port)); hw_state->mg_refclkin_ctl &= MG_REFCLKIN_CTL_OD_2_MUX_MASK; hw_state->mg_clktop2_hsclkctl = - intel_dkl_phy_read(dev_priv, DKL_CLKTOP2_HSCLKCTL(tc_port), 2); + intel_dkl_phy_read(dev_priv, DKL_CLKTOP2_HSCLKCTL(tc_port)); hw_state->mg_clktop2_hsclkctl &= MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK | MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK | @@ -3501,32 +3501,32 @@ static bool dkl_pll_get_hw_state(struct drm_i915_private *dev_priv, MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK; hw_state->mg_clktop2_coreclkctl1 = - intel_dkl_phy_read(dev_priv, DKL_CLKTOP2_CORECLKCTL1(tc_port), 2); + intel_dkl_phy_read(dev_priv, DKL_CLKTOP2_CORECLKCTL1(tc_port)); hw_state->mg_clktop2_coreclkctl1 &= MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK; - hw_state->mg_pll_div0 = intel_dkl_phy_read(dev_priv, DKL_PLL_DIV0(tc_port), 2); + hw_state->mg_pll_div0 = intel_dkl_phy_read(dev_priv, DKL_PLL_DIV0(tc_port)); val = DKL_PLL_DIV0_MASK; if (dev_priv->display.vbt.override_afc_startup) val |= DKL_PLL_DIV0_AFC_STARTUP_MASK; hw_state->mg_pll_div0 &= val; - hw_state->mg_pll_div1 = intel_dkl_phy_read(dev_priv, DKL_PLL_DIV1(tc_port), 2); + hw_state->mg_pll_div1 = intel_dkl_phy_read(dev_priv, DKL_PLL_DIV1(tc_port)); hw_state->mg_pll_div1 &= (DKL_PLL_DIV1_IREF_TRIM_MASK | DKL_PLL_DIV1_TDC_TARGET_CNT_MASK); - hw_state->mg_pll_ssc = intel_dkl_phy_read(dev_priv, DKL_PLL_SSC(tc_port), 2); + hw_state->mg_pll_ssc = intel_dkl_phy_read(dev_priv, DKL_PLL_SSC(tc_port)); hw_state->mg_pll_ssc &= (DKL_PLL_SSC_IREF_NDIV_RATIO_MASK | DKL_PLL_SSC_STEP_LEN_MASK | DKL_PLL_SSC_STEP_NUM_MASK | DKL_PLL_SSC_EN); - hw_state->mg_pll_bias = intel_dkl_phy_read(dev_priv, DKL_PLL_BIAS(tc_port), 2); + hw_state->mg_pll_bias = intel_dkl_phy_read(dev_priv, DKL_PLL_BIAS(tc_port)); hw_state->mg_pll_bias &= (DKL_PLL_BIAS_FRAC_EN_H | DKL_PLL_BIAS_FBDIV_FRAC_MASK); hw_state->mg_pll_tdc_coldst_bias = - intel_dkl_phy_read(dev_priv, DKL_PLL_TDC_COLDST_BIAS(tc_port), 2); + intel_dkl_phy_read(dev_priv, DKL_PLL_TDC_COLDST_BIAS(tc_port)); hw_state->mg_pll_tdc_coldst_bias &= (DKL_PLL_TDC_SSC_STEP_SIZE_MASK | DKL_PLL_TDC_FEED_FWD_GAIN_MASK); @@ -3715,57 +3715,57 @@ static void dkl_pll_write(struct drm_i915_private *dev_priv, * though on different building block */ /* All the registers are RMW */ - val = intel_dkl_phy_read(dev_priv, DKL_REFCLKIN_CTL(tc_port), 2); + val = intel_dkl_phy_read(dev_priv, DKL_REFCLKIN_CTL(tc_port)); val &= ~MG_REFCLKIN_CTL_OD_2_MUX_MASK; val |= hw_state->mg_refclkin_ctl; - intel_dkl_phy_write(dev_priv, DKL_REFCLKIN_CTL(tc_port), 2, val); + intel_dkl_phy_write(dev_priv, DKL_REFCLKIN_CTL(tc_port), val); - val = intel_dkl_phy_read(dev_priv, DKL_CLKTOP2_CORECLKCTL1(tc_port), 2); + val = intel_dkl_phy_read(dev_priv, DKL_CLKTOP2_CORECLKCTL1(tc_port)); val &= ~MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK; val |= hw_state->mg_clktop2_coreclkctl1; - intel_dkl_phy_write(dev_priv, DKL_CLKTOP2_CORECLKCTL1(tc_port), 2, val); + intel_dkl_phy_write(dev_priv, DKL_CLKTOP2_CORECLKCTL1(tc_port), val); - val = intel_dkl_phy_read(dev_priv, DKL_CLKTOP2_HSCLKCTL(tc_port), 2); + val = intel_dkl_phy_read(dev_priv, DKL_CLKTOP2_HSCLKCTL(tc_port)); val &= ~(MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK | MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK | MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK | MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK); val |= hw_state->mg_clktop2_hsclkctl; - intel_dkl_phy_write(dev_priv, DKL_CLKTOP2_HSCLKCTL(tc_port), 2, val); + intel_dkl_phy_write(dev_priv, DKL_CLKTOP2_HSCLKCTL(tc_port), val); val = DKL_PLL_DIV0_MASK; if (dev_priv->display.vbt.override_afc_startup) val |= DKL_PLL_DIV0_AFC_STARTUP_MASK; - intel_dkl_phy_rmw(dev_priv, DKL_PLL_DIV0(tc_port), 2, val, + intel_dkl_phy_rmw(dev_priv, DKL_PLL_DIV0(tc_port), val, hw_state->mg_pll_div0); - val = intel_dkl_phy_read(dev_priv, DKL_PLL_DIV1(tc_port), 2); + val = intel_dkl_phy_read(dev_priv, DKL_PLL_DIV1(tc_port)); val &= ~(DKL_PLL_DIV1_IREF_TRIM_MASK | DKL_PLL_DIV1_TDC_TARGET_CNT_MASK); val |= hw_state->mg_pll_div1; - intel_dkl_phy_write(dev_priv, DKL_PLL_DIV1(tc_port), 2, val); + intel_dkl_phy_write(dev_priv, DKL_PLL_DIV1(tc_port), val); - val = intel_dkl_phy_read(dev_priv, DKL_PLL_SSC(tc_port), 2); + val = intel_dkl_phy_read(dev_priv, DKL_PLL_SSC(tc_port)); val &= ~(DKL_PLL_SSC_IREF_NDIV_RATIO_MASK | DKL_PLL_SSC_STEP_LEN_MASK | DKL_PLL_SSC_STEP_NUM_MASK | DKL_PLL_SSC_EN); val |= hw_state->mg_pll_ssc; - intel_dkl_phy_write(dev_priv, DKL_PLL_SSC(tc_port), 2, val); + intel_dkl_phy_write(dev_priv, DKL_PLL_SSC(tc_port), val); - val = intel_dkl_phy_read(dev_priv, DKL_PLL_BIAS(tc_port), 2); + val = intel_dkl_phy_read(dev_priv, DKL_PLL_BIAS(tc_port)); val &= ~(DKL_PLL_BIAS_FRAC_EN_H | DKL_PLL_BIAS_FBDIV_FRAC_MASK); val |= hw_state->mg_pll_bias; - intel_dkl_phy_write(dev_priv, DKL_PLL_BIAS(tc_port), 2, val); + intel_dkl_phy_write(dev_priv, DKL_PLL_BIAS(tc_port), val); - val = intel_dkl_phy_read(dev_priv, DKL_PLL_TDC_COLDST_BIAS(tc_port), 2); + val = intel_dkl_phy_read(dev_priv, DKL_PLL_TDC_COLDST_BIAS(tc_port)); val &= ~(DKL_PLL_TDC_SSC_STEP_SIZE_MASK | DKL_PLL_TDC_FEED_FWD_GAIN_MASK); val |= hw_state->mg_pll_tdc_coldst_bias; - intel_dkl_phy_write(dev_priv, DKL_PLL_TDC_COLDST_BIAS(tc_port), 2, val); + intel_dkl_phy_write(dev_priv, DKL_PLL_TDC_COLDST_BIAS(tc_port), val); - intel_dkl_phy_posting_read(dev_priv, DKL_PLL_TDC_COLDST_BIAS(tc_port), 2); + intel_dkl_phy_posting_read(dev_priv, DKL_PLL_TDC_COLDST_BIAS(tc_port)); } static void icl_pll_power_enable(struct drm_i915_private *dev_priv, -- 2.37.1 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/tgl+: Fix race conditions during DKL PHY accesses (rev5) 2022-10-25 10:26 [Intel-gfx] [PATCH v3 0/4] drm/i915/tgl+: Fix race conditions during DKL PHY accesses Imre Deak ` (3 preceding siblings ...) 2022-10-25 10:26 ` [Intel-gfx] [PATCH v3 4/4] drm/i915/tgl+: Sanitize DKL PHY register definitions Imre Deak @ 2022-10-25 13:06 ` Patchwork 2022-10-25 13:06 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork ` (5 subsequent siblings) 10 siblings, 0 replies; 16+ messages in thread From: Patchwork @ 2022-10-25 13:06 UTC (permalink / raw) To: Imre Deak; +Cc: intel-gfx == Series Details == Series: drm/i915/tgl+: Fix race conditions during DKL PHY accesses (rev5) URL : https://patchwork.freedesktop.org/series/109963/ State : warning == Summary == Error: dim checkpatch failed 15062ed1404b drm/i915/tgl+: Add locking around DKL PHY register accesses Traceback (most recent call last): File "scripts/spdxcheck.py", line 6, in <module> from ply import lex, yacc ModuleNotFoundError: No module named 'ply' Traceback (most recent call last): File "scripts/spdxcheck.py", line 6, in <module> from ply import lex, yacc ModuleNotFoundError: No module named 'ply' -:218: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #218: new file mode 100644 total: 0 errors, 1 warnings, 0 checks, 442 lines checked d90f6b228a01 drm/i915: Rename intel_tc_phy_regs.h to intel_mg_phy_regs.h -:51: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #51: rename from drivers/gpu/drm/i915/display/intel_tc_phy_regs.h total: 0 errors, 1 warnings, 0 checks, 48 lines checked 4570d7dd4e54 drm/i915/tgl+: Move DKL PHY register definitions to intel_dkl_phy_regs.h Traceback (most recent call last): File "scripts/spdxcheck.py", line 6, in <module> from ply import lex, yacc ModuleNotFoundError: No module named 'ply' -:57: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #57: new file mode 100644 -:94: WARNING:LONG_LINE: line length of 108 exceeds 100 columns #94: FILE: drivers/gpu/drm/i915/display/intel_dkl_phy_regs.h:33: +#define DKL_PLL_DIV0_AFC_STARTUP(val) REG_FIELD_PREP(DKL_PLL_DIV0_AFC_STARTUP_MASK, (val)) -:199: WARNING:LONG_LINE: line length of 120 exceeds 100 columns #199: FILE: drivers/gpu/drm/i915/display/intel_dkl_phy_regs.h:138: +#define DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(val) REG_FIELD_PREP(DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK, (val)) -:201: WARNING:LONG_LINE: line length of 120 exceeds 100 columns #201: FILE: drivers/gpu/drm/i915/display/intel_dkl_phy_regs.h:140: +#define DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(val) REG_FIELD_PREP(DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK, (val)) total: 0 errors, 4 warnings, 0 checks, 413 lines checked 0b7eb0f5a4e6 drm/i915/tgl+: Sanitize DKL PHY register definitions -:294: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'phy_offset' - possible side-effects? #294: FILE: drivers/gpu/drm/i915/display/intel_dkl_phy_regs.h:39: +#define _DKL_REG(tc_port, phy_offset) \ + ((const struct intel_dkl_phy_reg) { \ + .reg = _DKL_REG_PHY_BASE(tc_port) + \ + _DKL_REG_BANK_OFFSET(phy_offset), \ + .bank_idx = _DKL_REG_BANK_IDX(phy_offset), \ + }) -:301: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'ln0_offs' - possible side-effects? #301: FILE: drivers/gpu/drm/i915/display/intel_dkl_phy_regs.h:46: +#define _DKL_REG_LN(tc_port, ln_idx, ln0_offs, ln1_offs) \ + _DKL_REG(tc_port, (ln0_offs) + (ln_idx) * ((ln1_offs) - (ln0_offs))) total: 0 errors, 0 warnings, 2 checks, 584 lines checked ^ permalink raw reply [flat|nested] 16+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/tgl+: Fix race conditions during DKL PHY accesses (rev5) 2022-10-25 10:26 [Intel-gfx] [PATCH v3 0/4] drm/i915/tgl+: Fix race conditions during DKL PHY accesses Imre Deak ` (4 preceding siblings ...) 2022-10-25 13:06 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/tgl+: Fix race conditions during DKL PHY accesses (rev5) Patchwork @ 2022-10-25 13:06 ` Patchwork 2022-10-25 13:30 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork ` (4 subsequent siblings) 10 siblings, 0 replies; 16+ messages in thread From: Patchwork @ 2022-10-25 13:06 UTC (permalink / raw) To: Imre Deak; +Cc: intel-gfx == Series Details == Series: drm/i915/tgl+: Fix race conditions during DKL PHY accesses (rev5) URL : https://patchwork.freedesktop.org/series/109963/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. ^ permalink raw reply [flat|nested] 16+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/tgl+: Fix race conditions during DKL PHY accesses (rev5) 2022-10-25 10:26 [Intel-gfx] [PATCH v3 0/4] drm/i915/tgl+: Fix race conditions during DKL PHY accesses Imre Deak ` (5 preceding siblings ...) 2022-10-25 13:06 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork @ 2022-10-25 13:30 ` Patchwork 2022-10-25 20:04 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork ` (3 subsequent siblings) 10 siblings, 0 replies; 16+ messages in thread From: Patchwork @ 2022-10-25 13:30 UTC (permalink / raw) To: Imre Deak; +Cc: intel-gfx [-- Attachment #1: Type: text/plain, Size: 8098 bytes --] == Series Details == Series: drm/i915/tgl+: Fix race conditions during DKL PHY accesses (rev5) URL : https://patchwork.freedesktop.org/series/109963/ State : success == Summary == CI Bug Log - changes from CI_DRM_12293 -> Patchwork_109963v5 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/index.html Participating hosts (42 -> 39) ------------------------------ Missing (3): fi-ctg-p8600 fi-icl-u2 fi-bdw-samus Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_109963v5: ### IGT changes ### #### Suppressed #### The following results come from untrusted machines, tests, or statuses. They do not affect the overall result. * igt@i915_selftest@live@hangcheck: - {bat-dg2-9}: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/bat-dg2-9/igt@i915_selftest@live@hangcheck.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/bat-dg2-9/igt@i915_selftest@live@hangcheck.html Known issues ------------ Here are the changes found in Patchwork_109963v5 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@gem_lmem_swapping@basic: - fi-apl-guc: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#4613]) +3 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/fi-apl-guc/igt@gem_lmem_swapping@basic.html * igt@gem_tiled_blits@basic: - fi-pnv-d510: [PASS][4] -> [SKIP][5] ([fdo#109271]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/fi-pnv-d510/igt@gem_tiled_blits@basic.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/fi-pnv-d510/igt@gem_tiled_blits@basic.html * igt@i915_selftest@live@gt_engines: - bat-dg1-5: [PASS][6] -> [INCOMPLETE][7] ([i915#4418]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/bat-dg1-5/igt@i915_selftest@live@gt_engines.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/bat-dg1-5/igt@i915_selftest@live@gt_engines.html * igt@kms_chamelium@common-hpd-after-suspend: - fi-hsw-4770: NOTRUN -> [SKIP][8] ([fdo#109271] / [fdo#111827]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/fi-hsw-4770/igt@kms_chamelium@common-hpd-after-suspend.html - bat-adlp-4: NOTRUN -> [SKIP][9] ([fdo#111827]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/bat-adlp-4/igt@kms_chamelium@common-hpd-after-suspend.html * igt@kms_chamelium@hdmi-crc-fast: - fi-apl-guc: NOTRUN -> [SKIP][10] ([fdo#109271] / [fdo#111827]) +8 similar issues [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/fi-apl-guc/igt@kms_chamelium@hdmi-crc-fast.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions-varying-size: - fi-bsw-kefka: [PASS][11] -> [FAIL][12] ([i915#6298]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions-varying-size.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions-varying-size.html * igt@kms_pipe_crc_basic@suspend-read-crc: - bat-adlp-4: NOTRUN -> [SKIP][13] ([i915#3546]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/bat-adlp-4/igt@kms_pipe_crc_basic@suspend-read-crc.html * igt@kms_psr@sprite_plane_onoff: - fi-apl-guc: NOTRUN -> [SKIP][14] ([fdo#109271]) +11 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/fi-apl-guc/igt@kms_psr@sprite_plane_onoff.html * igt@runner@aborted: - bat-dg1-5: NOTRUN -> [FAIL][15] ([i915#4312]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/bat-dg1-5/igt@runner@aborted.html #### Possible fixes #### * igt@gem_exec_suspend@basic-s3@smem: - {bat-rplp-1}: [DMESG-WARN][16] ([i915#2867]) -> [PASS][17] [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/bat-rplp-1/igt@gem_exec_suspend@basic-s3@smem.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/bat-rplp-1/igt@gem_exec_suspend@basic-s3@smem.html * igt@gem_linear_blits@basic: - fi-pnv-d510: [SKIP][18] ([fdo#109271]) -> [PASS][19] [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/fi-pnv-d510/igt@gem_linear_blits@basic.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/fi-pnv-d510/igt@gem_linear_blits@basic.html * igt@gem_render_tiled_blits@basic: - fi-apl-guc: [INCOMPLETE][20] ([i915#7056]) -> [PASS][21] [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/fi-apl-guc/igt@gem_render_tiled_blits@basic.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/fi-apl-guc/igt@gem_render_tiled_blits@basic.html * igt@i915_selftest@live@guc: - {bat-rpls-2}: [DMESG-WARN][22] ([i915#6471]) -> [PASS][23] [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/bat-rpls-2/igt@i915_selftest@live@guc.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/bat-rpls-2/igt@i915_selftest@live@guc.html * igt@i915_selftest@live@hangcheck: - fi-hsw-4770: [INCOMPLETE][24] ([i915#4785]) -> [PASS][25] [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/fi-hsw-4770/igt@i915_selftest@live@hangcheck.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/fi-hsw-4770/igt@i915_selftest@live@hangcheck.html * igt@i915_selftest@live@migrate: - bat-adlp-4: [INCOMPLETE][26] ([i915#7308]) -> [PASS][27] [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/bat-adlp-4/igt@i915_selftest@live@migrate.html [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/bat-adlp-4/igt@i915_selftest@live@migrate.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867 [i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546 [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312 [i915#4418]: https://gitlab.freedesktop.org/drm/intel/issues/4418 [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613 [i915#4785]: https://gitlab.freedesktop.org/drm/intel/issues/4785 [i915#6298]: https://gitlab.freedesktop.org/drm/intel/issues/6298 [i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367 [i915#6471]: https://gitlab.freedesktop.org/drm/intel/issues/6471 [i915#6818]: https://gitlab.freedesktop.org/drm/intel/issues/6818 [i915#6997]: https://gitlab.freedesktop.org/drm/intel/issues/6997 [i915#7056]: https://gitlab.freedesktop.org/drm/intel/issues/7056 [i915#7308]: https://gitlab.freedesktop.org/drm/intel/issues/7308 Build changes ------------- * Linux: CI_DRM_12293 -> Patchwork_109963v5 CI-20190529: 20190529 CI_DRM_12293: 508d090a36a87847ece5f75d4d0c12e96ca819a3 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_7026: ce0f97e7e0aa54c40049a8365b3d61773c92e588 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_109963v5: 508d090a36a87847ece5f75d4d0c12e96ca819a3 @ git://anongit.freedesktop.org/gfx-ci/linux ### Linux commits 1ad7ed888ab9 drm/i915/tgl+: Sanitize DKL PHY register definitions fcf84951b1cd drm/i915/tgl+: Move DKL PHY register definitions to intel_dkl_phy_regs.h b248a9a88514 drm/i915: Rename intel_tc_phy_regs.h to intel_mg_phy_regs.h d6e013eb483d drm/i915/tgl+: Add locking around DKL PHY register accesses == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/index.html [-- Attachment #2: Type: text/html, Size: 9407 bytes --] ^ permalink raw reply [flat|nested] 16+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/tgl+: Fix race conditions during DKL PHY accesses (rev5) 2022-10-25 10:26 [Intel-gfx] [PATCH v3 0/4] drm/i915/tgl+: Fix race conditions during DKL PHY accesses Imre Deak ` (6 preceding siblings ...) 2022-10-25 13:30 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork @ 2022-10-25 20:04 ` Patchwork 2022-10-26 13:00 ` Imre Deak 2022-10-26 17:12 ` Patchwork ` (2 subsequent siblings) 10 siblings, 1 reply; 16+ messages in thread From: Patchwork @ 2022-10-25 20:04 UTC (permalink / raw) To: Imre Deak; +Cc: intel-gfx [-- Attachment #1: Type: text/plain, Size: 28278 bytes --] == Series Details == Series: drm/i915/tgl+: Fix race conditions during DKL PHY accesses (rev5) URL : https://patchwork.freedesktop.org/series/109963/ State : failure == Summary == CI Bug Log - changes from CI_DRM_12293_full -> Patchwork_109963v5_full ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_109963v5_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_109963v5_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (9 -> 11) ------------------------------ Additional (2): shard-rkl shard-dg1 Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_109963v5_full: ### IGT changes ### #### Possible regressions #### * igt@kms_cursor_crc@cursor-suspend@pipe-b-edp-1: - shard-skl: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-skl7/igt@kms_cursor_crc@cursor-suspend@pipe-b-edp-1.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-skl9/igt@kms_cursor_crc@cursor-suspend@pipe-b-edp-1.html #### Suppressed #### The following results come from untrusted machines, tests, or statuses. They do not affect the overall result. * igt@sysfs_preempt_timeout@idempotent@rcs0: - {shard-dg1}: NOTRUN -> [FAIL][3] +4 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-dg1-15/igt@sysfs_preempt_timeout@idempotent@rcs0.html Known issues ------------ Here are the changes found in Patchwork_109963v5_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt@gem_eio@in-flight-contexts-10ms: - shard-tglb: [PASS][4] -> [TIMEOUT][5] ([i915#3063]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-tglb5/igt@gem_eio@in-flight-contexts-10ms.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-tglb6/igt@gem_eio@in-flight-contexts-10ms.html * igt@gem_eio@in-flight-suspend: - shard-skl: [PASS][6] -> [INCOMPLETE][7] ([i915#7112]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-skl10/igt@gem_eio@in-flight-suspend.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-skl6/igt@gem_eio@in-flight-suspend.html * igt@gem_exec_balancer@parallel: - shard-iclb: [PASS][8] -> [SKIP][9] ([i915#4525]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-iclb1/igt@gem_exec_balancer@parallel.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-iclb5/igt@gem_exec_balancer@parallel.html * igt@gem_exec_fair@basic-pace-share@rcs0: - shard-glk: [PASS][10] -> [FAIL][11] ([i915#2842]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-glk5/igt@gem_exec_fair@basic-pace-share@rcs0.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-glk1/igt@gem_exec_fair@basic-pace-share@rcs0.html * igt@gem_exec_fair@basic-pace-solo@rcs0: - shard-apl: [PASS][12] -> [FAIL][13] ([i915#2842]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-apl3/igt@gem_exec_fair@basic-pace-solo@rcs0.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-apl6/igt@gem_exec_fair@basic-pace-solo@rcs0.html * igt@gem_lmem_swapping@parallel-random: - shard-skl: NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#4613]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-skl7/igt@gem_lmem_swapping@parallel-random.html * igt@i915_pm_dc@dc6-dpms: - shard-iclb: [PASS][15] -> [FAIL][16] ([i915#3989] / [i915#454]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-iclb5/igt@i915_pm_dc@dc6-dpms.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-iclb3/igt@i915_pm_dc@dc6-dpms.html * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-async-flip: - shard-skl: NOTRUN -> [SKIP][17] ([fdo#109271]) +43 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-skl7/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html * igt@kms_color_chamelium@ctm-limited-range: - shard-skl: NOTRUN -> [SKIP][18] ([fdo#109271] / [fdo#111827]) +2 similar issues [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-skl7/igt@kms_color_chamelium@ctm-limited-range.html * igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1: - shard-skl: [PASS][19] -> [FAIL][20] ([i915#79]) +1 similar issue [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-skl9/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-skl7/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html * igt@kms_flip_scaled_crc@flip-64bpp-linear-to-32bpp-linear-downscaling@pipe-a-default-mode: - shard-iclb: NOTRUN -> [SKIP][21] ([i915#3555]) +2 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-linear-to-32bpp-linear-downscaling@pipe-a-default-mode.html * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling@pipe-a-valid-mode: - shard-iclb: NOTRUN -> [SKIP][22] ([i915#2587] / [i915#2672]) +1 similar issue [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-iclb5/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling@pipe-a-valid-mode.html * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling@pipe-a-default-mode: - shard-iclb: NOTRUN -> [SKIP][23] ([i915#2672]) +6 similar issues [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-iclb3/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling@pipe-a-default-mode.html * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-valid-mode: - shard-iclb: NOTRUN -> [SKIP][24] ([i915#2672] / [i915#3555]) [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-iclb6/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-valid-mode.html * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-render: - shard-apl: NOTRUN -> [SKIP][25] ([fdo#109271]) +6 similar issues [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-apl6/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-render.html * igt@kms_psr2_sf@plane-move-sf-dmg-area: - shard-skl: NOTRUN -> [SKIP][26] ([fdo#109271] / [i915#658]) [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-skl7/igt@kms_psr2_sf@plane-move-sf-dmg-area.html * igt@kms_psr2_su@page_flip-nv12: - shard-iclb: NOTRUN -> [SKIP][27] ([fdo#109642] / [fdo#111068] / [i915#658]) [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-iclb6/igt@kms_psr2_su@page_flip-nv12.html * igt@kms_psr@psr2_primary_page_flip: - shard-iclb: [PASS][28] -> [SKIP][29] ([fdo#109441]) +1 similar issue [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-iclb2/igt@kms_psr@psr2_primary_page_flip.html [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-iclb5/igt@kms_psr@psr2_primary_page_flip.html * igt@perf@stress-open-close: - shard-glk: [PASS][30] -> [INCOMPLETE][31] ([i915#5213]) [30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-glk7/igt@perf@stress-open-close.html [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-glk3/igt@perf@stress-open-close.html * igt@perf_pmu@interrupts: - shard-skl: [PASS][32] -> [FAIL][33] ([i915#7318]) [32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-skl4/igt@perf_pmu@interrupts.html [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-skl9/igt@perf_pmu@interrupts.html * igt@sysfs_clients@recycle-many: - shard-skl: NOTRUN -> [SKIP][34] ([fdo#109271] / [i915#2994]) [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-skl7/igt@sysfs_clients@recycle-many.html * igt@sysfs_heartbeat_interval@precise@vecs0: - shard-apl: [PASS][35] -> [FAIL][36] ([i915#1755]) [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-apl8/igt@sysfs_heartbeat_interval@precise@vecs0.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-apl7/igt@sysfs_heartbeat_interval@precise@vecs0.html #### Possible fixes #### * igt@gem_exec_balancer@parallel-bb-first: - shard-iclb: [SKIP][37] ([i915#4525]) -> [PASS][38] +1 similar issue [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-iclb7/igt@gem_exec_balancer@parallel-bb-first.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-iclb2/igt@gem_exec_balancer@parallel-bb-first.html * igt@gem_exec_fair@basic-none@vecs0: - shard-glk: [FAIL][39] ([i915#2842]) -> [PASS][40] [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-glk1/igt@gem_exec_fair@basic-none@vecs0.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-glk5/igt@gem_exec_fair@basic-none@vecs0.html * igt@i915_pm_dc@dc5-psr: - shard-skl: [FAIL][41] -> [PASS][42] [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-skl9/igt@i915_pm_dc@dc5-psr.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-skl6/igt@i915_pm_dc@dc5-psr.html * igt@i915_selftest@live@gt_heartbeat: - shard-apl: [DMESG-FAIL][43] ([i915#5334]) -> [PASS][44] [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-apl7/igt@i915_selftest@live@gt_heartbeat.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-apl3/igt@i915_selftest@live@gt_heartbeat.html * igt@kms_async_flips@alternate-sync-async-flip@pipe-b-edp-1: - shard-skl: [FAIL][45] ([i915#2521]) -> [PASS][46] [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-skl10/igt@kms_async_flips@alternate-sync-async-flip@pipe-b-edp-1.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-skl4/igt@kms_async_flips@alternate-sync-async-flip@pipe-b-edp-1.html * igt@kms_fbcon_fbt@psr-suspend: - shard-skl: [FAIL][47] ([i915#4767]) -> [PASS][48] [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-skl4/igt@kms_fbcon_fbt@psr-suspend.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-skl10/igt@kms_fbcon_fbt@psr-suspend.html * igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1: - shard-skl: [FAIL][49] ([i915#79]) -> [PASS][50] [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-skl9/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-skl7/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html * igt@kms_flip@flip-vs-expired-vblank-interruptible@c-hdmi-a1: - shard-glk: [FAIL][51] ([i915#79]) -> [PASS][52] +1 similar issue [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-glk7/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-hdmi-a1.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-glk3/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-hdmi-a1.html * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-blt: - shard-iclb: [FAIL][53] ([i915#2546]) -> [PASS][54] +2 similar issues [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-iclb2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-blt.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-iclb5/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-blt.html * igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-render: - shard-iclb: [FAIL][55] -> [PASS][56] [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-iclb2/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-render.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-iclb5/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-render.html * igt@kms_hdr@bpc-switch-suspend@pipe-a-dp-1: - shard-apl: [DMESG-WARN][57] ([i915#180]) -> [PASS][58] [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-apl3/igt@kms_hdr@bpc-switch-suspend@pipe-a-dp-1.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-apl6/igt@kms_hdr@bpc-switch-suspend@pipe-a-dp-1.html * igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-c-edp-1: - shard-iclb: [SKIP][59] ([i915#5235]) -> [PASS][60] +2 similar issues [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-iclb2/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-c-edp-1.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-iclb6/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-c-edp-1.html * igt@kms_psr@psr2_cursor_plane_move: - shard-iclb: [SKIP][61] ([fdo#109441]) -> [PASS][62] [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-iclb7/igt@kms_psr@psr2_cursor_plane_move.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-iclb2/igt@kms_psr@psr2_cursor_plane_move.html #### Warnings #### * igt@gem_exec_balancer@parallel-ordering: - shard-iclb: [FAIL][63] ([i915#6117]) -> [SKIP][64] ([i915#4525]) [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-iclb2/igt@gem_exec_balancer@parallel-ordering.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-iclb3/igt@gem_exec_balancer@parallel-ordering.html * igt@i915_pm_dc@dc3co-vpb-simulation: - shard-iclb: [SKIP][65] ([i915#658]) -> [SKIP][66] ([i915#588]) [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-iclb7/igt@i915_pm_dc@dc3co-vpb-simulation.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-iclb2/igt@i915_pm_dc@dc3co-vpb-simulation.html * igt@i915_pm_rc6_residency@rc6-idle@rcs0: - shard-iclb: [FAIL][67] ([i915#2684]) -> [WARN][68] ([i915#2684]) [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-iclb8/igt@i915_pm_rc6_residency@rc6-idle@rcs0.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-iclb1/igt@i915_pm_rc6_residency@rc6-idle@rcs0.html * igt@kms_psr2_sf@cursor-plane-update-sf: - shard-iclb: [SKIP][69] ([fdo#111068] / [i915#658]) -> [SKIP][70] ([i915#2920]) [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-iclb7/igt@kms_psr2_sf@cursor-plane-update-sf.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-iclb2/igt@kms_psr2_sf@cursor-plane-update-sf.html * igt@kms_psr2_sf@overlay-plane-update-continuous-sf: - shard-iclb: [SKIP][71] ([i915#2920]) -> [SKIP][72] ([fdo#111068] / [i915#658]) +1 similar issue [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-iclb2/igt@kms_psr2_sf@overlay-plane-update-continuous-sf.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-iclb5/igt@kms_psr2_sf@overlay-plane-update-continuous-sf.html * igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb: - shard-iclb: [SKIP][73] ([i915#658]) -> [SKIP][74] ([i915#2920]) [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-iclb7/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-iclb2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274 [fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283 [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285 [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289 [fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295 [fdo#109302]: https://bugs.freedesktop.org/show_bug.cgi?id=109302 [fdo#109303]: https://bugs.freedesktop.org/show_bug.cgi?id=109303 [fdo#109307]: https://bugs.freedesktop.org/show_bug.cgi?id=109307 [fdo#109308]: https://bugs.freedesktop.org/show_bug.cgi?id=109308 [fdo#109312]: https://bugs.freedesktop.org/show_bug.cgi?id=109312 [fdo#109313]: https://bugs.freedesktop.org/show_bug.cgi?id=109313 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506 [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642 [fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189 [fdo#110542]: https://bugs.freedesktop.org/show_bug.cgi?id=110542 [fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723 [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068 [fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614 [fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615 [fdo#111656]: https://bugs.freedesktop.org/show_bug.cgi?id=111656 [fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [fdo#112054]: https://bugs.freedesktop.org/show_bug.cgi?id=112054 [fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283 [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072 [i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155 [i915#1257]: https://gitlab.freedesktop.org/drm/intel/issues/1257 [i915#132]: https://gitlab.freedesktop.org/drm/intel/issues/132 [i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397 [i915#1755]: https://gitlab.freedesktop.org/drm/intel/issues/1755 [i915#1769]: https://gitlab.freedesktop.org/drm/intel/issues/1769 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825 [i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839 [i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845 [i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849 [i915#1850]: https://gitlab.freedesktop.org/drm/intel/issues/1850 [i915#1902]: https://gitlab.freedesktop.org/drm/intel/issues/1902 [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190 [i915#2410]: https://gitlab.freedesktop.org/drm/intel/issues/2410 [i915#2433]: https://gitlab.freedesktop.org/drm/intel/issues/2433 [i915#2435]: https://gitlab.freedesktop.org/drm/intel/issues/2435 [i915#2436]: https://gitlab.freedesktop.org/drm/intel/issues/2436 [i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437 [i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521 [i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527 [i915#2546]: https://gitlab.freedesktop.org/drm/intel/issues/2546 [i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582 [i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587 [i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672 [i915#2684]: https://gitlab.freedesktop.org/drm/intel/issues/2684 [i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705 [i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280 [i915#284]: https://gitlab.freedesktop.org/drm/intel/issues/284 [i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842 [i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920 [i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994 [i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002 [i915#3012]: https://gitlab.freedesktop.org/drm/intel/issues/3012 [i915#3063]: https://gitlab.freedesktop.org/drm/intel/issues/3063 [i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281 [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282 [i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291 [i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297 [i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299 [i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301 [i915#3318]: https://gitlab.freedesktop.org/drm/intel/issues/3318 [i915#3323]: https://gitlab.freedesktop.org/drm/intel/issues/3323 [i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359 [i915#3361]: https://gitlab.freedesktop.org/drm/intel/issues/3361 [i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458 [i915#3469]: https://gitlab.freedesktop.org/drm/intel/issues/3469 [i915#3528]: https://gitlab.freedesktop.org/drm/intel/issues/3528 [i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539 [i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546 [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555 [i915#3558]: https://gitlab.freedesktop.org/drm/intel/issues/3558 [i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637 [i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638 [i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689 [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708 [i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734 [i915#3742]: https://gitlab.freedesktop.org/drm/intel/issues/3742 [i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840 [i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886 [i915#3936]: https://gitlab.freedesktop.org/drm/intel/issues/3936 [i915#3952]: https://gitlab.freedesktop.org/drm/intel/issues/3952 [i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955 [i915#3989]: https://gitlab.freedesktop.org/drm/intel/issues/3989 [i915#4036]: https://gitlab.freedesktop.org/drm/intel/issues/4036 [i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070 [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077 [i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078 [i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079 [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083 [i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098 [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103 [i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212 [i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213 [i915#426]: https://gitlab.freedesktop.org/drm/intel/issues/426 [i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270 [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312 [i915#433]: https://gitlab.freedesktop.org/drm/intel/issues/433 [i915#4349]: https://gitlab.freedesktop.org/drm/intel/issues/4349 [i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525 [i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538 [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454 [i915#4565]: https://gitlab.freedesktop.org/drm/intel/issues/4565 [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613 [i915#4767]: https://gitlab.freedesktop.org/drm/intel/issues/4767 [i915#4771]: https://gitlab.freedesktop.org/drm/intel/issues/4771 [i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812 [i915#4818]: https://gitlab.freedesktop.org/drm/intel/issues/4818 [i915#4833]: https://gitlab.freedesktop.org/drm/intel/issues/4833 [i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852 [i915#4855]: https://gitlab.freedesktop.org/drm/intel/issues/4855 [i915#4859]: https://gitlab.freedesktop.org/drm/intel/issues/4859 [i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860 [i915#4874]: https://gitlab.freedesktop.org/drm/intel/issues/4874 [i915#4877]: https://gitlab.freedesktop.org/drm/intel/issues/4877 [i915#4880]: https://gitlab.freedesktop.org/drm/intel/issues/4880 [i915#4881]: https://gitlab.freedesktop.org/drm/intel/issues/4881 [i915#4884]: https://gitlab.freedesktop.org/drm/intel/issues/4884 [i915#4885]: https://gitlab.freedesktop.org/drm/intel/issues/4885 [i915#4958]: https://gitlab.freedesktop.org/drm/intel/issues/4958 [i915#4991]: https://gitlab.freedesktop.org/drm/intel/issues/4991 [i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176 [i915#5213]: https://gitlab.freedesktop.org/drm/intel/issues/5213 [i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235 [i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286 [i915#5288]: https://gitlab.freedesktop.org/drm/intel/issues/5288 [i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289 [i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325 [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533 [i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334 [i915#5439]: https://gitlab.freedesktop.org/drm/intel/issues/5439 [i915#5563]: https://gitlab.freedesktop.org/drm/intel/issues/5563 [i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784 [i915#588]: https://gitlab.freedesktop.org/drm/intel/issues/588 [i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095 [i915#6117]: https://gitlab.freedesktop.org/drm/intel/issues/6117 [i915#6248]: https://gitlab.freedesktop.org/drm/intel/issues/6248 [i915#6251]: https://gitlab.freedesktop.org/drm/intel/issues/6251 [i915#6252]: https://gitlab.freedesktop.org/drm/intel/issues/6252 [i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268 [i915#6301]: https://gitlab.freedesktop.org/drm/intel/issues/6301 [i915#6335]: https://gitlab.freedesktop.org/drm/intel/issues/6335 [i915#6412]: https://gitlab.freedesktop.org/drm/intel/issues/6412 [i915#6433]: https://gitlab.freedesktop.org/drm/intel/issues/6433 [i915#6463]: https://gitlab.freedesktop.org/drm/intel/issues/6463 [i915#6497]: https://gitlab.freedesktop.org/drm/intel/issues/6497 [i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524 [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658 [i915#6590]: https://gitlab.freedesktop.org/drm/intel/issues/6590 [i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621 [i915#6946]: https://gitlab.freedesktop.org/drm/intel/issues/6946 [i915#7112]: https://gitlab.freedesktop.org/drm/intel/issues/7112 [i915#7116]: https://gitlab.freedesktop.org/drm/intel/issues/7116 [i915#7142]: https://gitlab.freedesktop.org/drm/intel/issues/7142 [i915#7178]: https://gitlab.freedesktop.org/drm/intel/issues/7178 [i915#7247]: https://gitlab.freedesktop.org/drm/intel/issues/7247 [i915#7318]: https://gitlab.freedesktop.org/drm/intel/issues/7318 [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 Build changes ------------- * Linux: CI_DRM_12293 -> Patchwork_109963v5 CI-20190529: 20190529 CI_DRM_12293: 508d090a36a87847ece5f75d4d0c12e96ca819a3 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_7026: ce0f97e7e0aa54c40049a8365b3d61773c92e588 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_109963v5: 508d090a36a87847ece5f75d4d0c12e96ca819a3 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/index.html [-- Attachment #2: Type: text/html, Size: 22530 bytes --] ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/tgl+: Fix race conditions during DKL PHY accesses (rev5) 2022-10-25 20:04 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork @ 2022-10-26 13:00 ` Imre Deak 0 siblings, 0 replies; 16+ messages in thread From: Imre Deak @ 2022-10-26 13:00 UTC (permalink / raw) To: intel-gfx, Lakshminarayana Vudum, Jani Nikula, Ville Syrjälä On Tue, Oct 25, 2022 at 08:04:12PM +0000, Patchwork wrote: > == Series Details == > > Series: drm/i915/tgl+: Fix race conditions during DKL PHY accesses (rev5) > URL : https://patchwork.freedesktop.org/series/109963/ > State : failure > > == Summary == > > CI Bug Log - changes from CI_DRM_12293_full -> Patchwork_109963v5_full > ==================================================== > > Summary > ------- > > **FAILURE** > > Serious unknown changes coming with Patchwork_109963v5_full absolutely need to be > verified manually. > > If you think the reported changes have nothing to do with the changes > introduced in Patchwork_109963v5_full, please notify your bug team to allow them > to document this new failure mode, which will reduce false positives in CI. > > > > Participating hosts (9 -> 11) > ------------------------------ > > Additional (2): shard-rkl shard-dg1 > > Possible new issues > ------------------- > > Here are the unknown changes that may have been introduced in Patchwork_109963v5_full: > > ### IGT changes ### > > #### Possible regressions #### > > * igt@kms_cursor_crc@cursor-suspend@pipe-b-edp-1: > - shard-skl: [PASS][1] -> [INCOMPLETE][2] > [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-skl7/igt@kms_cursor_crc@cursor-suspend@pipe-b-edp-1.html > [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-skl9/igt@kms_cursor_crc@cursor-suspend@pipe-b-edp-1.html SKL doesn't have MG/DKL PHYs, so the above issue is unrelated. Thanks for the review/ack, patchset is pushed. > #### Suppressed #### > > The following results come from untrusted machines, tests, or statuses. > They do not affect the overall result. > > * igt@sysfs_preempt_timeout@idempotent@rcs0: > - {shard-dg1}: NOTRUN -> [FAIL][3] +4 similar issues > [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-dg1-15/igt@sysfs_preempt_timeout@idempotent@rcs0.html > > > Known issues > ------------ > > Here are the changes found in Patchwork_109963v5_full that come from known issues: > > ### IGT changes ### > > #### Issues hit #### > > * igt@gem_eio@in-flight-contexts-10ms: > - shard-tglb: [PASS][4] -> [TIMEOUT][5] ([i915#3063]) > [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-tglb5/igt@gem_eio@in-flight-contexts-10ms.html > [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-tglb6/igt@gem_eio@in-flight-contexts-10ms.html > > * igt@gem_eio@in-flight-suspend: > - shard-skl: [PASS][6] -> [INCOMPLETE][7] ([i915#7112]) > [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-skl10/igt@gem_eio@in-flight-suspend.html > [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-skl6/igt@gem_eio@in-flight-suspend.html > > * igt@gem_exec_balancer@parallel: > - shard-iclb: [PASS][8] -> [SKIP][9] ([i915#4525]) > [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-iclb1/igt@gem_exec_balancer@parallel.html > [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-iclb5/igt@gem_exec_balancer@parallel.html > > * igt@gem_exec_fair@basic-pace-share@rcs0: > - shard-glk: [PASS][10] -> [FAIL][11] ([i915#2842]) > [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-glk5/igt@gem_exec_fair@basic-pace-share@rcs0.html > [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-glk1/igt@gem_exec_fair@basic-pace-share@rcs0.html > > * igt@gem_exec_fair@basic-pace-solo@rcs0: > - shard-apl: [PASS][12] -> [FAIL][13] ([i915#2842]) > [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-apl3/igt@gem_exec_fair@basic-pace-solo@rcs0.html > [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-apl6/igt@gem_exec_fair@basic-pace-solo@rcs0.html > > * igt@gem_lmem_swapping@parallel-random: > - shard-skl: NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#4613]) > [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-skl7/igt@gem_lmem_swapping@parallel-random.html > > * igt@i915_pm_dc@dc6-dpms: > - shard-iclb: [PASS][15] -> [FAIL][16] ([i915#3989] / [i915#454]) > [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-iclb5/igt@i915_pm_dc@dc6-dpms.html > [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-iclb3/igt@i915_pm_dc@dc6-dpms.html > > * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-async-flip: > - shard-skl: NOTRUN -> [SKIP][17] ([fdo#109271]) +43 similar issues > [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-skl7/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html > > * igt@kms_color_chamelium@ctm-limited-range: > - shard-skl: NOTRUN -> [SKIP][18] ([fdo#109271] / [fdo#111827]) +2 similar issues > [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-skl7/igt@kms_color_chamelium@ctm-limited-range.html > > * igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1: > - shard-skl: [PASS][19] -> [FAIL][20] ([i915#79]) +1 similar issue > [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-skl9/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html > [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-skl7/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html > > * igt@kms_flip_scaled_crc@flip-64bpp-linear-to-32bpp-linear-downscaling@pipe-a-default-mode: > - shard-iclb: NOTRUN -> [SKIP][21] ([i915#3555]) +2 similar issues > [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-linear-to-32bpp-linear-downscaling@pipe-a-default-mode.html > > * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling@pipe-a-valid-mode: > - shard-iclb: NOTRUN -> [SKIP][22] ([i915#2587] / [i915#2672]) +1 similar issue > [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-iclb5/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling@pipe-a-valid-mode.html > > * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling@pipe-a-default-mode: > - shard-iclb: NOTRUN -> [SKIP][23] ([i915#2672]) +6 similar issues > [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-iclb3/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling@pipe-a-default-mode.html > > * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-valid-mode: > - shard-iclb: NOTRUN -> [SKIP][24] ([i915#2672] / [i915#3555]) > [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-iclb6/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-valid-mode.html > > * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-render: > - shard-apl: NOTRUN -> [SKIP][25] ([fdo#109271]) +6 similar issues > [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-apl6/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-render.html > > * igt@kms_psr2_sf@plane-move-sf-dmg-area: > - shard-skl: NOTRUN -> [SKIP][26] ([fdo#109271] / [i915#658]) > [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-skl7/igt@kms_psr2_sf@plane-move-sf-dmg-area.html > > * igt@kms_psr2_su@page_flip-nv12: > - shard-iclb: NOTRUN -> [SKIP][27] ([fdo#109642] / [fdo#111068] / [i915#658]) > [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-iclb6/igt@kms_psr2_su@page_flip-nv12.html > > * igt@kms_psr@psr2_primary_page_flip: > - shard-iclb: [PASS][28] -> [SKIP][29] ([fdo#109441]) +1 similar issue > [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-iclb2/igt@kms_psr@psr2_primary_page_flip.html > [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-iclb5/igt@kms_psr@psr2_primary_page_flip.html > > * igt@perf@stress-open-close: > - shard-glk: [PASS][30] -> [INCOMPLETE][31] ([i915#5213]) > [30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-glk7/igt@perf@stress-open-close.html > [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-glk3/igt@perf@stress-open-close.html > > * igt@perf_pmu@interrupts: > - shard-skl: [PASS][32] -> [FAIL][33] ([i915#7318]) > [32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-skl4/igt@perf_pmu@interrupts.html > [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-skl9/igt@perf_pmu@interrupts.html > > * igt@sysfs_clients@recycle-many: > - shard-skl: NOTRUN -> [SKIP][34] ([fdo#109271] / [i915#2994]) > [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-skl7/igt@sysfs_clients@recycle-many.html > > * igt@sysfs_heartbeat_interval@precise@vecs0: > - shard-apl: [PASS][35] -> [FAIL][36] ([i915#1755]) > [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-apl8/igt@sysfs_heartbeat_interval@precise@vecs0.html > [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-apl7/igt@sysfs_heartbeat_interval@precise@vecs0.html > > > #### Possible fixes #### > > * igt@gem_exec_balancer@parallel-bb-first: > - shard-iclb: [SKIP][37] ([i915#4525]) -> [PASS][38] +1 similar issue > [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-iclb7/igt@gem_exec_balancer@parallel-bb-first.html > [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-iclb2/igt@gem_exec_balancer@parallel-bb-first.html > > * igt@gem_exec_fair@basic-none@vecs0: > - shard-glk: [FAIL][39] ([i915#2842]) -> [PASS][40] > [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-glk1/igt@gem_exec_fair@basic-none@vecs0.html > [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-glk5/igt@gem_exec_fair@basic-none@vecs0.html > > * igt@i915_pm_dc@dc5-psr: > - shard-skl: [FAIL][41] -> [PASS][42] > [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-skl9/igt@i915_pm_dc@dc5-psr.html > [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-skl6/igt@i915_pm_dc@dc5-psr.html > > * igt@i915_selftest@live@gt_heartbeat: > - shard-apl: [DMESG-FAIL][43] ([i915#5334]) -> [PASS][44] > [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-apl7/igt@i915_selftest@live@gt_heartbeat.html > [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-apl3/igt@i915_selftest@live@gt_heartbeat.html > > * igt@kms_async_flips@alternate-sync-async-flip@pipe-b-edp-1: > - shard-skl: [FAIL][45] ([i915#2521]) -> [PASS][46] > [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-skl10/igt@kms_async_flips@alternate-sync-async-flip@pipe-b-edp-1.html > [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-skl4/igt@kms_async_flips@alternate-sync-async-flip@pipe-b-edp-1.html > > * igt@kms_fbcon_fbt@psr-suspend: > - shard-skl: [FAIL][47] ([i915#4767]) -> [PASS][48] > [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-skl4/igt@kms_fbcon_fbt@psr-suspend.html > [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-skl10/igt@kms_fbcon_fbt@psr-suspend.html > > * igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1: > - shard-skl: [FAIL][49] ([i915#79]) -> [PASS][50] > [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-skl9/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html > [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-skl7/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html > > * igt@kms_flip@flip-vs-expired-vblank-interruptible@c-hdmi-a1: > - shard-glk: [FAIL][51] ([i915#79]) -> [PASS][52] +1 similar issue > [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-glk7/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-hdmi-a1.html > [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-glk3/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-hdmi-a1.html > > * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-blt: > - shard-iclb: [FAIL][53] ([i915#2546]) -> [PASS][54] +2 similar issues > [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-iclb2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-blt.html > [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-iclb5/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-blt.html > > * igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-render: > - shard-iclb: [FAIL][55] -> [PASS][56] > [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-iclb2/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-render.html > [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-iclb5/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-render.html > > * igt@kms_hdr@bpc-switch-suspend@pipe-a-dp-1: > - shard-apl: [DMESG-WARN][57] ([i915#180]) -> [PASS][58] > [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-apl3/igt@kms_hdr@bpc-switch-suspend@pipe-a-dp-1.html > [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-apl6/igt@kms_hdr@bpc-switch-suspend@pipe-a-dp-1.html > > * igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-c-edp-1: > - shard-iclb: [SKIP][59] ([i915#5235]) -> [PASS][60] +2 similar issues > [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-iclb2/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-c-edp-1.html > [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-iclb6/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-c-edp-1.html > > * igt@kms_psr@psr2_cursor_plane_move: > - shard-iclb: [SKIP][61] ([fdo#109441]) -> [PASS][62] > [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-iclb7/igt@kms_psr@psr2_cursor_plane_move.html > [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-iclb2/igt@kms_psr@psr2_cursor_plane_move.html > > > #### Warnings #### > > * igt@gem_exec_balancer@parallel-ordering: > - shard-iclb: [FAIL][63] ([i915#6117]) -> [SKIP][64] ([i915#4525]) > [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-iclb2/igt@gem_exec_balancer@parallel-ordering.html > [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-iclb3/igt@gem_exec_balancer@parallel-ordering.html > > * igt@i915_pm_dc@dc3co-vpb-simulation: > - shard-iclb: [SKIP][65] ([i915#658]) -> [SKIP][66] ([i915#588]) > [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-iclb7/igt@i915_pm_dc@dc3co-vpb-simulation.html > [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-iclb2/igt@i915_pm_dc@dc3co-vpb-simulation.html > > * igt@i915_pm_rc6_residency@rc6-idle@rcs0: > - shard-iclb: [FAIL][67] ([i915#2684]) -> [WARN][68] ([i915#2684]) > [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-iclb8/igt@i915_pm_rc6_residency@rc6-idle@rcs0.html > [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-iclb1/igt@i915_pm_rc6_residency@rc6-idle@rcs0.html > > * igt@kms_psr2_sf@cursor-plane-update-sf: > - shard-iclb: [SKIP][69] ([fdo#111068] / [i915#658]) -> [SKIP][70] ([i915#2920]) > [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-iclb7/igt@kms_psr2_sf@cursor-plane-update-sf.html > [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-iclb2/igt@kms_psr2_sf@cursor-plane-update-sf.html > > * igt@kms_psr2_sf@overlay-plane-update-continuous-sf: > - shard-iclb: [SKIP][71] ([i915#2920]) -> [SKIP][72] ([fdo#111068] / [i915#658]) +1 similar issue > [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-iclb2/igt@kms_psr2_sf@overlay-plane-update-continuous-sf.html > [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-iclb5/igt@kms_psr2_sf@overlay-plane-update-continuous-sf.html > > * igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb: > - shard-iclb: [SKIP][73] ([i915#658]) -> [SKIP][74] ([i915#2920]) > [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-iclb7/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb.html > [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-iclb2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb.html > > > {name}: This element is suppressed. This means it is ignored when computing > the status of the difference (SUCCESS, WARNING, or FAILURE). > > [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 > [fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274 > [fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283 > [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285 > [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289 > [fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295 > [fdo#109302]: https://bugs.freedesktop.org/show_bug.cgi?id=109302 > [fdo#109303]: https://bugs.freedesktop.org/show_bug.cgi?id=109303 > [fdo#109307]: https://bugs.freedesktop.org/show_bug.cgi?id=109307 > [fdo#109308]: https://bugs.freedesktop.org/show_bug.cgi?id=109308 > [fdo#109312]: https://bugs.freedesktop.org/show_bug.cgi?id=109312 > [fdo#109313]: https://bugs.freedesktop.org/show_bug.cgi?id=109313 > [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 > [fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506 > [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642 > [fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189 > [fdo#110542]: https://bugs.freedesktop.org/show_bug.cgi?id=110542 > [fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723 > [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068 > [fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614 > [fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615 > [fdo#111656]: https://bugs.freedesktop.org/show_bug.cgi?id=111656 > [fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825 > [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 > [fdo#112054]: https://bugs.freedesktop.org/show_bug.cgi?id=112054 > [fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283 > [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072 > [i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155 > [i915#1257]: https://gitlab.freedesktop.org/drm/intel/issues/1257 > [i915#132]: https://gitlab.freedesktop.org/drm/intel/issues/132 > [i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397 > [i915#1755]: https://gitlab.freedesktop.org/drm/intel/issues/1755 > [i915#1769]: https://gitlab.freedesktop.org/drm/intel/issues/1769 > [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 > [i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825 > [i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839 > [i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845 > [i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849 > [i915#1850]: https://gitlab.freedesktop.org/drm/intel/issues/1850 > [i915#1902]: https://gitlab.freedesktop.org/drm/intel/issues/1902 > [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190 > [i915#2410]: https://gitlab.freedesktop.org/drm/intel/issues/2410 > [i915#2433]: https://gitlab.freedesktop.org/drm/intel/issues/2433 > [i915#2435]: https://gitlab.freedesktop.org/drm/intel/issues/2435 > [i915#2436]: https://gitlab.freedesktop.org/drm/intel/issues/2436 > [i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437 > [i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521 > [i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527 > [i915#2546]: https://gitlab.freedesktop.org/drm/intel/issues/2546 > [i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582 > [i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587 > [i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672 > [i915#2684]: https://gitlab.freedesktop.org/drm/intel/issues/2684 > [i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705 > [i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280 > [i915#284]: https://gitlab.freedesktop.org/drm/intel/issues/284 > [i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842 > [i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920 > [i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994 > [i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002 > [i915#3012]: https://gitlab.freedesktop.org/drm/intel/issues/3012 > [i915#3063]: https://gitlab.freedesktop.org/drm/intel/issues/3063 > [i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281 > [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282 > [i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291 > [i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297 > [i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299 > [i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301 > [i915#3318]: https://gitlab.freedesktop.org/drm/intel/issues/3318 > [i915#3323]: https://gitlab.freedesktop.org/drm/intel/issues/3323 > [i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359 > [i915#3361]: https://gitlab.freedesktop.org/drm/intel/issues/3361 > [i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458 > [i915#3469]: https://gitlab.freedesktop.org/drm/intel/issues/3469 > [i915#3528]: https://gitlab.freedesktop.org/drm/intel/issues/3528 > [i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539 > [i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546 > [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555 > [i915#3558]: https://gitlab.freedesktop.org/drm/intel/issues/3558 > [i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637 > [i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638 > [i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689 > [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708 > [i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734 > [i915#3742]: https://gitlab.freedesktop.org/drm/intel/issues/3742 > [i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840 > [i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886 > [i915#3936]: https://gitlab.freedesktop.org/drm/intel/issues/3936 > [i915#3952]: https://gitlab.freedesktop.org/drm/intel/issues/3952 > [i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955 > [i915#3989]: https://gitlab.freedesktop.org/drm/intel/issues/3989 > [i915#4036]: https://gitlab.freedesktop.org/drm/intel/issues/4036 > [i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070 > [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077 > [i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078 > [i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079 > [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083 > [i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098 > [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103 > [i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212 > [i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213 > [i915#426]: https://gitlab.freedesktop.org/drm/intel/issues/426 > [i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270 > [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312 > [i915#433]: https://gitlab.freedesktop.org/drm/intel/issues/433 > [i915#4349]: https://gitlab.freedesktop.org/drm/intel/issues/4349 > [i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525 > [i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538 > [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454 > [i915#4565]: https://gitlab.freedesktop.org/drm/intel/issues/4565 > [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613 > [i915#4767]: https://gitlab.freedesktop.org/drm/intel/issues/4767 > [i915#4771]: https://gitlab.freedesktop.org/drm/intel/issues/4771 > [i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812 > [i915#4818]: https://gitlab.freedesktop.org/drm/intel/issues/4818 > [i915#4833]: https://gitlab.freedesktop.org/drm/intel/issues/4833 > [i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852 > [i915#4855]: https://gitlab.freedesktop.org/drm/intel/issues/4855 > [i915#4859]: https://gitlab.freedesktop.org/drm/intel/issues/4859 > [i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860 > [i915#4874]: https://gitlab.freedesktop.org/drm/intel/issues/4874 > [i915#4877]: https://gitlab.freedesktop.org/drm/intel/issues/4877 > [i915#4880]: https://gitlab.freedesktop.org/drm/intel/issues/4880 > [i915#4881]: https://gitlab.freedesktop.org/drm/intel/issues/4881 > [i915#4884]: https://gitlab.freedesktop.org/drm/intel/issues/4884 > [i915#4885]: https://gitlab.freedesktop.org/drm/intel/issues/4885 > [i915#4958]: https://gitlab.freedesktop.org/drm/intel/issues/4958 > [i915#4991]: https://gitlab.freedesktop.org/drm/intel/issues/4991 > [i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176 > [i915#5213]: https://gitlab.freedesktop.org/drm/intel/issues/5213 > [i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235 > [i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286 > [i915#5288]: https://gitlab.freedesktop.org/drm/intel/issues/5288 > [i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289 > [i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325 > [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533 > [i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334 > [i915#5439]: https://gitlab.freedesktop.org/drm/intel/issues/5439 > [i915#5563]: https://gitlab.freedesktop.org/drm/intel/issues/5563 > [i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784 > [i915#588]: https://gitlab.freedesktop.org/drm/intel/issues/588 > [i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095 > [i915#6117]: https://gitlab.freedesktop.org/drm/intel/issues/6117 > [i915#6248]: https://gitlab.freedesktop.org/drm/intel/issues/6248 > [i915#6251]: https://gitlab.freedesktop.org/drm/intel/issues/6251 > [i915#6252]: https://gitlab.freedesktop.org/drm/intel/issues/6252 > [i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268 > [i915#6301]: https://gitlab.freedesktop.org/drm/intel/issues/6301 > [i915#6335]: https://gitlab.freedesktop.org/drm/intel/issues/6335 > [i915#6412]: https://gitlab.freedesktop.org/drm/intel/issues/6412 > [i915#6433]: https://gitlab.freedesktop.org/drm/intel/issues/6433 > [i915#6463]: https://gitlab.freedesktop.org/drm/intel/issues/6463 > [i915#6497]: https://gitlab.freedesktop.org/drm/intel/issues/6497 > [i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524 > [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658 > [i915#6590]: https://gitlab.freedesktop.org/drm/intel/issues/6590 > [i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621 > [i915#6946]: https://gitlab.freedesktop.org/drm/intel/issues/6946 > [i915#7112]: https://gitlab.freedesktop.org/drm/intel/issues/7112 > [i915#7116]: https://gitlab.freedesktop.org/drm/intel/issues/7116 > [i915#7142]: https://gitlab.freedesktop.org/drm/intel/issues/7142 > [i915#7178]: https://gitlab.freedesktop.org/drm/intel/issues/7178 > [i915#7247]: https://gitlab.freedesktop.org/drm/intel/issues/7247 > [i915#7318]: https://gitlab.freedesktop.org/drm/intel/issues/7318 > [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 > > > Build changes > ------------- > > * Linux: CI_DRM_12293 -> Patchwork_109963v5 > > CI-20190529: 20190529 > CI_DRM_12293: 508d090a36a87847ece5f75d4d0c12e96ca819a3 @ git://anongit.freedesktop.org/gfx-ci/linux > IGT_7026: ce0f97e7e0aa54c40049a8365b3d61773c92e588 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git > Patchwork_109963v5: 508d090a36a87847ece5f75d4d0c12e96ca819a3 @ git://anongit.freedesktop.org/gfx-ci/linux > piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit > > == Logs == > > For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/index.html ^ permalink raw reply [flat|nested] 16+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/tgl+: Fix race conditions during DKL PHY accesses (rev5) 2022-10-25 10:26 [Intel-gfx] [PATCH v3 0/4] drm/i915/tgl+: Fix race conditions during DKL PHY accesses Imre Deak ` (7 preceding siblings ...) 2022-10-25 20:04 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork @ 2022-10-26 17:12 ` Patchwork 2022-10-26 19:04 ` Patchwork 2022-10-26 19:32 ` [Intel-gfx] ✓ Fi.CI.IGT: success " Patchwork 10 siblings, 0 replies; 16+ messages in thread From: Patchwork @ 2022-10-26 17:12 UTC (permalink / raw) To: Imre Deak; +Cc: intel-gfx [-- Attachment #1: Type: text/plain, Size: 28278 bytes --] == Series Details == Series: drm/i915/tgl+: Fix race conditions during DKL PHY accesses (rev5) URL : https://patchwork.freedesktop.org/series/109963/ State : failure == Summary == CI Bug Log - changes from CI_DRM_12293_full -> Patchwork_109963v5_full ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_109963v5_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_109963v5_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (9 -> 11) ------------------------------ Additional (2): shard-rkl shard-dg1 Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_109963v5_full: ### IGT changes ### #### Possible regressions #### * igt@kms_cursor_crc@cursor-suspend@pipe-b-edp-1: - shard-skl: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-skl7/igt@kms_cursor_crc@cursor-suspend@pipe-b-edp-1.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-skl9/igt@kms_cursor_crc@cursor-suspend@pipe-b-edp-1.html #### Suppressed #### The following results come from untrusted machines, tests, or statuses. They do not affect the overall result. * igt@sysfs_preempt_timeout@idempotent@rcs0: - {shard-dg1}: NOTRUN -> [FAIL][3] +4 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-dg1-15/igt@sysfs_preempt_timeout@idempotent@rcs0.html Known issues ------------ Here are the changes found in Patchwork_109963v5_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt@gem_eio@in-flight-contexts-10ms: - shard-tglb: [PASS][4] -> [TIMEOUT][5] ([i915#3063]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-tglb5/igt@gem_eio@in-flight-contexts-10ms.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-tglb6/igt@gem_eio@in-flight-contexts-10ms.html * igt@gem_eio@in-flight-suspend: - shard-skl: [PASS][6] -> [INCOMPLETE][7] ([i915#7112]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-skl10/igt@gem_eio@in-flight-suspend.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-skl6/igt@gem_eio@in-flight-suspend.html * igt@gem_exec_balancer@parallel: - shard-iclb: [PASS][8] -> [SKIP][9] ([i915#4525]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-iclb1/igt@gem_exec_balancer@parallel.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-iclb5/igt@gem_exec_balancer@parallel.html * igt@gem_exec_fair@basic-pace-share@rcs0: - shard-glk: [PASS][10] -> [FAIL][11] ([i915#2842]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-glk5/igt@gem_exec_fair@basic-pace-share@rcs0.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-glk1/igt@gem_exec_fair@basic-pace-share@rcs0.html * igt@gem_exec_fair@basic-pace-solo@rcs0: - shard-apl: [PASS][12] -> [FAIL][13] ([i915#2842]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-apl3/igt@gem_exec_fair@basic-pace-solo@rcs0.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-apl6/igt@gem_exec_fair@basic-pace-solo@rcs0.html * igt@gem_lmem_swapping@parallel-random: - shard-skl: NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#4613]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-skl7/igt@gem_lmem_swapping@parallel-random.html * igt@i915_pm_dc@dc6-dpms: - shard-iclb: [PASS][15] -> [FAIL][16] ([i915#3989] / [i915#454]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-iclb5/igt@i915_pm_dc@dc6-dpms.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-iclb3/igt@i915_pm_dc@dc6-dpms.html * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-async-flip: - shard-skl: NOTRUN -> [SKIP][17] ([fdo#109271]) +43 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-skl7/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html * igt@kms_color_chamelium@ctm-limited-range: - shard-skl: NOTRUN -> [SKIP][18] ([fdo#109271] / [fdo#111827]) +2 similar issues [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-skl7/igt@kms_color_chamelium@ctm-limited-range.html * igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1: - shard-skl: [PASS][19] -> [FAIL][20] ([i915#79]) +1 similar issue [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-skl9/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-skl7/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html * igt@kms_flip_scaled_crc@flip-64bpp-linear-to-32bpp-linear-downscaling@pipe-a-default-mode: - shard-iclb: NOTRUN -> [SKIP][21] ([i915#3555]) +2 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-linear-to-32bpp-linear-downscaling@pipe-a-default-mode.html * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling@pipe-a-valid-mode: - shard-iclb: NOTRUN -> [SKIP][22] ([i915#2587] / [i915#2672]) +1 similar issue [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-iclb5/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling@pipe-a-valid-mode.html * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling@pipe-a-default-mode: - shard-iclb: NOTRUN -> [SKIP][23] ([i915#2672]) +6 similar issues [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-iclb3/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling@pipe-a-default-mode.html * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-valid-mode: - shard-iclb: NOTRUN -> [SKIP][24] ([i915#2672] / [i915#3555]) [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-iclb6/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-valid-mode.html * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-render: - shard-apl: NOTRUN -> [SKIP][25] ([fdo#109271]) +6 similar issues [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-apl6/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-render.html * igt@kms_psr2_sf@plane-move-sf-dmg-area: - shard-skl: NOTRUN -> [SKIP][26] ([fdo#109271] / [i915#658]) [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-skl7/igt@kms_psr2_sf@plane-move-sf-dmg-area.html * igt@kms_psr2_su@page_flip-nv12: - shard-iclb: NOTRUN -> [SKIP][27] ([fdo#109642] / [fdo#111068] / [i915#658]) [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-iclb6/igt@kms_psr2_su@page_flip-nv12.html * igt@kms_psr@psr2_primary_page_flip: - shard-iclb: [PASS][28] -> [SKIP][29] ([fdo#109441]) +1 similar issue [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-iclb2/igt@kms_psr@psr2_primary_page_flip.html [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-iclb5/igt@kms_psr@psr2_primary_page_flip.html * igt@perf@stress-open-close: - shard-glk: [PASS][30] -> [INCOMPLETE][31] ([i915#5213]) [30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-glk7/igt@perf@stress-open-close.html [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-glk3/igt@perf@stress-open-close.html * igt@perf_pmu@interrupts: - shard-skl: [PASS][32] -> [FAIL][33] ([i915#7318]) [32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-skl4/igt@perf_pmu@interrupts.html [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-skl9/igt@perf_pmu@interrupts.html * igt@sysfs_clients@recycle-many: - shard-skl: NOTRUN -> [SKIP][34] ([fdo#109271] / [i915#2994]) [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-skl7/igt@sysfs_clients@recycle-many.html * igt@sysfs_heartbeat_interval@precise@vecs0: - shard-apl: [PASS][35] -> [FAIL][36] ([i915#1755]) [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-apl8/igt@sysfs_heartbeat_interval@precise@vecs0.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-apl7/igt@sysfs_heartbeat_interval@precise@vecs0.html #### Possible fixes #### * igt@gem_exec_balancer@parallel-bb-first: - shard-iclb: [SKIP][37] ([i915#4525]) -> [PASS][38] +1 similar issue [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-iclb7/igt@gem_exec_balancer@parallel-bb-first.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-iclb2/igt@gem_exec_balancer@parallel-bb-first.html * igt@gem_exec_fair@basic-none@vecs0: - shard-glk: [FAIL][39] ([i915#2842]) -> [PASS][40] [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-glk1/igt@gem_exec_fair@basic-none@vecs0.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-glk5/igt@gem_exec_fair@basic-none@vecs0.html * igt@i915_pm_dc@dc5-psr: - shard-skl: [FAIL][41] -> [PASS][42] [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-skl9/igt@i915_pm_dc@dc5-psr.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-skl6/igt@i915_pm_dc@dc5-psr.html * igt@i915_selftest@live@gt_heartbeat: - shard-apl: [DMESG-FAIL][43] ([i915#5334]) -> [PASS][44] [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-apl7/igt@i915_selftest@live@gt_heartbeat.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-apl3/igt@i915_selftest@live@gt_heartbeat.html * igt@kms_async_flips@alternate-sync-async-flip@pipe-b-edp-1: - shard-skl: [FAIL][45] ([i915#2521]) -> [PASS][46] [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-skl10/igt@kms_async_flips@alternate-sync-async-flip@pipe-b-edp-1.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-skl4/igt@kms_async_flips@alternate-sync-async-flip@pipe-b-edp-1.html * igt@kms_fbcon_fbt@psr-suspend: - shard-skl: [FAIL][47] ([i915#4767]) -> [PASS][48] [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-skl4/igt@kms_fbcon_fbt@psr-suspend.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-skl10/igt@kms_fbcon_fbt@psr-suspend.html * igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1: - shard-skl: [FAIL][49] ([i915#79]) -> [PASS][50] [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-skl9/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-skl7/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html * igt@kms_flip@flip-vs-expired-vblank-interruptible@c-hdmi-a1: - shard-glk: [FAIL][51] ([i915#79]) -> [PASS][52] +1 similar issue [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-glk7/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-hdmi-a1.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-glk3/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-hdmi-a1.html * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-blt: - shard-iclb: [FAIL][53] ([i915#2546]) -> [PASS][54] +2 similar issues [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-iclb2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-blt.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-iclb5/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-blt.html * igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-render: - shard-iclb: [FAIL][55] -> [PASS][56] [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-iclb2/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-render.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-iclb5/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-render.html * igt@kms_hdr@bpc-switch-suspend@pipe-a-dp-1: - shard-apl: [DMESG-WARN][57] ([i915#180]) -> [PASS][58] [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-apl3/igt@kms_hdr@bpc-switch-suspend@pipe-a-dp-1.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-apl6/igt@kms_hdr@bpc-switch-suspend@pipe-a-dp-1.html * igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-c-edp-1: - shard-iclb: [SKIP][59] ([i915#5235]) -> [PASS][60] +2 similar issues [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-iclb2/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-c-edp-1.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-iclb6/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-c-edp-1.html * igt@kms_psr@psr2_cursor_plane_move: - shard-iclb: [SKIP][61] ([fdo#109441]) -> [PASS][62] [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-iclb7/igt@kms_psr@psr2_cursor_plane_move.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-iclb2/igt@kms_psr@psr2_cursor_plane_move.html #### Warnings #### * igt@gem_exec_balancer@parallel-ordering: - shard-iclb: [FAIL][63] ([i915#6117]) -> [SKIP][64] ([i915#4525]) [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-iclb2/igt@gem_exec_balancer@parallel-ordering.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-iclb3/igt@gem_exec_balancer@parallel-ordering.html * igt@i915_pm_dc@dc3co-vpb-simulation: - shard-iclb: [SKIP][65] ([i915#658]) -> [SKIP][66] ([i915#588]) [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-iclb7/igt@i915_pm_dc@dc3co-vpb-simulation.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-iclb2/igt@i915_pm_dc@dc3co-vpb-simulation.html * igt@i915_pm_rc6_residency@rc6-idle@rcs0: - shard-iclb: [FAIL][67] ([i915#2684]) -> [WARN][68] ([i915#2684]) [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-iclb8/igt@i915_pm_rc6_residency@rc6-idle@rcs0.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-iclb1/igt@i915_pm_rc6_residency@rc6-idle@rcs0.html * igt@kms_psr2_sf@cursor-plane-update-sf: - shard-iclb: [SKIP][69] ([fdo#111068] / [i915#658]) -> [SKIP][70] ([i915#2920]) [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-iclb7/igt@kms_psr2_sf@cursor-plane-update-sf.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-iclb2/igt@kms_psr2_sf@cursor-plane-update-sf.html * igt@kms_psr2_sf@overlay-plane-update-continuous-sf: - shard-iclb: [SKIP][71] ([i915#2920]) -> [SKIP][72] ([fdo#111068] / [i915#658]) +1 similar issue [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-iclb2/igt@kms_psr2_sf@overlay-plane-update-continuous-sf.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-iclb5/igt@kms_psr2_sf@overlay-plane-update-continuous-sf.html * igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb: - shard-iclb: [SKIP][73] ([i915#658]) -> [SKIP][74] ([i915#2920]) [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-iclb7/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-iclb2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274 [fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283 [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285 [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289 [fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295 [fdo#109302]: https://bugs.freedesktop.org/show_bug.cgi?id=109302 [fdo#109303]: https://bugs.freedesktop.org/show_bug.cgi?id=109303 [fdo#109307]: https://bugs.freedesktop.org/show_bug.cgi?id=109307 [fdo#109308]: https://bugs.freedesktop.org/show_bug.cgi?id=109308 [fdo#109312]: https://bugs.freedesktop.org/show_bug.cgi?id=109312 [fdo#109313]: https://bugs.freedesktop.org/show_bug.cgi?id=109313 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506 [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642 [fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189 [fdo#110542]: https://bugs.freedesktop.org/show_bug.cgi?id=110542 [fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723 [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068 [fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614 [fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615 [fdo#111656]: https://bugs.freedesktop.org/show_bug.cgi?id=111656 [fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [fdo#112054]: https://bugs.freedesktop.org/show_bug.cgi?id=112054 [fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283 [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072 [i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155 [i915#1257]: https://gitlab.freedesktop.org/drm/intel/issues/1257 [i915#132]: https://gitlab.freedesktop.org/drm/intel/issues/132 [i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397 [i915#1755]: https://gitlab.freedesktop.org/drm/intel/issues/1755 [i915#1769]: https://gitlab.freedesktop.org/drm/intel/issues/1769 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825 [i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839 [i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845 [i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849 [i915#1850]: https://gitlab.freedesktop.org/drm/intel/issues/1850 [i915#1902]: https://gitlab.freedesktop.org/drm/intel/issues/1902 [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190 [i915#2410]: https://gitlab.freedesktop.org/drm/intel/issues/2410 [i915#2433]: https://gitlab.freedesktop.org/drm/intel/issues/2433 [i915#2435]: https://gitlab.freedesktop.org/drm/intel/issues/2435 [i915#2436]: https://gitlab.freedesktop.org/drm/intel/issues/2436 [i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437 [i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521 [i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527 [i915#2546]: https://gitlab.freedesktop.org/drm/intel/issues/2546 [i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582 [i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587 [i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672 [i915#2684]: https://gitlab.freedesktop.org/drm/intel/issues/2684 [i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705 [i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280 [i915#284]: https://gitlab.freedesktop.org/drm/intel/issues/284 [i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842 [i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920 [i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994 [i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002 [i915#3012]: https://gitlab.freedesktop.org/drm/intel/issues/3012 [i915#3063]: https://gitlab.freedesktop.org/drm/intel/issues/3063 [i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281 [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282 [i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291 [i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297 [i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299 [i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301 [i915#3318]: https://gitlab.freedesktop.org/drm/intel/issues/3318 [i915#3323]: https://gitlab.freedesktop.org/drm/intel/issues/3323 [i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359 [i915#3361]: https://gitlab.freedesktop.org/drm/intel/issues/3361 [i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458 [i915#3469]: https://gitlab.freedesktop.org/drm/intel/issues/3469 [i915#3528]: https://gitlab.freedesktop.org/drm/intel/issues/3528 [i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539 [i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546 [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555 [i915#3558]: https://gitlab.freedesktop.org/drm/intel/issues/3558 [i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637 [i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638 [i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689 [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708 [i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734 [i915#3742]: https://gitlab.freedesktop.org/drm/intel/issues/3742 [i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840 [i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886 [i915#3936]: https://gitlab.freedesktop.org/drm/intel/issues/3936 [i915#3952]: https://gitlab.freedesktop.org/drm/intel/issues/3952 [i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955 [i915#3989]: https://gitlab.freedesktop.org/drm/intel/issues/3989 [i915#4036]: https://gitlab.freedesktop.org/drm/intel/issues/4036 [i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070 [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077 [i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078 [i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079 [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083 [i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098 [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103 [i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212 [i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213 [i915#426]: https://gitlab.freedesktop.org/drm/intel/issues/426 [i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270 [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312 [i915#433]: https://gitlab.freedesktop.org/drm/intel/issues/433 [i915#4349]: https://gitlab.freedesktop.org/drm/intel/issues/4349 [i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525 [i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538 [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454 [i915#4565]: https://gitlab.freedesktop.org/drm/intel/issues/4565 [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613 [i915#4767]: https://gitlab.freedesktop.org/drm/intel/issues/4767 [i915#4771]: https://gitlab.freedesktop.org/drm/intel/issues/4771 [i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812 [i915#4818]: https://gitlab.freedesktop.org/drm/intel/issues/4818 [i915#4833]: https://gitlab.freedesktop.org/drm/intel/issues/4833 [i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852 [i915#4855]: https://gitlab.freedesktop.org/drm/intel/issues/4855 [i915#4859]: https://gitlab.freedesktop.org/drm/intel/issues/4859 [i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860 [i915#4874]: https://gitlab.freedesktop.org/drm/intel/issues/4874 [i915#4877]: https://gitlab.freedesktop.org/drm/intel/issues/4877 [i915#4880]: https://gitlab.freedesktop.org/drm/intel/issues/4880 [i915#4881]: https://gitlab.freedesktop.org/drm/intel/issues/4881 [i915#4884]: https://gitlab.freedesktop.org/drm/intel/issues/4884 [i915#4885]: https://gitlab.freedesktop.org/drm/intel/issues/4885 [i915#4958]: https://gitlab.freedesktop.org/drm/intel/issues/4958 [i915#4991]: https://gitlab.freedesktop.org/drm/intel/issues/4991 [i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176 [i915#5213]: https://gitlab.freedesktop.org/drm/intel/issues/5213 [i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235 [i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286 [i915#5288]: https://gitlab.freedesktop.org/drm/intel/issues/5288 [i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289 [i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325 [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533 [i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334 [i915#5439]: https://gitlab.freedesktop.org/drm/intel/issues/5439 [i915#5563]: https://gitlab.freedesktop.org/drm/intel/issues/5563 [i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784 [i915#588]: https://gitlab.freedesktop.org/drm/intel/issues/588 [i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095 [i915#6117]: https://gitlab.freedesktop.org/drm/intel/issues/6117 [i915#6248]: https://gitlab.freedesktop.org/drm/intel/issues/6248 [i915#6251]: https://gitlab.freedesktop.org/drm/intel/issues/6251 [i915#6252]: https://gitlab.freedesktop.org/drm/intel/issues/6252 [i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268 [i915#6301]: https://gitlab.freedesktop.org/drm/intel/issues/6301 [i915#6335]: https://gitlab.freedesktop.org/drm/intel/issues/6335 [i915#6412]: https://gitlab.freedesktop.org/drm/intel/issues/6412 [i915#6433]: https://gitlab.freedesktop.org/drm/intel/issues/6433 [i915#6463]: https://gitlab.freedesktop.org/drm/intel/issues/6463 [i915#6497]: https://gitlab.freedesktop.org/drm/intel/issues/6497 [i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524 [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658 [i915#6590]: https://gitlab.freedesktop.org/drm/intel/issues/6590 [i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621 [i915#6946]: https://gitlab.freedesktop.org/drm/intel/issues/6946 [i915#7112]: https://gitlab.freedesktop.org/drm/intel/issues/7112 [i915#7116]: https://gitlab.freedesktop.org/drm/intel/issues/7116 [i915#7142]: https://gitlab.freedesktop.org/drm/intel/issues/7142 [i915#7178]: https://gitlab.freedesktop.org/drm/intel/issues/7178 [i915#7247]: https://gitlab.freedesktop.org/drm/intel/issues/7247 [i915#7318]: https://gitlab.freedesktop.org/drm/intel/issues/7318 [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 Build changes ------------- * Linux: CI_DRM_12293 -> Patchwork_109963v5 CI-20190529: 20190529 CI_DRM_12293: 508d090a36a87847ece5f75d4d0c12e96ca819a3 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_7026: ce0f97e7e0aa54c40049a8365b3d61773c92e588 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_109963v5: 508d090a36a87847ece5f75d4d0c12e96ca819a3 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/index.html [-- Attachment #2: Type: text/html, Size: 22530 bytes --] ^ permalink raw reply [flat|nested] 16+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/tgl+: Fix race conditions during DKL PHY accesses (rev5) 2022-10-25 10:26 [Intel-gfx] [PATCH v3 0/4] drm/i915/tgl+: Fix race conditions during DKL PHY accesses Imre Deak ` (8 preceding siblings ...) 2022-10-26 17:12 ` Patchwork @ 2022-10-26 19:04 ` Patchwork 2022-10-26 19:32 ` [Intel-gfx] ✓ Fi.CI.IGT: success " Patchwork 10 siblings, 0 replies; 16+ messages in thread From: Patchwork @ 2022-10-26 19:04 UTC (permalink / raw) To: Imre Deak; +Cc: intel-gfx [-- Attachment #1: Type: text/plain, Size: 28278 bytes --] == Series Details == Series: drm/i915/tgl+: Fix race conditions during DKL PHY accesses (rev5) URL : https://patchwork.freedesktop.org/series/109963/ State : failure == Summary == CI Bug Log - changes from CI_DRM_12293_full -> Patchwork_109963v5_full ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_109963v5_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_109963v5_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (9 -> 11) ------------------------------ Additional (2): shard-rkl shard-dg1 Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_109963v5_full: ### IGT changes ### #### Possible regressions #### * igt@kms_cursor_crc@cursor-suspend@pipe-b-edp-1: - shard-skl: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-skl7/igt@kms_cursor_crc@cursor-suspend@pipe-b-edp-1.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-skl9/igt@kms_cursor_crc@cursor-suspend@pipe-b-edp-1.html #### Suppressed #### The following results come from untrusted machines, tests, or statuses. They do not affect the overall result. * igt@sysfs_preempt_timeout@idempotent@rcs0: - {shard-dg1}: NOTRUN -> [FAIL][3] +4 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-dg1-15/igt@sysfs_preempt_timeout@idempotent@rcs0.html Known issues ------------ Here are the changes found in Patchwork_109963v5_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt@gem_eio@in-flight-contexts-10ms: - shard-tglb: [PASS][4] -> [TIMEOUT][5] ([i915#3063]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-tglb5/igt@gem_eio@in-flight-contexts-10ms.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-tglb6/igt@gem_eio@in-flight-contexts-10ms.html * igt@gem_eio@in-flight-suspend: - shard-skl: [PASS][6] -> [INCOMPLETE][7] ([i915#7112]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-skl10/igt@gem_eio@in-flight-suspend.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-skl6/igt@gem_eio@in-flight-suspend.html * igt@gem_exec_balancer@parallel: - shard-iclb: [PASS][8] -> [SKIP][9] ([i915#4525]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-iclb1/igt@gem_exec_balancer@parallel.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-iclb5/igt@gem_exec_balancer@parallel.html * igt@gem_exec_fair@basic-pace-share@rcs0: - shard-glk: [PASS][10] -> [FAIL][11] ([i915#2842]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-glk5/igt@gem_exec_fair@basic-pace-share@rcs0.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-glk1/igt@gem_exec_fair@basic-pace-share@rcs0.html * igt@gem_exec_fair@basic-pace-solo@rcs0: - shard-apl: [PASS][12] -> [FAIL][13] ([i915#2842]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-apl3/igt@gem_exec_fair@basic-pace-solo@rcs0.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-apl6/igt@gem_exec_fair@basic-pace-solo@rcs0.html * igt@gem_lmem_swapping@parallel-random: - shard-skl: NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#4613]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-skl7/igt@gem_lmem_swapping@parallel-random.html * igt@i915_pm_dc@dc6-dpms: - shard-iclb: [PASS][15] -> [FAIL][16] ([i915#3989] / [i915#454]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-iclb5/igt@i915_pm_dc@dc6-dpms.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-iclb3/igt@i915_pm_dc@dc6-dpms.html * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-async-flip: - shard-skl: NOTRUN -> [SKIP][17] ([fdo#109271]) +43 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-skl7/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html * igt@kms_color_chamelium@ctm-limited-range: - shard-skl: NOTRUN -> [SKIP][18] ([fdo#109271] / [fdo#111827]) +2 similar issues [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-skl7/igt@kms_color_chamelium@ctm-limited-range.html * igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1: - shard-skl: [PASS][19] -> [FAIL][20] ([i915#79]) +1 similar issue [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-skl9/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-skl7/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html * igt@kms_flip_scaled_crc@flip-64bpp-linear-to-32bpp-linear-downscaling@pipe-a-default-mode: - shard-iclb: NOTRUN -> [SKIP][21] ([i915#3555]) +2 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-linear-to-32bpp-linear-downscaling@pipe-a-default-mode.html * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling@pipe-a-valid-mode: - shard-iclb: NOTRUN -> [SKIP][22] ([i915#2587] / [i915#2672]) +1 similar issue [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-iclb5/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling@pipe-a-valid-mode.html * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling@pipe-a-default-mode: - shard-iclb: NOTRUN -> [SKIP][23] ([i915#2672]) +6 similar issues [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-iclb3/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling@pipe-a-default-mode.html * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-valid-mode: - shard-iclb: NOTRUN -> [SKIP][24] ([i915#2672] / [i915#3555]) [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-iclb6/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-valid-mode.html * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-render: - shard-apl: NOTRUN -> [SKIP][25] ([fdo#109271]) +6 similar issues [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-apl6/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-render.html * igt@kms_psr2_sf@plane-move-sf-dmg-area: - shard-skl: NOTRUN -> [SKIP][26] ([fdo#109271] / [i915#658]) [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-skl7/igt@kms_psr2_sf@plane-move-sf-dmg-area.html * igt@kms_psr2_su@page_flip-nv12: - shard-iclb: NOTRUN -> [SKIP][27] ([fdo#109642] / [fdo#111068] / [i915#658]) [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-iclb6/igt@kms_psr2_su@page_flip-nv12.html * igt@kms_psr@psr2_primary_page_flip: - shard-iclb: [PASS][28] -> [SKIP][29] ([fdo#109441]) +1 similar issue [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-iclb2/igt@kms_psr@psr2_primary_page_flip.html [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-iclb5/igt@kms_psr@psr2_primary_page_flip.html * igt@perf@stress-open-close: - shard-glk: [PASS][30] -> [INCOMPLETE][31] ([i915#5213]) [30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-glk7/igt@perf@stress-open-close.html [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-glk3/igt@perf@stress-open-close.html * igt@perf_pmu@interrupts: - shard-skl: [PASS][32] -> [FAIL][33] ([i915#7318]) [32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-skl4/igt@perf_pmu@interrupts.html [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-skl9/igt@perf_pmu@interrupts.html * igt@sysfs_clients@recycle-many: - shard-skl: NOTRUN -> [SKIP][34] ([fdo#109271] / [i915#2994]) [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-skl7/igt@sysfs_clients@recycle-many.html * igt@sysfs_heartbeat_interval@precise@vecs0: - shard-apl: [PASS][35] -> [FAIL][36] ([i915#1755]) [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-apl8/igt@sysfs_heartbeat_interval@precise@vecs0.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-apl7/igt@sysfs_heartbeat_interval@precise@vecs0.html #### Possible fixes #### * igt@gem_exec_balancer@parallel-bb-first: - shard-iclb: [SKIP][37] ([i915#4525]) -> [PASS][38] +1 similar issue [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-iclb7/igt@gem_exec_balancer@parallel-bb-first.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-iclb2/igt@gem_exec_balancer@parallel-bb-first.html * igt@gem_exec_fair@basic-none@vecs0: - shard-glk: [FAIL][39] ([i915#2842]) -> [PASS][40] [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-glk1/igt@gem_exec_fair@basic-none@vecs0.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-glk5/igt@gem_exec_fair@basic-none@vecs0.html * igt@i915_pm_dc@dc5-psr: - shard-skl: [FAIL][41] -> [PASS][42] [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-skl9/igt@i915_pm_dc@dc5-psr.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-skl6/igt@i915_pm_dc@dc5-psr.html * igt@i915_selftest@live@gt_heartbeat: - shard-apl: [DMESG-FAIL][43] ([i915#5334]) -> [PASS][44] [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-apl7/igt@i915_selftest@live@gt_heartbeat.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-apl3/igt@i915_selftest@live@gt_heartbeat.html * igt@kms_async_flips@alternate-sync-async-flip@pipe-b-edp-1: - shard-skl: [FAIL][45] ([i915#2521]) -> [PASS][46] [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-skl10/igt@kms_async_flips@alternate-sync-async-flip@pipe-b-edp-1.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-skl4/igt@kms_async_flips@alternate-sync-async-flip@pipe-b-edp-1.html * igt@kms_fbcon_fbt@psr-suspend: - shard-skl: [FAIL][47] ([i915#4767]) -> [PASS][48] [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-skl4/igt@kms_fbcon_fbt@psr-suspend.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-skl10/igt@kms_fbcon_fbt@psr-suspend.html * igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1: - shard-skl: [FAIL][49] ([i915#79]) -> [PASS][50] [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-skl9/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-skl7/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html * igt@kms_flip@flip-vs-expired-vblank-interruptible@c-hdmi-a1: - shard-glk: [FAIL][51] ([i915#79]) -> [PASS][52] +1 similar issue [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-glk7/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-hdmi-a1.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-glk3/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-hdmi-a1.html * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-blt: - shard-iclb: [FAIL][53] ([i915#2546]) -> [PASS][54] +2 similar issues [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-iclb2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-blt.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-iclb5/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-blt.html * igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-render: - shard-iclb: [FAIL][55] -> [PASS][56] [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-iclb2/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-render.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-iclb5/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-render.html * igt@kms_hdr@bpc-switch-suspend@pipe-a-dp-1: - shard-apl: [DMESG-WARN][57] ([i915#180]) -> [PASS][58] [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-apl3/igt@kms_hdr@bpc-switch-suspend@pipe-a-dp-1.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-apl6/igt@kms_hdr@bpc-switch-suspend@pipe-a-dp-1.html * igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-c-edp-1: - shard-iclb: [SKIP][59] ([i915#5235]) -> [PASS][60] +2 similar issues [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-iclb2/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-c-edp-1.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-iclb6/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-c-edp-1.html * igt@kms_psr@psr2_cursor_plane_move: - shard-iclb: [SKIP][61] ([fdo#109441]) -> [PASS][62] [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-iclb7/igt@kms_psr@psr2_cursor_plane_move.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-iclb2/igt@kms_psr@psr2_cursor_plane_move.html #### Warnings #### * igt@gem_exec_balancer@parallel-ordering: - shard-iclb: [FAIL][63] ([i915#6117]) -> [SKIP][64] ([i915#4525]) [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-iclb2/igt@gem_exec_balancer@parallel-ordering.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-iclb3/igt@gem_exec_balancer@parallel-ordering.html * igt@i915_pm_dc@dc3co-vpb-simulation: - shard-iclb: [SKIP][65] ([i915#658]) -> [SKIP][66] ([i915#588]) [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-iclb7/igt@i915_pm_dc@dc3co-vpb-simulation.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-iclb2/igt@i915_pm_dc@dc3co-vpb-simulation.html * igt@i915_pm_rc6_residency@rc6-idle@rcs0: - shard-iclb: [FAIL][67] ([i915#2684]) -> [WARN][68] ([i915#2684]) [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-iclb8/igt@i915_pm_rc6_residency@rc6-idle@rcs0.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-iclb1/igt@i915_pm_rc6_residency@rc6-idle@rcs0.html * igt@kms_psr2_sf@cursor-plane-update-sf: - shard-iclb: [SKIP][69] ([fdo#111068] / [i915#658]) -> [SKIP][70] ([i915#2920]) [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-iclb7/igt@kms_psr2_sf@cursor-plane-update-sf.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-iclb2/igt@kms_psr2_sf@cursor-plane-update-sf.html * igt@kms_psr2_sf@overlay-plane-update-continuous-sf: - shard-iclb: [SKIP][71] ([i915#2920]) -> [SKIP][72] ([fdo#111068] / [i915#658]) +1 similar issue [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-iclb2/igt@kms_psr2_sf@overlay-plane-update-continuous-sf.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-iclb5/igt@kms_psr2_sf@overlay-plane-update-continuous-sf.html * igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb: - shard-iclb: [SKIP][73] ([i915#658]) -> [SKIP][74] ([i915#2920]) [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-iclb7/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-iclb2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274 [fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283 [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285 [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289 [fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295 [fdo#109302]: https://bugs.freedesktop.org/show_bug.cgi?id=109302 [fdo#109303]: https://bugs.freedesktop.org/show_bug.cgi?id=109303 [fdo#109307]: https://bugs.freedesktop.org/show_bug.cgi?id=109307 [fdo#109308]: https://bugs.freedesktop.org/show_bug.cgi?id=109308 [fdo#109312]: https://bugs.freedesktop.org/show_bug.cgi?id=109312 [fdo#109313]: https://bugs.freedesktop.org/show_bug.cgi?id=109313 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506 [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642 [fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189 [fdo#110542]: https://bugs.freedesktop.org/show_bug.cgi?id=110542 [fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723 [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068 [fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614 [fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615 [fdo#111656]: https://bugs.freedesktop.org/show_bug.cgi?id=111656 [fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [fdo#112054]: https://bugs.freedesktop.org/show_bug.cgi?id=112054 [fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283 [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072 [i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155 [i915#1257]: https://gitlab.freedesktop.org/drm/intel/issues/1257 [i915#132]: https://gitlab.freedesktop.org/drm/intel/issues/132 [i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397 [i915#1755]: https://gitlab.freedesktop.org/drm/intel/issues/1755 [i915#1769]: https://gitlab.freedesktop.org/drm/intel/issues/1769 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825 [i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839 [i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845 [i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849 [i915#1850]: https://gitlab.freedesktop.org/drm/intel/issues/1850 [i915#1902]: https://gitlab.freedesktop.org/drm/intel/issues/1902 [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190 [i915#2410]: https://gitlab.freedesktop.org/drm/intel/issues/2410 [i915#2433]: https://gitlab.freedesktop.org/drm/intel/issues/2433 [i915#2435]: https://gitlab.freedesktop.org/drm/intel/issues/2435 [i915#2436]: https://gitlab.freedesktop.org/drm/intel/issues/2436 [i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437 [i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521 [i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527 [i915#2546]: https://gitlab.freedesktop.org/drm/intel/issues/2546 [i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582 [i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587 [i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672 [i915#2684]: https://gitlab.freedesktop.org/drm/intel/issues/2684 [i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705 [i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280 [i915#284]: https://gitlab.freedesktop.org/drm/intel/issues/284 [i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842 [i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920 [i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994 [i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002 [i915#3012]: https://gitlab.freedesktop.org/drm/intel/issues/3012 [i915#3063]: https://gitlab.freedesktop.org/drm/intel/issues/3063 [i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281 [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282 [i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291 [i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297 [i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299 [i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301 [i915#3318]: https://gitlab.freedesktop.org/drm/intel/issues/3318 [i915#3323]: https://gitlab.freedesktop.org/drm/intel/issues/3323 [i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359 [i915#3361]: https://gitlab.freedesktop.org/drm/intel/issues/3361 [i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458 [i915#3469]: https://gitlab.freedesktop.org/drm/intel/issues/3469 [i915#3528]: https://gitlab.freedesktop.org/drm/intel/issues/3528 [i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539 [i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546 [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555 [i915#3558]: https://gitlab.freedesktop.org/drm/intel/issues/3558 [i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637 [i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638 [i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689 [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708 [i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734 [i915#3742]: https://gitlab.freedesktop.org/drm/intel/issues/3742 [i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840 [i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886 [i915#3936]: https://gitlab.freedesktop.org/drm/intel/issues/3936 [i915#3952]: https://gitlab.freedesktop.org/drm/intel/issues/3952 [i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955 [i915#3989]: https://gitlab.freedesktop.org/drm/intel/issues/3989 [i915#4036]: https://gitlab.freedesktop.org/drm/intel/issues/4036 [i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070 [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077 [i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078 [i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079 [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083 [i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098 [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103 [i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212 [i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213 [i915#426]: https://gitlab.freedesktop.org/drm/intel/issues/426 [i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270 [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312 [i915#433]: https://gitlab.freedesktop.org/drm/intel/issues/433 [i915#4349]: https://gitlab.freedesktop.org/drm/intel/issues/4349 [i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525 [i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538 [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454 [i915#4565]: https://gitlab.freedesktop.org/drm/intel/issues/4565 [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613 [i915#4767]: https://gitlab.freedesktop.org/drm/intel/issues/4767 [i915#4771]: https://gitlab.freedesktop.org/drm/intel/issues/4771 [i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812 [i915#4818]: https://gitlab.freedesktop.org/drm/intel/issues/4818 [i915#4833]: https://gitlab.freedesktop.org/drm/intel/issues/4833 [i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852 [i915#4855]: https://gitlab.freedesktop.org/drm/intel/issues/4855 [i915#4859]: https://gitlab.freedesktop.org/drm/intel/issues/4859 [i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860 [i915#4874]: https://gitlab.freedesktop.org/drm/intel/issues/4874 [i915#4877]: https://gitlab.freedesktop.org/drm/intel/issues/4877 [i915#4880]: https://gitlab.freedesktop.org/drm/intel/issues/4880 [i915#4881]: https://gitlab.freedesktop.org/drm/intel/issues/4881 [i915#4884]: https://gitlab.freedesktop.org/drm/intel/issues/4884 [i915#4885]: https://gitlab.freedesktop.org/drm/intel/issues/4885 [i915#4958]: https://gitlab.freedesktop.org/drm/intel/issues/4958 [i915#4991]: https://gitlab.freedesktop.org/drm/intel/issues/4991 [i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176 [i915#5213]: https://gitlab.freedesktop.org/drm/intel/issues/5213 [i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235 [i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286 [i915#5288]: https://gitlab.freedesktop.org/drm/intel/issues/5288 [i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289 [i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325 [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533 [i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334 [i915#5439]: https://gitlab.freedesktop.org/drm/intel/issues/5439 [i915#5563]: https://gitlab.freedesktop.org/drm/intel/issues/5563 [i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784 [i915#588]: https://gitlab.freedesktop.org/drm/intel/issues/588 [i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095 [i915#6117]: https://gitlab.freedesktop.org/drm/intel/issues/6117 [i915#6248]: https://gitlab.freedesktop.org/drm/intel/issues/6248 [i915#6251]: https://gitlab.freedesktop.org/drm/intel/issues/6251 [i915#6252]: https://gitlab.freedesktop.org/drm/intel/issues/6252 [i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268 [i915#6301]: https://gitlab.freedesktop.org/drm/intel/issues/6301 [i915#6335]: https://gitlab.freedesktop.org/drm/intel/issues/6335 [i915#6412]: https://gitlab.freedesktop.org/drm/intel/issues/6412 [i915#6433]: https://gitlab.freedesktop.org/drm/intel/issues/6433 [i915#6463]: https://gitlab.freedesktop.org/drm/intel/issues/6463 [i915#6497]: https://gitlab.freedesktop.org/drm/intel/issues/6497 [i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524 [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658 [i915#6590]: https://gitlab.freedesktop.org/drm/intel/issues/6590 [i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621 [i915#6946]: https://gitlab.freedesktop.org/drm/intel/issues/6946 [i915#7112]: https://gitlab.freedesktop.org/drm/intel/issues/7112 [i915#7116]: https://gitlab.freedesktop.org/drm/intel/issues/7116 [i915#7142]: https://gitlab.freedesktop.org/drm/intel/issues/7142 [i915#7178]: https://gitlab.freedesktop.org/drm/intel/issues/7178 [i915#7247]: https://gitlab.freedesktop.org/drm/intel/issues/7247 [i915#7318]: https://gitlab.freedesktop.org/drm/intel/issues/7318 [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 Build changes ------------- * Linux: CI_DRM_12293 -> Patchwork_109963v5 CI-20190529: 20190529 CI_DRM_12293: 508d090a36a87847ece5f75d4d0c12e96ca819a3 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_7026: ce0f97e7e0aa54c40049a8365b3d61773c92e588 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_109963v5: 508d090a36a87847ece5f75d4d0c12e96ca819a3 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/index.html [-- Attachment #2: Type: text/html, Size: 22530 bytes --] ^ permalink raw reply [flat|nested] 16+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/tgl+: Fix race conditions during DKL PHY accesses (rev5) 2022-10-25 10:26 [Intel-gfx] [PATCH v3 0/4] drm/i915/tgl+: Fix race conditions during DKL PHY accesses Imre Deak ` (9 preceding siblings ...) 2022-10-26 19:04 ` Patchwork @ 2022-10-26 19:32 ` Patchwork 10 siblings, 0 replies; 16+ messages in thread From: Patchwork @ 2022-10-26 19:32 UTC (permalink / raw) To: Imre Deak; +Cc: intel-gfx [-- Attachment #1: Type: text/plain, Size: 28008 bytes --] == Series Details == Series: drm/i915/tgl+: Fix race conditions during DKL PHY accesses (rev5) URL : https://patchwork.freedesktop.org/series/109963/ State : success == Summary == CI Bug Log - changes from CI_DRM_12293_full -> Patchwork_109963v5_full ==================================================== Summary ------- **SUCCESS** No regressions found. Participating hosts (9 -> 11) ------------------------------ Additional (2): shard-rkl shard-dg1 Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_109963v5_full: ### IGT changes ### #### Suppressed #### The following results come from untrusted machines, tests, or statuses. They do not affect the overall result. * igt@sysfs_preempt_timeout@idempotent@rcs0: - {shard-dg1}: NOTRUN -> [FAIL][1] +4 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-dg1-15/igt@sysfs_preempt_timeout@idempotent@rcs0.html Known issues ------------ Here are the changes found in Patchwork_109963v5_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt@gem_eio@in-flight-contexts-10ms: - shard-tglb: [PASS][2] -> [TIMEOUT][3] ([i915#3063]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-tglb5/igt@gem_eio@in-flight-contexts-10ms.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-tglb6/igt@gem_eio@in-flight-contexts-10ms.html * igt@gem_eio@in-flight-suspend: - shard-skl: [PASS][4] -> [INCOMPLETE][5] ([i915#7112]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-skl10/igt@gem_eio@in-flight-suspend.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-skl6/igt@gem_eio@in-flight-suspend.html * igt@gem_exec_balancer@parallel: - shard-iclb: [PASS][6] -> [SKIP][7] ([i915#4525]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-iclb1/igt@gem_exec_balancer@parallel.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-iclb5/igt@gem_exec_balancer@parallel.html * igt@gem_exec_fair@basic-pace-share@rcs0: - shard-glk: [PASS][8] -> [FAIL][9] ([i915#2842]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-glk5/igt@gem_exec_fair@basic-pace-share@rcs0.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-glk1/igt@gem_exec_fair@basic-pace-share@rcs0.html * igt@gem_exec_fair@basic-pace-solo@rcs0: - shard-apl: [PASS][10] -> [FAIL][11] ([i915#2842]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-apl3/igt@gem_exec_fair@basic-pace-solo@rcs0.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-apl6/igt@gem_exec_fair@basic-pace-solo@rcs0.html * igt@gem_lmem_swapping@parallel-random: - shard-skl: NOTRUN -> [SKIP][12] ([fdo#109271] / [i915#4613]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-skl7/igt@gem_lmem_swapping@parallel-random.html * igt@i915_pm_dc@dc6-dpms: - shard-iclb: [PASS][13] -> [FAIL][14] ([i915#3989] / [i915#454]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-iclb5/igt@i915_pm_dc@dc6-dpms.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-iclb3/igt@i915_pm_dc@dc6-dpms.html * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-async-flip: - shard-skl: NOTRUN -> [SKIP][15] ([fdo#109271]) +43 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-skl7/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html * igt@kms_color_chamelium@ctm-limited-range: - shard-skl: NOTRUN -> [SKIP][16] ([fdo#109271] / [fdo#111827]) +2 similar issues [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-skl7/igt@kms_color_chamelium@ctm-limited-range.html * igt@kms_cursor_crc@cursor-suspend@pipe-b-edp-1: - shard-skl: [PASS][17] -> [INCOMPLETE][18] ([i915#6951]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-skl7/igt@kms_cursor_crc@cursor-suspend@pipe-b-edp-1.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-skl9/igt@kms_cursor_crc@cursor-suspend@pipe-b-edp-1.html * igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1: - shard-skl: [PASS][19] -> [FAIL][20] ([i915#79]) +1 similar issue [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-skl9/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-skl7/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html * igt@kms_flip_scaled_crc@flip-64bpp-linear-to-32bpp-linear-downscaling@pipe-a-default-mode: - shard-iclb: NOTRUN -> [SKIP][21] ([i915#3555]) +2 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-linear-to-32bpp-linear-downscaling@pipe-a-default-mode.html * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling@pipe-a-valid-mode: - shard-iclb: NOTRUN -> [SKIP][22] ([i915#2587] / [i915#2672]) +1 similar issue [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-iclb5/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling@pipe-a-valid-mode.html * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling@pipe-a-default-mode: - shard-iclb: NOTRUN -> [SKIP][23] ([i915#2672]) +6 similar issues [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-iclb3/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling@pipe-a-default-mode.html * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-valid-mode: - shard-iclb: NOTRUN -> [SKIP][24] ([i915#2672] / [i915#3555]) [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-iclb6/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-valid-mode.html * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-render: - shard-apl: NOTRUN -> [SKIP][25] ([fdo#109271]) +6 similar issues [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-apl6/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-render.html * igt@kms_psr2_sf@plane-move-sf-dmg-area: - shard-skl: NOTRUN -> [SKIP][26] ([fdo#109271] / [i915#658]) [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-skl7/igt@kms_psr2_sf@plane-move-sf-dmg-area.html * igt@kms_psr2_su@page_flip-nv12: - shard-iclb: NOTRUN -> [SKIP][27] ([fdo#109642] / [fdo#111068] / [i915#658]) [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-iclb6/igt@kms_psr2_su@page_flip-nv12.html * igt@kms_psr@psr2_primary_page_flip: - shard-iclb: [PASS][28] -> [SKIP][29] ([fdo#109441]) +1 similar issue [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-iclb2/igt@kms_psr@psr2_primary_page_flip.html [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-iclb5/igt@kms_psr@psr2_primary_page_flip.html * igt@perf@stress-open-close: - shard-glk: [PASS][30] -> [INCOMPLETE][31] ([i915#5213]) [30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-glk7/igt@perf@stress-open-close.html [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-glk3/igt@perf@stress-open-close.html * igt@perf_pmu@interrupts: - shard-skl: [PASS][32] -> [FAIL][33] ([i915#7318]) [32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-skl4/igt@perf_pmu@interrupts.html [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-skl9/igt@perf_pmu@interrupts.html * igt@sysfs_clients@recycle-many: - shard-skl: NOTRUN -> [SKIP][34] ([fdo#109271] / [i915#2994]) [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-skl7/igt@sysfs_clients@recycle-many.html * igt@sysfs_heartbeat_interval@precise@vecs0: - shard-apl: [PASS][35] -> [FAIL][36] ([i915#1755]) [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-apl8/igt@sysfs_heartbeat_interval@precise@vecs0.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-apl7/igt@sysfs_heartbeat_interval@precise@vecs0.html #### Possible fixes #### * igt@gem_exec_balancer@parallel-bb-first: - shard-iclb: [SKIP][37] ([i915#4525]) -> [PASS][38] +1 similar issue [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-iclb7/igt@gem_exec_balancer@parallel-bb-first.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-iclb2/igt@gem_exec_balancer@parallel-bb-first.html * igt@gem_exec_fair@basic-none@vecs0: - shard-glk: [FAIL][39] ([i915#2842]) -> [PASS][40] [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-glk1/igt@gem_exec_fair@basic-none@vecs0.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-glk5/igt@gem_exec_fair@basic-none@vecs0.html * igt@i915_pm_dc@dc5-psr: - shard-skl: [FAIL][41] -> [PASS][42] [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-skl9/igt@i915_pm_dc@dc5-psr.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-skl6/igt@i915_pm_dc@dc5-psr.html * igt@i915_selftest@live@gt_heartbeat: - shard-apl: [DMESG-FAIL][43] ([i915#5334]) -> [PASS][44] [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-apl7/igt@i915_selftest@live@gt_heartbeat.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-apl3/igt@i915_selftest@live@gt_heartbeat.html * igt@kms_async_flips@alternate-sync-async-flip@pipe-b-edp-1: - shard-skl: [FAIL][45] ([i915#2521]) -> [PASS][46] [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-skl10/igt@kms_async_flips@alternate-sync-async-flip@pipe-b-edp-1.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-skl4/igt@kms_async_flips@alternate-sync-async-flip@pipe-b-edp-1.html * igt@kms_fbcon_fbt@psr-suspend: - shard-skl: [FAIL][47] ([i915#4767]) -> [PASS][48] [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-skl4/igt@kms_fbcon_fbt@psr-suspend.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-skl10/igt@kms_fbcon_fbt@psr-suspend.html * igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1: - shard-skl: [FAIL][49] ([i915#79]) -> [PASS][50] [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-skl9/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-skl7/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html * igt@kms_flip@flip-vs-expired-vblank-interruptible@c-hdmi-a1: - shard-glk: [FAIL][51] ([i915#79]) -> [PASS][52] +1 similar issue [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-glk7/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-hdmi-a1.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-glk3/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-hdmi-a1.html * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-blt: - shard-iclb: [FAIL][53] ([i915#2546]) -> [PASS][54] +2 similar issues [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-iclb2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-blt.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-iclb5/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-blt.html * igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-render: - shard-iclb: [FAIL][55] -> [PASS][56] [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-iclb2/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-render.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-iclb5/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-render.html * igt@kms_hdr@bpc-switch-suspend@pipe-a-dp-1: - shard-apl: [DMESG-WARN][57] ([i915#180]) -> [PASS][58] [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-apl3/igt@kms_hdr@bpc-switch-suspend@pipe-a-dp-1.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-apl6/igt@kms_hdr@bpc-switch-suspend@pipe-a-dp-1.html * igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-c-edp-1: - shard-iclb: [SKIP][59] ([i915#5235]) -> [PASS][60] +2 similar issues [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-iclb2/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-c-edp-1.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-iclb6/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-c-edp-1.html * igt@kms_psr@psr2_cursor_plane_move: - shard-iclb: [SKIP][61] ([fdo#109441]) -> [PASS][62] [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-iclb7/igt@kms_psr@psr2_cursor_plane_move.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-iclb2/igt@kms_psr@psr2_cursor_plane_move.html #### Warnings #### * igt@gem_exec_balancer@parallel-ordering: - shard-iclb: [FAIL][63] ([i915#6117]) -> [SKIP][64] ([i915#4525]) [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-iclb2/igt@gem_exec_balancer@parallel-ordering.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-iclb3/igt@gem_exec_balancer@parallel-ordering.html * igt@i915_pm_dc@dc3co-vpb-simulation: - shard-iclb: [SKIP][65] ([i915#658]) -> [SKIP][66] ([i915#588]) [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-iclb7/igt@i915_pm_dc@dc3co-vpb-simulation.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-iclb2/igt@i915_pm_dc@dc3co-vpb-simulation.html * igt@i915_pm_rc6_residency@rc6-idle@rcs0: - shard-iclb: [FAIL][67] ([i915#2684]) -> [WARN][68] ([i915#2684]) [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-iclb8/igt@i915_pm_rc6_residency@rc6-idle@rcs0.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-iclb1/igt@i915_pm_rc6_residency@rc6-idle@rcs0.html * igt@kms_psr2_sf@cursor-plane-update-sf: - shard-iclb: [SKIP][69] ([fdo#111068] / [i915#658]) -> [SKIP][70] ([i915#2920]) [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-iclb7/igt@kms_psr2_sf@cursor-plane-update-sf.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-iclb2/igt@kms_psr2_sf@cursor-plane-update-sf.html * igt@kms_psr2_sf@overlay-plane-update-continuous-sf: - shard-iclb: [SKIP][71] ([i915#2920]) -> [SKIP][72] ([fdo#111068] / [i915#658]) +1 similar issue [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-iclb2/igt@kms_psr2_sf@overlay-plane-update-continuous-sf.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-iclb5/igt@kms_psr2_sf@overlay-plane-update-continuous-sf.html * igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb: - shard-iclb: [SKIP][73] ([i915#658]) -> [SKIP][74] ([i915#2920]) [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-iclb7/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-iclb2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274 [fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283 [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285 [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289 [fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295 [fdo#109302]: https://bugs.freedesktop.org/show_bug.cgi?id=109302 [fdo#109303]: https://bugs.freedesktop.org/show_bug.cgi?id=109303 [fdo#109307]: https://bugs.freedesktop.org/show_bug.cgi?id=109307 [fdo#109308]: https://bugs.freedesktop.org/show_bug.cgi?id=109308 [fdo#109312]: https://bugs.freedesktop.org/show_bug.cgi?id=109312 [fdo#109313]: https://bugs.freedesktop.org/show_bug.cgi?id=109313 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506 [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642 [fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189 [fdo#110542]: https://bugs.freedesktop.org/show_bug.cgi?id=110542 [fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723 [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068 [fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614 [fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615 [fdo#111656]: https://bugs.freedesktop.org/show_bug.cgi?id=111656 [fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [fdo#112054]: https://bugs.freedesktop.org/show_bug.cgi?id=112054 [fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283 [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072 [i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155 [i915#1257]: https://gitlab.freedesktop.org/drm/intel/issues/1257 [i915#132]: https://gitlab.freedesktop.org/drm/intel/issues/132 [i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397 [i915#1755]: https://gitlab.freedesktop.org/drm/intel/issues/1755 [i915#1769]: https://gitlab.freedesktop.org/drm/intel/issues/1769 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825 [i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839 [i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845 [i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849 [i915#1850]: https://gitlab.freedesktop.org/drm/intel/issues/1850 [i915#1902]: https://gitlab.freedesktop.org/drm/intel/issues/1902 [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190 [i915#2410]: https://gitlab.freedesktop.org/drm/intel/issues/2410 [i915#2433]: https://gitlab.freedesktop.org/drm/intel/issues/2433 [i915#2435]: https://gitlab.freedesktop.org/drm/intel/issues/2435 [i915#2436]: https://gitlab.freedesktop.org/drm/intel/issues/2436 [i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437 [i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521 [i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527 [i915#2546]: https://gitlab.freedesktop.org/drm/intel/issues/2546 [i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582 [i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587 [i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672 [i915#2684]: https://gitlab.freedesktop.org/drm/intel/issues/2684 [i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705 [i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280 [i915#284]: https://gitlab.freedesktop.org/drm/intel/issues/284 [i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842 [i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920 [i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994 [i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002 [i915#3012]: https://gitlab.freedesktop.org/drm/intel/issues/3012 [i915#3063]: https://gitlab.freedesktop.org/drm/intel/issues/3063 [i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281 [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282 [i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291 [i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297 [i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299 [i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301 [i915#3318]: https://gitlab.freedesktop.org/drm/intel/issues/3318 [i915#3323]: https://gitlab.freedesktop.org/drm/intel/issues/3323 [i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359 [i915#3361]: https://gitlab.freedesktop.org/drm/intel/issues/3361 [i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458 [i915#3469]: https://gitlab.freedesktop.org/drm/intel/issues/3469 [i915#3528]: https://gitlab.freedesktop.org/drm/intel/issues/3528 [i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539 [i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546 [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555 [i915#3558]: https://gitlab.freedesktop.org/drm/intel/issues/3558 [i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637 [i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638 [i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689 [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708 [i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734 [i915#3742]: https://gitlab.freedesktop.org/drm/intel/issues/3742 [i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840 [i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886 [i915#3936]: https://gitlab.freedesktop.org/drm/intel/issues/3936 [i915#3952]: https://gitlab.freedesktop.org/drm/intel/issues/3952 [i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955 [i915#3989]: https://gitlab.freedesktop.org/drm/intel/issues/3989 [i915#4036]: https://gitlab.freedesktop.org/drm/intel/issues/4036 [i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070 [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077 [i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078 [i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079 [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083 [i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098 [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103 [i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212 [i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213 [i915#426]: https://gitlab.freedesktop.org/drm/intel/issues/426 [i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270 [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312 [i915#433]: https://gitlab.freedesktop.org/drm/intel/issues/433 [i915#4349]: https://gitlab.freedesktop.org/drm/intel/issues/4349 [i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525 [i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538 [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454 [i915#4565]: https://gitlab.freedesktop.org/drm/intel/issues/4565 [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613 [i915#4767]: https://gitlab.freedesktop.org/drm/intel/issues/4767 [i915#4771]: https://gitlab.freedesktop.org/drm/intel/issues/4771 [i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812 [i915#4818]: https://gitlab.freedesktop.org/drm/intel/issues/4818 [i915#4833]: https://gitlab.freedesktop.org/drm/intel/issues/4833 [i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852 [i915#4855]: https://gitlab.freedesktop.org/drm/intel/issues/4855 [i915#4859]: https://gitlab.freedesktop.org/drm/intel/issues/4859 [i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860 [i915#4874]: https://gitlab.freedesktop.org/drm/intel/issues/4874 [i915#4877]: https://gitlab.freedesktop.org/drm/intel/issues/4877 [i915#4880]: https://gitlab.freedesktop.org/drm/intel/issues/4880 [i915#4881]: https://gitlab.freedesktop.org/drm/intel/issues/4881 [i915#4884]: https://gitlab.freedesktop.org/drm/intel/issues/4884 [i915#4885]: https://gitlab.freedesktop.org/drm/intel/issues/4885 [i915#4958]: https://gitlab.freedesktop.org/drm/intel/issues/4958 [i915#4991]: https://gitlab.freedesktop.org/drm/intel/issues/4991 [i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176 [i915#5213]: https://gitlab.freedesktop.org/drm/intel/issues/5213 [i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235 [i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286 [i915#5288]: https://gitlab.freedesktop.org/drm/intel/issues/5288 [i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289 [i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325 [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533 [i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334 [i915#5439]: https://gitlab.freedesktop.org/drm/intel/issues/5439 [i915#5563]: https://gitlab.freedesktop.org/drm/intel/issues/5563 [i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784 [i915#588]: https://gitlab.freedesktop.org/drm/intel/issues/588 [i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095 [i915#6117]: https://gitlab.freedesktop.org/drm/intel/issues/6117 [i915#6248]: https://gitlab.freedesktop.org/drm/intel/issues/6248 [i915#6251]: https://gitlab.freedesktop.org/drm/intel/issues/6251 [i915#6252]: https://gitlab.freedesktop.org/drm/intel/issues/6252 [i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268 [i915#6301]: https://gitlab.freedesktop.org/drm/intel/issues/6301 [i915#6335]: https://gitlab.freedesktop.org/drm/intel/issues/6335 [i915#6412]: https://gitlab.freedesktop.org/drm/intel/issues/6412 [i915#6433]: https://gitlab.freedesktop.org/drm/intel/issues/6433 [i915#6463]: https://gitlab.freedesktop.org/drm/intel/issues/6463 [i915#6497]: https://gitlab.freedesktop.org/drm/intel/issues/6497 [i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524 [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658 [i915#6590]: https://gitlab.freedesktop.org/drm/intel/issues/6590 [i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621 [i915#6946]: https://gitlab.freedesktop.org/drm/intel/issues/6946 [i915#6951]: https://gitlab.freedesktop.org/drm/intel/issues/6951 [i915#7112]: https://gitlab.freedesktop.org/drm/intel/issues/7112 [i915#7116]: https://gitlab.freedesktop.org/drm/intel/issues/7116 [i915#7142]: https://gitlab.freedesktop.org/drm/intel/issues/7142 [i915#7178]: https://gitlab.freedesktop.org/drm/intel/issues/7178 [i915#7247]: https://gitlab.freedesktop.org/drm/intel/issues/7247 [i915#7318]: https://gitlab.freedesktop.org/drm/intel/issues/7318 [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 Build changes ------------- * Linux: CI_DRM_12293 -> Patchwork_109963v5 CI-20190529: 20190529 CI_DRM_12293: 508d090a36a87847ece5f75d4d0c12e96ca819a3 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_7026: ce0f97e7e0aa54c40049a8365b3d61773c92e588 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_109963v5: 508d090a36a87847ece5f75d4d0c12e96ca819a3 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/index.html [-- Attachment #2: Type: text/html, Size: 22240 bytes --] ^ permalink raw reply [flat|nested] 16+ messages in thread
end of thread, other threads:[~2022-10-26 19:32 UTC | newest] Thread overview: 16+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2022-10-25 10:26 [Intel-gfx] [PATCH v3 0/4] drm/i915/tgl+: Fix race conditions during DKL PHY accesses Imre Deak 2022-10-25 10:26 ` [Intel-gfx] [PATCH v3 1/4] drm/i915/tgl+: Add locking around DKL PHY register accesses Imre Deak 2022-10-25 11:44 ` [Intel-gfx] [PATCH v4 " Imre Deak 2022-10-25 10:26 ` [Intel-gfx] [PATCH v3 2/4] drm/i915: Rename intel_tc_phy_regs.h to intel_mg_phy_regs.h Imre Deak 2022-10-25 10:26 ` [Intel-gfx] [PATCH v3 3/4] drm/i915/tgl+: Move DKL PHY register definitions to intel_dkl_phy_regs.h Imre Deak 2022-10-25 11:44 ` [Intel-gfx] [PATCH v4 " Imre Deak 2022-10-25 10:26 ` [Intel-gfx] [PATCH v3 4/4] drm/i915/tgl+: Sanitize DKL PHY register definitions Imre Deak 2022-10-25 11:44 ` [Intel-gfx] [PATCH v4 " Imre Deak 2022-10-25 13:06 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/tgl+: Fix race conditions during DKL PHY accesses (rev5) Patchwork 2022-10-25 13:06 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork 2022-10-25 13:30 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2022-10-25 20:04 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork 2022-10-26 13:00 ` Imre Deak 2022-10-26 17:12 ` Patchwork 2022-10-26 19:04 ` Patchwork 2022-10-26 19:32 ` [Intel-gfx] ✓ Fi.CI.IGT: success " Patchwork
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