From: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH v6 12/16] drm/i915/perf: Apply Wa_18013179988
Date: Wed, 26 Oct 2022 22:20:58 +0000 [thread overview]
Message-ID: <20221026222102.5526-13-umesh.nerlige.ramappa@intel.com> (raw)
In-Reply-To: <20221026222102.5526-1-umesh.nerlige.ramappa@intel.com>
OA reports in the OA buffer contain an OA timestamp field that helps
user calculate delta between 2 OA reports. The calculation relies on the
CS timestamp frequency to convert the timestamp value to nanoseconds.
The CS timestamp frequency is a function of the CTC_SHIFT value in
RPM_CONFIG0.
In DG2, OA unit assumes that the CTC_SHIFT is 3, instead of using the
actual value from RPM_CONFIG0. At the user level, this results in an
error in calculating delta between 2 OA reports since the OA timestamp
is not shifted in the same manner as CS timestamp. Also the periodicity
of the reports is different from what the user configured because of
mismatch in the CS and OA frequencies.
The issue also affects MI_REPORT_PERF_COUNT command.
To resolve this, return actual OA timestamp frequency to the user in
i915_getparam_ioctl, so that user can calculate the right OA exponent as
well as interpret the reports correctly.
MR: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18893
v2:
- Use REG_FIELD_GET (Ashutosh)
- Update commit msg
Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
---
drivers/gpu/drm/i915/i915_getparam.c | 3 +++
drivers/gpu/drm/i915/i915_perf.c | 30 ++++++++++++++++++++++++++--
drivers/gpu/drm/i915/i915_perf.h | 2 ++
include/uapi/drm/i915_drm.h | 6 ++++++
4 files changed, 39 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_getparam.c b/drivers/gpu/drm/i915/i915_getparam.c
index 342c8ca6414e..3047e80e1163 100644
--- a/drivers/gpu/drm/i915/i915_getparam.c
+++ b/drivers/gpu/drm/i915/i915_getparam.c
@@ -175,6 +175,9 @@ int i915_getparam_ioctl(struct drm_device *dev, void *data,
case I915_PARAM_PERF_REVISION:
value = i915_perf_ioctl_version();
break;
+ case I915_PARAM_OA_TIMESTAMP_FREQUENCY:
+ value = i915_perf_oa_timestamp_frequency(i915);
+ break;
default:
DRM_DEBUG("Unknown parameter %d\n", param->param);
return -EINVAL;
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index e14d16ac47de..b73d91b792df 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -3109,6 +3109,30 @@ get_sseu_config(struct intel_sseu *out_sseu,
return i915_gem_user_to_context_sseu(engine->gt, drm_sseu, out_sseu);
}
+/*
+ * OA timestamp frequency = CS timestamp frequency in most platforms. On some
+ * platforms OA unit ignores the CTC_SHIFT and the 2 timestamps differ. In such
+ * cases, return the adjusted CS timestamp frequency to the user.
+ */
+u32 i915_perf_oa_timestamp_frequency(struct drm_i915_private *i915)
+{
+ /* Wa_18013179988:dg2 */
+ if (IS_DG2(i915)) {
+ intel_wakeref_t wakeref;
+ u32 reg, shift;
+
+ with_intel_runtime_pm(to_gt(i915)->uncore->rpm, wakeref)
+ reg = intel_uncore_read(to_gt(i915)->uncore, RPM_CONFIG0);
+
+ shift = REG_FIELD_GET(GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK,
+ reg);
+
+ return to_gt(i915)->clock_frequency << (3 - shift);
+ }
+
+ return to_gt(i915)->clock_frequency;
+}
+
/**
* i915_oa_stream_init - validate combined props for OA stream and init
* @stream: An i915 perf stream
@@ -3830,8 +3854,10 @@ i915_perf_open_ioctl_locked(struct i915_perf *perf,
static u64 oa_exponent_to_ns(struct i915_perf *perf, int exponent)
{
- return intel_gt_clock_interval_to_ns(to_gt(perf->i915),
- 2ULL << exponent);
+ u64 nom = (2ULL << exponent) * NSEC_PER_SEC;
+ u32 den = i915_perf_oa_timestamp_frequency(perf->i915);
+
+ return div_u64(nom + den - 1, den);
}
static __always_inline bool
diff --git a/drivers/gpu/drm/i915/i915_perf.h b/drivers/gpu/drm/i915/i915_perf.h
index 1d1329e5af3a..f96e09a4af04 100644
--- a/drivers/gpu/drm/i915/i915_perf.h
+++ b/drivers/gpu/drm/i915/i915_perf.h
@@ -57,4 +57,6 @@ static inline void i915_oa_config_put(struct i915_oa_config *oa_config)
kref_put(&oa_config->ref, i915_oa_config_release);
}
+u32 i915_perf_oa_timestamp_frequency(struct drm_i915_private *i915);
+
#endif /* __I915_PERF_H__ */
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 158b35fb28f3..c346b1923d11 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -765,6 +765,12 @@ typedef struct drm_i915_irq_wait {
/* Query if the kernel supports the I915_USERPTR_PROBE flag. */
#define I915_PARAM_HAS_USERPTR_PROBE 56
+/*
+ * Frequency of the timestamps in OA reports. This used to be the same as the CS
+ * timestamp frequency, but differs on some platforms.
+ */
+#define I915_PARAM_OA_TIMESTAMP_FREQUENCY 57
+
/* Must be kept compact -- no holes and well documented */
/**
--
2.25.1
next prev parent reply other threads:[~2022-10-26 22:21 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-26 22:20 [Intel-gfx] [PATCH v6 00/16] Add DG2 OA support Umesh Nerlige Ramappa
2022-10-26 22:20 ` [Intel-gfx] [PATCH v6 01/16] drm/i915/perf: Fix OA filtering logic for GuC mode Umesh Nerlige Ramappa
2022-10-26 22:20 ` [Intel-gfx] [PATCH v6 02/16] drm/i915/perf: Add 32-bit OAG and OAR formats for DG2 Umesh Nerlige Ramappa
2022-10-26 22:20 ` [Intel-gfx] [PATCH v6 03/16] drm/i915/perf: Fix noa wait predication " Umesh Nerlige Ramappa
2022-10-26 22:20 ` [Intel-gfx] [PATCH v6 04/16] drm/i915/perf: Determine gen12 oa ctx offset at runtime Umesh Nerlige Ramappa
2022-10-26 22:20 ` [Intel-gfx] [PATCH v6 05/16] drm/i915/perf: Enable bytes per clock reporting in OA Umesh Nerlige Ramappa
2022-10-26 22:20 ` [Intel-gfx] [PATCH v6 06/16] drm/i915/perf: Simply use stream->ctx Umesh Nerlige Ramappa
2022-10-26 22:20 ` [Intel-gfx] [PATCH v6 07/16] drm/i915/perf: Move gt-specific data from i915->perf to gt->perf Umesh Nerlige Ramappa
2022-10-26 22:20 ` [Intel-gfx] [PATCH v6 08/16] drm/i915/perf: Replace gt->perf.lock with stream->lock for file ops Umesh Nerlige Ramappa
2022-10-26 22:20 ` [Intel-gfx] [PATCH v6 09/16] drm/i915/perf: Use gt-specific ggtt for OA and noa-wait buffers Umesh Nerlige Ramappa
2022-10-26 22:20 ` [Intel-gfx] [PATCH v6 10/16] drm/i915/perf: Store a pointer to oa_format in oa_buffer Umesh Nerlige Ramappa
2022-10-26 22:20 ` [Intel-gfx] [PATCH v6 11/16] drm/i915/perf: Add Wa_1508761755:dg2 Umesh Nerlige Ramappa
2022-10-26 22:20 ` Umesh Nerlige Ramappa [this message]
2022-10-26 22:20 ` [Intel-gfx] [PATCH v6 13/16] drm/i915/perf: Save/restore EU flex counters across reset Umesh Nerlige Ramappa
2022-10-26 22:21 ` [Intel-gfx] [PATCH v6 14/16] drm/i915/guc: Support OA when Wa_16011777198 is enabled Umesh Nerlige Ramappa
2022-10-26 22:21 ` [Intel-gfx] [PATCH v6 15/16] drm/i915/perf: complete programming whitelisting for XEHPSDV Umesh Nerlige Ramappa
2022-10-26 22:21 ` [Intel-gfx] [PATCH v6 16/16] drm/i915/perf: Enable OA for DG2 Umesh Nerlige Ramappa
2022-10-27 3:35 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add DG2 OA support (rev11) Patchwork
2022-10-27 4:01 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-10-27 15:08 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2022-10-27 19:34 ` Umesh Nerlige Ramappa
2022-10-27 19:44 ` Umesh Nerlige Ramappa
2022-10-27 18:57 ` [Intel-gfx] [PATCH v6 00/16] Add DG2 OA support Lionel Landwerlin
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