From: Swati Sharma <swati2.sharma@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH v2 2/8] drm/i915/dp: Check if DSC supports the given output_format
Date: Fri, 28 Oct 2022 16:49:47 +0530 [thread overview]
Message-ID: <20221028111953.12552-3-swati2.sharma@intel.com> (raw)
In-Reply-To: <20221028111953.12552-1-swati2.sharma@intel.com>
From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Go with DSC only if the given output_format is supported.
v2: Use drm helper to get DSC format support for sink.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 28 +++++++++++++++++++++++++
1 file changed, 28 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 7400d6b4c587..a5c31ac1ec73 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1464,6 +1464,31 @@ static int intel_dp_dsc_compute_params(struct intel_encoder *encoder,
return drm_dsc_compute_rc_parameters(vdsc_cfg);
}
+static bool intel_dp_dsc_supports_format(struct intel_dp *intel_dp,
+ enum intel_output_format output_format)
+{
+ u8 sink_dsc_format;
+
+ switch (output_format) {
+ case INTEL_OUTPUT_FORMAT_RGB:
+ sink_dsc_format = DP_DSC_RGB;
+ break;
+ case INTEL_OUTPUT_FORMAT_YCBCR444:
+ sink_dsc_format = DP_DSC_YCbCr444;
+ break;
+ case INTEL_OUTPUT_FORMAT_YCBCR420:
+ if (min(intel_dp_source_dsc_version_minor(intel_dp),
+ intel_dp_sink_dsc_version_minor(intel_dp)) < 2)
+ return false;
+ sink_dsc_format = DP_DSC_YCbCr420_Native;
+ break;
+ default:
+ return false;
+ }
+
+ return drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd, sink_dsc_format);
+}
+
static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
struct intel_crtc_state *pipe_config,
struct drm_connector_state *conn_state,
@@ -1482,6 +1507,9 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
if (!intel_dp_supports_dsc(intel_dp, pipe_config))
return -EINVAL;
+ if (!intel_dp_dsc_supports_format(intel_dp, pipe_config->output_format))
+ return -EINVAL;
+
pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, conn_state->max_requested_bpc);
if (intel_dp->force_dsc_bpc) {
--
2.25.1
next prev parent reply other threads:[~2022-10-28 11:18 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-28 11:19 [Intel-gfx] [PATCH v5 0/8] Enable YCbCr420 for VDSC Swati Sharma
2022-10-28 11:19 ` [Intel-gfx] [PATCH 1/8] drm/dp_helper: Add helper to check if the sink supports given format with DSC Swati Sharma
2022-10-28 11:19 ` Swati Sharma [this message]
2022-10-28 11:19 ` [Intel-gfx] [PATCH v4 3/8] drm/i915: Adding the new registers for DSC Swati Sharma
2022-10-28 11:19 ` [Intel-gfx] [PATCH v4 4/8] drm/i915: Enable YCbCr420 for VDSC Swati Sharma
2022-10-28 11:19 ` [Intel-gfx] [PATCH v4 5/8] drm/i915: Fill in native_420 field Swati Sharma
2022-10-28 11:19 ` [Intel-gfx] [PATCH 6/8] drm/i915/dsc: Add debugfs entry to validate DSC YCbCr420 Swati Sharma
2022-10-28 11:19 ` [Intel-gfx] [PATCH 7/8] drm/i915/dsc: Allow DSC only with YCbCr420 format when forced from debugfs Swati Sharma
2022-10-28 11:19 ` [Intel-gfx] [PATCH 8/8] drm/i915: Code styling fixes Swati Sharma
2022-10-28 13:43 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Enable YCbCr420 for VDSC Patchwork
2022-10-28 13:43 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-10-28 14:04 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-10-29 2:03 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
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