* [Intel-gfx] [PATCH 2/2] drm/i915/display: Add CDCLK Support for MTL
2022-09-28 19:04 [Intel-gfx] [PATCH 1/2] drm/i915/display: Do both crawl and squash when changing cdclk Anusha Srivatsa
@ 2022-09-28 19:04 ` Anusha Srivatsa
2022-09-28 19:23 ` Ville Syrjälä
0 siblings, 1 reply; 15+ messages in thread
From: Anusha Srivatsa @ 2022-09-28 19:04 UTC (permalink / raw)
To: intel-gfx
As per bSpec MTL has 38.4 MHz Reference clock.
MTL does support squasher like DG2 but only for lower
frequencies. Change the has_cdclk_squasher()
helper to reflect this.
bxt_get_cdclk() is not properly calculating HW clock for MTL,
because the squash formula is only prepared for DG2.
Apart from adding the cdclk table, align cdclk support with the
new cdclk_crawl_and_squash() introduced in previous patch.
BSpec: 65243
Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 95 +++++++++++++++++++++-
1 file changed, 93 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index f7bc1013b149..6271eed0d7cf 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1222,7 +1222,7 @@ static void skl_cdclk_uninit_hw(struct drm_i915_private *dev_priv)
static bool has_cdclk_squasher(struct drm_i915_private *i915)
{
- return IS_DG2(i915);
+ return DISPLAY_VER(i915) >= 14 || IS_DG2(i915);
}
struct intel_cdclk_vals {
@@ -1350,6 +1350,16 @@ static const struct intel_cdclk_vals dg2_cdclk_table[] = {
{}
};
+static const struct intel_cdclk_vals mtl_cdclk_table[] = {
+ { .refclk = 38400, .cdclk = 172800, .divider = 2, .ratio = 16, .waveform = 0xad5a },
+ { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 16, .waveform = 0xb6b6 },
+ { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16, .waveform = 0x0000 },
+ { .refclk = 38400, .cdclk = 480000, .divider = 2, .ratio = 25, .waveform = 0x0000 },
+ { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29, .waveform = 0x0000 },
+ { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34, .waveform = 0x0000 },
+ {}
+};
+
static int bxt_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk)
{
const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table;
@@ -1479,6 +1489,76 @@ static void bxt_de_pll_readout(struct drm_i915_private *dev_priv,
cdclk_config->vco = ratio * cdclk_config->ref;
}
+static void mtl_get_cdclk(struct drm_i915_private *i915,
+ struct intel_cdclk_config *cdclk_config)
+{
+ const struct intel_cdclk_vals *table = i915->display.cdclk.table;
+ u32 squash_ctl, divider, waveform;
+ int div, i, ratio;
+
+ bxt_de_pll_readout(i915, cdclk_config);
+
+ cdclk_config->bypass = cdclk_config->ref / 2;
+
+ if (cdclk_config->vco == 0) {
+ cdclk_config->cdclk = cdclk_config->bypass;
+ goto out;
+ }
+
+ divider = intel_de_read(i915, CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
+ switch (divider) {
+ case BXT_CDCLK_CD2X_DIV_SEL_1:
+ div = 2;
+ break;
+ case BXT_CDCLK_CD2X_DIV_SEL_1_5:
+ div = 3;
+ break;
+ case BXT_CDCLK_CD2X_DIV_SEL_2:
+ div = 4;
+ break;
+ case BXT_CDCLK_CD2X_DIV_SEL_4:
+ div = 8;
+ break;
+ default:
+ MISSING_CASE(divider);
+ return;
+ }
+
+ squash_ctl = intel_de_read(i915, CDCLK_SQUASH_CTL);
+ if (squash_ctl & CDCLK_SQUASH_ENABLE)
+ waveform = squash_ctl & CDCLK_SQUASH_WAVEFORM_MASK;
+ else
+ waveform = 0;
+
+ ratio = cdclk_config->vco / cdclk_config->ref;
+
+ for (i = 0, cdclk_config->cdclk = 0; table[i].refclk; i++) {
+ if (table[i].refclk != cdclk_config->ref)
+ continue;
+
+ if (table[i].divider != div)
+ continue;
+
+ if (table[i].waveform != waveform)
+ continue;
+
+ if (table[i].ratio != ratio)
+ continue;
+
+ cdclk_config->cdclk = table[i].cdclk;
+ break;
+ }
+
+out:
+ /*
+ * Can't read this out :( Let's assume it's
+ * at least what the CDCLK frequency requires.
+ */
+ cdclk_config->voltage_level =
+ intel_cdclk_calc_voltage_level(i915, cdclk_config->cdclk);
+}
+
+
static void bxt_get_cdclk(struct drm_i915_private *dev_priv,
struct intel_cdclk_config *cdclk_config)
{
@@ -3138,6 +3218,13 @@ u32 intel_read_rawclk(struct drm_i915_private *dev_priv)
return freq;
}
+static const struct intel_cdclk_funcs mtl_cdclk_funcs = {
+ .get_cdclk = mtl_get_cdclk,
+ .set_cdclk = bxt_set_cdclk,
+ .modeset_calc_cdclk = bxt_modeset_calc_cdclk,
+ .calc_voltage_level = tgl_calc_voltage_level,
+};
+
static const struct intel_cdclk_funcs tgl_cdclk_funcs = {
.get_cdclk = bxt_get_cdclk,
.set_cdclk = bxt_set_cdclk,
@@ -3273,7 +3360,11 @@ static const struct intel_cdclk_funcs i830_cdclk_funcs = {
*/
void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
{
- if (IS_DG2(dev_priv)) {
+
+ if (IS_METEORLAKE(dev_priv)) {
+ dev_priv->display.funcs.cdclk = &mtl_cdclk_funcs;
+ dev_priv->display.cdclk.table = mtl_cdclk_table;
+ } else if (IS_DG2(dev_priv)) {
dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
dev_priv->display.cdclk.table = dg2_cdclk_table;
} else if (IS_ALDERLAKE_P(dev_priv)) {
--
2.25.1
^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [Intel-gfx] [PATCH 2/2] drm/i915/display: Add CDCLK Support for MTL
2022-09-28 19:04 ` [Intel-gfx] [PATCH 2/2] drm/i915/display: Add CDCLK Support for MTL Anusha Srivatsa
@ 2022-09-28 19:23 ` Ville Syrjälä
2022-09-28 21:16 ` Srivatsa, Anusha
0 siblings, 1 reply; 15+ messages in thread
From: Ville Syrjälä @ 2022-09-28 19:23 UTC (permalink / raw)
To: Anusha Srivatsa; +Cc: intel-gfx
On Wed, Sep 28, 2022 at 12:04:15PM -0700, Anusha Srivatsa wrote:
> As per bSpec MTL has 38.4 MHz Reference clock.
> MTL does support squasher like DG2 but only for lower
> frequencies. Change the has_cdclk_squasher()
> helper to reflect this.
>
> bxt_get_cdclk() is not properly calculating HW clock for MTL,
> because the squash formula is only prepared for DG2.
> Apart from adding the cdclk table, align cdclk support with the
> new cdclk_crawl_and_squash() introduced in previous patch.
>
> BSpec: 65243
> Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 95 +++++++++++++++++++++-
> 1 file changed, 93 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index f7bc1013b149..6271eed0d7cf 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -1222,7 +1222,7 @@ static void skl_cdclk_uninit_hw(struct drm_i915_private *dev_priv)
>
> static bool has_cdclk_squasher(struct drm_i915_private *i915)
> {
> - return IS_DG2(i915);
> + return DISPLAY_VER(i915) >= 14 || IS_DG2(i915);
> }
>
> struct intel_cdclk_vals {
> @@ -1350,6 +1350,16 @@ static const struct intel_cdclk_vals dg2_cdclk_table[] = {
> {}
> };
>
> +static const struct intel_cdclk_vals mtl_cdclk_table[] = {
> + { .refclk = 38400, .cdclk = 172800, .divider = 2, .ratio = 16, .waveform = 0xad5a },
> + { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 16, .waveform = 0xb6b6 },
> + { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16, .waveform = 0x0000 },
> + { .refclk = 38400, .cdclk = 480000, .divider = 2, .ratio = 25, .waveform = 0x0000 },
> + { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29, .waveform = 0x0000 },
> + { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34, .waveform = 0x0000 },
> + {}
> +};
> +
> static int bxt_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk)
> {
> const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table;
> @@ -1479,6 +1489,76 @@ static void bxt_de_pll_readout(struct drm_i915_private *dev_priv,
> cdclk_config->vco = ratio * cdclk_config->ref;
> }
>
> +static void mtl_get_cdclk(struct drm_i915_private *i915,
> + struct intel_cdclk_config *cdclk_config)
> +{
> + const struct intel_cdclk_vals *table = i915->display.cdclk.table;
> + u32 squash_ctl, divider, waveform;
> + int div, i, ratio;
> +
> + bxt_de_pll_readout(i915, cdclk_config);
> +
> + cdclk_config->bypass = cdclk_config->ref / 2;
> +
> + if (cdclk_config->vco == 0) {
> + cdclk_config->cdclk = cdclk_config->bypass;
> + goto out;
> + }
> +
> + divider = intel_de_read(i915, CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
> + switch (divider) {
> + case BXT_CDCLK_CD2X_DIV_SEL_1:
> + div = 2;
> + break;
> + case BXT_CDCLK_CD2X_DIV_SEL_1_5:
> + div = 3;
> + break;
> + case BXT_CDCLK_CD2X_DIV_SEL_2:
> + div = 4;
> + break;
> + case BXT_CDCLK_CD2X_DIV_SEL_4:
> + div = 8;
> + break;
> + default:
> + MISSING_CASE(divider);
> + return;
> + }
> +
> + squash_ctl = intel_de_read(i915, CDCLK_SQUASH_CTL);
> + if (squash_ctl & CDCLK_SQUASH_ENABLE)
> + waveform = squash_ctl & CDCLK_SQUASH_WAVEFORM_MASK;
> + else
> + waveform = 0;
> +
> + ratio = cdclk_config->vco / cdclk_config->ref;
> +
> + for (i = 0, cdclk_config->cdclk = 0; table[i].refclk; i++) {
> + if (table[i].refclk != cdclk_config->ref)
> + continue;
> +
> + if (table[i].divider != div)
> + continue;
> +
> + if (table[i].waveform != waveform)
> + continue;
> +
> + if (table[i].ratio != ratio)
> + continue;
> +
> + cdclk_config->cdclk = table[i].cdclk;
> + break;
> + }
NAK. Readout must not depend on these tables. Otherwise it's not
proper readout and bugs can slip through. What is the supposed problem
with the already existing code?
> +out:
> + /*
> + * Can't read this out :( Let's assume it's
> + * at least what the CDCLK frequency requires.
> + */
> + cdclk_config->voltage_level =
> + intel_cdclk_calc_voltage_level(i915, cdclk_config->cdclk);
> +}
> +
> +
> static void bxt_get_cdclk(struct drm_i915_private *dev_priv,
> struct intel_cdclk_config *cdclk_config)
> {
> @@ -3138,6 +3218,13 @@ u32 intel_read_rawclk(struct drm_i915_private *dev_priv)
> return freq;
> }
>
> +static const struct intel_cdclk_funcs mtl_cdclk_funcs = {
> + .get_cdclk = mtl_get_cdclk,
> + .set_cdclk = bxt_set_cdclk,
> + .modeset_calc_cdclk = bxt_modeset_calc_cdclk,
> + .calc_voltage_level = tgl_calc_voltage_level,
> +};
> +
> static const struct intel_cdclk_funcs tgl_cdclk_funcs = {
> .get_cdclk = bxt_get_cdclk,
> .set_cdclk = bxt_set_cdclk,
> @@ -3273,7 +3360,11 @@ static const struct intel_cdclk_funcs i830_cdclk_funcs = {
> */
> void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
> {
> - if (IS_DG2(dev_priv)) {
> +
> + if (IS_METEORLAKE(dev_priv)) {
> + dev_priv->display.funcs.cdclk = &mtl_cdclk_funcs;
> + dev_priv->display.cdclk.table = mtl_cdclk_table;
> + } else if (IS_DG2(dev_priv)) {
> dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
> dev_priv->display.cdclk.table = dg2_cdclk_table;
> } else if (IS_ALDERLAKE_P(dev_priv)) {
> --
> 2.25.1
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [Intel-gfx] [PATCH 2/2] drm/i915/display: Add CDCLK Support for MTL
2022-09-28 19:23 ` Ville Syrjälä
@ 2022-09-28 21:16 ` Srivatsa, Anusha
0 siblings, 0 replies; 15+ messages in thread
From: Srivatsa, Anusha @ 2022-09-28 21:16 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx@lists.freedesktop.org
> -----Original Message-----
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Sent: Wednesday, September 28, 2022 12:24 PM
> To: Srivatsa, Anusha <anusha.srivatsa@intel.com>
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH 2/2] drm/i915/display: Add CDCLK Support for
> MTL
>
> On Wed, Sep 28, 2022 at 12:04:15PM -0700, Anusha Srivatsa wrote:
> > As per bSpec MTL has 38.4 MHz Reference clock.
> > MTL does support squasher like DG2 but only for lower frequencies.
> > Change the has_cdclk_squasher() helper to reflect this.
> >
> > bxt_get_cdclk() is not properly calculating HW clock for MTL, because
> > the squash formula is only prepared for DG2.
> > Apart from adding the cdclk table, align cdclk support with the new
> > cdclk_crawl_and_squash() introduced in previous patch.
> >
> > BSpec: 65243
> > Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> > Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_cdclk.c | 95
> > +++++++++++++++++++++-
> > 1 file changed, 93 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
> > b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > index f7bc1013b149..6271eed0d7cf 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > @@ -1222,7 +1222,7 @@ static void skl_cdclk_uninit_hw(struct
> > drm_i915_private *dev_priv)
> >
> > static bool has_cdclk_squasher(struct drm_i915_private *i915) {
> > - return IS_DG2(i915);
> > + return DISPLAY_VER(i915) >= 14 || IS_DG2(i915);
> > }
> >
> > struct intel_cdclk_vals {
> > @@ -1350,6 +1350,16 @@ static const struct intel_cdclk_vals
> dg2_cdclk_table[] = {
> > {}
> > };
> >
> > +static const struct intel_cdclk_vals mtl_cdclk_table[] = {
> > + { .refclk = 38400, .cdclk = 172800, .divider = 2, .ratio = 16, .waveform
> = 0xad5a },
> > + { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 16, .waveform
> = 0xb6b6 },
> > + { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16, .waveform
> = 0x0000 },
> > + { .refclk = 38400, .cdclk = 480000, .divider = 2, .ratio = 25, .waveform
> = 0x0000 },
> > + { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29, .waveform
> = 0x0000 },
> > + { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34, .waveform
> = 0x0000 },
> > + {}
> > +};
> > +
> > static int bxt_calc_cdclk(struct drm_i915_private *dev_priv, int
> > min_cdclk) {
> > const struct intel_cdclk_vals *table =
> > dev_priv->display.cdclk.table; @@ -1479,6 +1489,76 @@ static void
> bxt_de_pll_readout(struct drm_i915_private *dev_priv,
> > cdclk_config->vco = ratio * cdclk_config->ref; }
> >
> > +static void mtl_get_cdclk(struct drm_i915_private *i915,
> > + struct intel_cdclk_config *cdclk_config) {
> > + const struct intel_cdclk_vals *table = i915->display.cdclk.table;
> > + u32 squash_ctl, divider, waveform;
> > + int div, i, ratio;
> > +
> > + bxt_de_pll_readout(i915, cdclk_config);
> > +
> > + cdclk_config->bypass = cdclk_config->ref / 2;
> > +
> > + if (cdclk_config->vco == 0) {
> > + cdclk_config->cdclk = cdclk_config->bypass;
> > + goto out;
> > + }
> > +
> > + divider = intel_de_read(i915, CDCLK_CTL) &
> BXT_CDCLK_CD2X_DIV_SEL_MASK;
> > + switch (divider) {
> > + case BXT_CDCLK_CD2X_DIV_SEL_1:
> > + div = 2;
> > + break;
> > + case BXT_CDCLK_CD2X_DIV_SEL_1_5:
> > + div = 3;
> > + break;
> > + case BXT_CDCLK_CD2X_DIV_SEL_2:
> > + div = 4;
> > + break;
> > + case BXT_CDCLK_CD2X_DIV_SEL_4:
> > + div = 8;
> > + break;
> > + default:
> > + MISSING_CASE(divider);
> > + return;
> > + }
> > +
> > + squash_ctl = intel_de_read(i915, CDCLK_SQUASH_CTL);
> > + if (squash_ctl & CDCLK_SQUASH_ENABLE)
> > + waveform = squash_ctl &
> CDCLK_SQUASH_WAVEFORM_MASK;
> > + else
> > + waveform = 0;
> > +
> > + ratio = cdclk_config->vco / cdclk_config->ref;
> > +
> > + for (i = 0, cdclk_config->cdclk = 0; table[i].refclk; i++) {
> > + if (table[i].refclk != cdclk_config->ref)
> > + continue;
> > +
> > + if (table[i].divider != div)
> > + continue;
> > +
> > + if (table[i].waveform != waveform)
> > + continue;
> > +
> > + if (table[i].ratio != ratio)
> > + continue;
> > +
> > + cdclk_config->cdclk = table[i].cdclk;
> > + break;
> > + }
>
> NAK. Readout must not depend on these tables. Otherwise it's not proper
> readout and bugs can slip through. What is the supposed problem with the
> already existing code?
IIRC we were getting wrong values with the existing mathematical calculations for cdclk. This way we force to pick an entry from the table.
Anusha
> > +out:
> > + /*
> > + * Can't read this out :( Let's assume it's
> > + * at least what the CDCLK frequency requires.
> > + */
> > + cdclk_config->voltage_level =
> > + intel_cdclk_calc_voltage_level(i915, cdclk_config->cdclk); }
> > +
> > +
> > static void bxt_get_cdclk(struct drm_i915_private *dev_priv,
> > struct intel_cdclk_config *cdclk_config) { @@ -
> 3138,6 +3218,13
> > @@ u32 intel_read_rawclk(struct drm_i915_private *dev_priv)
> > return freq;
> > }
> >
> > +static const struct intel_cdclk_funcs mtl_cdclk_funcs = {
> > + .get_cdclk = mtl_get_cdclk,
> > + .set_cdclk = bxt_set_cdclk,
> > + .modeset_calc_cdclk = bxt_modeset_calc_cdclk,
> > + .calc_voltage_level = tgl_calc_voltage_level, };
> > +
> > static const struct intel_cdclk_funcs tgl_cdclk_funcs = {
> > .get_cdclk = bxt_get_cdclk,
> > .set_cdclk = bxt_set_cdclk,
> > @@ -3273,7 +3360,11 @@ static const struct intel_cdclk_funcs
> i830_cdclk_funcs = {
> > */
> > void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv) {
> > - if (IS_DG2(dev_priv)) {
> > +
> > + if (IS_METEORLAKE(dev_priv)) {
> > + dev_priv->display.funcs.cdclk = &mtl_cdclk_funcs;
> > + dev_priv->display.cdclk.table = mtl_cdclk_table;
> > + } else if (IS_DG2(dev_priv)) {
> > dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
> > dev_priv->display.cdclk.table = dg2_cdclk_table;
> > } else if (IS_ALDERLAKE_P(dev_priv)) {
> > --
> > 2.25.1
>
> --
> Ville Syrjälä
> Intel
^ permalink raw reply [flat|nested] 15+ messages in thread
* [Intel-gfx] [PATCH 2/2] drm/i915/display: Add CDCLK Support for MTL
2022-09-30 21:34 [Intel-gfx] [PATCH 1/2] drm/i915/display: Do both crawl and squash when changing cdclk Anusha Srivatsa
@ 2022-09-30 21:34 ` Anusha Srivatsa
0 siblings, 0 replies; 15+ messages in thread
From: Anusha Srivatsa @ 2022-09-30 21:34 UTC (permalink / raw)
To: intel-gfx
As per bSpec MTL has 38.4 MHz Reference clock.
MTL does support squasher like DG2 but only for lower
frequencies. Change the has_cdclk_squasher()
helper to reflect this.
v2: Revert to using bxt_get_cdclk()
BSpec: 65243
Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 25 ++++++++++++++++++++--
1 file changed, 23 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index f7bc1013b149..b467aade750a 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1222,7 +1222,7 @@ static void skl_cdclk_uninit_hw(struct drm_i915_private *dev_priv)
static bool has_cdclk_squasher(struct drm_i915_private *i915)
{
- return IS_DG2(i915);
+ return DISPLAY_VER(i915) >= 14 || IS_DG2(i915);
}
struct intel_cdclk_vals {
@@ -1350,6 +1350,16 @@ static const struct intel_cdclk_vals dg2_cdclk_table[] = {
{}
};
+static const struct intel_cdclk_vals mtl_cdclk_table[] = {
+ { .refclk = 38400, .cdclk = 172800, .divider = 2, .ratio = 16, .waveform = 0xad5a },
+ { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 16, .waveform = 0xb6b6 },
+ { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16, .waveform = 0x0000 },
+ { .refclk = 38400, .cdclk = 480000, .divider = 2, .ratio = 25, .waveform = 0x0000 },
+ { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29, .waveform = 0x0000 },
+ { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34, .waveform = 0x0000 },
+ {}
+};
+
static int bxt_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk)
{
const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table;
@@ -3138,6 +3148,13 @@ u32 intel_read_rawclk(struct drm_i915_private *dev_priv)
return freq;
}
+static const struct intel_cdclk_funcs mtl_cdclk_funcs = {
+ .get_cdclk = bxt_get_cdclk,
+ .set_cdclk = bxt_set_cdclk,
+ .modeset_calc_cdclk = bxt_modeset_calc_cdclk,
+ .calc_voltage_level = tgl_calc_voltage_level,
+};
+
static const struct intel_cdclk_funcs tgl_cdclk_funcs = {
.get_cdclk = bxt_get_cdclk,
.set_cdclk = bxt_set_cdclk,
@@ -3273,7 +3290,11 @@ static const struct intel_cdclk_funcs i830_cdclk_funcs = {
*/
void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
{
- if (IS_DG2(dev_priv)) {
+
+ if (IS_METEORLAKE(dev_priv)) {
+ dev_priv->display.funcs.cdclk = &mtl_cdclk_funcs;
+ dev_priv->display.cdclk.table = mtl_cdclk_table;
+ } else if (IS_DG2(dev_priv)) {
dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
dev_priv->display.cdclk.table = dg2_cdclk_table;
} else if (IS_ALDERLAKE_P(dev_priv)) {
--
2.25.1
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [Intel-gfx] [PATCH 2/2] drm/i915/display: Add CDCLK Support for MTL
2022-10-13 23:32 [Intel-gfx] [PATCH 1/2] drm/i915/display: Do both crawl and squash when changing cdclk Anusha Srivatsa
@ 2022-10-13 23:32 ` Anusha Srivatsa
0 siblings, 0 replies; 15+ messages in thread
From: Anusha Srivatsa @ 2022-10-13 23:32 UTC (permalink / raw)
To: intel-gfx
As per bSpec MTL has 38.4 MHz Reference clock.
MTL does support squasher like DG2 but only for lower
frequencies. Change the has_cdclk_squasher()
helper to reflect this.
v2: Revert to using bxt_get_cdclk()
BSpec: 65243
Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 24 ++++++++++++++++++++--
1 file changed, 22 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 430b4cb0a8ab..f44cffeb1f94 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1222,7 +1222,7 @@ static void skl_cdclk_uninit_hw(struct drm_i915_private *dev_priv)
static bool has_cdclk_squasher(struct drm_i915_private *i915)
{
- return IS_DG2(i915);
+ return DISPLAY_VER(i915) >= 14 || IS_DG2(i915);
}
struct intel_cdclk_vals {
@@ -1350,6 +1350,16 @@ static const struct intel_cdclk_vals dg2_cdclk_table[] = {
{}
};
+static const struct intel_cdclk_vals mtl_cdclk_table[] = {
+ { .refclk = 38400, .cdclk = 172800, .divider = 2, .ratio = 16, .waveform = 0xad5a },
+ { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 16, .waveform = 0xb6b6 },
+ { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16, .waveform = 0x0000 },
+ { .refclk = 38400, .cdclk = 480000, .divider = 2, .ratio = 25, .waveform = 0x0000 },
+ { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29, .waveform = 0x0000 },
+ { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34, .waveform = 0x0000 },
+ {}
+};
+
static int bxt_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk)
{
const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table;
@@ -3149,6 +3159,13 @@ u32 intel_read_rawclk(struct drm_i915_private *dev_priv)
return freq;
}
+static const struct intel_cdclk_funcs mtl_cdclk_funcs = {
+ .get_cdclk = bxt_get_cdclk,
+ .set_cdclk = bxt_set_cdclk,
+ .modeset_calc_cdclk = bxt_modeset_calc_cdclk,
+ .calc_voltage_level = tgl_calc_voltage_level,
+};
+
static const struct intel_cdclk_funcs tgl_cdclk_funcs = {
.get_cdclk = bxt_get_cdclk,
.set_cdclk = bxt_set_cdclk,
@@ -3284,7 +3301,10 @@ static const struct intel_cdclk_funcs i830_cdclk_funcs = {
*/
void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
{
- if (IS_DG2(dev_priv)) {
+ if (IS_METEORLAKE(dev_priv)) {
+ dev_priv->display.funcs.cdclk = &mtl_cdclk_funcs;
+ dev_priv->display.cdclk.table = mtl_cdclk_table;
+ } else if (IS_DG2(dev_priv)) {
dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
dev_priv->display.cdclk.table = dg2_cdclk_table;
} else if (IS_ALDERLAKE_P(dev_priv)) {
--
2.25.1
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [Intel-gfx] [PATCH 2/2] drm/i915/display: Add CDCLK Support for MTL
2022-10-26 23:22 [Intel-gfx] [PATCH 1/2] drm/i915/display: Do both crawl and squash when changing cdclk Anusha Srivatsa
@ 2022-10-26 23:22 ` Anusha Srivatsa
0 siblings, 0 replies; 15+ messages in thread
From: Anusha Srivatsa @ 2022-10-26 23:22 UTC (permalink / raw)
To: intel-gfx
As per bSpec MTL has 38.4 MHz Reference clock.
MTL does support squasher like DG2 but only for lower
frequencies. Change the has_cdclk_squasher()
helper to reflect this.
v2: Revert to using bxt_get_cdclk()
BSpec: 65243
Cc: Clint Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 22 +++++++++++++++++++++-
1 file changed, 21 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 6a775367f02a..28253cb310ca 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1345,6 +1345,16 @@ static const struct intel_cdclk_vals dg2_cdclk_table[] = {
{}
};
+static const struct intel_cdclk_vals mtl_cdclk_table[] = {
+ { .refclk = 38400, .cdclk = 172800, .divider = 2, .ratio = 16, .waveform = 0xad5a },
+ { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 16, .waveform = 0xb6b6 },
+ { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16, .waveform = 0x0000 },
+ { .refclk = 38400, .cdclk = 480000, .divider = 2, .ratio = 25, .waveform = 0x0000 },
+ { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29, .waveform = 0x0000 },
+ { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34, .waveform = 0x0000 },
+ {}
+};
+
static int bxt_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk)
{
const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table;
@@ -3160,6 +3170,13 @@ u32 intel_read_rawclk(struct drm_i915_private *dev_priv)
return freq;
}
+static const struct intel_cdclk_funcs mtl_cdclk_funcs = {
+ .get_cdclk = bxt_get_cdclk,
+ .set_cdclk = bxt_set_cdclk,
+ .modeset_calc_cdclk = bxt_modeset_calc_cdclk,
+ .calc_voltage_level = tgl_calc_voltage_level,
+};
+
static const struct intel_cdclk_funcs tgl_cdclk_funcs = {
.get_cdclk = bxt_get_cdclk,
.set_cdclk = bxt_set_cdclk,
@@ -3295,7 +3312,10 @@ static const struct intel_cdclk_funcs i830_cdclk_funcs = {
*/
void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
{
- if (IS_DG2(dev_priv)) {
+ if (IS_METEORLAKE(dev_priv)) {
+ dev_priv->display.funcs.cdclk = &mtl_cdclk_funcs;
+ dev_priv->display.cdclk.table = mtl_cdclk_table;
+ } else if (IS_DG2(dev_priv)) {
dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
dev_priv->display.cdclk.table = dg2_cdclk_table;
} else if (IS_ALDERLAKE_P(dev_priv)) {
--
2.25.1
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [Intel-gfx] [PATCH 2/2] drm/i915/display: Add CDCLK Support for MTL
2022-10-28 21:32 [Intel-gfx] [PATCH 1/2] drm/i915/display: Do both crawl and squash when changing cdclk Anusha Srivatsa
@ 2022-10-28 21:32 ` Anusha Srivatsa
2022-10-31 17:58 ` Taylor, Clinton A
0 siblings, 1 reply; 15+ messages in thread
From: Anusha Srivatsa @ 2022-10-28 21:32 UTC (permalink / raw)
To: intel-gfx
As per bSpec MTL has 38.4 MHz Reference clock.
Addin gthe cdclk tables and cdclk_funcs that MTL
will use.
v2: Revert to using bxt_get_cdclk()
BSpec: 65243
Cc: Clint Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 22 +++++++++++++++++++++-
1 file changed, 21 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index d79cf282faa8..54ac7f9a1253 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1345,6 +1345,16 @@ static const struct intel_cdclk_vals dg2_cdclk_table[] = {
{}
};
+static const struct intel_cdclk_vals mtl_cdclk_table[] = {
+ { .refclk = 38400, .cdclk = 172800, .divider = 2, .ratio = 16, .waveform = 0xad5a },
+ { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 16, .waveform = 0xb6b6 },
+ { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16, .waveform = 0x0000 },
+ { .refclk = 38400, .cdclk = 480000, .divider = 2, .ratio = 25, .waveform = 0x0000 },
+ { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29, .waveform = 0x0000 },
+ { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34, .waveform = 0x0000 },
+ {}
+};
+
static int bxt_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk)
{
const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table;
@@ -3159,6 +3169,13 @@ u32 intel_read_rawclk(struct drm_i915_private *dev_priv)
return freq;
}
+static const struct intel_cdclk_funcs mtl_cdclk_funcs = {
+ .get_cdclk = bxt_get_cdclk,
+ .set_cdclk = bxt_set_cdclk,
+ .modeset_calc_cdclk = bxt_modeset_calc_cdclk,
+ .calc_voltage_level = tgl_calc_voltage_level,
+};
+
static const struct intel_cdclk_funcs tgl_cdclk_funcs = {
.get_cdclk = bxt_get_cdclk,
.set_cdclk = bxt_set_cdclk,
@@ -3294,7 +3311,10 @@ static const struct intel_cdclk_funcs i830_cdclk_funcs = {
*/
void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
{
- if (IS_DG2(dev_priv)) {
+ if (IS_METEORLAKE(dev_priv)) {
+ dev_priv->display.funcs.cdclk = &mtl_cdclk_funcs;
+ dev_priv->display.cdclk.table = mtl_cdclk_table;
+ } else if (IS_DG2(dev_priv)) {
dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
dev_priv->display.cdclk.table = dg2_cdclk_table;
} else if (IS_ALDERLAKE_P(dev_priv)) {
--
2.25.1
^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [Intel-gfx] [PATCH 2/2] drm/i915/display: Add CDCLK Support for MTL
2022-10-28 21:32 ` [Intel-gfx] [PATCH 2/2] drm/i915/display: Add CDCLK Support for MTL Anusha Srivatsa
@ 2022-10-31 17:58 ` Taylor, Clinton A
0 siblings, 0 replies; 15+ messages in thread
From: Taylor, Clinton A @ 2022-10-31 17:58 UTC (permalink / raw)
To: Srivatsa, Anusha, intel-gfx@lists.freedesktop.org
See below
-----Original Message-----
From: Srivatsa, Anusha <anusha.srivatsa@intel.com>
Sent: Friday, October 28, 2022 2:32 PM
To: intel-gfx@lists.freedesktop.org
Cc: Srivatsa, Anusha <anusha.srivatsa@intel.com>; Taylor, Clinton A <clinton.a.taylor@intel.com>
Subject: [PATCH 2/2] drm/i915/display: Add CDCLK Support for MTL
As per bSpec MTL has 38.4 MHz Reference clock.
Addin gthe cdclk tables and cdclk_funcs that MTL will use.
Spelling issue here. With this fixed
Reviewed-by: Clint Taylor <Clinton.A.Taylor@intel.com>
-Clint
v2: Revert to using bxt_get_cdclk()
BSpec: 65243
Cc: Clint Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 22 +++++++++++++++++++++-
1 file changed, 21 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index d79cf282faa8..54ac7f9a1253 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1345,6 +1345,16 @@ static const struct intel_cdclk_vals dg2_cdclk_table[] = {
{}
};
+static const struct intel_cdclk_vals mtl_cdclk_table[] = {
+ { .refclk = 38400, .cdclk = 172800, .divider = 2, .ratio = 16, .waveform = 0xad5a },
+ { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 16, .waveform = 0xb6b6 },
+ { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16, .waveform = 0x0000 },
+ { .refclk = 38400, .cdclk = 480000, .divider = 2, .ratio = 25, .waveform = 0x0000 },
+ { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29, .waveform = 0x0000 },
+ { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34, .waveform = 0x0000 },
+ {}
+};
+
static int bxt_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk) {
const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table; @@ -3159,6 +3169,13 @@ u32 intel_read_rawclk(struct drm_i915_private *dev_priv)
return freq;
}
+static const struct intel_cdclk_funcs mtl_cdclk_funcs = {
+ .get_cdclk = bxt_get_cdclk,
+ .set_cdclk = bxt_set_cdclk,
+ .modeset_calc_cdclk = bxt_modeset_calc_cdclk,
+ .calc_voltage_level = tgl_calc_voltage_level, };
+
static const struct intel_cdclk_funcs tgl_cdclk_funcs = {
.get_cdclk = bxt_get_cdclk,
.set_cdclk = bxt_set_cdclk,
@@ -3294,7 +3311,10 @@ static const struct intel_cdclk_funcs i830_cdclk_funcs = {
*/
void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv) {
- if (IS_DG2(dev_priv)) {
+ if (IS_METEORLAKE(dev_priv)) {
+ dev_priv->display.funcs.cdclk = &mtl_cdclk_funcs;
+ dev_priv->display.cdclk.table = mtl_cdclk_table;
+ } else if (IS_DG2(dev_priv)) {
dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
dev_priv->display.cdclk.table = dg2_cdclk_table;
} else if (IS_ALDERLAKE_P(dev_priv)) {
--
2.25.1
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [Intel-gfx] [PATCH 1/2] drm/i915/display: Do both crawl and squash when changing cdclk
@ 2022-10-31 22:56 Anusha Srivatsa
2022-10-31 22:56 ` [Intel-gfx] [PATCH 2/2] drm/i915/display: Add CDCLK Support for MTL Anusha Srivatsa
` (4 more replies)
0 siblings, 5 replies; 15+ messages in thread
From: Anusha Srivatsa @ 2022-10-31 22:56 UTC (permalink / raw)
To: intel-gfx; +Cc: Balasubramani Vivekanandan
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
For MTL, changing cdclk from between certain frequencies has
both squash and crawl. Use the current cdclk config and
the new(desired) cdclk config to construtc a mid cdclk config.
Set the cdclk twice:
- Current cdclk -> mid cdclk
- mid cdclk -> desired cdclk
v2: Add check in intel_modeset_calc_cdclk() to avoid cdclk
change via modeset for platforms that support squash_crawl sequences(Ville)
v3: Add checks for:
- scenario where only slow clock is used and
cdclk is actually 0 (bringing up display).
- PLLs are on before looking up the waveform.
- Squash and crawl capability checks.(Ville)
v4: Rebase
- Move checks to be more consistent (Ville)
- Add comments (Bala)
v5:
- Further small changes. Move checks around.
- Make if-else better looking (Ville)
Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 156 +++++++++++++++++----
1 file changed, 128 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index eada931cb1c8..d79cf282faa8 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1716,37 +1716,74 @@ static void dg2_cdclk_squash_program(struct drm_i915_private *i915,
intel_de_write(i915, CDCLK_SQUASH_CTL, squash_ctl);
}
-static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
- const struct intel_cdclk_config *cdclk_config,
- enum pipe pipe)
+static int cdclk_squash_divider(u16 waveform)
+{
+ return hweight16(waveform ?: 0xffff);
+}
+
+static bool cdclk_crawl_and_squash(struct drm_i915_private *i915,
+ const struct intel_cdclk_config *old_cdclk_config,
+ const struct intel_cdclk_config *new_cdclk_config,
+ struct intel_cdclk_config *mid_cdclk_config)
+{
+ u16 old_waveform, new_waveform, mid_waveform;
+ int size = 16;
+ int div = 2;
+
+ /* Return if both Squash and Crawl are not present */
+ if (!HAS_CDCLK_CRAWL(i915) || !HAS_CDCLK_SQUASH(i915))
+ return false;
+
+ old_waveform = cdclk_squash_waveform(i915, old_cdclk_config->cdclk);
+ new_waveform = cdclk_squash_waveform(i915, new_cdclk_config->cdclk);
+
+ /* Return if Squash only or Crawl only is the desired action */
+ if (old_cdclk_config->vco <= 0 || new_cdclk_config->vco <= 0 ||
+ old_cdclk_config->vco == new_cdclk_config->vco ||
+ old_waveform == new_waveform)
+ return false;
+
+ *mid_cdclk_config = *new_cdclk_config;
+
+ /* Populate the mid_cdclk_config accordingly.
+ * - If moving to a higher cdclk, the desired action is squashing.
+ * The mid cdclk config should have the new (squash) waveform.
+ * - If moving to a lower cdclk, the desired action is crawling.
+ * The mid cdclk config should have the new vco.
+ */
+
+ if (cdclk_squash_divider(new_waveform) > cdclk_squash_divider(old_waveform)) {
+ mid_cdclk_config->vco = old_cdclk_config->vco;
+ mid_waveform = new_waveform;
+ } else {
+ mid_cdclk_config->vco = new_cdclk_config->vco;
+ mid_waveform = old_waveform;
+ }
+
+ mid_cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_squash_divider(mid_waveform) *
+ mid_cdclk_config->vco, size * div);
+
+ /* make sure the mid clock came out sane */
+
+ drm_WARN_ON(&i915->drm, mid_cdclk_config->cdclk <
+ min(old_cdclk_config->cdclk, new_cdclk_config->cdclk));
+ drm_WARN_ON(&i915->drm, mid_cdclk_config->cdclk >
+ i915->display.cdclk.max_cdclk_freq);
+ drm_WARN_ON(&i915->drm, cdclk_squash_waveform(i915, mid_cdclk_config->cdclk) !=
+ mid_waveform);
+
+ return true;
+}
+
+static void _bxt_set_cdclk(struct drm_i915_private *dev_priv,
+ const struct intel_cdclk_config *cdclk_config,
+ enum pipe pipe)
{
int cdclk = cdclk_config->cdclk;
int vco = cdclk_config->vco;
u32 val;
u16 waveform;
int clock;
- int ret;
-
- /* Inform power controller of upcoming frequency change. */
- if (DISPLAY_VER(dev_priv) >= 11)
- ret = skl_pcode_request(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL,
- SKL_CDCLK_PREPARE_FOR_CHANGE,
- SKL_CDCLK_READY_FOR_CHANGE,
- SKL_CDCLK_READY_FOR_CHANGE, 3);
- else
- /*
- * BSpec requires us to wait up to 150usec, but that leads to
- * timeouts; the 2ms used here is based on experiment.
- */
- ret = snb_pcode_write_timeout(&dev_priv->uncore,
- HSW_PCODE_DE_WRITE_FREQ_REQ,
- 0x80000000, 150, 2);
- if (ret) {
- drm_err(&dev_priv->drm,
- "Failed to inform PCU about cdclk change (err %d, freq %d)\n",
- ret, cdclk);
- return;
- }
if (HAS_CDCLK_CRAWL(dev_priv) && dev_priv->display.cdclk.hw.vco > 0 && vco > 0) {
if (dev_priv->display.cdclk.hw.vco != vco)
@@ -1781,6 +1818,44 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
if (pipe != INVALID_PIPE)
intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(dev_priv, pipe));
+}
+
+static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
+ const struct intel_cdclk_config *cdclk_config,
+ enum pipe pipe)
+{
+ struct intel_cdclk_config mid_cdclk_config;
+ int cdclk = cdclk_config->cdclk;
+ int ret;
+
+ /* Inform power controller of upcoming frequency change. */
+ if (DISPLAY_VER(dev_priv) >= 11)
+ ret = skl_pcode_request(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL,
+ SKL_CDCLK_PREPARE_FOR_CHANGE,
+ SKL_CDCLK_READY_FOR_CHANGE,
+ SKL_CDCLK_READY_FOR_CHANGE, 3);
+ else
+ /*
+ * BSpec requires us to wait up to 150usec, but that leads to
+ * timeouts; the 2ms used here is based on experiment.
+ */
+ ret = snb_pcode_write_timeout(&dev_priv->uncore,
+ HSW_PCODE_DE_WRITE_FREQ_REQ,
+ 0x80000000, 150, 2);
+ if (ret) {
+ drm_err(&dev_priv->drm,
+ "Failed to inform PCU about cdclk change (err %d, freq %d)\n",
+ ret, cdclk);
+ return;
+ }
+
+ if (cdclk_crawl_and_squash(dev_priv, &dev_priv->display.cdclk.hw,
+ cdclk_config, &mid_cdclk_config)) {
+ _bxt_set_cdclk(dev_priv, &mid_cdclk_config, pipe);
+ _bxt_set_cdclk(dev_priv, cdclk_config, pipe);
+ } else {
+ _bxt_set_cdclk(dev_priv, cdclk_config, pipe);
+ }
if (DISPLAY_VER(dev_priv) >= 11) {
ret = snb_pcode_write(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL,
@@ -1953,6 +2028,26 @@ void intel_cdclk_uninit_hw(struct drm_i915_private *i915)
skl_cdclk_uninit_hw(i915);
}
+static bool intel_cdclk_can_crawl_and_squash(struct drm_i915_private *i915,
+ const struct intel_cdclk_config *a,
+ const struct intel_cdclk_config *b)
+{
+ u16 old_waveform;
+ u16 new_waveform;
+
+ if (a->vco == 0 || b->vco == 0)
+ return false;
+
+ if (!HAS_CDCLK_CRAWL(i915) && !HAS_CDCLK_SQUASH(i915))
+ return false;
+
+ old_waveform = cdclk_squash_waveform(i915, a->cdclk);
+ new_waveform = cdclk_squash_waveform(i915, b->cdclk);
+
+ return a->vco != b->vco &&
+ old_waveform != new_waveform;
+}
+
static bool intel_cdclk_can_crawl(struct drm_i915_private *dev_priv,
const struct intel_cdclk_config *a,
const struct intel_cdclk_config *b)
@@ -2759,9 +2854,14 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state)
pipe = INVALID_PIPE;
}
- if (intel_cdclk_can_squash(dev_priv,
- &old_cdclk_state->actual,
- &new_cdclk_state->actual)) {
+ if (intel_cdclk_can_crawl_and_squash(dev_priv,
+ &old_cdclk_state->actual,
+ &new_cdclk_state->actual)) {
+ drm_dbg_kms(&dev_priv->drm,
+ "Can change cdclk via crawling and squashing\n");
+ } else if (intel_cdclk_can_squash(dev_priv,
+ &old_cdclk_state->actual,
+ &new_cdclk_state->actual)) {
drm_dbg_kms(&dev_priv->drm,
"Can change cdclk via squashing\n");
} else if (intel_cdclk_can_crawl(dev_priv,
--
2.25.1
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [Intel-gfx] [PATCH 2/2] drm/i915/display: Add CDCLK Support for MTL
2022-10-31 22:56 [Intel-gfx] [PATCH 1/2] drm/i915/display: Do both crawl and squash when changing cdclk Anusha Srivatsa
@ 2022-10-31 22:56 ` Anusha Srivatsa
2022-11-01 0:33 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/display: Do both crawl and squash when changing cdclk Patchwork
` (3 subsequent siblings)
4 siblings, 0 replies; 15+ messages in thread
From: Anusha Srivatsa @ 2022-10-31 22:56 UTC (permalink / raw)
To: intel-gfx
As per bSpec MTL has 38.4 MHz Reference clock.
Adding the cdclk tables and cdclk_funcs that MTL
will use.
v2: Revert to using bxt_get_cdclk()
BSpec: 65243
Cc: Clint Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Reviewed-by: Clint Taylor <Clinton.A.Taylor@intel.com>
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 22 +++++++++++++++++++++-
1 file changed, 21 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index d79cf282faa8..54ac7f9a1253 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1345,6 +1345,16 @@ static const struct intel_cdclk_vals dg2_cdclk_table[] = {
{}
};
+static const struct intel_cdclk_vals mtl_cdclk_table[] = {
+ { .refclk = 38400, .cdclk = 172800, .divider = 2, .ratio = 16, .waveform = 0xad5a },
+ { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 16, .waveform = 0xb6b6 },
+ { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16, .waveform = 0x0000 },
+ { .refclk = 38400, .cdclk = 480000, .divider = 2, .ratio = 25, .waveform = 0x0000 },
+ { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29, .waveform = 0x0000 },
+ { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34, .waveform = 0x0000 },
+ {}
+};
+
static int bxt_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk)
{
const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table;
@@ -3159,6 +3169,13 @@ u32 intel_read_rawclk(struct drm_i915_private *dev_priv)
return freq;
}
+static const struct intel_cdclk_funcs mtl_cdclk_funcs = {
+ .get_cdclk = bxt_get_cdclk,
+ .set_cdclk = bxt_set_cdclk,
+ .modeset_calc_cdclk = bxt_modeset_calc_cdclk,
+ .calc_voltage_level = tgl_calc_voltage_level,
+};
+
static const struct intel_cdclk_funcs tgl_cdclk_funcs = {
.get_cdclk = bxt_get_cdclk,
.set_cdclk = bxt_set_cdclk,
@@ -3294,7 +3311,10 @@ static const struct intel_cdclk_funcs i830_cdclk_funcs = {
*/
void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
{
- if (IS_DG2(dev_priv)) {
+ if (IS_METEORLAKE(dev_priv)) {
+ dev_priv->display.funcs.cdclk = &mtl_cdclk_funcs;
+ dev_priv->display.cdclk.table = mtl_cdclk_table;
+ } else if (IS_DG2(dev_priv)) {
dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
dev_priv->display.cdclk.table = dg2_cdclk_table;
} else if (IS_ALDERLAKE_P(dev_priv)) {
--
2.25.1
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/display: Do both crawl and squash when changing cdclk
2022-10-31 22:56 [Intel-gfx] [PATCH 1/2] drm/i915/display: Do both crawl and squash when changing cdclk Anusha Srivatsa
2022-10-31 22:56 ` [Intel-gfx] [PATCH 2/2] drm/i915/display: Add CDCLK Support for MTL Anusha Srivatsa
@ 2022-11-01 0:33 ` Patchwork
2022-11-01 2:29 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
` (2 subsequent siblings)
4 siblings, 0 replies; 15+ messages in thread
From: Patchwork @ 2022-11-01 0:33 UTC (permalink / raw)
To: Anusha Srivatsa; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 6902 bytes --]
== Series Details ==
Series: series starting with [1/2] drm/i915/display: Do both crawl and squash when changing cdclk
URL : https://patchwork.freedesktop.org/series/110347/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12325 -> Patchwork_110347v1
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/index.html
Participating hosts (40 -> 29)
------------------------------
Additional (1): fi-rkl-11600
Missing (12): fi-cml-u2 bat-dg2-8 bat-adlm-1 bat-dg2-9 bat-adlp-6 bat-adlp-4 bat-adln-1 bat-rplp-1 bat-rpls-1 bat-rpls-2 bat-dg2-11 bat-jsl-1
Known issues
------------
Here are the changes found in Patchwork_110347v1 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_huc_copy@huc-copy:
- fi-rkl-11600: NOTRUN -> [SKIP][1] ([i915#2190])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/fi-rkl-11600/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@parallel-random-engines:
- fi-rkl-11600: NOTRUN -> [SKIP][2] ([i915#4613]) +3 similar issues
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/fi-rkl-11600/igt@gem_lmem_swapping@parallel-random-engines.html
* igt@gem_render_tiled_blits@basic:
- fi-apl-guc: [PASS][3] -> [INCOMPLETE][4] ([i915#7056])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12325/fi-apl-guc/igt@gem_render_tiled_blits@basic.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/fi-apl-guc/igt@gem_render_tiled_blits@basic.html
* igt@gem_tiled_pread_basic:
- fi-rkl-11600: NOTRUN -> [SKIP][5] ([i915#3282])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/fi-rkl-11600/igt@gem_tiled_pread_basic.html
* igt@i915_pm_backlight@basic-brightness:
- fi-rkl-11600: NOTRUN -> [SKIP][6] ([i915#3012])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/fi-rkl-11600/igt@i915_pm_backlight@basic-brightness.html
* igt@i915_suspend@basic-s3-without-i915:
- fi-rkl-11600: NOTRUN -> [INCOMPLETE][7] ([i915#4817])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/fi-rkl-11600/igt@i915_suspend@basic-s3-without-i915.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-rkl-11600: NOTRUN -> [SKIP][8] ([fdo#111827]) +7 similar issues
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/fi-rkl-11600/igt@kms_chamelium@hdmi-hpd-fast.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor:
- fi-rkl-11600: NOTRUN -> [SKIP][9] ([i915#4103])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/fi-rkl-11600/igt@kms_cursor_legacy@basic-busy-flip-before-cursor.html
* igt@kms_force_connector_basic@force-load-detect:
- fi-rkl-11600: NOTRUN -> [SKIP][10] ([fdo#109285] / [i915#4098])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/fi-rkl-11600/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_psr@sprite_plane_onoff:
- fi-rkl-11600: NOTRUN -> [SKIP][11] ([i915#1072]) +3 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/fi-rkl-11600/igt@kms_psr@sprite_plane_onoff.html
* igt@kms_setmode@basic-clone-single-crtc:
- fi-rkl-11600: NOTRUN -> [SKIP][12] ([i915#3555] / [i915#4098])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/fi-rkl-11600/igt@kms_setmode@basic-clone-single-crtc.html
* igt@prime_vgem@basic-read:
- fi-rkl-11600: NOTRUN -> [SKIP][13] ([fdo#109295] / [i915#3291] / [i915#3708]) +2 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/fi-rkl-11600/igt@prime_vgem@basic-read.html
* igt@prime_vgem@basic-userptr:
- fi-rkl-11600: NOTRUN -> [SKIP][14] ([fdo#109295] / [i915#3301] / [i915#3708])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/fi-rkl-11600/igt@prime_vgem@basic-userptr.html
#### Possible fixes ####
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions-varying-size:
- fi-bsw-kefka: [FAIL][15] ([i915#6298]) -> [PASS][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12325/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions-varying-size.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions-varying-size.html
* igt@kms_pipe_crc_basic@suspend-read-crc@pipe-b-hdmi-a-2:
- fi-icl-u2: [DMESG-WARN][17] ([i915#2867]) -> [PASS][18]
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12325/fi-icl-u2/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-b-hdmi-a-2.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/fi-icl-u2/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-b-hdmi-a-2.html
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867
[i915#3012]: https://gitlab.freedesktop.org/drm/intel/issues/3012
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4817]: https://gitlab.freedesktop.org/drm/intel/issues/4817
[i915#6298]: https://gitlab.freedesktop.org/drm/intel/issues/6298
[i915#7056]: https://gitlab.freedesktop.org/drm/intel/issues/7056
Build changes
-------------
* Linux: CI_DRM_12325 -> Patchwork_110347v1
CI-20190529: 20190529
CI_DRM_12325: 1a90222aa5e5bb86ffcbde5ba9611659a23f0df6 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7032: 372c56225e12578a7a4a6bcc5b79eb40b643fcde @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_110347v1: 1a90222aa5e5bb86ffcbde5ba9611659a23f0df6 @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
34c8135ad9e7 drm/i915/display: Add CDCLK Support for MTL
6abe82916883 drm/i915/display: Do both crawl and squash when changing cdclk
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/index.html
[-- Attachment #2: Type: text/html, Size: 8082 bytes --]
^ permalink raw reply [flat|nested] 15+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/2] drm/i915/display: Do both crawl and squash when changing cdclk
2022-10-31 22:56 [Intel-gfx] [PATCH 1/2] drm/i915/display: Do both crawl and squash when changing cdclk Anusha Srivatsa
2022-10-31 22:56 ` [Intel-gfx] [PATCH 2/2] drm/i915/display: Add CDCLK Support for MTL Anusha Srivatsa
2022-11-01 0:33 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/display: Do both crawl and squash when changing cdclk Patchwork
@ 2022-11-01 2:29 ` Patchwork
2022-11-01 23:25 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/display: Do both crawl and squash when changing cdclk (rev2) Patchwork
2022-11-02 7:59 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
4 siblings, 0 replies; 15+ messages in thread
From: Patchwork @ 2022-11-01 2:29 UTC (permalink / raw)
To: Anusha Srivatsa; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 35591 bytes --]
== Series Details ==
Series: series starting with [1/2] drm/i915/display: Do both crawl and squash when changing cdclk
URL : https://patchwork.freedesktop.org/series/110347/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12325_full -> Patchwork_110347v1_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_110347v1_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_110347v1_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (11 -> 9)
------------------------------
Missing (2): shard-rkl shard-dg1
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_110347v1_full:
### IGT changes ###
#### Possible regressions ####
* igt@gen9_exec_parse@allowed-single:
- shard-skl: [PASS][1] -> [DMESG-WARN][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12325/shard-skl9/igt@gen9_exec_parse@allowed-single.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/shard-skl10/igt@gen9_exec_parse@allowed-single.html
* igt@kms_async_flips@async-flip-with-page-flip-events@pipe-a-edp-1:
- shard-skl: [PASS][3] -> [FAIL][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12325/shard-skl7/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-a-edp-1.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/shard-skl5/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-a-edp-1.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling@pipe-a-valid-mode:
- shard-iclb: [PASS][5] -> [FAIL][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12325/shard-iclb7/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling@pipe-a-valid-mode.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/shard-iclb6/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling@pipe-a-valid-mode.html
* igt@kms_plane_multiple@tiling-x@pipe-c-edp-1:
- shard-tglb: [PASS][7] -> [INCOMPLETE][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12325/shard-tglb7/igt@kms_plane_multiple@tiling-x@pipe-c-edp-1.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/shard-tglb8/igt@kms_plane_multiple@tiling-x@pipe-c-edp-1.html
Known issues
------------
Here are the changes found in Patchwork_110347v1_full that come from known issues:
### CI changes ###
#### Issues hit ####
* boot:
- shard-glk: ([PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25], [PASS][26], [PASS][27], [PASS][28], [PASS][29], [PASS][30], [PASS][31], [PASS][32], [PASS][33]) -> ([FAIL][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49], [PASS][50], [PASS][51], [PASS][52], [PASS][53], [PASS][54], [PASS][55], [PASS][56], [PASS][57], [PASS][58]) ([i915#4392])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12325/shard-glk9/boot.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12325/shard-glk9/boot.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12325/shard-glk9/boot.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12325/shard-glk9/boot.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12325/shard-glk8/boot.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12325/shard-glk8/boot.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12325/shard-glk8/boot.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12325/shard-glk7/boot.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12325/shard-glk7/boot.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12325/shard-glk7/boot.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12325/shard-glk6/boot.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12325/shard-glk6/boot.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12325/shard-glk6/boot.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12325/shard-glk5/boot.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12325/shard-glk5/boot.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12325/shard-glk5/boot.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12325/shard-glk3/boot.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12325/shard-glk3/boot.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12325/shard-glk3/boot.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12325/shard-glk2/boot.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12325/shard-glk2/boot.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12325/shard-glk2/boot.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12325/shard-glk1/boot.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12325/shard-glk1/boot.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12325/shard-glk1/boot.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/shard-glk1/boot.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/shard-glk1/boot.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/shard-glk1/boot.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/shard-glk1/boot.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/shard-glk2/boot.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/shard-glk2/boot.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/shard-glk2/boot.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/shard-glk3/boot.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/shard-glk3/boot.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/shard-glk3/boot.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/shard-glk5/boot.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/shard-glk5/boot.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/shard-glk5/boot.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/shard-glk6/boot.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/shard-glk6/boot.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/shard-glk6/boot.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/shard-glk6/boot.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/shard-glk7/boot.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/shard-glk7/boot.html
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/shard-glk8/boot.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/shard-glk8/boot.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/shard-glk8/boot.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/shard-glk9/boot.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/shard-glk9/boot.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/shard-glk9/boot.html
- shard-skl: ([PASS][59], [PASS][60], [PASS][61], [PASS][62], [PASS][63], [PASS][64], [PASS][65], [PASS][66], [PASS][67], [PASS][68], [PASS][69], [PASS][70], [PASS][71], [PASS][72], [PASS][73], [PASS][74], [PASS][75], [PASS][76], [PASS][77], [PASS][78], [PASS][79], [PASS][80]) -> ([PASS][81], [PASS][82], [PASS][83], [PASS][84], [PASS][85], [PASS][86], [FAIL][87], [PASS][88], [PASS][89], [PASS][90], [PASS][91], [PASS][92], [PASS][93], [PASS][94], [PASS][95], [PASS][96], [PASS][97], [PASS][98], [PASS][99], [PASS][100], [PASS][101], [FAIL][102]) ([i915#5032])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12325/shard-skl9/boot.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12325/shard-skl9/boot.html
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12325/shard-skl9/boot.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12325/shard-skl7/boot.html
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12325/shard-skl7/boot.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12325/shard-skl7/boot.html
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12325/shard-skl6/boot.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12325/shard-skl6/boot.html
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12325/shard-skl6/boot.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12325/shard-skl5/boot.html
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12325/shard-skl4/boot.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12325/shard-skl4/boot.html
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12325/shard-skl4/boot.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12325/shard-skl4/boot.html
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12325/shard-skl3/boot.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12325/shard-skl3/boot.html
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12325/shard-skl1/boot.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12325/shard-skl1/boot.html
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12325/shard-skl1/boot.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12325/shard-skl10/boot.html
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12325/shard-skl10/boot.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12325/shard-skl10/boot.html
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/shard-skl1/boot.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/shard-skl4/boot.html
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/shard-skl4/boot.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/shard-skl10/boot.html
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/shard-skl4/boot.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/shard-skl10/boot.html
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/shard-skl3/boot.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/shard-skl10/boot.html
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/shard-skl1/boot.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/shard-skl10/boot.html
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/shard-skl9/boot.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/shard-skl9/boot.html
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/shard-skl9/boot.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/shard-skl7/boot.html
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/shard-skl7/boot.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/shard-skl7/boot.html
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/shard-skl6/boot.html
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/shard-skl6/boot.html
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/shard-skl6/boot.html
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/shard-skl5/boot.html
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/shard-skl5/boot.html
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/shard-skl5/boot.html
### IGT changes ###
#### Issues hit ####
* igt@dmabuf@all@dma_fence_chain:
- shard-skl: NOTRUN -> [INCOMPLETE][103] ([i915#6949])
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/shard-skl7/igt@dmabuf@all@dma_fence_chain.html
* igt@gem_exec_balancer@parallel-bb-first:
- shard-iclb: [PASS][104] -> [SKIP][105] ([i915#4525]) +1 similar issue
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12325/shard-iclb2/igt@gem_exec_balancer@parallel-bb-first.html
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/shard-iclb8/igt@gem_exec_balancer@parallel-bb-first.html
* igt@gem_exec_fair@basic-pace@vcs1:
- shard-iclb: NOTRUN -> [FAIL][106] ([i915#2842])
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/shard-iclb1/igt@gem_exec_fair@basic-pace@vcs1.html
* igt@gem_lmem_swapping@massive:
- shard-skl: NOTRUN -> [SKIP][107] ([fdo#109271] / [i915#4613])
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/shard-skl4/igt@gem_lmem_swapping@massive.html
* igt@gem_softpin@evict-single-offset:
- shard-tglb: [PASS][108] -> [FAIL][109] ([i915#4171])
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12325/shard-tglb2/igt@gem_softpin@evict-single-offset.html
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/shard-tglb7/igt@gem_softpin@evict-single-offset.html
* igt@i915_pm_backlight@fade:
- shard-iclb: [PASS][110] -> [DMESG-WARN][111] ([i915#402])
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12325/shard-iclb7/igt@i915_pm_backlight@fade.html
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/shard-iclb6/igt@i915_pm_backlight@fade.html
* igt@i915_selftest@live@gt_heartbeat:
- shard-skl: NOTRUN -> [DMESG-FAIL][112] ([i915#5334])
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/shard-skl4/igt@i915_selftest@live@gt_heartbeat.html
* igt@i915_selftest@live@gt_pm:
- shard-skl: NOTRUN -> [DMESG-FAIL][113] ([i915#1886])
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/shard-skl4/igt@i915_selftest@live@gt_pm.html
* igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip:
- shard-iclb: NOTRUN -> [SKIP][114] ([i915#5286])
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/shard-iclb1/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip.html
* igt@kms_big_fb@x-tiled-64bpp-rotate-90:
- shard-iclb: NOTRUN -> [SKIP][115] ([fdo#110725] / [fdo#111614])
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/shard-iclb1/igt@kms_big_fb@x-tiled-64bpp-rotate-90.html
* igt@kms_big_fb@yf-tiled-8bpp-rotate-180:
- shard-iclb: NOTRUN -> [SKIP][116] ([fdo#110723])
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/shard-iclb1/igt@kms_big_fb@yf-tiled-8bpp-rotate-180.html
* igt@kms_ccs@pipe-a-crc-primary-basic-y_tiled_gen12_rc_ccs_cc:
- shard-skl: NOTRUN -> [SKIP][117] ([fdo#109271] / [i915#3886]) +2 similar issues
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/shard-skl7/igt@kms_ccs@pipe-a-crc-primary-basic-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-b-missing-ccs-buffer-y_tiled_gen12_rc_ccs:
- shard-iclb: NOTRUN -> [SKIP][118] ([fdo#109278]) +1 similar issue
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/shard-iclb1/igt@kms_ccs@pipe-b-missing-ccs-buffer-y_tiled_gen12_rc_ccs.html
* igt@kms_chamelium@hdmi-crc-multiple:
- shard-skl: NOTRUN -> [SKIP][119] ([fdo#109271] / [fdo#111827]) +3 similar issues
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/shard-skl4/igt@kms_chamelium@hdmi-crc-multiple.html
* igt@kms_chamelium@hdmi-crc-nonplanar-formats:
- shard-iclb: NOTRUN -> [SKIP][120] ([fdo#109284] / [fdo#111827])
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/shard-iclb1/igt@kms_chamelium@hdmi-crc-nonplanar-formats.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@c-hdmi-a2:
- shard-glk: [PASS][121] -> [FAIL][122] ([i915#79])
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12325/shard-glk1/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-hdmi-a2.html
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/shard-glk8/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-hdmi-a2.html
* igt@kms_flip@flip-vs-expired-vblank@a-edp1:
- shard-skl: [PASS][123] -> [FAIL][124] ([i915#79]) +1 similar issue
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12325/shard-skl4/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/shard-skl10/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
* igt@kms_flip@flip-vs-suspend@c-dp1:
- shard-apl: [PASS][125] -> [DMESG-WARN][126] ([i915#180]) +1 similar issue
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12325/shard-apl7/igt@kms_flip@flip-vs-suspend@c-dp1.html
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/shard-apl8/igt@kms_flip@flip-vs-suspend@c-dp1.html
* igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-upscaling@pipe-a-valid-mode:
- shard-iclb: NOTRUN -> [SKIP][127] ([i915#2587] / [i915#2672]) +1 similar issue
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/shard-iclb1/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-upscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling@pipe-a-default-mode:
- shard-iclb: NOTRUN -> [SKIP][128] ([i915#2672]) +4 similar issues
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-valid-mode:
- shard-iclb: NOTRUN -> [SKIP][129] ([i915#2672] / [i915#3555])
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/shard-iclb5/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-valid-mode.html
* igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-mmap-gtt:
- shard-skl: NOTRUN -> [SKIP][130] ([fdo#109271]) +64 similar issues
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/shard-skl7/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-mmap-cpu:
- shard-iclb: NOTRUN -> [SKIP][131] ([fdo#109280]) +5 similar issues
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/shard-iclb1/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-mmap-cpu.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-pgflip-blt:
- shard-iclb: [PASS][132] -> [FAIL][133] ([i915#2546])
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12325/shard-iclb7/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-pgflip-blt.html
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/shard-iclb6/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-pgflip-blt.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-pgflip-blt:
- shard-skl: [PASS][134] -> [DMESG-WARN][135] ([i915#1982])
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12325/shard-skl7/igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-pgflip-blt.html
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/shard-skl6/igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-pgflip-blt.html
* igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-wc:
- shard-apl: NOTRUN -> [SKIP][136] ([fdo#109271]) +22 similar issues
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/shard-apl2/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-wc.html
* igt@kms_plane_alpha_blend@alpha-opaque-fb@pipe-b-edp-1:
- shard-skl: NOTRUN -> [FAIL][137] ([i915#4573]) +2 similar issues
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/shard-skl4/igt@kms_plane_alpha_blend@alpha-opaque-fb@pipe-b-edp-1.html
* igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-5@pipe-b-edp-1:
- shard-iclb: [PASS][138] -> [SKIP][139] ([i915#5176]) +2 similar issues
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12325/shard-iclb3/igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-5@pipe-b-edp-1.html
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/shard-iclb2/igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-5@pipe-b-edp-1.html
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-a-edp-1:
- shard-iclb: [PASS][140] -> [SKIP][141] ([i915#5235]) +5 similar issues
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12325/shard-iclb3/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-a-edp-1.html
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/shard-iclb2/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-a-edp-1.html
* igt@kms_psr2_su@frontbuffer-xrgb8888:
- shard-iclb: NOTRUN -> [SKIP][142] ([fdo#109642] / [fdo#111068] / [i915#658])
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/shard-iclb8/igt@kms_psr2_su@frontbuffer-xrgb8888.html
* igt@kms_psr2_su@page_flip-nv12@pipe-b-edp-1:
- shard-iclb: NOTRUN -> [FAIL][143] ([i915#5939]) +2 similar issues
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/shard-iclb2/igt@kms_psr2_su@page_flip-nv12@pipe-b-edp-1.html
* igt@kms_psr@psr2_sprite_plane_onoff:
- shard-iclb: [PASS][144] -> [SKIP][145] ([fdo#109441]) +2 similar issues
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12325/shard-iclb2/igt@kms_psr@psr2_sprite_plane_onoff.html
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/shard-iclb8/igt@kms_psr@psr2_sprite_plane_onoff.html
* igt@kms_psr_stress_test@flip-primary-invalidate-overlay:
- shard-iclb: [PASS][146] -> [SKIP][147] ([i915#5519])
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12325/shard-iclb6/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/shard-iclb7/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
* igt@kms_writeback@writeback-fb-id:
- shard-skl: NOTRUN -> [SKIP][148] ([fdo#109271] / [i915#2437]) +1 similar issue
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/shard-skl7/igt@kms_writeback@writeback-fb-id.html
* igt@perf@polling:
- shard-skl: [PASS][149] -> [FAIL][150] ([i915#1542])
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12325/shard-skl9/igt@perf@polling.html
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/shard-skl6/igt@perf@polling.html
* igt@sysfs_heartbeat_interval@mixed@vecs0:
- shard-skl: [PASS][151] -> [FAIL][152] ([i915#1731])
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12325/shard-skl7/igt@sysfs_heartbeat_interval@mixed@vecs0.html
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/shard-skl6/igt@sysfs_heartbeat_interval@mixed@vecs0.html
#### Possible fixes ####
* igt@gem_ctx_persistence@many-contexts:
- shard-iclb: [INCOMPLETE][153] -> [PASS][154]
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12325/shard-iclb5/igt@gem_ctx_persistence@many-contexts.html
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/shard-iclb1/igt@gem_ctx_persistence@many-contexts.html
* igt@gem_exec_balancer@parallel-keep-in-fence:
- shard-iclb: [SKIP][155] ([i915#4525]) -> [PASS][156] +1 similar issue
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12325/shard-iclb6/igt@gem_exec_balancer@parallel-keep-in-fence.html
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/shard-iclb2/igt@gem_exec_balancer@parallel-keep-in-fence.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-iclb: [FAIL][157] ([i915#2842]) -> [PASS][158]
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12325/shard-iclb3/igt@gem_exec_fair@basic-none-share@rcs0.html
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/shard-iclb5/igt@gem_exec_fair@basic-none-share@rcs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-apl: [FAIL][159] ([i915#2842]) -> [PASS][160]
[159]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12325/shard-apl8/igt@gem_exec_fair@basic-pace-share@rcs0.html
[160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/shard-apl1/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gen9_exec_parse@allowed-single:
- shard-apl: [DMESG-WARN][161] ([i915#5566] / [i915#716]) -> [PASS][162]
[161]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12325/shard-apl7/igt@gen9_exec_parse@allowed-single.html
[162]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/shard-apl3/igt@gen9_exec_parse@allowed-single.html
* igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions-varying-size:
- shard-glk: [FAIL][163] ([i915#2346]) -> [PASS][164]
[163]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12325/shard-glk9/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions-varying-size.html
[164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/shard-glk5/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions-varying-size.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1:
- shard-skl: [FAIL][165] ([i915#79]) -> [PASS][166] +1 similar issue
[165]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12325/shard-skl10/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
[166]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/shard-skl1/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
* igt@kms_flip@wf_vblank-ts-check@a-edp1:
- shard-skl: [FAIL][167] ([i915#2122]) -> [PASS][168] +1 similar issue
[167]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12325/shard-skl3/igt@kms_flip@wf_vblank-ts-check@a-edp1.html
[168]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/shard-skl9/igt@kms_flip@wf_vblank-ts-check@a-edp1.html
* igt@kms_psr@psr2_sprite_blt:
- shard-iclb: [SKIP][169] ([fdo#109441]) -> [PASS][170] +3 similar issues
[169]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12325/shard-iclb6/igt@kms_psr@psr2_sprite_blt.html
[170]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/shard-iclb2/igt@kms_psr@psr2_sprite_blt.html
* igt@kms_psr_stress_test@flip-primary-invalidate-overlay:
- shard-tglb: [SKIP][171] ([i915#5519]) -> [PASS][172]
[171]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12325/shard-tglb2/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
[172]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/shard-tglb1/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
* igt@kms_vblank@pipe-a-ts-continuation-suspend:
- shard-apl: [DMESG-WARN][173] ([i915#180]) -> [PASS][174]
[173]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12325/shard-apl6/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
[174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/shard-apl2/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
* igt@perf_pmu@all-busy-idle-check-all:
- shard-skl: [DMESG-WARN][175] ([i915#1982]) -> [PASS][176]
[175]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12325/shard-skl6/igt@perf_pmu@all-busy-idle-check-all.html
[176]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/shard-skl1/igt@perf_pmu@all-busy-idle-check-all.html
* igt@perf_pmu@interrupts:
- shard-skl: [FAIL][177] ([i915#7318]) -> [PASS][178]
[177]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12325/shard-skl7/igt@perf_pmu@interrupts.html
[178]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/shard-skl9/igt@perf_pmu@interrupts.html
#### Warnings ####
* igt@gem_exec_balancer@parallel-ordering:
- shard-iclb: [SKIP][179] ([i915#4525]) -> [FAIL][180] ([i915#6117])
[179]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12325/shard-iclb6/igt@gem_exec_balancer@parallel-ordering.html
[180]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/shard-iclb2/igt@gem_exec_balancer@parallel-ordering.html
* igt@gem_pread@exhaustion:
- shard-apl: [WARN][181] ([i915#2658]) -> [INCOMPLETE][182] ([i915#7248])
[181]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12325/shard-apl7/igt@gem_pread@exhaustion.html
[182]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/shard-apl8/igt@gem_pread@exhaustion.html
- shard-glk: [INCOMPLETE][183] ([i915#7248]) -> [WARN][184] ([i915#2658])
[183]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12325/shard-glk3/igt@gem_pread@exhaustion.html
[184]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/shard-glk1/igt@gem_pread@exhaustion.html
* igt@kms_psr2_sf@cursor-plane-move-continuous-sf:
- shard-iclb: [SKIP][185] ([i915#2920]) -> [SKIP][186] ([i915#658])
[185]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12325/shard-iclb2/igt@kms_psr2_sf@cursor-plane-move-continuous-sf.html
[186]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/shard-iclb8/igt@kms_psr2_sf@cursor-plane-move-continuous-sf.html
* igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-sf:
- shard-iclb: [SKIP][187] ([i915#658]) -> [SKIP][188] ([i915#2920])
[187]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12325/shard-iclb6/igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-sf.html
[188]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/shard-iclb2/igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-sf.html
* igt@runner@aborted:
- shard-apl: ([FAIL][189], [FAIL][190], [FAIL][191], [FAIL][192]) ([fdo#109271] / [i915#3002] / [i915#4312]) -> ([FAIL][193], [FAIL][194], [FAIL][195], [FAIL][196]) ([i915#180] / [i915#3002] / [i915#4312])
[189]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12325/shard-apl7/igt@runner@aborted.html
[190]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12325/shard-apl6/igt@runner@aborted.html
[191]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12325/shard-apl6/igt@runner@aborted.html
[192]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12325/shard-apl2/igt@runner@aborted.html
[193]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/shard-apl8/igt@runner@aborted.html
[194]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/shard-apl7/igt@runner@aborted.html
[195]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/shard-apl2/igt@runner@aborted.html
[196]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/shard-apl2/igt@runner@aborted.html
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
[fdo#110725]: https://bugs.freedesktop.org/show_bug.cgi?id=110725
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542
[i915#1731]: https://gitlab.freedesktop.org/drm/intel/issues/1731
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
[i915#2546]: https://gitlab.freedesktop.org/drm/intel/issues/2546
[i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
[i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
[i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
[i915#4171]: https://gitlab.freedesktop.org/drm/intel/issues/4171
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4392]: https://gitlab.freedesktop.org/drm/intel/issues/4392
[i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525
[i915#4573]: https://gitlab.freedesktop.org/drm/intel/issues/4573
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#5032]: https://gitlab.freedesktop.org/drm/intel/issues/5032
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
[i915#5519]: https://gitlab.freedesktop.org/drm/intel/issues/5519
[i915#5566]: https://gitlab.freedesktop.org/drm/intel/issues/5566
[i915#5939]: https://gitlab.freedesktop.org/drm/intel/issues/5939
[i915#6117]: https://gitlab.freedesktop.org/drm/intel/issues/6117
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#6949]: https://gitlab.freedesktop.org/drm/intel/issues/6949
[i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
[i915#7248]: https://gitlab.freedesktop.org/drm/intel/issues/7248
[i915#7318]: https://gitlab.freedesktop.org/drm/intel/issues/7318
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
Build changes
-------------
* Linux: CI_DRM_12325 -> Patchwork_110347v1
CI-20190529: 20190529
CI_DRM_12325: 1a90222aa5e5bb86ffcbde5ba9611659a23f0df6 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7032: 372c56225e12578a7a4a6bcc5b79eb40b643fcde @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_110347v1: 1a90222aa5e5bb86ffcbde5ba9611659a23f0df6 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v1/index.html
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^ permalink raw reply [flat|nested] 15+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/display: Do both crawl and squash when changing cdclk (rev2)
2022-10-31 22:56 [Intel-gfx] [PATCH 1/2] drm/i915/display: Do both crawl and squash when changing cdclk Anusha Srivatsa
` (2 preceding siblings ...)
2022-11-01 2:29 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
@ 2022-11-01 23:25 ` Patchwork
2022-11-02 7:59 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
4 siblings, 0 replies; 15+ messages in thread
From: Patchwork @ 2022-11-01 23:25 UTC (permalink / raw)
To: Anusha Srivatsa; +Cc: intel-gfx
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== Series Details ==
Series: series starting with [1/2] drm/i915/display: Do both crawl and squash when changing cdclk (rev2)
URL : https://patchwork.freedesktop.org/series/110347/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12329 -> Patchwork_110347v2
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v2/index.html
Participating hosts (40 -> 29)
------------------------------
Missing (11): bat-dg2-8 bat-adlm-1 bat-dg2-9 bat-adlp-6 bat-adlp-4 bat-adln-1 bat-rplp-1 bat-rpls-1 bat-rpls-2 bat-dg2-11 bat-jsl-1
Known issues
------------
Here are the changes found in Patchwork_110347v2 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@core_hotunplug@unbind-rebind:
- fi-apl-guc: [PASS][1] -> [INCOMPLETE][2] ([i915#7073])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12329/fi-apl-guc/igt@core_hotunplug@unbind-rebind.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v2/fi-apl-guc/igt@core_hotunplug@unbind-rebind.html
* igt@i915_selftest@live@gt_heartbeat:
- fi-cfl-guc: [PASS][3] -> [DMESG-FAIL][4] ([i915#5334])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12329/fi-cfl-guc/igt@i915_selftest@live@gt_heartbeat.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v2/fi-cfl-guc/igt@i915_selftest@live@gt_heartbeat.html
#### Possible fixes ####
* igt@debugfs_test@read_all_entries:
- {fi-tgl-mst}: [DMESG-WARN][5] ([i915#6434]) -> [PASS][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12329/fi-tgl-mst/igt@debugfs_test@read_all_entries.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v2/fi-tgl-mst/igt@debugfs_test@read_all_entries.html
* igt@gem_exec_gttfill@basic:
- fi-pnv-d510: [FAIL][7] ([i915#7229]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12329/fi-pnv-d510/igt@gem_exec_gttfill@basic.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v2/fi-pnv-d510/igt@gem_exec_gttfill@basic.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
[i915#6434]: https://gitlab.freedesktop.org/drm/intel/issues/6434
[i915#7073]: https://gitlab.freedesktop.org/drm/intel/issues/7073
[i915#7229]: https://gitlab.freedesktop.org/drm/intel/issues/7229
Build changes
-------------
* Linux: CI_DRM_12329 -> Patchwork_110347v2
CI-20190529: 20190529
CI_DRM_12329: aeb0d740b4011006d27dc0ac4d5c2ae7c6da4066 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7037: 6a25c53624502fc85cec3cf0a0bf244a2346e30f @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_110347v2: aeb0d740b4011006d27dc0ac4d5c2ae7c6da4066 @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
db8ade4d8794 drm/i915/display: Add CDCLK Support for MTL
7d65fabe426b drm/i915/display: Do both crawl and squash when changing cdclk
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v2/index.html
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^ permalink raw reply [flat|nested] 15+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915/display: Do both crawl and squash when changing cdclk (rev2)
2022-10-31 22:56 [Intel-gfx] [PATCH 1/2] drm/i915/display: Do both crawl and squash when changing cdclk Anusha Srivatsa
` (3 preceding siblings ...)
2022-11-01 23:25 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/display: Do both crawl and squash when changing cdclk (rev2) Patchwork
@ 2022-11-02 7:59 ` Patchwork
4 siblings, 0 replies; 15+ messages in thread
From: Patchwork @ 2022-11-02 7:59 UTC (permalink / raw)
To: Anusha Srivatsa; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 21959 bytes --]
== Series Details ==
Series: series starting with [1/2] drm/i915/display: Do both crawl and squash when changing cdclk (rev2)
URL : https://patchwork.freedesktop.org/series/110347/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12329_full -> Patchwork_110347v2_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (9 -> 9)
------------------------------
No changes in participating hosts
Known issues
------------
Here are the changes found in Patchwork_110347v2_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_balancer@parallel-contexts:
- shard-iclb: [PASS][1] -> [SKIP][2] ([i915#4525]) +1 similar issue
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12329/shard-iclb2/igt@gem_exec_balancer@parallel-contexts.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v2/shard-iclb3/igt@gem_exec_balancer@parallel-contexts.html
* igt@gem_exec_fair@basic-pace@vcs1:
- shard-iclb: NOTRUN -> [FAIL][3] ([i915#2842])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v2/shard-iclb2/igt@gem_exec_fair@basic-pace@vcs1.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-glk: [PASS][4] -> [FAIL][5] ([i915#2842]) +2 similar issues
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12329/shard-glk5/igt@gem_exec_fair@basic-throttle@rcs0.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v2/shard-glk6/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@gem_pxp@create-protected-buffer:
- shard-tglb: NOTRUN -> [SKIP][6] ([i915#4270])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v2/shard-tglb8/igt@gem_pxp@create-protected-buffer.html
* igt@gem_softpin@evict-single-offset:
- shard-tglb: [PASS][7] -> [FAIL][8] ([i915#4171])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12329/shard-tglb5/igt@gem_softpin@evict-single-offset.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v2/shard-tglb7/igt@gem_softpin@evict-single-offset.html
* igt@gem_userptr_blits@dmabuf-unsync:
- shard-tglb: NOTRUN -> [SKIP][9] ([i915#3297])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v2/shard-tglb8/igt@gem_userptr_blits@dmabuf-unsync.html
* igt@gen9_exec_parse@allowed-single:
- shard-apl: [PASS][10] -> [DMESG-WARN][11] ([i915#5566] / [i915#716])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12329/shard-apl1/igt@gen9_exec_parse@allowed-single.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v2/shard-apl2/igt@gen9_exec_parse@allowed-single.html
* igt@gen9_exec_parse@batch-without-end:
- shard-tglb: NOTRUN -> [SKIP][12] ([i915#2527] / [i915#2856])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v2/shard-tglb8/igt@gen9_exec_parse@batch-without-end.html
* igt@i915_module_load@resize-bar:
- shard-tglb: NOTRUN -> [SKIP][13] ([i915#6412])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v2/shard-tglb8/igt@i915_module_load@resize-bar.html
* igt@i915_query@hwconfig_table:
- shard-tglb: NOTRUN -> [SKIP][14] ([i915#6245])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v2/shard-tglb8/igt@i915_query@hwconfig_table.html
* igt@i915_selftest@live@gt_heartbeat:
- shard-apl: [PASS][15] -> [DMESG-FAIL][16] ([i915#5334])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12329/shard-apl1/igt@i915_selftest@live@gt_heartbeat.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v2/shard-apl2/igt@i915_selftest@live@gt_heartbeat.html
* igt@kms_async_flips@alternate-sync-async-flip@pipe-a-edp-1:
- shard-skl: [PASS][17] -> [FAIL][18] ([i915#2521])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12329/shard-skl9/igt@kms_async_flips@alternate-sync-async-flip@pipe-a-edp-1.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v2/shard-skl6/igt@kms_async_flips@alternate-sync-async-flip@pipe-a-edp-1.html
* igt@kms_big_fb@4-tiled-64bpp-rotate-90:
- shard-tglb: NOTRUN -> [SKIP][19] ([i915#5286]) +1 similar issue
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v2/shard-tglb8/igt@kms_big_fb@4-tiled-64bpp-rotate-90.html
* igt@kms_big_fb@yf-tiled-64bpp-rotate-90:
- shard-tglb: NOTRUN -> [SKIP][20] ([fdo#111615])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v2/shard-tglb8/igt@kms_big_fb@yf-tiled-64bpp-rotate-90.html
* igt@kms_ccs@pipe-a-bad-aux-stride-y_tiled_gen12_rc_ccs_cc:
- shard-skl: NOTRUN -> [SKIP][21] ([fdo#109271] / [i915#3886]) +3 similar issues
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v2/shard-skl9/igt@kms_ccs@pipe-a-bad-aux-stride-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-a-crc-primary-basic-y_tiled_gen12_mc_ccs:
- shard-apl: NOTRUN -> [SKIP][22] ([fdo#109271] / [i915#3886]) +1 similar issue
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v2/shard-apl3/igt@kms_ccs@pipe-a-crc-primary-basic-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-c-crc-sprite-planes-basic-y_tiled_ccs:
- shard-tglb: NOTRUN -> [SKIP][23] ([i915#3689]) +2 similar issues
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v2/shard-tglb8/igt@kms_ccs@pipe-c-crc-sprite-planes-basic-y_tiled_ccs.html
* igt@kms_chamelium@hdmi-crc-multiple:
- shard-skl: NOTRUN -> [SKIP][24] ([fdo#109271] / [fdo#111827]) +3 similar issues
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v2/shard-skl9/igt@kms_chamelium@hdmi-crc-multiple.html
* igt@kms_chamelium@hdmi-hpd-storm:
- shard-apl: NOTRUN -> [SKIP][25] ([fdo#109271] / [fdo#111827])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v2/shard-apl3/igt@kms_chamelium@hdmi-hpd-storm.html
* igt@kms_chamelium@vga-frame-dump:
- shard-tglb: NOTRUN -> [SKIP][26] ([fdo#109284] / [fdo#111827]) +1 similar issue
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v2/shard-tglb8/igt@kms_chamelium@vga-frame-dump.html
* igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-legacy:
- shard-skl: [PASS][27] -> [FAIL][28] ([i915#2346])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12329/shard-skl3/igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-legacy.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v2/shard-skl3/igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-legacy.html
* igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions-varying-size:
- shard-glk: [PASS][29] -> [FAIL][30] ([i915#2346])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12329/shard-glk1/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions-varying-size.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v2/shard-glk5/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions-varying-size.html
* igt@kms_dp_tiled_display@basic-test-pattern:
- shard-tglb: NOTRUN -> [SKIP][31] ([i915#426])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v2/shard-tglb8/igt@kms_dp_tiled_display@basic-test-pattern.html
* igt@kms_flip@2x-nonexisting-fb:
- shard-apl: NOTRUN -> [SKIP][32] ([fdo#109271]) +20 similar issues
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v2/shard-apl3/igt@kms_flip@2x-nonexisting-fb.html
* igt@kms_flip@blocking-wf_vblank@b-edp1:
- shard-skl: [PASS][33] -> [FAIL][34] ([i915#2122])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12329/shard-skl3/igt@kms_flip@blocking-wf_vblank@b-edp1.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v2/shard-skl3/igt@kms_flip@blocking-wf_vblank@b-edp1.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1:
- shard-skl: [PASS][35] -> [FAIL][36] ([i915#79])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12329/shard-skl7/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v2/shard-skl9/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html
* igt@kms_flip@flip-vs-suspend-interruptible@b-dp1:
- shard-apl: [PASS][37] -> [DMESG-WARN][38] ([i915#180]) +1 similar issue
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12329/shard-apl2/igt@kms_flip@flip-vs-suspend-interruptible@b-dp1.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v2/shard-apl3/igt@kms_flip@flip-vs-suspend-interruptible@b-dp1.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling@pipe-a-default-mode:
- shard-iclb: NOTRUN -> [SKIP][39] ([i915#3555]) +1 similar issue
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v2/shard-iclb2/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-default-mode:
- shard-iclb: NOTRUN -> [SKIP][40] ([i915#2672]) +1 similar issue
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v2/shard-iclb2/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-downscaling@pipe-a-valid-mode:
- shard-iclb: NOTRUN -> [SKIP][41] ([i915#2587] / [i915#2672]) +1 similar issue
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v2/shard-iclb7/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-downscaling@pipe-a-valid-mode.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-shrfb-draw-mmap-cpu:
- shard-skl: NOTRUN -> [SKIP][42] ([fdo#109271]) +79 similar issues
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v2/shard-skl3/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-shrfb-draw-mmap-cpu.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-move:
- shard-tglb: NOTRUN -> [SKIP][43] ([fdo#109280] / [fdo#111825]) +2 similar issues
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v2/shard-tglb8/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-move.html
* igt@kms_frontbuffer_tracking@fbcpsr-modesetfrombusy:
- shard-tglb: NOTRUN -> [SKIP][44] ([i915#6497]) +2 similar issues
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v2/shard-tglb8/igt@kms_frontbuffer_tracking@fbcpsr-modesetfrombusy.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-c-edp-1:
- shard-tglb: NOTRUN -> [SKIP][45] ([i915#5235]) +3 similar issues
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v2/shard-tglb8/igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-c-edp-1.html
* igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-sf:
- shard-tglb: NOTRUN -> [SKIP][46] ([i915#2920])
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v2/shard-tglb8/igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-sf.html
* igt@kms_psr2_sf@overlay-plane-move-continuous-sf:
- shard-apl: NOTRUN -> [SKIP][47] ([fdo#109271] / [i915#658])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v2/shard-apl3/igt@kms_psr2_sf@overlay-plane-move-continuous-sf.html
* igt@kms_psr2_su@frontbuffer-xrgb8888:
- shard-iclb: NOTRUN -> [SKIP][48] ([fdo#109642] / [fdo#111068] / [i915#658])
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v2/shard-iclb8/igt@kms_psr2_su@frontbuffer-xrgb8888.html
* igt@kms_psr2_su@page_flip-xrgb8888:
- shard-tglb: NOTRUN -> [SKIP][49] ([i915#7037])
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v2/shard-tglb8/igt@kms_psr2_su@page_flip-xrgb8888.html
* igt@kms_psr@psr2_cursor_mmap_gtt:
- shard-iclb: [PASS][50] -> [SKIP][51] ([fdo#109441]) +2 similar issues
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12329/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_gtt.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v2/shard-iclb3/igt@kms_psr@psr2_cursor_mmap_gtt.html
* igt@kms_rotation_crc@sprite-rotation-90-pos-100-0:
- shard-skl: NOTRUN -> [DMESG-WARN][52] ([i915#1982])
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v2/shard-skl9/igt@kms_rotation_crc@sprite-rotation-90-pos-100-0.html
* igt@kms_setmode@clone-exclusive-crtc:
- shard-tglb: NOTRUN -> [SKIP][53] ([i915#3555]) +1 similar issue
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v2/shard-tglb8/igt@kms_setmode@clone-exclusive-crtc.html
* igt@kms_tv_load_detect@load-detect:
- shard-tglb: NOTRUN -> [SKIP][54] ([fdo#109309])
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v2/shard-tglb8/igt@kms_tv_load_detect@load-detect.html
* igt@sysfs_clients@split-25:
- shard-skl: NOTRUN -> [SKIP][55] ([fdo#109271] / [i915#2994])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v2/shard-skl9/igt@sysfs_clients@split-25.html
* igt@sysfs_heartbeat_interval@mixed@bcs0:
- shard-skl: NOTRUN -> [FAIL][56] ([i915#1731])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v2/shard-skl3/igt@sysfs_heartbeat_interval@mixed@bcs0.html
#### Possible fixes ####
* igt@kms_cursor_crc@cursor-suspend@pipe-c-dp-1:
- shard-apl: [DMESG-WARN][57] ([i915#180]) -> [PASS][58]
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12329/shard-apl3/igt@kms_cursor_crc@cursor-suspend@pipe-c-dp-1.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v2/shard-apl3/igt@kms_cursor_crc@cursor-suspend@pipe-c-dp-1.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1:
- shard-skl: [FAIL][59] ([i915#79]) -> [PASS][60]
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12329/shard-skl7/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v2/shard-skl9/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling@pipe-a-default-mode:
- shard-iclb: [SKIP][61] ([i915#3555]) -> [PASS][62]
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12329/shard-iclb2/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling@pipe-a-default-mode.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v2/shard-iclb3/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling@pipe-a-default-mode.html
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-c-edp-1:
- shard-iclb: [SKIP][63] ([i915#5235]) -> [PASS][64] +2 similar issues
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12329/shard-iclb2/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-c-edp-1.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v2/shard-iclb8/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-c-edp-1.html
* igt@kms_psr@psr2_no_drrs:
- shard-iclb: [SKIP][65] ([fdo#109441]) -> [PASS][66] +2 similar issues
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12329/shard-iclb8/igt@kms_psr@psr2_no_drrs.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v2/shard-iclb2/igt@kms_psr@psr2_no_drrs.html
#### Warnings ####
* igt@gem_pwrite@basic-exhaustion:
- shard-glk: [WARN][67] ([i915#2658]) -> [INCOMPLETE][68] ([i915#7248])
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12329/shard-glk8/igt@gem_pwrite@basic-exhaustion.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v2/shard-glk9/igt@gem_pwrite@basic-exhaustion.html
* igt@i915_pm_dc@dc3co-vpb-simulation:
- shard-iclb: [SKIP][69] ([i915#658]) -> [SKIP][70] ([i915#588])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12329/shard-iclb8/igt@i915_pm_dc@dc3co-vpb-simulation.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v2/shard-iclb2/igt@i915_pm_dc@dc3co-vpb-simulation.html
* igt@kms_psr2_sf@cursor-plane-move-continuous-sf:
- shard-iclb: [SKIP][71] ([i915#2920]) -> [SKIP][72] ([i915#658])
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12329/shard-iclb2/igt@kms_psr2_sf@cursor-plane-move-continuous-sf.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v2/shard-iclb8/igt@kms_psr2_sf@cursor-plane-move-continuous-sf.html
* igt@kms_psr2_sf@plane-move-sf-dmg-area:
- shard-iclb: [SKIP][73] ([fdo#111068] / [i915#658]) -> [SKIP][74] ([i915#2920])
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12329/shard-iclb8/igt@kms_psr2_sf@plane-move-sf-dmg-area.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v2/shard-iclb2/igt@kms_psr2_sf@plane-move-sf-dmg-area.html
* igt@runner@aborted:
- shard-apl: ([FAIL][75], [FAIL][76], [FAIL][77]) ([i915#3002] / [i915#4312]) -> ([FAIL][78], [FAIL][79], [FAIL][80], [FAIL][81]) ([fdo#109271] / [i915#180] / [i915#3002] / [i915#4312])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12329/shard-apl7/igt@runner@aborted.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12329/shard-apl3/igt@runner@aborted.html
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12329/shard-apl8/igt@runner@aborted.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v2/shard-apl1/igt@runner@aborted.html
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v2/shard-apl2/igt@runner@aborted.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v2/shard-apl6/igt@runner@aborted.html
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v2/shard-apl3/igt@runner@aborted.html
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109309]: https://bugs.freedesktop.org/show_bug.cgi?id=109309
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1731]: https://gitlab.freedesktop.org/drm/intel/issues/1731
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521
[i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
[i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
[i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
[i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
[i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994
[i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#4171]: https://gitlab.freedesktop.org/drm/intel/issues/4171
[i915#426]: https://gitlab.freedesktop.org/drm/intel/issues/426
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
[i915#5566]: https://gitlab.freedesktop.org/drm/intel/issues/5566
[i915#588]: https://gitlab.freedesktop.org/drm/intel/issues/588
[i915#6245]: https://gitlab.freedesktop.org/drm/intel/issues/6245
[i915#6412]: https://gitlab.freedesktop.org/drm/intel/issues/6412
[i915#6497]: https://gitlab.freedesktop.org/drm/intel/issues/6497
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#7037]: https://gitlab.freedesktop.org/drm/intel/issues/7037
[i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
[i915#7248]: https://gitlab.freedesktop.org/drm/intel/issues/7248
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
Build changes
-------------
* Linux: CI_DRM_12329 -> Patchwork_110347v2
CI-20190529: 20190529
CI_DRM_12329: aeb0d740b4011006d27dc0ac4d5c2ae7c6da4066 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7037: 6a25c53624502fc85cec3cf0a0bf244a2346e30f @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_110347v2: aeb0d740b4011006d27dc0ac4d5c2ae7c6da4066 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110347v2/index.html
[-- Attachment #2: Type: text/html, Size: 26256 bytes --]
^ permalink raw reply [flat|nested] 15+ messages in thread
* [Intel-gfx] [PATCH 2/2] drm/i915/display: Add CDCLK Support for MTL
2022-11-04 22:26 [Intel-gfx] [PATCH 1/2] drm/i915/display: Do both crawl and squash when changing cdclk Anusha Srivatsa
@ 2022-11-04 22:26 ` Anusha Srivatsa
0 siblings, 0 replies; 15+ messages in thread
From: Anusha Srivatsa @ 2022-11-04 22:26 UTC (permalink / raw)
To: intel-gfx
As per bSpec MTL has 38.4 MHz Reference clock.
Adding the cdclk tables and cdclk_funcs that MTL
will use.
v2: Revert to using bxt_get_cdclk()
BSpec: 65243
Cc: Clint Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Reviewed-by: Clint Taylor <Clinton.A.Taylor@intel.com>
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 22 +++++++++++++++++++++-
1 file changed, 21 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index d1e0763513be..e7374fd92da9 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1345,6 +1345,16 @@ static const struct intel_cdclk_vals dg2_cdclk_table[] = {
{}
};
+static const struct intel_cdclk_vals mtl_cdclk_table[] = {
+ { .refclk = 38400, .cdclk = 172800, .divider = 2, .ratio = 16, .waveform = 0xad5a },
+ { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 16, .waveform = 0xb6b6 },
+ { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16, .waveform = 0x0000 },
+ { .refclk = 38400, .cdclk = 480000, .divider = 2, .ratio = 25, .waveform = 0x0000 },
+ { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29, .waveform = 0x0000 },
+ { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34, .waveform = 0x0000 },
+ {}
+};
+
static int bxt_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk)
{
const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table;
@@ -3164,6 +3174,13 @@ u32 intel_read_rawclk(struct drm_i915_private *dev_priv)
return freq;
}
+static const struct intel_cdclk_funcs mtl_cdclk_funcs = {
+ .get_cdclk = bxt_get_cdclk,
+ .set_cdclk = bxt_set_cdclk,
+ .modeset_calc_cdclk = bxt_modeset_calc_cdclk,
+ .calc_voltage_level = tgl_calc_voltage_level,
+};
+
static const struct intel_cdclk_funcs tgl_cdclk_funcs = {
.get_cdclk = bxt_get_cdclk,
.set_cdclk = bxt_set_cdclk,
@@ -3299,7 +3316,10 @@ static const struct intel_cdclk_funcs i830_cdclk_funcs = {
*/
void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
{
- if (IS_DG2(dev_priv)) {
+ if (IS_METEORLAKE(dev_priv)) {
+ dev_priv->display.funcs.cdclk = &mtl_cdclk_funcs;
+ dev_priv->display.cdclk.table = mtl_cdclk_table;
+ } else if (IS_DG2(dev_priv)) {
dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
dev_priv->display.cdclk.table = dg2_cdclk_table;
} else if (IS_ALDERLAKE_P(dev_priv)) {
--
2.25.1
^ permalink raw reply related [flat|nested] 15+ messages in thread
end of thread, other threads:[~2022-11-04 22:26 UTC | newest]
Thread overview: 15+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2022-10-31 22:56 [Intel-gfx] [PATCH 1/2] drm/i915/display: Do both crawl and squash when changing cdclk Anusha Srivatsa
2022-10-31 22:56 ` [Intel-gfx] [PATCH 2/2] drm/i915/display: Add CDCLK Support for MTL Anusha Srivatsa
2022-11-01 0:33 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/display: Do both crawl and squash when changing cdclk Patchwork
2022-11-01 2:29 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2022-11-01 23:25 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/display: Do both crawl and squash when changing cdclk (rev2) Patchwork
2022-11-02 7:59 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
-- strict thread matches above, loose matches on Subject: below --
2022-11-04 22:26 [Intel-gfx] [PATCH 1/2] drm/i915/display: Do both crawl and squash when changing cdclk Anusha Srivatsa
2022-11-04 22:26 ` [Intel-gfx] [PATCH 2/2] drm/i915/display: Add CDCLK Support for MTL Anusha Srivatsa
2022-10-28 21:32 [Intel-gfx] [PATCH 1/2] drm/i915/display: Do both crawl and squash when changing cdclk Anusha Srivatsa
2022-10-28 21:32 ` [Intel-gfx] [PATCH 2/2] drm/i915/display: Add CDCLK Support for MTL Anusha Srivatsa
2022-10-31 17:58 ` Taylor, Clinton A
2022-10-26 23:22 [Intel-gfx] [PATCH 1/2] drm/i915/display: Do both crawl and squash when changing cdclk Anusha Srivatsa
2022-10-26 23:22 ` [Intel-gfx] [PATCH 2/2] drm/i915/display: Add CDCLK Support for MTL Anusha Srivatsa
2022-10-13 23:32 [Intel-gfx] [PATCH 1/2] drm/i915/display: Do both crawl and squash when changing cdclk Anusha Srivatsa
2022-10-13 23:32 ` [Intel-gfx] [PATCH 2/2] drm/i915/display: Add CDCLK Support for MTL Anusha Srivatsa
2022-09-30 21:34 [Intel-gfx] [PATCH 1/2] drm/i915/display: Do both crawl and squash when changing cdclk Anusha Srivatsa
2022-09-30 21:34 ` [Intel-gfx] [PATCH 2/2] drm/i915/display: Add CDCLK Support for MTL Anusha Srivatsa
2022-09-28 19:04 [Intel-gfx] [PATCH 1/2] drm/i915/display: Do both crawl and squash when changing cdclk Anusha Srivatsa
2022-09-28 19:04 ` [Intel-gfx] [PATCH 2/2] drm/i915/display: Add CDCLK Support for MTL Anusha Srivatsa
2022-09-28 19:23 ` Ville Syrjälä
2022-09-28 21:16 ` Srivatsa, Anusha
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