[Intel-gfx] [PATCH 5/6] drm/915: Extend dual PPS handlind for ICP+

[Ville Syrjala <ville.syrjala@linux.intel.com>]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

On the PCH side the second PPS was introduced in ICP. Let's
make sure we examine both power sequencer on ICP+ as well.

Note that DG1/2 south block only has the single PPS, so need
to exclude the fake DG1/2 PCHs.

Cc: Animesh Manna <animesh.manna@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_pps.c | 15 ++++++++++++---
 1 file changed, 12 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
index ff4f1def59d2..f3ac4eee4d39 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -401,6 +401,15 @@ struct pps_registers {
 	i915_reg_t pp_div;
 };
 
+static bool has_dual_bxt_pps(struct drm_i915_private *i915)
+{
+	if (IS_GEMINILAKE(i915) || IS_BROXTON(i915))
+		return true;
+
+	return INTEL_PCH_TYPE(i915) >= PCH_ICP &&
+		INTEL_PCH_TYPE(i915) < PCH_DG1;
+}
+
 static void intel_pps_get_registers(struct intel_dp *intel_dp,
 				    struct pps_registers *regs)
 {
@@ -409,7 +418,7 @@ static void intel_pps_get_registers(struct intel_dp *intel_dp,
 
 	memset(regs, 0, sizeof(*regs));
 
-	if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
+	if (has_dual_bxt_pps(dev_priv))
 		pps_idx = bxt_power_sequencer_idx(intel_dp);
 	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 		pps_idx = vlv_power_sequencer_pipe(intel_dp);
@@ -1478,7 +1487,7 @@ void intel_pps_init(struct intel_dp *intel_dp)
 	pps_init_timestamps(intel_dp);
 
 	with_intel_pps_lock(intel_dp, wakeref) {
-		if (IS_GEMINILAKE(i915) || IS_BROXTON(i915))
+		if (has_dual_bxt_pps(i915))
 			bxt_initial_power_sequencer_setup(intel_dp);
 		else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
 			vlv_initial_power_sequencer_setup(intel_dp);
@@ -1512,7 +1521,7 @@ void intel_pps_init_late(struct intel_dp *intel_dp)
 
 	with_intel_pps_lock(intel_dp, wakeref) {
 		/* Reinit delays after per-panel info has been parsed from VBT */
-		if (IS_GEMINILAKE(i915) || IS_BROXTON(i915))
+		if (has_dual_bxt_pps(i915))
 			bxt_pps_init_late(intel_dp);
 		memset(&intel_dp->pps.pps_delays, 0, sizeof(intel_dp->pps.pps_delays));
 		pps_init_delays(intel_dp);
-- 
2.37.4