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From: Imre Deak <imre.deak@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Jani Nikula <jani.nikula@intel.com>
Subject: [Intel-gfx] [PATCH v4 2/9] drm/i915: Preallocate the debug power domain wakerefs array
Date: Mon, 14 Nov 2022 14:22:44 +0200	[thread overview]
Message-ID: <20221114122251.21327-3-imre.deak@intel.com> (raw)
In-Reply-To: <20221114122251.21327-1-imre.deak@intel.com>

Since the current size of intel_display_power_domain_set struct is
close to 1kB, it's better to use preallocated memory for it. The only
user of the intel_display_power_get/put_in_set() allocating the struct
on stack is hsw_get_pipe_config(), so we can avoid potential stack
overallocations by moving the struct here to the preallocated
intel_crtc struct (hsw_get_pipe_config() is non-reentrant wrt. each
CRTC).

This patch replaces
https://lore.kernel.org/intel-gfx/20221107170917.3566758-5-imre.deak@intel.com/T/#md3f6cdf17fcd

Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c       | 11 +++++------
 drivers/gpu/drm/i915/display/intel_display_types.h |  1 +
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 7cceaa6b11663..a0d5c56e8331c 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -4050,20 +4050,19 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc,
 				struct intel_crtc_state *pipe_config)
 {
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-	struct intel_display_power_domain_set power_domain_set = { };
 	bool active;
 	u32 tmp;
 
-	if (!intel_display_power_get_in_set_if_enabled(dev_priv, &power_domain_set,
+	if (!intel_display_power_get_in_set_if_enabled(dev_priv, &crtc->hw_readout_power_domains,
 						       POWER_DOMAIN_PIPE(crtc->pipe)))
 		return false;
 
 	pipe_config->shared_dpll = NULL;
 
-	active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_set);
+	active = hsw_get_transcoder_state(crtc, pipe_config, &crtc->hw_readout_power_domains);
 
 	if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
-	    bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_set)) {
+	    bxt_get_dsi_transcoder_state(crtc, pipe_config, &crtc->hw_readout_power_domains)) {
 		drm_WARN_ON(&dev_priv->drm, active);
 		active = true;
 	}
@@ -4122,7 +4121,7 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc,
 		pipe_config->ips_linetime =
 			REG_FIELD_GET(HSW_IPS_LINETIME_MASK, tmp);
 
-	if (intel_display_power_get_in_set_if_enabled(dev_priv, &power_domain_set,
+	if (intel_display_power_get_in_set_if_enabled(dev_priv, &crtc->hw_readout_power_domains,
 						      POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe))) {
 		if (DISPLAY_VER(dev_priv) >= 9)
 			skl_get_pfit_config(pipe_config);
@@ -4153,7 +4152,7 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc,
 	}
 
 out:
-	intel_display_power_put_all_in_set(dev_priv, &power_domain_set);
+	intel_display_power_put_all_in_set(dev_priv, &crtc->hw_readout_power_domains);
 
 	return active;
 }
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 8da87cbb172bd..f07395065a69f 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1375,6 +1375,7 @@ struct intel_crtc {
 	u16 vmax_vblank_start;
 
 	struct intel_display_power_domain_set enabled_power_domains;
+	struct intel_display_power_domain_set hw_readout_power_domains;
 	struct intel_overlay *overlay;
 
 	struct intel_crtc_state *config;
-- 
2.37.1


  parent reply	other threads:[~2022-11-14 12:23 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-11-14 12:22 [Intel-gfx] [PATCH v4 0/9] drm/i915: drm/i915/tgl+: Enable DC power states on all eDP ports Imre Deak
2022-11-14 12:22 ` [Intel-gfx] [PATCH v4 1/9] drm/i915: Fix warn in intel_display_power_*_domain() functions Imre Deak
2022-11-14 12:22 ` Imre Deak [this message]
2022-11-14 12:22 ` [Intel-gfx] [PATCH v4 3/9] drm/i915: Move the POWER_DOMAIN_AUX_IO_A definition to its logical place Imre Deak
2022-11-14 12:22 ` [Intel-gfx] [PATCH v4 4/9] drm/i915: Use the AUX_IO power domain only for eDP/PSR port Imre Deak
2022-11-14 12:22 ` [Intel-gfx] [PATCH v4 5/9] drm/i915/tgl+: Enable display DC power states on all eDP ports Imre Deak
2022-11-14 12:22 ` [Intel-gfx] [PATCH v4 6/9] drm/i915: Add missing AUX_IO_A power domain->well mappings Imre Deak
2022-11-14 12:22 ` [Intel-gfx] [PATCH v4 7/9] drm/i915: Add missing DC_OFF " Imre Deak
2022-11-14 12:22 ` [Intel-gfx] [PATCH v4 8/9] drm/i915: Factor out function to get/put AUX_IO power for main link Imre Deak
2022-11-14 12:22 ` [Intel-gfx] [PATCH v4 9/9] drm/i915/mtl+: Don't enable the AUX_IO power for non-eDP port main links Imre Deak
2022-11-17 13:24   ` Ville Syrjälä
2022-11-17 13:56     ` Imre Deak
2022-11-14 19:39 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: drm/i915/tgl+: Enable DC power states on all eDP ports Patchwork
2022-11-14 20:01 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-11-15  0:48 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork

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