From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH 01/13] drm/i915: Shorten GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED a bit
Date: Wed, 23 Nov 2022 17:26:26 +0200 [thread overview]
Message-ID: <20221123152638.20622-2-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <20221123152638.20622-1-ville.syrjala@linux.intel.com>
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
s/GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED/GAMMA_MODE_MODE_12BIT_MULTI_SEG/
to make this thing slightly shorter.
Also fix up the platform comment while at it.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_color.c | 10 +++++-----
drivers/gpu/drm/i915/i915_reg.h | 2 +-
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 842d58da3128..956b221860e6 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -1212,7 +1212,7 @@ static void icl_load_luts(const struct intel_crtc_state *crtc_state)
case GAMMA_MODE_MODE_8BIT:
ilk_load_lut_8(crtc, post_csc_lut);
break;
- case GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED:
+ case GAMMA_MODE_MODE_12BIT_MULTI_SEG:
icl_program_gamma_superfine_segment(crtc_state);
icl_program_gamma_multi_segment(crtc_state);
ivb_load_lut_ext_max(crtc_state);
@@ -2091,7 +2091,7 @@ static u32 icl_gamma_mode(const struct intel_crtc_state *crtc_state)
else if (DISPLAY_VER(i915) >= 13)
gamma_mode |= GAMMA_MODE_MODE_10BIT;
else
- gamma_mode |= GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED;
+ gamma_mode |= GAMMA_MODE_MODE_12BIT_MULTI_SEG;
return gamma_mode;
}
@@ -2283,7 +2283,7 @@ static int icl_post_csc_lut_precision(const struct intel_crtc_state *crtc_state)
return 8;
case GAMMA_MODE_MODE_10BIT:
return 10;
- case GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED:
+ case GAMMA_MODE_MODE_12BIT_MULTI_SEG:
return 16;
default:
MISSING_CASE(crtc_state->gamma_mode);
@@ -2455,7 +2455,7 @@ static bool icl_lut_equal(const struct intel_crtc_state *crtc_state,
/* hw readout broken except for the super fine segment :( */
if ((crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) ==
- GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED)
+ GAMMA_MODE_MODE_12BIT_MULTI_SEG)
check_size = 9;
return intel_lut_equal(blob1, blob2, check_size,
@@ -2971,7 +2971,7 @@ static void icl_read_luts(struct intel_crtc_state *crtc_state)
case GAMMA_MODE_MODE_10BIT:
crtc_state->post_csc_lut = bdw_read_lut_10(crtc, PAL_PREC_INDEX_VALUE(0));
break;
- case GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED:
+ case GAMMA_MODE_MODE_12BIT_MULTI_SEG:
crtc_state->post_csc_lut = icl_read_lut_multi_segment(crtc);
break;
default:
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0b90fe6a28f7..b1c314093737 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5316,7 +5316,7 @@
#define GAMMA_MODE_MODE_10BIT (1 << 0)
#define GAMMA_MODE_MODE_12BIT (2 << 0)
#define GAMMA_MODE_MODE_SPLIT (3 << 0) /* ivb-bdw */
-#define GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED (3 << 0) /* icl + */
+#define GAMMA_MODE_MODE_12BIT_MULTI_SEG (3 << 0) /* icl-tgl */
/* Display Internal Timeout Register */
#define RM_TIMEOUT _MMIO(0x42060)
--
2.37.4
next prev parent reply other threads:[~2022-11-23 15:27 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-23 15:26 [Intel-gfx] [PATCH 00/13] drm/i915: Gamma/DSB prep work Ville Syrjala
2022-11-23 15:26 ` Ville Syrjala [this message]
2022-12-01 5:40 ` [Intel-gfx] [PATCH 01/13] drm/i915: Shorten GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED a bit Nautiyal, Ankit K
2022-12-07 5:28 ` Shankar, Uma
2022-11-23 15:26 ` [Intel-gfx] [PATCH 02/13] drm/i915: Clean up GAMMA_MODE defines Ville Syrjala
2022-12-01 5:42 ` Nautiyal, Ankit K
2022-11-23 15:26 ` [Intel-gfx] [PATCH 03/13] drm/i915: Define skl+ palette anti-collision bit Ville Syrjala
2022-12-07 5:49 ` Shankar, Uma
2022-11-23 15:26 ` [Intel-gfx] [PATCH 04/13] drm/i915: Clean up various indexed LUT registers Ville Syrjala
2022-12-01 5:45 ` Nautiyal, Ankit K
2022-12-07 8:45 ` Shankar, Uma
2022-12-07 10:22 ` Shankar, Uma
2022-11-23 15:26 ` [Intel-gfx] [PATCH 05/13] drm/i915: Standardize auto-increment LUT load procedure Ville Syrjala
2022-12-01 5:48 ` Nautiyal, Ankit K
2022-12-07 9:06 ` Shankar, Uma
2022-11-23 15:26 ` [Intel-gfx] [PATCH 06/13] drm/i915: Document LUT "max" register precision Ville Syrjala
2022-12-01 5:53 ` Nautiyal, Ankit K
2022-12-07 9:07 ` Shankar, Uma
2022-11-23 15:26 ` [Intel-gfx] [PATCH 07/13] drm/i915: Move the DSB->mmio fallback into the LUT code Ville Syrjala
2022-12-01 6:05 ` Nautiyal, Ankit K
2022-12-07 9:15 ` Shankar, Uma
2022-11-23 15:26 ` [Intel-gfx] [PATCH 08/13] drm/i915: Move the DSB setup/cleaup into the color code Ville Syrjala
2022-12-07 9:29 ` Shankar, Uma
2022-11-23 15:26 ` [Intel-gfx] [PATCH 09/13] drm/i915: Make DSB lower level Ville Syrjala
2022-12-01 6:21 ` Nautiyal, Ankit K
2022-12-07 9:44 ` Shankar, Uma
2022-11-23 15:26 ` [Intel-gfx] [PATCH 10/13] drm/i915: Disable DSB usage specifically for LUTs Ville Syrjala
2022-12-01 6:24 ` Nautiyal, Ankit K
2022-12-07 9:51 ` Shankar, Uma
2022-11-23 15:26 ` [Intel-gfx] [PATCH 11/13] Revert "drm/i915: Disable DSB usage for now" Ville Syrjala
2022-12-01 6:26 ` Nautiyal, Ankit K
2022-12-07 9:53 ` Shankar, Uma
2022-11-23 15:26 ` [Intel-gfx] [PATCH 12/13] drm/i915: Use ilk_lut_write*() for all ilk+ gamma modes Ville Syrjala
2022-12-07 10:18 ` Shankar, Uma
2022-11-23 15:26 ` [Intel-gfx] [PATCH 13/13] drm/i915: Do state check for color management changes Ville Syrjala
2022-11-23 18:24 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Gamma/DSB prep work Patchwork
2022-11-23 18:24 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-11-23 18:24 ` [Intel-gfx] ✗ Fi.CI.DOCS: " Patchwork
2022-11-23 18:43 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
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