From: Andi Shyti <andi.shyti@linux.intel.com>
To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org
Cc: "Thomas Hellström" <thomas.hellstrom@linux.intel.com>,
"Chris Wilson" <chris@chris-wilson.co.uk>,
"Matthew Auld" <matthew.auld@intel.com>
Subject: [Intel-gfx] [PATCH v4 1/5] drm/i915: Limit the display memory alignment to 32 bit instead of 64
Date: Thu, 1 Dec 2022 00:58:01 +0100 [thread overview]
Message-ID: <20221130235805.221010-2-andi.shyti@linux.intel.com> (raw)
In-Reply-To: <20221130235805.221010-1-andi.shyti@linux.intel.com>
The coming commit "drm/i915: Introduce guard pages to i915_vma"
from Chris, was originally changing display_alignment to u32
from u64. The reason is that the display GGTT is and will be
limited o 4GB.
Put it in a separate patch and use "max(...)" instead of
"max_t(64, ...)" when asigning the value. We can safely use max
as we know beforehand that the comparison is between two u32
variables.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
drivers/gpu/drm/i915/display/intel_fb_pin.c | 2 +-
drivers/gpu/drm/i915/gem/i915_gem_domain.c | 2 +-
drivers/gpu/drm/i915/i915_vma_types.h | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fb_pin.c b/drivers/gpu/drm/i915/display/intel_fb_pin.c
index 6900acbb1381c..1aca7552a85d0 100644
--- a/drivers/gpu/drm/i915/display/intel_fb_pin.c
+++ b/drivers/gpu/drm/i915/display/intel_fb_pin.c
@@ -91,7 +91,7 @@ intel_pin_fb_obj_dpt(struct drm_framebuffer *fb,
goto err;
}
- vma->display_alignment = max_t(u64, vma->display_alignment, alignment);
+ vma->display_alignment = max(vma->display_alignment, alignment);
i915_gem_object_flush_if_display(obj);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_domain.c b/drivers/gpu/drm/i915/gem/i915_gem_domain.c
index d44a152ce6800..850776a783ac7 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_domain.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_domain.c
@@ -444,7 +444,7 @@ i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
if (IS_ERR(vma))
return vma;
- vma->display_alignment = max_t(u64, vma->display_alignment, alignment);
+ vma->display_alignment = max(vma->display_alignment, alignment);
i915_vma_mark_scanout(vma);
i915_gem_object_flush_if_display_locked(obj);
diff --git a/drivers/gpu/drm/i915/i915_vma_types.h b/drivers/gpu/drm/i915/i915_vma_types.h
index ec0f6c9f57d02..0375812792b9c 100644
--- a/drivers/gpu/drm/i915/i915_vma_types.h
+++ b/drivers/gpu/drm/i915/i915_vma_types.h
@@ -197,7 +197,6 @@ struct i915_vma {
struct i915_fence_reg *fence;
u64 size;
- u64 display_alignment;
struct i915_page_sizes page_sizes;
/* mmap-offset associated with fencing for this vma */
@@ -205,6 +204,7 @@ struct i915_vma {
u32 fence_size;
u32 fence_alignment;
+ u32 display_alignment;
/**
* Count of the number of times this vma has been opened by different
--
2.38.1
next prev parent reply other threads:[~2022-11-30 23:58 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-30 23:58 [Intel-gfx] [PATCH v4 0/5] Add guard padding around i915_vma Andi Shyti
2022-11-30 23:58 ` Andi Shyti [this message]
2022-11-30 23:58 ` [Intel-gfx] [PATCH v4 2/5] drm/i915: Wrap all access to i915_vma.node.start|size Andi Shyti
2022-11-30 23:58 ` [Intel-gfx] [PATCH v4 3/5] drm/i915: Introduce guard pages to i915_vma Andi Shyti
2022-12-01 8:59 ` Tvrtko Ursulin
2022-12-01 10:45 ` Andi Shyti
2022-12-01 10:50 ` Tvrtko Ursulin
2022-12-01 14:44 ` [Intel-gfx] [PATCH v5 " Andi Shyti
2022-12-01 14:51 ` Tvrtko Ursulin
2022-12-01 20:39 ` [Intel-gfx] [PATCH v6 " Andi Shyti
2022-12-02 10:20 ` Tvrtko Ursulin
2022-12-02 11:11 ` Andi Shyti
2022-12-02 12:38 ` Tvrtko Ursulin
2022-11-30 23:58 ` [Intel-gfx] [PATCH v4 4/5] drm/i915: Refine VT-d scanout workaround Andi Shyti
2022-12-01 9:00 ` Tvrtko Ursulin
2022-11-30 23:58 ` [Intel-gfx] [PATCH v4 5/5] Revert "drm/i915: Improve on suspend / resume time with VT-d enabled" Andi Shyti
2022-12-01 9:02 ` Tvrtko Ursulin
2022-12-01 0:59 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for add guard padding around i915_vma (rev4) Patchwork
2022-12-01 0:59 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-12-01 1:26 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2022-12-01 15:01 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for add guard padding around i915_vma (rev5) Patchwork
2022-12-01 15:01 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-12-01 16:07 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2022-12-01 21:05 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for add guard padding around i915_vma (rev6) Patchwork
2022-12-01 21:30 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2022-12-02 14:13 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for add guard padding around i915_vma (rev7) Patchwork
2022-12-02 14:13 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-12-02 14:43 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-12-03 2:27 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2022-12-05 14:47 ` Andi Shyti
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