From: Andi Shyti <andi.shyti@linux.intel.com>
To: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Cc: "Thomas Hellström" <thomas.hellstrom@linux.intel.com>,
intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org,
"Chris Wilson" <chris@chris-wilson.co.uk>,
"Matthew Auld" <matthew.auld@intel.com>
Subject: Re: [Intel-gfx] [PATCH v6 3/5] drm/i915: Introduce guard pages to i915_vma
Date: Fri, 2 Dec 2022 12:11:30 +0100 [thread overview]
Message-ID: <Y4ndYv5C6K39C8PP@ashyti-mobl2.lan> (raw)
In-Reply-To: <8a8152b6-a7f9-7ecb-4e5b-2b961f8e3ee2@linux.intel.com>
Hi Tvrtko,
On Fri, Dec 02, 2022 at 10:20:11AM +0000, Tvrtko Ursulin wrote:
>
> On 01/12/2022 20:39, Andi Shyti wrote:
> > From: Chris Wilson <chris@chris-wilson.co.uk>
> >
> > Introduce the concept of padding the i915_vma with guard pages before
> > and after. The major consequence is that all ordinary uses of i915_vma
> > must use i915_vma_offset/i915_vma_size and not i915_vma.node.start/size
> > directly, as the drm_mm_node will include the guard pages that surround
> > our object.
> >
> > The biggest connundrum is how exactly to mix requesting a fixed address
> > with guard pages, particularly through the existing uABI. The user does
> > not know about guard pages, so such must be transparent to the user, and
> > so the execobj.offset must be that of the object itself excluding the
> > guard. So a PIN_OFFSET_FIXED must then be exclusive of the guard pages.
> > The caveat is that some placements will be impossible with guard pages,
> > as wrap arounds need to be avoided, and the vma itself will require a
> > larger node. We must not report EINVAL but ENOSPC as these are unavailable
> > locations within the GTT rather than conflicting user requirements.
> >
> > In the next patch, we start using guard pages for scanout objects. While
> > these are limited to GGTT vma, on a few platforms these vma (or at least
> > an alias of the vma) is shared with userspace, so we may leak the
> > existence of such guards if we are not careful to ensure that the
> > execobj.offset is transparent and excludes the guards. (On such platforms
> > like ivb, without full-ppgtt, userspace has to use relocations so the
> > presence of more untouchable regions within its GTT such be of no further
> > issue.)
> >
> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
> > Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> > Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
> > ---
> > Hi Tvrtko,
> >
> > I removed your r-b in this version because I restored the original value
> > of the guard being aligned with the vma size alignment. Turns out that
> > CI failed with the latest version because the guard was becoming too big
> > (we would have hit the GEM_BUG_ON)[*].
> >
> > The reason why now the guard is aligned with the vma alignment is that
> > the area is already aligned and if we use as a starting address start +
> > guard, guard needs to be aligned, otherwise we screw up all the memory
> > alignment.
> >
> > Let me know if it makes sense to you.
>
> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>
> Conditional to promise of a prioritised follow up improvement, if it turns
> out GGTT wastage due a bit over zealous guard size comes to bite.
Sure! I'll be alert!
There are some unrelated failures from CI, just to be sure I sent
last night a trybot run.
Thanks, Tvrtko!
Andi
next prev parent reply other threads:[~2022-12-02 11:13 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-30 23:58 [Intel-gfx] [PATCH v4 0/5] Add guard padding around i915_vma Andi Shyti
2022-11-30 23:58 ` [Intel-gfx] [PATCH v4 1/5] drm/i915: Limit the display memory alignment to 32 bit instead of 64 Andi Shyti
2022-11-30 23:58 ` [Intel-gfx] [PATCH v4 2/5] drm/i915: Wrap all access to i915_vma.node.start|size Andi Shyti
2022-11-30 23:58 ` [Intel-gfx] [PATCH v4 3/5] drm/i915: Introduce guard pages to i915_vma Andi Shyti
2022-12-01 8:59 ` Tvrtko Ursulin
2022-12-01 10:45 ` Andi Shyti
2022-12-01 10:50 ` Tvrtko Ursulin
2022-12-01 14:44 ` [Intel-gfx] [PATCH v5 " Andi Shyti
2022-12-01 14:51 ` Tvrtko Ursulin
2022-12-01 20:39 ` [Intel-gfx] [PATCH v6 " Andi Shyti
2022-12-02 10:20 ` Tvrtko Ursulin
2022-12-02 11:11 ` Andi Shyti [this message]
2022-12-02 12:38 ` Tvrtko Ursulin
2022-11-30 23:58 ` [Intel-gfx] [PATCH v4 4/5] drm/i915: Refine VT-d scanout workaround Andi Shyti
2022-12-01 9:00 ` Tvrtko Ursulin
2022-11-30 23:58 ` [Intel-gfx] [PATCH v4 5/5] Revert "drm/i915: Improve on suspend / resume time with VT-d enabled" Andi Shyti
2022-12-01 9:02 ` Tvrtko Ursulin
2022-12-01 0:59 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for add guard padding around i915_vma (rev4) Patchwork
2022-12-01 0:59 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-12-01 1:26 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2022-12-01 15:01 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for add guard padding around i915_vma (rev5) Patchwork
2022-12-01 15:01 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-12-01 16:07 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2022-12-01 21:05 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for add guard padding around i915_vma (rev6) Patchwork
2022-12-01 21:30 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2022-12-02 14:13 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for add guard padding around i915_vma (rev7) Patchwork
2022-12-02 14:13 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-12-02 14:43 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-12-03 2:27 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2022-12-05 14:47 ` Andi Shyti
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