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From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH 1/4] drm/i915/vrr: Make registers latch in a consitent place on icl/tgl
Date: Fri,  2 Dec 2022 15:44:09 +0200	[thread overview]
Message-ID: <20221202134412.21943-2-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <20221202134412.21943-1-ville.syrjala@linux.intel.com>

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Account for the framestart delay when calculating the "pipeline full"
value for icl/tgl vrr. This puts the start of vblank (ie. where the
double bufferd registers get latched) to a consistent place regardless
of what framestart delay value is used. framestart delay does not
change where start of vblank occurs in non-vrr mode and I can't see
any reason why we'd want different behaviour in vrr mode.

Currently framestart delay is always set to 1, and the hardcoded 4
scanlines in the code means we're currently delaying the start of
vblank by three extra lines. And with framestart delay set to 4 we'd
have no extra delay.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_vrr.c | 13 ++-----------
 1 file changed, 2 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 7b1357e82b69..6655dd2c1684 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -153,18 +153,9 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
 		crtc_state->vrr.guardband =
 			crtc_state->vrr.vmin - adjusted_mode->crtc_vdisplay;
 	} else {
-		/*
-		 * FIXME: s/4/framestart_delay/ to get consistent
-		 * earliest/latest points for register latching regardless
-		 * of the framestart_delay used?
-		 *
-		 * FIXME: this really needs the extra scanline to provide consistent
-		 * behaviour for all framestart_delay values. Otherwise with
-		 * framestart_delay==4 we will end up extending the min vblank by
-		 * one extra line.
-		 */
 		crtc_state->vrr.pipeline_full =
-			min(255, crtc_state->vrr.vmin - adjusted_mode->crtc_vdisplay - 4 - 1);
+			min(255, crtc_state->vrr.vmin - adjusted_mode->crtc_vdisplay -
+			    crtc_state->framestart_delay - 1);
 	}
 
 	crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
-- 
2.37.4


  reply	other threads:[~2022-12-02 13:44 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-12-02 13:44 [Intel-gfx] [PATCH 0/4] drm/i915/vrr: VRR fixes Ville Syrjala
2022-12-02 13:44 ` Ville Syrjala [this message]
2022-12-05 20:13   ` [Intel-gfx] [PATCH 1/4] drm/i915/vrr: Make registers latch in a consitent place on icl/tgl Navare, Manasi
2022-12-07 15:06     ` Ville Syrjälä
2022-12-02 13:44 ` [Intel-gfx] [PATCH 2/4] drm/i915/vrr: Fix guardband/vblank exit length calculation for adl+ Ville Syrjala
2022-12-05 20:34   ` Navare, Manasi
2022-12-07 15:10     ` Ville Syrjälä
2022-12-07 21:05       ` Navare, Manasi
2022-12-07 21:35         ` Ville Syrjälä
2022-12-08 18:42           ` Navare, Manasi
2022-12-02 13:44 ` [Intel-gfx] [PATCH 3/4] drm/i915/vrr: Reorder transcoder vs. vrr enable/disable Ville Syrjala
2022-12-05 20:48   ` Navare, Manasi
2022-12-02 13:44 ` [Intel-gfx] [PATCH 4/4] drm/i915/vrr: Be more careful with the bits in TRANS_VRR_CTL Ville Syrjala
2022-12-05 20:55   ` Navare, Manasi
2022-12-02 14:50 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/vrr: VRR fixes Patchwork
2022-12-02 15:23 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2022-12-07 17:05 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/vrr: VRR fixes (rev2) Patchwork
2022-12-07 17:24 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-12-07 22:34 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork

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