From: "Navare, Manasi" <manasi.d.navare@intel.com>
To: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 3/4] drm/i915/vrr: Reorder transcoder vs. vrr enable/disable
Date: Mon, 5 Dec 2022 12:48:43 -0800 [thread overview]
Message-ID: <20221205204843.GA1209860@mdnavare-mobl1.jf.intel.com> (raw)
In-Reply-To: <20221202134412.21943-4-ville.syrjala@linux.intel.com>
On Fri, Dec 02, 2022 at 03:44:11PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> On mtl it looks like disabling VRR after the transcoder has
> been disabled can cause the pipe/transcoder to get stuck
> when re-enabled in non-vrr mode. Reversing the order seems to
> help.
>
> Bspec is extremely confused about the VRR enable/disable sequence
> anyway, and this now more closely matches the non-modeset VRR
> sequence, whereas the full modeset sequence still claims that
> the original order is fine. But since we eventually want to toggle
> VRR without a full modeset anyway this seems like the better order
> to follow.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Manasi
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 5f9a2410fc4c..69595cbb2766 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -2726,10 +2726,10 @@ static void intel_ddi_post_disable(struct intel_atomic_state *state,
> if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST)) {
> intel_crtc_vblank_off(old_crtc_state);
>
> - intel_disable_transcoder(old_crtc_state);
> -
> intel_vrr_disable(old_crtc_state);
>
> + intel_disable_transcoder(old_crtc_state);
> +
> intel_ddi_disable_transcoder_func(old_crtc_state);
>
> intel_dsc_disable(old_crtc_state);
> @@ -2946,13 +2946,13 @@ static void intel_enable_ddi(struct intel_atomic_state *state,
> if (!intel_crtc_is_bigjoiner_slave(crtc_state))
> intel_ddi_enable_transcoder_func(encoder, crtc_state);
>
> - intel_vrr_enable(encoder, crtc_state);
> -
> /* Enable/Disable DP2.0 SDP split config before transcoder */
> intel_audio_sdp_split_update(encoder, crtc_state);
>
> intel_enable_transcoder(crtc_state);
>
> + intel_vrr_enable(encoder, crtc_state);
> +
> intel_crtc_vblank_on(crtc_state);
>
> if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
> --
> 2.37.4
>
next prev parent reply other threads:[~2022-12-05 20:48 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-12-02 13:44 [Intel-gfx] [PATCH 0/4] drm/i915/vrr: VRR fixes Ville Syrjala
2022-12-02 13:44 ` [Intel-gfx] [PATCH 1/4] drm/i915/vrr: Make registers latch in a consitent place on icl/tgl Ville Syrjala
2022-12-05 20:13 ` Navare, Manasi
2022-12-07 15:06 ` Ville Syrjälä
2022-12-02 13:44 ` [Intel-gfx] [PATCH 2/4] drm/i915/vrr: Fix guardband/vblank exit length calculation for adl+ Ville Syrjala
2022-12-05 20:34 ` Navare, Manasi
2022-12-07 15:10 ` Ville Syrjälä
2022-12-07 21:05 ` Navare, Manasi
2022-12-07 21:35 ` Ville Syrjälä
2022-12-08 18:42 ` Navare, Manasi
2022-12-02 13:44 ` [Intel-gfx] [PATCH 3/4] drm/i915/vrr: Reorder transcoder vs. vrr enable/disable Ville Syrjala
2022-12-05 20:48 ` Navare, Manasi [this message]
2022-12-02 13:44 ` [Intel-gfx] [PATCH 4/4] drm/i915/vrr: Be more careful with the bits in TRANS_VRR_CTL Ville Syrjala
2022-12-05 20:55 ` Navare, Manasi
2022-12-02 14:50 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/vrr: VRR fixes Patchwork
2022-12-02 15:23 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2022-12-07 17:05 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/vrr: VRR fixes (rev2) Patchwork
2022-12-07 17:24 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-12-07 22:34 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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