[Intel-gfx] [PATCH] drm/i915/selftests: keep same cache settings as timeline

[Intel-gfx] [PATCH] drm/i915/selftests: keep same cache settings as timeline

[fei.yang]

From: Fei Yang <fei.yang@intel.com>

On MTL, objects allocated through i915_gem_object_create_internal() are
mapped as uncached in GPU by default because HAS_LLC is false. However
in the live_hwsp_read selftest these watcher objects are mapped as WB
on CPU side. The conseqence is that the updates done by the GPU are not
immediately visible to CPU, thus the selftest is randomly failing due to
the stale data in CPU cache. Solution can be either setting WC for CPU +
UC for GPU, or WB for CPU + 1-way coherent WB for GPU.
To keep the consistency, let's simply inherit the same cache settings
from the timeline, which is WB for CPU + 1-way coherent WB for GPU,
because this test is supposed to emulate the behavior of the timeline
anyway.

v2: copy cache settings from timeline instead of setting it to WC
    (Suggested by Chris)

Signed-off-by: Fei Yang <fei.yang@intel.com>
Reviewed-by: Chris Wilson <chris.p.wilson@linux.intel.com>
Acked-by: Jonathan Cavitt <jonathan.cavitt@intel.com>
Acked-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/gt/selftest_timeline.c | 14 +++++++++++---
 1 file changed, 11 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/selftest_timeline.c b/drivers/gpu/drm/i915/gt/selftest_timeline.c
index 522d0190509c..631aaed9bc3d 100644
--- a/drivers/gpu/drm/i915/gt/selftest_timeline.c
+++ b/drivers/gpu/drm/i915/gt/selftest_timeline.c
@@ -825,7 +825,8 @@ static bool cmp_gte(u32 a, u32 b)
 	return a >= b;
 }
 
-static int setup_watcher(struct hwsp_watcher *w, struct intel_gt *gt)
+static int setup_watcher(struct hwsp_watcher *w, struct intel_gt *gt,
+			 struct intel_timeline *tl)
 {
 	struct drm_i915_gem_object *obj;
 	struct i915_vma *vma;
@@ -834,7 +835,10 @@ static int setup_watcher(struct hwsp_watcher *w, struct intel_gt *gt)
 	if (IS_ERR(obj))
 		return PTR_ERR(obj);
 
-	w->map = i915_gem_object_pin_map_unlocked(obj, I915_MAP_WB);
+	/* keep the same cache settings as timeline */
+	i915_gem_object_set_cache_coherency(obj, tl->hwsp_ggtt->obj->cache_level);
+	w->map = i915_gem_object_pin_map_unlocked(obj,
+			page_unmask_bits(tl->hwsp_ggtt->obj->mm.mapping));
 	if (IS_ERR(w->map)) {
 		i915_gem_object_put(obj);
 		return PTR_ERR(w->map);
@@ -1004,8 +1008,10 @@ static int live_hwsp_read(void *arg)
 	if (!tl->has_initial_breadcrumb)
 		goto out_free;
 
+	selftest_tl_pin(tl);
+
 	for (i = 0; i < ARRAY_SIZE(watcher); i++) {
-		err = setup_watcher(&watcher[i], gt);
+		err = setup_watcher(&watcher[i], gt, tl);
 		if (err)
 			goto out;
 	}
@@ -1160,6 +1166,8 @@ static int live_hwsp_read(void *arg)
 	for (i = 0; i < ARRAY_SIZE(watcher); i++)
 		cleanup_watcher(&watcher[i]);
 
+	intel_timeline_unpin(tl);
+
 	if (igt_flush_test(gt->i915))
 		err = -EIO;
 
-- 
2.25.1

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/selftests: keep same cache settings as timeline

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 3732 bytes --]

== Series Details ==

Series: drm/i915/selftests: keep same cache settings as timeline
URL   : https://patchwork.freedesktop.org/series/114879/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_12829 -> Patchwork_114879v1
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_114879v1 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_114879v1, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114879v1/index.html

Participating hosts (36 -> 33)
------------------------------

  Missing    (3): fi-kbl-soraka bat-rpls-2 fi-snb-2520m 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_114879v1:

### IGT changes ###

#### Possible regressions ####

  * igt@i915_selftest@live@gt_mocs:
    - bat-adlm-1:         [PASS][1] -> [INCOMPLETE][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12829/bat-adlm-1/igt@i915_selftest@live@gt_mocs.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114879v1/bat-adlm-1/igt@i915_selftest@live@gt_mocs.html

  
Known issues
------------

  Here are the changes found in Patchwork_114879v1 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_selftest@live@gt_lrc:
    - bat-adln-1:         [PASS][3] -> [INCOMPLETE][4] ([i915#7609])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12829/bat-adln-1/igt@i915_selftest@live@gt_lrc.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114879v1/bat-adln-1/igt@i915_selftest@live@gt_lrc.html

  * igt@i915_selftest@live@reset:
    - bat-rpls-1:         [PASS][5] -> [ABORT][6] ([i915#4983])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12829/bat-rpls-1/igt@i915_selftest@live@reset.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114879v1/bat-rpls-1/igt@i915_selftest@live@reset.html

  * igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence:
    - bat-dg2-11:         NOTRUN -> [SKIP][7] ([i915#5354]) +2 similar issues
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114879v1/bat-dg2-11/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence.html

  * igt@kms_pipe_crc_basic@suspend-read-crc@pipe-d-hdmi-a-3:
    - bat-dg2-11:         [PASS][8] -> [INCOMPLETE][9] ([i915#7908])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12829/bat-dg2-11/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-d-hdmi-a-3.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114879v1/bat-dg2-11/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-d-hdmi-a-3.html

  
  [i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
  [i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
  [i915#7609]: https://gitlab.freedesktop.org/drm/intel/issues/7609
  [i915#7908]: https://gitlab.freedesktop.org/drm/intel/issues/7908


Build changes
-------------

  * Linux: CI_DRM_12829 -> Patchwork_114879v1

  CI-20190529: 20190529
  CI_DRM_12829: d947159409deea43f404f35cc758740c714c8888 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7185: 6707461ddb214bb8a75c5fcf2747941c9d9b11ae @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_114879v1: d947159409deea43f404f35cc758740c714c8888 @ git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

cbae2647cd44 drm/i915/selftests: keep same cache settings as timeline

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114879v1/index.html

[-- Attachment #2: Type: text/html, Size: 4463 bytes --]

[Intel-gfx] [PATCH] drm/i915/selftests: keep same cache settings as timeline

[fei.yang]

From: Fei Yang <fei.yang@intel.com>

On MTL, objects allocated through i915_gem_object_create_internal() are
mapped as uncached in GPU by default because HAS_LLC is false. However
in the live_hwsp_read selftest these watcher objects are mapped as WB
on CPU side. The conseqence is that the updates done by the GPU are not
immediately visible to CPU, thus the selftest is randomly failing due to
the stale data in CPU cache. Solution can be either setting WC for CPU +
UC for GPU, or WB for CPU + 1-way coherent WB for GPU.
To keep the consistency, let's simply inherit the same cache settings
from the timeline, which is WB for CPU + 1-way coherent WB for GPU,
because this test is supposed to emulate the behavior of the timeline
anyway.

Signed-off-by: Fei Yang <fei.yang@intel.com>
---
 drivers/gpu/drm/i915/gt/selftest_timeline.c | 14 +++++++++++---
 1 file changed, 11 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/selftest_timeline.c b/drivers/gpu/drm/i915/gt/selftest_timeline.c
index 522d0190509c..631aaed9bc3d 100644
--- a/drivers/gpu/drm/i915/gt/selftest_timeline.c
+++ b/drivers/gpu/drm/i915/gt/selftest_timeline.c
@@ -825,7 +825,8 @@ static bool cmp_gte(u32 a, u32 b)
 	return a >= b;
 }
 
-static int setup_watcher(struct hwsp_watcher *w, struct intel_gt *gt)
+static int setup_watcher(struct hwsp_watcher *w, struct intel_gt *gt,
+			 struct intel_timeline *tl)
 {
 	struct drm_i915_gem_object *obj;
 	struct i915_vma *vma;
@@ -834,7 +835,10 @@ static int setup_watcher(struct hwsp_watcher *w, struct intel_gt *gt)
 	if (IS_ERR(obj))
 		return PTR_ERR(obj);
 
-	w->map = i915_gem_object_pin_map_unlocked(obj, I915_MAP_WB);
+	/* keep the same cache settings as timeline */
+	i915_gem_object_set_cache_coherency(obj, tl->hwsp_ggtt->obj->cache_level);
+	w->map = i915_gem_object_pin_map_unlocked(obj,
+			page_unmask_bits(tl->hwsp_ggtt->obj->mm.mapping));
 	if (IS_ERR(w->map)) {
 		i915_gem_object_put(obj);
 		return PTR_ERR(w->map);
@@ -1004,8 +1008,10 @@ static int live_hwsp_read(void *arg)
 	if (!tl->has_initial_breadcrumb)
 		goto out_free;
 
+	selftest_tl_pin(tl);
+
 	for (i = 0; i < ARRAY_SIZE(watcher); i++) {
-		err = setup_watcher(&watcher[i], gt);
+		err = setup_watcher(&watcher[i], gt, tl);
 		if (err)
 			goto out;
 	}
@@ -1160,6 +1166,8 @@ static int live_hwsp_read(void *arg)
 	for (i = 0; i < ARRAY_SIZE(watcher); i++)
 		cleanup_watcher(&watcher[i]);
 
+	intel_timeline_unpin(tl);
+
 	if (igt_flush_test(gt->i915))
 		err = -EIO;
 
-- 
2.25.1

Re: [Intel-gfx] [PATCH] drm/i915/selftests: keep same cache settings as timeline

[Matt Roper]

On Wed, Mar 15, 2023 at 11:08:00AM -0700, fei.yang@intel.com wrote:
> From: Fei Yang <fei.yang@intel.com>
> 
> On MTL, objects allocated through i915_gem_object_create_internal() are
> mapped as uncached in GPU by default because HAS_LLC is false. However
> in the live_hwsp_read selftest these watcher objects are mapped as WB
> on CPU side. The conseqence is that the updates done by the GPU are not
> immediately visible to CPU, thus the selftest is randomly failing due to
> the stale data in CPU cache. Solution can be either setting WC for CPU +
> UC for GPU, or WB for CPU + 1-way coherent WB for GPU.
> To keep the consistency, let's simply inherit the same cache settings
> from the timeline, which is WB for CPU + 1-way coherent WB for GPU,
> because this test is supposed to emulate the behavior of the timeline
> anyway.
> 
> Signed-off-by: Fei Yang <fei.yang@intel.com>

It looks like there might be an indentation mistake on the second line
of the i915_gem_object_pin_map_unlocked() call, but we can fix that up
while applying; no need to re-send.

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

Is there an FDO issue # for the random failures thar were being seen?
If so, we should add a Closes: or References: tag here.


Matt

> ---
>  drivers/gpu/drm/i915/gt/selftest_timeline.c | 14 +++++++++++---
>  1 file changed, 11 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/selftest_timeline.c b/drivers/gpu/drm/i915/gt/selftest_timeline.c
> index 522d0190509c..631aaed9bc3d 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_timeline.c
> +++ b/drivers/gpu/drm/i915/gt/selftest_timeline.c
> @@ -825,7 +825,8 @@ static bool cmp_gte(u32 a, u32 b)
>  	return a >= b;
>  }
>  
> -static int setup_watcher(struct hwsp_watcher *w, struct intel_gt *gt)
> +static int setup_watcher(struct hwsp_watcher *w, struct intel_gt *gt,
> +			 struct intel_timeline *tl)
>  {
>  	struct drm_i915_gem_object *obj;
>  	struct i915_vma *vma;
> @@ -834,7 +835,10 @@ static int setup_watcher(struct hwsp_watcher *w, struct intel_gt *gt)
>  	if (IS_ERR(obj))
>  		return PTR_ERR(obj);
>  
> -	w->map = i915_gem_object_pin_map_unlocked(obj, I915_MAP_WB);
> +	/* keep the same cache settings as timeline */
> +	i915_gem_object_set_cache_coherency(obj, tl->hwsp_ggtt->obj->cache_level);
> +	w->map = i915_gem_object_pin_map_unlocked(obj,
> +			page_unmask_bits(tl->hwsp_ggtt->obj->mm.mapping));
>  	if (IS_ERR(w->map)) {
>  		i915_gem_object_put(obj);
>  		return PTR_ERR(w->map);
> @@ -1004,8 +1008,10 @@ static int live_hwsp_read(void *arg)
>  	if (!tl->has_initial_breadcrumb)
>  		goto out_free;
>  
> +	selftest_tl_pin(tl);
> +
>  	for (i = 0; i < ARRAY_SIZE(watcher); i++) {
> -		err = setup_watcher(&watcher[i], gt);
> +		err = setup_watcher(&watcher[i], gt, tl);
>  		if (err)
>  			goto out;
>  	}
> @@ -1160,6 +1166,8 @@ static int live_hwsp_read(void *arg)
>  	for (i = 0; i < ARRAY_SIZE(watcher); i++)
>  		cleanup_watcher(&watcher[i]);
>  
> +	intel_timeline_unpin(tl);
> +
>  	if (igt_flush_test(gt->i915))
>  		err = -EIO;
>  
> -- 
> 2.25.1
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [Intel-gfx] [PATCH] drm/i915/selftests: keep same cache settings as timeline

[Yang, Fei]

>> From: Fei Yang <fei.yang@intel.com>
>>
>> On MTL, objects allocated through i915_gem_object_create_internal() are
>> mapped as uncached in GPU by default because HAS_LLC is false. However
>> in the live_hwsp_read selftest these watcher objects are mapped as WB
>> on CPU side. The conseqence is that the updates done by the GPU are not
>> immediately visible to CPU, thus the selftest is randomly failing due to
>> the stale data in CPU cache. Solution can be either setting WC for CPU +
>> UC for GPU, or WB for CPU + 1-way coherent WB for GPU.
>> To keep the consistency, let's simply inherit the same cache settings
>> from the timeline, which is WB for CPU + 1-way coherent WB for GPU,
>> because this test is supposed to emulate the behavior of the timeline
>> anyway.
>>
>> Signed-off-by: Fei Yang <fei.yang@intel.com>
>
> It looks like there might be an indentation mistake on the second line
> of the i915_gem_object_pin_map_unlocked() call, but we can fix that up
> while applying; no need to re-send.
>
> Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

Thanks for reviewing.

> Is there an FDO issue # for the random failures thar were being seen?
> If so, we should add a Closes: or References: tag here.

I'm not aware of a FDO filed for this failure. That might be because the
issue is reproduced on MTL which might not be widely available to the
community yet.

> Matt
>> ---
>>  drivers/gpu/drm/i915/gt/selftest_timeline.c | 14 +++++++++++---
>>  1 file changed, 11 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/gt/selftest_timeline.c b/drivers/gpu/drm/i915/gt/selftest_timeline.c
>> index 522d0190509c..631aaed9bc3d 100644
>> --- a/drivers/gpu/drm/i915/gt/selftest_timeline.c
>> +++ b/drivers/gpu/drm/i915/gt/selftest_timeline.c
>> @@ -825,7 +825,8 @@ static bool cmp_gte(u32 a, u32 b)
>>        return a >= b;
>>  }
>>
>> -static int setup_watcher(struct hwsp_watcher *w, struct intel_gt *gt)
>> +static int setup_watcher(struct hwsp_watcher *w, struct intel_gt *gt,
>> +                      struct intel_timeline *tl)
>>  {
>>        struct drm_i915_gem_object *obj;
>>        struct i915_vma *vma;
>> @@ -834,7 +835,10 @@ static int setup_watcher(struct hwsp_watcher *w, struct intel_gt *gt)
>>        if (IS_ERR(obj))
>>                return PTR_ERR(obj);
>>
>> -     w->map = i915_gem_object_pin_map_unlocked(obj, I915_MAP_WB);
>> +     /* keep the same cache settings as timeline */
>> +     i915_gem_object_set_cache_coherency(obj, tl->hwsp_ggtt->obj->cache_level);
>> +     w->map = i915_gem_object_pin_map_unlocked(obj,
>> +                     page_unmask_bits(tl->hwsp_ggtt->obj->mm.mapping));
>>        if (IS_ERR(w->map)) {
>>                i915_gem_object_put(obj);
>>                return PTR_ERR(w->map);
>> @@ -1004,8 +1008,10 @@ static int live_hwsp_read(void *arg)
>>        if (!tl->has_initial_breadcrumb)
>>                goto out_free;
>>
>> +     selftest_tl_pin(tl);
>> +
>>        for (i = 0; i < ARRAY_SIZE(watcher); i++) {
>> -             err = setup_watcher(&watcher[i], gt);
>> +             err = setup_watcher(&watcher[i], gt, tl);
>>                if (err)
>>                        goto out;
>>        }
>> @@ -1160,6 +1166,8 @@ static int live_hwsp_read(void *arg)
>>        for (i = 0; i < ARRAY_SIZE(watcher); i++)
>>                cleanup_watcher(&watcher[i]);
>>
>> +     intel_timeline_unpin(tl);
>> +
>>        if (igt_flush_test(gt->i915))
>>                err = -EIO;
>>
>> --
>> 2.25.1

Re: [Intel-gfx] [PATCH] drm/i915/selftests: keep same cache settings as timeline

[Matt Roper]

On Thu, Mar 16, 2023 at 08:43:46PM -0700, Yang, Fei wrote:
> >> From: Fei Yang <fei.yang@intel.com>
> >>
> >> On MTL, objects allocated through i915_gem_object_create_internal() are
> >> mapped as uncached in GPU by default because HAS_LLC is false. However
> >> in the live_hwsp_read selftest these watcher objects are mapped as WB
> >> on CPU side. The conseqence is that the updates done by the GPU are not
> >> immediately visible to CPU, thus the selftest is randomly failing due to
> >> the stale data in CPU cache. Solution can be either setting WC for CPU +
> >> UC for GPU, or WB for CPU + 1-way coherent WB for GPU.
> >> To keep the consistency, let's simply inherit the same cache settings
> >> from the timeline, which is WB for CPU + 1-way coherent WB for GPU,
> >> because this test is supposed to emulate the behavior of the timeline
> >> anyway.
> >>
> >> Signed-off-by: Fei Yang <fei.yang@intel.com>
> >
> > It looks like there might be an indentation mistake on the second line
> > of the i915_gem_object_pin_map_unlocked() call, but we can fix that up
> > while applying; no need to re-send.
> >
> > Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> 
> Thanks for reviewing.
> 
> > Is there an FDO issue # for the random failures thar were being seen?
> > If so, we should add a Closes: or References: tag here.
> 
> I'm not aware of a FDO filed for this failure. That might be because the
> issue is reproduced on MTL which might not be widely available to the
> community yet.

Yeah, I was thinking CI would have filed some, but I just remembered we
don't have public CI setup yet for MTL, so no automated bugs are coming
in yet.

Applied to drm-intel-gt-next.  Thanks for the patch.


Matt

> 
> > Matt
> >> ---
> >>  drivers/gpu/drm/i915/gt/selftest_timeline.c | 14 +++++++++++---
> >>  1 file changed, 11 insertions(+), 3 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/gt/selftest_timeline.c b/drivers/gpu/drm/i915/gt/selftest_timeline.c
> >> index 522d0190509c..631aaed9bc3d 100644
> >> --- a/drivers/gpu/drm/i915/gt/selftest_timeline.c
> >> +++ b/drivers/gpu/drm/i915/gt/selftest_timeline.c
> >> @@ -825,7 +825,8 @@ static bool cmp_gte(u32 a, u32 b)
> >>        return a >= b;
> >>  }
> >>
> >> -static int setup_watcher(struct hwsp_watcher *w, struct intel_gt *gt)
> >> +static int setup_watcher(struct hwsp_watcher *w, struct intel_gt *gt,
> >> +                      struct intel_timeline *tl)
> >>  {
> >>        struct drm_i915_gem_object *obj;
> >>        struct i915_vma *vma;
> >> @@ -834,7 +835,10 @@ static int setup_watcher(struct hwsp_watcher *w, struct intel_gt *gt)
> >>        if (IS_ERR(obj))
> >>                return PTR_ERR(obj);
> >>
> >> -     w->map = i915_gem_object_pin_map_unlocked(obj, I915_MAP_WB);
> >> +     /* keep the same cache settings as timeline */
> >> +     i915_gem_object_set_cache_coherency(obj, tl->hwsp_ggtt->obj->cache_level);
> >> +     w->map = i915_gem_object_pin_map_unlocked(obj,
> >> +                     page_unmask_bits(tl->hwsp_ggtt->obj->mm.mapping));
> >>        if (IS_ERR(w->map)) {
> >>                i915_gem_object_put(obj);
> >>                return PTR_ERR(w->map);
> >> @@ -1004,8 +1008,10 @@ static int live_hwsp_read(void *arg)
> >>        if (!tl->has_initial_breadcrumb)
> >>                goto out_free;
> >>
> >> +     selftest_tl_pin(tl);
> >> +
> >>        for (i = 0; i < ARRAY_SIZE(watcher); i++) {
> >> -             err = setup_watcher(&watcher[i], gt);
> >> +             err = setup_watcher(&watcher[i], gt, tl);
> >>                if (err)
> >>                        goto out;
> >>        }
> >> @@ -1160,6 +1166,8 @@ static int live_hwsp_read(void *arg)
> >>        for (i = 0; i < ARRAY_SIZE(watcher); i++)
> >>                cleanup_watcher(&watcher[i]);
> >>
> >> +     intel_timeline_unpin(tl);
> >> +
> >>        if (igt_flush_test(gt->i915))
> >>                err = -EIO;
> >>
> >> --
> >> 2.25.1

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation