[Intel-gfx] [PATCH 0/5] More MTL WA and powerwell patches

[Intel-gfx] [PATCH 0/5] More MTL WA and powerwell patches

[Radhakrishna Sripada]

This series adds 2 MTL WA's, 2 patches to fix re-use
"DC off" power wells and another patch to sync BIOS and
driver for C6 enabling.

Haridhar Kalvala (1):
  drm/i915/mtl: WA to clear RDOP clock gating

Madhumitha Tolakanahalli Pradeep (1):
  drm/i915/mtl: Extend Wa_22011802037 to MTL A-step

Matt Roper (2):
  drm/i915: Use separate "DC off" power well for ADL-P and DG2
  drm/i915/mtl: Re-use ADL-P's "DC off" power well

Vinay Belgaumkar (1):
  drm/i915/mtl: Synchronize i915/BIOS on C6 enabling

 .../i915/display/intel_display_power_map.c    | 57 +++++++++++++------
 drivers/gpu/drm/i915/gt/intel_rc6.c           | 21 +++++++
 drivers/gpu/drm/i915/gt/intel_rc6_types.h     |  1 +
 drivers/gpu/drm/i915/gt/intel_workarounds.c   |  3 +
 .../gpu/drm/i915/gt/uc/intel_guc_submission.c |  4 +-
 5 files changed, 67 insertions(+), 19 deletions(-)

-- 
2.34.1

[Intel-gfx] [PATCH 1/5] drm/i915: Use separate "DC off" power well for ADL-P and DG2

[Radhakrishna Sripada]

From: Matt Roper <matthew.d.roper@intel.com>

Although ADL-P and DG2 both use the same general power well setup, the
DC5/DC6 requirements are slightly different which means each platform
should have its own "DC off" power well.

DG2 (i.e., Xe_HPD IP) requires that DC5 be disabled whenever PG2 is
active.  However ADL-P (i.e., Xe_LPD IP) only requires DC5/DC6 to be
disabled when the PGC or PGD subwells are active; we should be able to
remain in these DC states when PGB and general PG2 functionality is in
use.

Bspec: 49193
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
---
 .../i915/display/intel_display_power_map.c    | 41 +++++++++++++++++--
 1 file changed, 38 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c b/drivers/gpu/drm/i915/display/intel_display_power_map.c
index 6645eb1911d8..d9e02cc9cf3c 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_map.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c
@@ -1301,7 +1301,8 @@ I915_DECL_PW_DOMAINS(xelpd_pwdoms_pw_2,
  */
 
 I915_DECL_PW_DOMAINS(xelpd_pwdoms_dc_off,
-	XELPD_PW_2_POWER_DOMAINS,
+	XELPD_PW_C_POWER_DOMAINS,
+	XELPD_PW_D_POWER_DOMAINS,
 	POWER_DOMAIN_PORT_DSI,
 	POWER_DOMAIN_AUDIO_MMIO,
 	POWER_DOMAIN_AUX_A,
@@ -1310,14 +1311,38 @@ I915_DECL_PW_DOMAINS(xelpd_pwdoms_dc_off,
 	POWER_DOMAIN_DC_OFF,
 	POWER_DOMAIN_INIT);
 
-static const struct i915_power_well_desc xelpd_power_wells_main[] = {
+static const struct i915_power_well_desc xelpd_power_wells_dcoff[] = {
 	{
 		.instances = &I915_PW_INSTANCES(
 			I915_PW("DC_off", &xelpd_pwdoms_dc_off,
 				.id = SKL_DISP_DC_OFF),
 		),
 		.ops = &gen9_dc_off_power_well_ops,
-	}, {
+	}
+};
+
+I915_DECL_PW_DOMAINS(xehpd_pwdoms_dc_off,
+	XELPD_PW_2_POWER_DOMAINS,
+	POWER_DOMAIN_PORT_DSI,
+	POWER_DOMAIN_AUDIO_MMIO,
+	POWER_DOMAIN_AUX_A,
+	POWER_DOMAIN_AUX_B,
+	POWER_DOMAIN_MODESET,
+	POWER_DOMAIN_DC_OFF,
+	POWER_DOMAIN_INIT);
+
+static const struct i915_power_well_desc xehpd_power_wells_dcoff[] = {
+	{
+		.instances = &I915_PW_INSTANCES(
+			I915_PW("DC_off", &xehpd_pwdoms_dc_off,
+				.id = SKL_DISP_DC_OFF),
+		),
+		.ops = &gen9_dc_off_power_well_ops,
+	}
+};
+
+static const struct i915_power_well_desc xelpd_power_wells_main[] = {
+	{
 		.instances = &I915_PW_INSTANCES(
 			I915_PW("PW_2", &xelpd_pwdoms_pw_2,
 				.hsw.idx = ICL_PW_CTL_IDX_PW_2,
@@ -1400,6 +1425,14 @@ static const struct i915_power_well_desc xelpd_power_wells_main[] = {
 static const struct i915_power_well_desc_list xelpd_power_wells[] = {
 	I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
 	I915_PW_DESCRIPTORS(icl_power_wells_pw_1),
+	I915_PW_DESCRIPTORS(xelpd_power_wells_dcoff),
+	I915_PW_DESCRIPTORS(xelpd_power_wells_main),
+};
+
+static const struct i915_power_well_desc_list xehpd_power_wells[] = {
+	I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
+	I915_PW_DESCRIPTORS(icl_power_wells_pw_1),
+	I915_PW_DESCRIPTORS(xehpd_power_wells_dcoff),
 	I915_PW_DESCRIPTORS(xelpd_power_wells_main),
 };
 
@@ -1624,6 +1657,8 @@ int intel_display_power_map_init(struct i915_power_domains *power_domains)
 
 	if (DISPLAY_VER(i915) >= 14)
 		return set_power_wells(power_domains, xelpdp_power_wells);
+	else if (IS_DG2(i915))
+		return set_power_wells(power_domains, xehpd_power_wells);
 	else if (DISPLAY_VER(i915) >= 13)
 		return set_power_wells(power_domains, xelpd_power_wells);
 	else if (IS_DG1(i915))
-- 
2.34.1

Re: [Intel-gfx] [PATCH 1/5] drm/i915: Use separate "DC off" power well for ADL-P and DG2

[Imre Deak]

On Thu, Mar 16, 2023 at 01:25:45PM -0700, Radhakrishna Sripada wrote:
> From: Matt Roper <matthew.d.roper@intel.com>
> 
> Although ADL-P and DG2 both use the same general power well setup, the
> DC5/DC6 requirements are slightly different which means each platform
> should have its own "DC off" power well.
> 
> DG2 (i.e., Xe_HPD IP) requires that DC5 be disabled whenever PG2 is
> active.  However ADL-P (i.e., Xe_LPD IP) only requires DC5/DC6 to be
> disabled when the PGC or PGD subwells are active; we should be able to
> remain in these DC states when PGB and general PG2 functionality is in
> use.
> 
> Bspec: 49193
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> ---
>  .../i915/display/intel_display_power_map.c    | 41 +++++++++++++++++--
>  1 file changed, 38 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c b/drivers/gpu/drm/i915/display/intel_display_power_map.c
> index 6645eb1911d8..d9e02cc9cf3c 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power_map.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c
> @@ -1301,7 +1301,8 @@ I915_DECL_PW_DOMAINS(xelpd_pwdoms_pw_2,
>   */
>  
>  I915_DECL_PW_DOMAINS(xelpd_pwdoms_dc_off,
> -	XELPD_PW_2_POWER_DOMAINS,
> +	XELPD_PW_C_POWER_DOMAINS,
> +	XELPD_PW_D_POWER_DOMAINS,
>  	POWER_DOMAIN_PORT_DSI,
>  	POWER_DOMAIN_AUDIO_MMIO,
>  	POWER_DOMAIN_AUX_A,
> @@ -1310,14 +1311,38 @@ I915_DECL_PW_DOMAINS(xelpd_pwdoms_dc_off,
>  	POWER_DOMAIN_DC_OFF,
>  	POWER_DOMAIN_INIT);
>  
> -static const struct i915_power_well_desc xelpd_power_wells_main[] = {
> +static const struct i915_power_well_desc xelpd_power_wells_dcoff[] = {

Nit: Here and in the xehpd defintion, s/dcoff/dc_off/ to match other platforms.

>  	{
>  		.instances = &I915_PW_INSTANCES(
>  			I915_PW("DC_off", &xelpd_pwdoms_dc_off,
>  				.id = SKL_DISP_DC_OFF),
>  		),
>  		.ops = &gen9_dc_off_power_well_ops,
> -	}, {
> +	}
> +};
> +
> +I915_DECL_PW_DOMAINS(xehpd_pwdoms_dc_off,
> +	XELPD_PW_2_POWER_DOMAINS,
> +	POWER_DOMAIN_PORT_DSI,
> +	POWER_DOMAIN_AUDIO_MMIO,
> +	POWER_DOMAIN_AUX_A,
> +	POWER_DOMAIN_AUX_B,
> +	POWER_DOMAIN_MODESET,
> +	POWER_DOMAIN_DC_OFF,
> +	POWER_DOMAIN_INIT);
> +
> +static const struct i915_power_well_desc xehpd_power_wells_dcoff[] = {
> +	{
> +		.instances = &I915_PW_INSTANCES(
> +			I915_PW("DC_off", &xehpd_pwdoms_dc_off,
> +				.id = SKL_DISP_DC_OFF),
> +		),
> +		.ops = &gen9_dc_off_power_well_ops,
> +	}
> +};

Could you move the xehpd definitions to precede xehpd_power_wells[]?

Patches 1, 2 look ok to me:
Reviewed-by: Imre Deak <imre.deak@intel.com>

> +
> +static const struct i915_power_well_desc xelpd_power_wells_main[] = {
> +	{
>  		.instances = &I915_PW_INSTANCES(
>  			I915_PW("PW_2", &xelpd_pwdoms_pw_2,
>  				.hsw.idx = ICL_PW_CTL_IDX_PW_2,
> @@ -1400,6 +1425,14 @@ static const struct i915_power_well_desc xelpd_power_wells_main[] = {
>  static const struct i915_power_well_desc_list xelpd_power_wells[] = {
>  	I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
>  	I915_PW_DESCRIPTORS(icl_power_wells_pw_1),
> +	I915_PW_DESCRIPTORS(xelpd_power_wells_dcoff),
> +	I915_PW_DESCRIPTORS(xelpd_power_wells_main),
> +};
> +
> +static const struct i915_power_well_desc_list xehpd_power_wells[] = {
> +	I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
> +	I915_PW_DESCRIPTORS(icl_power_wells_pw_1),
> +	I915_PW_DESCRIPTORS(xehpd_power_wells_dcoff),
>  	I915_PW_DESCRIPTORS(xelpd_power_wells_main),
>  };
>  
> @@ -1624,6 +1657,8 @@ int intel_display_power_map_init(struct i915_power_domains *power_domains)
>  
>  	if (DISPLAY_VER(i915) >= 14)
>  		return set_power_wells(power_domains, xelpdp_power_wells);
> +	else if (IS_DG2(i915))
> +		return set_power_wells(power_domains, xehpd_power_wells);
>  	else if (DISPLAY_VER(i915) >= 13)
>  		return set_power_wells(power_domains, xelpd_power_wells);
>  	else if (IS_DG1(i915))
> -- 
> 2.34.1
> 

Re: [Intel-gfx] [PATCH 1/5] drm/i915: Use separate "DC off" power well for ADL-P and DG2

[Sripada, Radhakrishna]

> -----Original Message-----
> From: Deak, Imre <imre.deak@intel.com>
> Sent: Friday, March 17, 2023 10:43 AM
> To: Sripada, Radhakrishna <radhakrishna.sripada@intel.com>
> Cc: intel-gfx@lists.freedesktop.org; De Marchi, Lucas
> <lucas.demarchi@intel.com>
> Subject: Re: [Intel-gfx] [PATCH 1/5] drm/i915: Use separate "DC off" power well
> for ADL-P and DG2
> 
> On Thu, Mar 16, 2023 at 01:25:45PM -0700, Radhakrishna Sripada wrote:
> > From: Matt Roper <matthew.d.roper@intel.com>
> >
> > Although ADL-P and DG2 both use the same general power well setup, the
> > DC5/DC6 requirements are slightly different which means each platform
> > should have its own "DC off" power well.
> >
> > DG2 (i.e., Xe_HPD IP) requires that DC5 be disabled whenever PG2 is
> > active.  However ADL-P (i.e., Xe_LPD IP) only requires DC5/DC6 to be
> > disabled when the PGC or PGD subwells are active; we should be able to
> > remain in these DC states when PGB and general PG2 functionality is in
> > use.
> >
> > Bspec: 49193
> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> > ---
> >  .../i915/display/intel_display_power_map.c    | 41 +++++++++++++++++--
> >  1 file changed, 38 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c
> b/drivers/gpu/drm/i915/display/intel_display_power_map.c
> > index 6645eb1911d8..d9e02cc9cf3c 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_power_map.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c
> > @@ -1301,7 +1301,8 @@ I915_DECL_PW_DOMAINS(xelpd_pwdoms_pw_2,
> >   */
> >
> >  I915_DECL_PW_DOMAINS(xelpd_pwdoms_dc_off,
> > -	XELPD_PW_2_POWER_DOMAINS,
> > +	XELPD_PW_C_POWER_DOMAINS,
> > +	XELPD_PW_D_POWER_DOMAINS,
> >  	POWER_DOMAIN_PORT_DSI,
> >  	POWER_DOMAIN_AUDIO_MMIO,
> >  	POWER_DOMAIN_AUX_A,
> > @@ -1310,14 +1311,38 @@
> I915_DECL_PW_DOMAINS(xelpd_pwdoms_dc_off,
> >  	POWER_DOMAIN_DC_OFF,
> >  	POWER_DOMAIN_INIT);
> >
> > -static const struct i915_power_well_desc xelpd_power_wells_main[] = {
> > +static const struct i915_power_well_desc xelpd_power_wells_dcoff[] = {
> 
> Nit: Here and in the xehpd defintion, s/dcoff/dc_off/ to match other platforms.
> 
> >  	{
> >  		.instances = &I915_PW_INSTANCES(
> >  			I915_PW("DC_off", &xelpd_pwdoms_dc_off,
> >  				.id = SKL_DISP_DC_OFF),
> >  		),
> >  		.ops = &gen9_dc_off_power_well_ops,
> > -	}, {
> > +	}
> > +};
> > +
> > +I915_DECL_PW_DOMAINS(xehpd_pwdoms_dc_off,
> > +	XELPD_PW_2_POWER_DOMAINS,
> > +	POWER_DOMAIN_PORT_DSI,
> > +	POWER_DOMAIN_AUDIO_MMIO,
> > +	POWER_DOMAIN_AUX_A,
> > +	POWER_DOMAIN_AUX_B,
> > +	POWER_DOMAIN_MODESET,
> > +	POWER_DOMAIN_DC_OFF,
> > +	POWER_DOMAIN_INIT);
> > +
> > +static const struct i915_power_well_desc xehpd_power_wells_dcoff[] = {
> > +	{
> > +		.instances = &I915_PW_INSTANCES(
> > +			I915_PW("DC_off", &xehpd_pwdoms_dc_off,
> > +				.id = SKL_DISP_DC_OFF),
> > +		),
> > +		.ops = &gen9_dc_off_power_well_ops,
> > +	}
> > +};
> 
> Could you move the xehpd definitions to precede xehpd_power_wells[]?
> 
> Patches 1, 2 look ok to me:
> Reviewed-by: Imre Deak <imre.deak@intel.com>
Thank you for the R-b merged Patches 1, 2

- Radhakrishna(RK) Sripada
> 
> > +
> > +static const struct i915_power_well_desc xelpd_power_wells_main[] = {
> > +	{
> >  		.instances = &I915_PW_INSTANCES(
> >  			I915_PW("PW_2", &xelpd_pwdoms_pw_2,
> >  				.hsw.idx = ICL_PW_CTL_IDX_PW_2,
> > @@ -1400,6 +1425,14 @@ static const struct i915_power_well_desc
> xelpd_power_wells_main[] = {
> >  static const struct i915_power_well_desc_list xelpd_power_wells[] = {
> >  	I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
> >  	I915_PW_DESCRIPTORS(icl_power_wells_pw_1),
> > +	I915_PW_DESCRIPTORS(xelpd_power_wells_dcoff),
> > +	I915_PW_DESCRIPTORS(xelpd_power_wells_main),
> > +};
> > +
> > +static const struct i915_power_well_desc_list xehpd_power_wells[] = {
> > +	I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
> > +	I915_PW_DESCRIPTORS(icl_power_wells_pw_1),
> > +	I915_PW_DESCRIPTORS(xehpd_power_wells_dcoff),
> >  	I915_PW_DESCRIPTORS(xelpd_power_wells_main),
> >  };
> >
> > @@ -1624,6 +1657,8 @@ int intel_display_power_map_init(struct
> i915_power_domains *power_domains)
> >
> >  	if (DISPLAY_VER(i915) >= 14)
> >  		return set_power_wells(power_domains, xelpdp_power_wells);
> > +	else if (IS_DG2(i915))
> > +		return set_power_wells(power_domains, xehpd_power_wells);
> >  	else if (DISPLAY_VER(i915) >= 13)
> >  		return set_power_wells(power_domains, xelpd_power_wells);
> >  	else if (IS_DG1(i915))
> > --
> > 2.34.1
> >

[Intel-gfx] [PATCH 2/5] drm/i915/mtl: Re-use ADL-P's "DC off" power well

[Radhakrishna Sripada]

From: Matt Roper <matthew.d.roper@intel.com>

As with ADL-P, MTL's "DC off" power well should be a dependency of the
PGC and PGD power wells, not the entire PG2 well.  In fact, the DC5/DC6
requirements between the two platforms are the same, so the Xe_LPD "DC
off" well definition can just be re-used for Xe_LPD+.

Bspec: 49193
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
---
 .../drm/i915/display/intel_display_power_map.c   | 16 +---------------
 1 file changed, 1 insertion(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c b/drivers/gpu/drm/i915/display/intel_display_power_map.c
index d9e02cc9cf3c..452b6cbdfd98 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_map.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c
@@ -1456,15 +1456,6 @@ I915_DECL_PW_DOMAINS(xelpdp_pwdoms_pw_2,
 	XELPDP_PW_2_POWER_DOMAINS,
 	POWER_DOMAIN_INIT);
 
-I915_DECL_PW_DOMAINS(xelpdp_pwdoms_dc_off,
-	XELPDP_PW_2_POWER_DOMAINS,
-	POWER_DOMAIN_AUDIO_MMIO,
-	POWER_DOMAIN_MODESET,
-	POWER_DOMAIN_AUX_A,
-	POWER_DOMAIN_AUX_B,
-	POWER_DOMAIN_DC_OFF,
-	POWER_DOMAIN_INIT);
-
 I915_DECL_PW_DOMAINS(xelpdp_pwdoms_aux_tc1,
 	POWER_DOMAIN_AUX_USBC1,
 	POWER_DOMAIN_AUX_TBT1);
@@ -1483,12 +1474,6 @@ I915_DECL_PW_DOMAINS(xelpdp_pwdoms_aux_tc4,
 
 static const struct i915_power_well_desc xelpdp_power_wells_main[] = {
 	{
-		.instances = &I915_PW_INSTANCES(
-			I915_PW("DC_off", &xelpdp_pwdoms_dc_off,
-				.id = SKL_DISP_DC_OFF),
-		),
-		.ops = &gen9_dc_off_power_well_ops,
-	}, {
 		.instances = &I915_PW_INSTANCES(
 			I915_PW("PW_2", &xelpdp_pwdoms_pw_2,
 				.hsw.idx = ICL_PW_CTL_IDX_PW_2,
@@ -1545,6 +1530,7 @@ static const struct i915_power_well_desc xelpdp_power_wells_main[] = {
 static const struct i915_power_well_desc_list xelpdp_power_wells[] = {
 	I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
 	I915_PW_DESCRIPTORS(icl_power_wells_pw_1),
+	I915_PW_DESCRIPTORS(xelpd_power_wells_dcoff),
 	I915_PW_DESCRIPTORS(xelpdp_power_wells_main),
 };
 
-- 
2.34.1

[Intel-gfx] [PATCH 3/5] drm/i915/mtl: Extend Wa_22011802037 to MTL A-step

[Radhakrishna Sripada]

From: Madhumitha Tolakanahalli Pradeep <madhumitha.tolakanahalli.pradeep@intel.com>

Wa_22011802037 was being applied to all graphics_ver 11 & 12. This patch
updates the if statement to apply the W/A to right platforms and extends
it to MTL-M:A0.

Signed-off-by: Madhumitha Tolakanahalli Pradeep <madhumitha.tolakanahalli.pradeep@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
---
 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 88e881b100cf..e8c4fb9c4901 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -1629,7 +1629,9 @@ static void guc_reset_state(struct intel_context *ce, u32 head, bool scrub)
 
 static void guc_engine_reset_prepare(struct intel_engine_cs *engine)
 {
-	if (!IS_GRAPHICS_VER(engine->i915, 11, 12))
+	if (!(IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
+	    (GRAPHICS_VER(engine->i915) >= 11 &&
+	     GRAPHICS_VER_FULL(engine->i915) < IP_VER(12, 70))))
 		return;
 
 	intel_engine_stop_cs(engine);
-- 
2.34.1

[Intel-gfx] [PATCH dii-client v1.1] drm/i915/mtl: Extend Wa_22011802037 to MTL A-step

[Radhakrishna Sripada]

From: Madhumitha Tolakanahalli Pradeep <madhumitha.tolakanahalli.pradeep@intel.com>

Wa_22011802037 was being applied to all graphics_ver 11 & 12. This patch
updates the if statement to apply the W/A to right platforms and extends
it to MTL-M:A0.

v1.1: Fix checkpatch warning.

Signed-off-by: Madhumitha Tolakanahalli Pradeep <madhumitha.tolakanahalli.pradeep@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
---
 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 88e881b100cf..a099406dcc38 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -1629,7 +1629,9 @@ static void guc_reset_state(struct intel_context *ce, u32 head, bool scrub)
 
 static void guc_engine_reset_prepare(struct intel_engine_cs *engine)
 {
-	if (!IS_GRAPHICS_VER(engine->i915, 11, 12))
+	if (!(IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
+	      (GRAPHICS_VER(engine->i915) >= 11 &&
+	       GRAPHICS_VER_FULL(engine->i915) < IP_VER(12, 70))))
 		return;
 
 	intel_engine_stop_cs(engine);
-- 
2.34.1

Re: [Intel-gfx] [PATCH dii-client v1.1] drm/i915/mtl: Extend Wa_22011802037 to MTL A-step

[Lucas De Marchi]

On Thu, Mar 16, 2023 at 01:41:43PM -0700, Radhakrishna Sripada wrote:
>From: Madhumitha Tolakanahalli Pradeep <madhumitha.tolakanahalli.pradeep@intel.com>
>
>Wa_22011802037 was being applied to all graphics_ver 11 & 12. This patch
>updates the if statement to apply the W/A to right platforms and extends
>it to MTL-M:A0.

it should be any A stepping, not just A0. But the code is correct, it's
only here that is wrong.

btw wrong subject-prefix here, not sure CI will pick it up for
execution.

>
>v1.1: Fix checkpatch warning.
>
>Signed-off-by: Madhumitha Tolakanahalli Pradeep <madhumitha.tolakanahalli.pradeep@intel.com>
>Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
>---
> drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
>diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
>index 88e881b100cf..a099406dcc38 100644
>--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
>+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
>@@ -1629,7 +1629,9 @@ static void guc_reset_state(struct intel_context *ce, u32 head, bool scrub)
>
> static void guc_engine_reset_prepare(struct intel_engine_cs *engine)
> {
>-	if (!IS_GRAPHICS_VER(engine->i915, 11, 12))
>+	if (!(IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
>+	      (GRAPHICS_VER(engine->i915) >= 11 &&
>+	       GRAPHICS_VER_FULL(engine->i915) < IP_VER(12, 70))))

the double negation + parenthesis + line wrap make it hard to read.
It seems that in commit 0667429ce68e ("drm/i915/reset: Add additional
steps for Wa_22011802037 for execlist backend") the Wa comment got
misplaced as the call to intel_engine_stop_cs() is part of the Wa
handling, no?

+Umesh

Maybe let's change to a positive check and move the Wa comment to be
above the check?

	static void guc_engine_reset_prepare(struct intel_engine_cs *engine)
	{
		/*
		 * Wa_22011802037: stop the cs and wait for any pending mi force
		 * wakeups
		 */
		if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
		    (GRAPHICS_VER(gt->i915) >= 11 &&
		     GRAPHICS_VER_FULL(gt->i915) < IP_VER(12, 70))) {
			 intel_engine_stop_cs(engine);
			 intel_engine_wait_for_pending_mi_fw(engine);
		}
	}


This matches the condition checked everywhere else in the driver:

	$ git grep Wa_22011802037
	drivers/gpu/drm/i915/gt/intel_engine_cs.c:       * Wa_22011802037: Prior to doing a reset, ensure CS is
	drivers/gpu/drm/i915/gt/intel_engine_cs.c: * Wa_22011802037:gen12: In addition to stopping the cs, we need to wait for any
	drivers/gpu/drm/i915/gt/intel_execlists_submission.c:    * Wa_22011802037: In addition to stopping the cs, we need
	drivers/gpu/drm/i915/gt/uc/intel_guc.c: /* Wa_22011802037: graphics version 11/12 */
	drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c:       * Wa_22011802037: In addition to stopping the cs, we need

Btw then comments about graphics versions didn't age well: they are not matching
the code anymore


Lucas De Marchi

[Intel-gfx] [PATCH 4/5] drm/i915/mtl: Synchronize i915/BIOS on C6 enabling

[Radhakrishna Sripada]

From: Vinay Belgaumkar <vinay.belgaumkar@intel.com>

If BIOS enables/disables C6, i915 should do the same. Also, retain
this value across driver reloads. This is needed only for MTL as
of now due to an existing bug in OA which needs C6 disabled for
it to function. BIOS behavior is also different across platforms
in terms of how C6 is enabled.

v2: Review comments (Umesh)
v3: Cache the C6 enable value for all MTL. The OA WA is needed only
for A/B step, but we don't need to check for that here.
v4: Rename to mtl_check_bios_c6_setup()

Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_rc6.c       | 21 +++++++++++++++++++++
 drivers/gpu/drm/i915/gt/intel_rc6_types.h |  1 +
 2 files changed, 22 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c
index f4150f61f39c..517d14e29aac 100644
--- a/drivers/gpu/drm/i915/gt/intel_rc6.c
+++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
@@ -420,6 +420,15 @@ static void vlv_rc6_enable(struct intel_rc6 *rc6)
 	    GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
 }
 
+static bool mtl_check_bios_c6_setup(struct intel_rc6 *rc6)
+{
+	struct intel_uncore *uncore = rc6_to_uncore(rc6);
+
+	rc6->bios_rc_state = intel_uncore_read(uncore, GEN6_RC_STATE);
+
+	return rc6->bios_rc_state & RC_SW_TARGET_STATE_MASK;
+}
+
 static bool bxt_check_bios_rc6_setup(struct intel_rc6 *rc6)
 {
 	struct intel_uncore *uncore = rc6_to_uncore(rc6);
@@ -503,6 +512,13 @@ static bool rc6_supported(struct intel_rc6 *rc6)
 		return false;
 	}
 
+	if (IS_METEORLAKE(gt->i915) &&
+	    !mtl_check_bios_c6_setup(rc6)) {
+		drm_notice(&i915->drm,
+			   "C6 disabled by BIOS\n");
+		return false;
+	}
+
 	if (IS_MTL_MEDIA_STEP(gt->i915, STEP_A0, STEP_B0) &&
 	    gt->type == GT_MEDIA) {
 		drm_notice(&i915->drm,
@@ -707,9 +723,14 @@ void intel_rc6_disable(struct intel_rc6 *rc6)
 void intel_rc6_fini(struct intel_rc6 *rc6)
 {
 	struct drm_i915_gem_object *pctx;
+	struct intel_uncore *uncore = rc6_to_uncore(rc6);
 
 	intel_rc6_disable(rc6);
 
+	/* We want the BIOS C6 state preserved across loads for MTL */
+	if (IS_METEORLAKE(rc6_to_i915(rc6)))
+		set(uncore, GEN6_RC_STATE, rc6->bios_rc_state);
+
 	pctx = fetch_and_zero(&rc6->pctx);
 	if (pctx)
 		i915_gem_object_put(pctx);
diff --git a/drivers/gpu/drm/i915/gt/intel_rc6_types.h b/drivers/gpu/drm/i915/gt/intel_rc6_types.h
index fa23c4dce00b..57bb437bcbbd 100644
--- a/drivers/gpu/drm/i915/gt/intel_rc6_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_rc6_types.h
@@ -29,6 +29,7 @@ struct intel_rc6 {
 	u64 cur_residency[INTEL_RC6_RES_MAX];
 
 	u32 ctl_enable;
+	u32 bios_rc_state;
 
 	struct drm_i915_gem_object *pctx;
 
-- 
2.34.1

Re: [Intel-gfx] [PATCH 4/5] drm/i915/mtl: Synchronize i915/BIOS on C6 enabling

[Umesh Nerlige Ramappa]

On Thu, Mar 16, 2023 at 01:25:48PM -0700, Radhakrishna Sripada wrote:
>From: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
>
>If BIOS enables/disables C6, i915 should do the same. Also, retain
>this value across driver reloads. This is needed only for MTL as
>of now due to an existing bug in OA which needs C6 disabled for
>it to function. BIOS behavior is also different across platforms
>in terms of how C6 is enabled.
>
>v2: Review comments (Umesh)
>v3: Cache the C6 enable value for all MTL. The OA WA is needed only
>for A/B step, but we don't need to check for that here.
>v4: Rename to mtl_check_bios_c6_setup()
>
>Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
>Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>

This one's already pushed with the MTL OA series.

Regards,
Umesh

Re: [Intel-gfx] [PATCH 4/5] drm/i915/mtl: Synchronize i915/BIOS on C6 enabling

[Radhakrishna Sripada]

On Thu, Apr 20, 2023 at 01:05:27PM -0700, Umesh Nerlige Ramappa wrote:
> On Thu, Mar 16, 2023 at 01:25:48PM -0700, Radhakrishna Sripada wrote:
> > From: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
> > 
> > If BIOS enables/disables C6, i915 should do the same. Also, retain
> > this value across driver reloads. This is needed only for MTL as
> > of now due to an existing bug in OA which needs C6 disabled for
> > it to function. BIOS behavior is also different across platforms
> > in terms of how C6 is enabled.
> > 
> > v2: Review comments (Umesh)
> > v3: Cache the C6 enable value for all MTL. The OA WA is needed only
> > for A/B step, but we don't need to check for that here.
> > v4: Rename to mtl_check_bios_c6_setup()
> > 
> > Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
> > Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> 
> This one's already pushed with the MTL OA series.
Thank you for the update. Skipped this patch in the latest rev at [1].

[1] https://patchwork.freedesktop.org/series/115292/#rev3

- Radhakrishna Sripada
> 
> Regards,
> Umesh

[Intel-gfx] [PATCH 5/5] drm/i915/mtl: WA to clear RDOP clock gating

[Radhakrishna Sripada]

From: Haridhar Kalvala <haridhar.kalvala@intel.com>

Workaround implementation to clear RDOP clock gating.

Bspec: 33453

Signed-off-by: Haridhar Kalvala <haridhar.kalvala@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index e7ee24bcad89..92cfc71324c4 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1703,6 +1703,9 @@ xelpg_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
 		/* Wa_18018781329 */
 		wa_mcr_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB);
 		wa_mcr_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB);
+
+		/* Wa_14015795083 */
+		wa_write_clr(wal, GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE);
 	}
 
 	/*
-- 
2.34.1

[Intel-gfx] ✗ Fi.CI.BAT: failure for More MTL WA and powerwell patches (rev2)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 8106 bytes --]

== Series Details ==

Series: More MTL WA and powerwell patches (rev2)
URL   : https://patchwork.freedesktop.org/series/115292/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_12872 -> Patchwork_115292v2
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_115292v2 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_115292v2, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115292v2/index.html

Participating hosts (35 -> 35)
------------------------------

  Additional (2): bat-atsm-1 fi-pnv-d510 
  Missing    (2): fi-kbl-soraka fi-snb-2520m 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_115292v2:

### IGT changes ###

#### Possible regressions ####

  * igt@i915_module_load@load:
    - bat-dg2-11:         [PASS][1] -> [ABORT][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12872/bat-dg2-11/igt@i915_module_load@load.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115292v2/bat-dg2-11/igt@i915_module_load@load.html
    - bat-adlm-1:         [PASS][3] -> [ABORT][4]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12872/bat-adlm-1/igt@i915_module_load@load.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115292v2/bat-adlm-1/igt@i915_module_load@load.html

  
Known issues
------------

  Here are the changes found in Patchwork_115292v2 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@fbdev@eof:
    - bat-atsm-1:         NOTRUN -> [SKIP][5] ([i915#2582]) +4 similar issues
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115292v2/bat-atsm-1/igt@fbdev@eof.html

  * igt@gem_mmap@basic:
    - bat-atsm-1:         NOTRUN -> [SKIP][6] ([i915#4083])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115292v2/bat-atsm-1/igt@gem_mmap@basic.html

  * igt@gem_sync@basic-each:
    - bat-atsm-1:         NOTRUN -> [FAIL][7] ([i915#8062]) +1 similar issue
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115292v2/bat-atsm-1/igt@gem_sync@basic-each.html

  * igt@gem_tiled_fence_blits@basic:
    - bat-atsm-1:         NOTRUN -> [SKIP][8] ([i915#4077]) +2 similar issues
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115292v2/bat-atsm-1/igt@gem_tiled_fence_blits@basic.html

  * igt@gem_tiled_pread_basic:
    - bat-atsm-1:         NOTRUN -> [SKIP][9] ([i915#4079]) +1 similar issue
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115292v2/bat-atsm-1/igt@gem_tiled_pread_basic.html

  * igt@i915_hangman@error-state-basic:
    - bat-atsm-1:         NOTRUN -> [ABORT][10] ([i915#8060])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115292v2/bat-atsm-1/igt@i915_hangman@error-state-basic.html

  * igt@i915_selftest@live@execlists:
    - fi-bsw-n3050:       [PASS][11] -> [ABORT][12] ([i915#7911])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12872/fi-bsw-n3050/igt@i915_selftest@live@execlists.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115292v2/fi-bsw-n3050/igt@i915_selftest@live@execlists.html

  * igt@i915_selftest@live@slpc:
    - bat-rpls-1:         [PASS][13] -> [DMESG-FAIL][14] ([i915#6367])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12872/bat-rpls-1/igt@i915_selftest@live@slpc.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115292v2/bat-rpls-1/igt@i915_selftest@live@slpc.html

  * igt@kms_chamelium_hpd@common-hpd-after-suspend:
    - bat-dg1-5:          NOTRUN -> [SKIP][15] ([i915#7828])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115292v2/bat-dg1-5/igt@kms_chamelium_hpd@common-hpd-after-suspend.html
    - bat-adln-1:         NOTRUN -> [SKIP][16] ([i915#7828])
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115292v2/bat-adln-1/igt@kms_chamelium_hpd@common-hpd-after-suspend.html

  * igt@kms_pipe_crc_basic@suspend-read-crc@pipe-b-dp-3:
    - bat-dg2-9:          [PASS][17] -> [FAIL][18] ([fdo#103375]) +1 similar issue
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12872/bat-dg2-9/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-b-dp-3.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115292v2/bat-dg2-9/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-b-dp-3.html

  * igt@kms_pipe_crc_basic@suspend-read-crc@pipe-c-dp-3:
    - bat-dg2-9:          [PASS][19] -> [FAIL][20] ([fdo#103375] / [i915#7932])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12872/bat-dg2-9/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-c-dp-3.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115292v2/bat-dg2-9/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-c-dp-3.html

  * igt@kms_psr@primary_page_flip:
    - fi-pnv-d510:        NOTRUN -> [SKIP][21] ([fdo#109271]) +38 similar issues
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115292v2/fi-pnv-d510/igt@kms_psr@primary_page_flip.html

  
#### Possible fixes ####

  * igt@dmabuf@all-tests@dma_fence:
    - bat-adln-1:         [FAIL][22] ([i915#8064]) -> [PASS][23]
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12872/bat-adln-1/igt@dmabuf@all-tests@dma_fence.html
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115292v2/bat-adln-1/igt@dmabuf@all-tests@dma_fence.html

  * igt@dmabuf@all-tests@sanitycheck:
    - bat-adln-1:         [ABORT][24] ([i915#8144]) -> [PASS][25]
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12872/bat-adln-1/igt@dmabuf@all-tests@sanitycheck.html
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115292v2/bat-adln-1/igt@dmabuf@all-tests@sanitycheck.html

  * igt@i915_selftest@live@hangcheck:
    - bat-dg1-5:          [ABORT][26] ([i915#4983]) -> [PASS][27]
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12872/bat-dg1-5/igt@i915_selftest@live@hangcheck.html
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115292v2/bat-dg1-5/igt@i915_selftest@live@hangcheck.html

  
  [fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
  [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
  [i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
  [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
  [i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
  [i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
  [i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
  [i915#7911]: https://gitlab.freedesktop.org/drm/intel/issues/7911
  [i915#7932]: https://gitlab.freedesktop.org/drm/intel/issues/7932
  [i915#8060]: https://gitlab.freedesktop.org/drm/intel/issues/8060
  [i915#8062]: https://gitlab.freedesktop.org/drm/intel/issues/8062
  [i915#8064]: https://gitlab.freedesktop.org/drm/intel/issues/8064
  [i915#8144]: https://gitlab.freedesktop.org/drm/intel/issues/8144


Build changes
-------------

  * Linux: CI_DRM_12872 -> Patchwork_115292v2

  CI-20190529: 20190529
  CI_DRM_12872: f65e171596ef70c076fe02be596de29e83cfc8a3 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7202: b4ec7dac375eed2dda89c64d4de94c4c9205b601 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_115292v2: f65e171596ef70c076fe02be596de29e83cfc8a3 @ git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

f2cb9ac39f74 drm/i915/mtl: WA to clear RDOP clock gating
69acbf599183 drm/i915/mtl: Synchronize i915/BIOS on C6 enabling
8c5ddb6aadac drm/i915/mtl: Extend Wa_22011802037 to MTL A-step
baf84b01bec6 drm/i915/mtl: Re-use ADL-P's "DC off" power well
ffa4a6bde432 drm/i915: Use separate "DC off" power well for ADL-P and DG2

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115292v2/index.html

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