From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: dri-devel@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH 3/6] drm/i915: Fix CHV CGM CSC coefficient sign handling
Date: Wed, 12 Apr 2023 01:29:28 +0300 [thread overview]
Message-ID: <20230411222931.15127-4-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <20230411222931.15127-1-ville.syrjala@linux.intel.com>
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
The CHV CGM CSC coefficients are in s4.12 two's complement
format. Fix the CTM->CGM conversion to handle that correctly
instead of pretending that the hw coefficients are also
in some sign-magnitude format.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_color.c | 46 ++++++++++++++--------
1 file changed, 29 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 4fc16cac052d..63141f4ed372 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -568,29 +568,41 @@ static void icl_load_csc_matrix(const struct intel_crtc_state *crtc_state)
icl_update_output_csc(crtc, &crtc_state->output_csc);
}
+static u16 ctm_to_twos_complement(u64 coeff, int int_bits, int frac_bits)
+{
+ s64 c = CTM_COEFF_ABS(coeff);
+
+ /* leave an extra bit for rounding */
+ c >>= 32 - frac_bits - 1;
+
+ /* round and drop the extra bit */
+ c = (c + 1) >> 1;
+
+ if (CTM_COEFF_NEGATIVE(coeff))
+ c = -c;
+
+ c = clamp(c, -(s64)BIT(int_bits + frac_bits - 1),
+ (s64)(BIT(int_bits + frac_bits - 1) - 1));
+
+ return c & (BIT(int_bits + frac_bits) - 1);
+}
+
+/*
+ * CHV Color Gamut Mapping (CGM) CSC
+ * |r| | c0 c1 c2 | |r|
+ * |g| = | c3 c4 c5 | x |g|
+ * |b| | c6 c7 c8 | |b|
+ *
+ * Coefficients are two's complement s4.12.
+ */
static void chv_cgm_csc_convert_ctm(const struct intel_crtc_state *crtc_state,
struct intel_csc_matrix *csc)
{
const struct drm_color_ctm *ctm = crtc_state->hw.ctm->data;
int i;
- for (i = 0; i < 9; i++) {
- u64 abs_coeff = ((1ULL << 63) - 1) & ctm->matrix[i];
-
- /* Round coefficient. */
- abs_coeff += 1 << (32 - 13);
- /* Clamp to hardware limits. */
- abs_coeff = clamp_val(abs_coeff, 0, CTM_COEFF_8_0 - 1);
-
- csc->coeff[i] = 0;
-
- /* Write coefficients in S3.12 format. */
- if (ctm->matrix[i] & (1ULL << 63))
- csc->coeff[i] |= 1 << 15;
-
- csc->coeff[i] |= ((abs_coeff >> 32) & 7) << 12;
- csc->coeff[i] |= (abs_coeff >> 20) & 0xfff;
- }
+ for (i = 0; i < 9; i++)
+ csc->coeff[i] = ctm_to_twos_complement(ctm->matrix[i], 4, 12);
}
static void chv_load_cgm_csc(struct intel_crtc *crtc,
--
2.39.2
next prev parent reply other threads:[~2023-04-11 22:29 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-11 22:29 [Intel-gfx] [PATCH 0/6] drm/i915: CTM stuff mostly Ville Syrjala
2023-04-11 22:29 ` [Intel-gfx] [PATCH 1/6] drm/uapi: Document CTM matrix better Ville Syrjala
2023-04-27 22:31 ` Xaver Hugl
2023-04-28 13:39 ` Ville Syrjälä
2023-04-28 9:27 ` Simon Ser
2023-04-11 22:29 ` [Intel-gfx] [PATCH 2/6] drm/i915: Expose crtc CTM property on ilk/snb Ville Syrjala
2023-04-11 22:29 ` Ville Syrjala [this message]
2023-04-11 22:29 ` [Intel-gfx] [PATCH 4/6] drm/i915: Implement CTM property support for VLV Ville Syrjala
2023-04-11 22:29 ` [Intel-gfx] [PATCH 5/6] drm/i915: No 10bit gamma on desktop gen3 parts Ville Syrjala
2023-04-11 22:29 ` [Intel-gfx] [PATCH 6/6] drm/i915: Do state check for color management changes Ville Syrjala
2023-04-12 1:58 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: CTM stuff mostly Patchwork
2023-04-12 1:58 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-04-12 2:15 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2023-04-12 6:12 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: CTM stuff mostly (rev2) Patchwork
2023-04-12 6:12 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-04-12 6:27 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2023-04-13 5:50 ` Patchwork
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