* [Intel-gfx] [PATCH] drm/i915/gt: Mask media GuC interrupts
@ 2023-04-14 16:25 Andi Shyti
2023-04-14 17:01 ` Ceraolo Spurio, Daniele
2023-04-14 18:44 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for " Patchwork
0 siblings, 2 replies; 4+ messages in thread
From: Andi Shyti @ 2023-04-14 16:25 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: Matt Roper, Andi Shyti, Nirmoy Das
MTL features a dedicated media engine that operates on its
independent GT, requiring activation of its specific interrupt
set.
Enable the necessary interrupts in a single action when the media
engine is present, bypassing the need to iterate through all the
GTs.
Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
---
Hi,
I'm starting with v0 as this patch is very different from the
ones proposed recently.
After all the discussions on this patch, I took Matt's suggestion
since it seemed the most immediate.
However, in the long run, I agree that we should have a
specific mtl_ function for enabling interrupts.
Thank you Matt and Daniele for your input.
If this patch hasn't missed anything, is it too optimistic to
expect MTL to boot? :-)
Andi
drivers/gpu/drm/i915/gt/intel_gt_irq.c | 14 ++++++++------
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
index 1b25a60391522..162a27b4c4095 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
@@ -254,7 +254,6 @@ void gen11_gt_irq_postinstall(struct intel_gt *gt)
{
struct intel_uncore *uncore = gt->uncore;
u32 irqs = GT_RENDER_USER_INTERRUPT;
- u32 guc_mask = intel_uc_wants_guc(>->uc) ? GUC_INTR_GUC2HOST : 0;
u32 gsc_mask = 0;
u32 dmask;
u32 smask;
@@ -309,17 +308,20 @@ void gen11_gt_irq_postinstall(struct intel_gt *gt)
if (gsc_mask)
intel_uncore_write(uncore, GEN11_GUNIT_CSME_INTR_MASK, ~gsc_mask);
- if (guc_mask) {
+ if (intel_uc_wants_guc(>->uc)) {
+ u32 guc_mask = GUC_INTR_GUC2HOST;
/* the enable bit is common for both GTs but the masks are separate */
- u32 mask = gt->type == GT_MEDIA ?
- REG_FIELD_PREP(ENGINE0_MASK, guc_mask) :
- REG_FIELD_PREP(ENGINE1_MASK, guc_mask);
+ u32 mask = REG_FIELD_PREP(ENGINE1_MASK, guc_mask);
+
+ /* Mask the GuC interrupts of media engine if present */
+ if (MEDIA_VER(gt->i915) >= 13)
+ mask |= REG_FIELD_PREP(ENGINE0_MASK, guc_mask);
intel_uncore_write(uncore, GEN11_GUC_SG_INTR_ENABLE,
REG_FIELD_PREP(ENGINE1_MASK, guc_mask));
/* we might not be the first GT to write this reg */
- intel_uncore_rmw(uncore, MTL_GUC_MGUC_INTR_MASK, mask, 0);
+ intel_uncore_write(uncore, MTL_GUC_MGUC_INTR_MASK, mask);
}
/*
--
2.39.2
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/gt: Mask media GuC interrupts
2023-04-14 16:25 [Intel-gfx] [PATCH] drm/i915/gt: Mask media GuC interrupts Andi Shyti
@ 2023-04-14 17:01 ` Ceraolo Spurio, Daniele
2023-04-14 17:54 ` Andi Shyti
2023-04-14 18:44 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for " Patchwork
1 sibling, 1 reply; 4+ messages in thread
From: Ceraolo Spurio, Daniele @ 2023-04-14 17:01 UTC (permalink / raw)
To: Andi Shyti, intel-gfx, dri-devel; +Cc: Matt Roper, Andi Shyti, Nirmoy Das
On 4/14/2023 9:25 AM, Andi Shyti wrote:
> MTL features a dedicated media engine that operates on its
> independent GT, requiring activation of its specific interrupt
> set.
>
> Enable the necessary interrupts in a single action when the media
> engine is present, bypassing the need to iterate through all the
> GTs.
>
> Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
> ---
> Hi,
>
> I'm starting with v0 as this patch is very different from the
> ones proposed recently.
>
> After all the discussions on this patch, I took Matt's suggestion
> since it seemed the most immediate.
>
> However, in the long run, I agree that we should have a
> specific mtl_ function for enabling interrupts.
>
> Thank you Matt and Daniele for your input.
>
> If this patch hasn't missed anything, is it too optimistic to
> expect MTL to boot? :-)
The GSC engine also has interrupts tied to the media GT and those are
conditional, so that engine won't work with just this patch. The system
might boot because the GSC engine gets disabled if the FW is not there,
but IMO if we want a single function to handle both GTs we need to do it
proper support for the engines and not hack around just the GuC.
Daniele
>
> Andi
>
> drivers/gpu/drm/i915/gt/intel_gt_irq.c | 14 ++++++++------
> 1 file changed, 8 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
> index 1b25a60391522..162a27b4c4095 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
> @@ -254,7 +254,6 @@ void gen11_gt_irq_postinstall(struct intel_gt *gt)
> {
> struct intel_uncore *uncore = gt->uncore;
> u32 irqs = GT_RENDER_USER_INTERRUPT;
> - u32 guc_mask = intel_uc_wants_guc(>->uc) ? GUC_INTR_GUC2HOST : 0;
> u32 gsc_mask = 0;
> u32 dmask;
> u32 smask;
> @@ -309,17 +308,20 @@ void gen11_gt_irq_postinstall(struct intel_gt *gt)
> if (gsc_mask)
> intel_uncore_write(uncore, GEN11_GUNIT_CSME_INTR_MASK, ~gsc_mask);
>
> - if (guc_mask) {
> + if (intel_uc_wants_guc(>->uc)) {
> + u32 guc_mask = GUC_INTR_GUC2HOST;
> /* the enable bit is common for both GTs but the masks are separate */
> - u32 mask = gt->type == GT_MEDIA ?
> - REG_FIELD_PREP(ENGINE0_MASK, guc_mask) :
> - REG_FIELD_PREP(ENGINE1_MASK, guc_mask);
> + u32 mask = REG_FIELD_PREP(ENGINE1_MASK, guc_mask);
> +
> + /* Mask the GuC interrupts of media engine if present */
> + if (MEDIA_VER(gt->i915) >= 13)
> + mask |= REG_FIELD_PREP(ENGINE0_MASK, guc_mask);
>
> intel_uncore_write(uncore, GEN11_GUC_SG_INTR_ENABLE,
> REG_FIELD_PREP(ENGINE1_MASK, guc_mask));
>
> /* we might not be the first GT to write this reg */
> - intel_uncore_rmw(uncore, MTL_GUC_MGUC_INTR_MASK, mask, 0);
> + intel_uncore_write(uncore, MTL_GUC_MGUC_INTR_MASK, mask);
> }
>
> /*
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/gt: Mask media GuC interrupts
2023-04-14 17:01 ` Ceraolo Spurio, Daniele
@ 2023-04-14 17:54 ` Andi Shyti
0 siblings, 0 replies; 4+ messages in thread
From: Andi Shyti @ 2023-04-14 17:54 UTC (permalink / raw)
To: Ceraolo Spurio, Daniele
Cc: Andi Shyti, intel-gfx, dri-devel, Matt Roper, Nirmoy Das
Hi Daniele,
> > MTL features a dedicated media engine that operates on its
> > independent GT, requiring activation of its specific interrupt
> > set.
> >
> > Enable the necessary interrupts in a single action when the media
> > engine is present, bypassing the need to iterate through all the
> > GTs.
> >
> > Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
> > ---
> > Hi,
> >
> > I'm starting with v0 as this patch is very different from the
> > ones proposed recently.
> >
> > After all the discussions on this patch, I took Matt's suggestion
> > since it seemed the most immediate.
> >
> > However, in the long run, I agree that we should have a
> > specific mtl_ function for enabling interrupts.
> >
> > Thank you Matt and Daniele for your input.
> >
> > If this patch hasn't missed anything, is it too optimistic to
> > expect MTL to boot? :-)
>
> The GSC engine also has interrupts tied to the media GT and those are
> conditional, so that engine won't work with just this patch. The system
> might boot because the GSC engine gets disabled if the FW is not there, but
> IMO if we want a single function to handle both GTs we need to do it proper
> support for the engines and not hack around just the GuC.
yeah... we are already having too many things to handle and at
this point I don't see any better way to handle this other than
using for_each_gt() as it was first sent.
Besides, they are different GT's, why not using for_each_gt?
Thank you, Daniele,
Andi
^ permalink raw reply [flat|nested] 4+ messages in thread
* [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/gt: Mask media GuC interrupts
2023-04-14 16:25 [Intel-gfx] [PATCH] drm/i915/gt: Mask media GuC interrupts Andi Shyti
2023-04-14 17:01 ` Ceraolo Spurio, Daniele
@ 2023-04-14 18:44 ` Patchwork
1 sibling, 0 replies; 4+ messages in thread
From: Patchwork @ 2023-04-14 18:44 UTC (permalink / raw)
To: Andi Shyti; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 6498 bytes --]
== Series Details ==
Series: drm/i915/gt: Mask media GuC interrupts
URL : https://patchwork.freedesktop.org/series/116493/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13008 -> Patchwork_116493v1
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_116493v1 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_116493v1, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116493v1/index.html
Participating hosts (37 -> 36)
------------------------------
Missing (1): fi-snb-2520m
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_116493v1:
### IGT changes ###
#### Possible regressions ####
* igt@i915_module_load@load:
- bat-rpls-1: [PASS][1] -> [ABORT][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13008/bat-rpls-1/igt@i915_module_load@load.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116493v1/bat-rpls-1/igt@i915_module_load@load.html
- bat-dg1-5: [PASS][3] -> [ABORT][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13008/bat-dg1-5/igt@i915_module_load@load.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116493v1/bat-dg1-5/igt@i915_module_load@load.html
- bat-dg1-7: [PASS][5] -> [ABORT][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13008/bat-dg1-7/igt@i915_module_load@load.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116493v1/bat-dg1-7/igt@i915_module_load@load.html
- bat-adln-1: [PASS][7] -> [ABORT][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13008/bat-adln-1/igt@i915_module_load@load.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116493v1/bat-adln-1/igt@i915_module_load@load.html
- bat-rplp-1: [PASS][9] -> [ABORT][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13008/bat-rplp-1/igt@i915_module_load@load.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116493v1/bat-rplp-1/igt@i915_module_load@load.html
- bat-atsm-1: [PASS][11] -> [ABORT][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13008/bat-atsm-1/igt@i915_module_load@load.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116493v1/bat-atsm-1/igt@i915_module_load@load.html
- bat-rpls-2: [PASS][13] -> [ABORT][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13008/bat-rpls-2/igt@i915_module_load@load.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116493v1/bat-rpls-2/igt@i915_module_load@load.html
* igt@i915_selftest@live@gem:
- bat-adls-5: [PASS][15] -> [DMESG-WARN][16] +48 similar issues
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13008/bat-adls-5/igt@i915_selftest@live@gem.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116493v1/bat-adls-5/igt@i915_selftest@live@gem.html
#### Warnings ####
* igt@i915_selftest@live@hangcheck:
- bat-adls-5: [DMESG-WARN][17] ([i915#5591]) -> [DMESG-WARN][18]
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13008/bat-adls-5/igt@i915_selftest@live@hangcheck.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116493v1/bat-adls-5/igt@i915_selftest@live@hangcheck.html
Known issues
------------
Here are the changes found in Patchwork_116493v1 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_module_load@load:
- bat-adlp-6: [PASS][19] -> [ABORT][20] ([i915#8189])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13008/bat-adlp-6/igt@i915_module_load@load.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116493v1/bat-adlp-6/igt@i915_module_load@load.html
- bat-adlp-9: [PASS][21] -> [ABORT][22] ([i915#8189])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13008/bat-adlp-9/igt@i915_module_load@load.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116493v1/bat-adlp-9/igt@i915_module_load@load.html
- bat-dg2-11: [PASS][23] -> [ABORT][24] ([i915#7931] / [i915#8189])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13008/bat-dg2-11/igt@i915_module_load@load.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116493v1/bat-dg2-11/igt@i915_module_load@load.html
- bat-dg2-9: [PASS][25] -> [ABORT][26] ([i915#7931] / [i915#8189])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13008/bat-dg2-9/igt@i915_module_load@load.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116493v1/bat-dg2-9/igt@i915_module_load@load.html
- bat-dg2-8: [PASS][27] -> [ABORT][28] ([i915#7931] / [i915#8189])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13008/bat-dg2-8/igt@i915_module_load@load.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116493v1/bat-dg2-8/igt@i915_module_load@load.html
* igt@kms_pipe_crc_basic@suspend-read-crc@pipe-a-hdmi-a-1:
- fi-rkl-11600: [PASS][29] -> [FAIL][30] ([fdo#103375])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13008/fi-rkl-11600/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-a-hdmi-a-1.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116493v1/fi-rkl-11600/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-a-hdmi-a-1.html
[fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
[i915#5591]: https://gitlab.freedesktop.org/drm/intel/issues/5591
[i915#7931]: https://gitlab.freedesktop.org/drm/intel/issues/7931
[i915#8189]: https://gitlab.freedesktop.org/drm/intel/issues/8189
Build changes
-------------
* Linux: CI_DRM_13008 -> Patchwork_116493v1
CI-20190529: 20190529
CI_DRM_13008: 7862c60adcb74785d0063f6d978adf8c38cda97c @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7256: 066fa5410180730b85f61e4f3073da9a2055dc49 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_116493v1: 7862c60adcb74785d0063f6d978adf8c38cda97c @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
0ecee96eb7cb drm/i915/gt: Mask media GuC interrupts
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116493v1/index.html
[-- Attachment #2: Type: text/html, Size: 7771 bytes --]
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2023-04-14 18:44 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2023-04-14 16:25 [Intel-gfx] [PATCH] drm/i915/gt: Mask media GuC interrupts Andi Shyti
2023-04-14 17:01 ` Ceraolo Spurio, Daniele
2023-04-14 17:54 ` Andi Shyti
2023-04-14 18:44 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for " Patchwork
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox