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* [Intel-gfx] [PATCH v3] drm/i915: Make IRQ reset and postinstall multi-gt aware
@ 2023-04-16 22:46 Andi Shyti
  2023-04-16 23:42 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Make IRQ reset and postinstall multi-gt aware (rev3) Patchwork
                   ` (3 more replies)
  0 siblings, 4 replies; 5+ messages in thread
From: Andi Shyti @ 2023-04-16 22:46 UTC (permalink / raw)
  To: intel-gfx, dri-devel; +Cc: Andi Shyti, Matt Roper, Nirmoy Das

In multi-gt systems IRQs need to be reset and enabled per GT.

This might add some redundancy when handling interrupts for
engines that might not exist in every tile, but helps to keep the
code cleaner and more understandable.

Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
Hi,

Following the most recent discussions, it appears that the
cleanest method for handling multi-GT interrupts in MTL is to
utilize for_each_gt in the reset and post-install functions.

Attempting to configure everything in one go requires addressing
certain exceptions, which could ultimately make the code appear
more complex and hacky. Moreover, the media-GT is managed while
configuring a different GT.

Thank you Daniele and Matt for the valuable exchange of opinions.

This patch has been tested on trybot and allows MTL to boot and
execute some BAT tests.

Andi

Changelog
=========
v2 -> v3
 - keep GUnit irq initialization out of the for_each_gt() loop as
   the media GT doesn't have a GUnit.
v1 -> v2
 - improve description in the commit log.

 drivers/gpu/drm/i915/i915_irq.c | 17 +++++++++++------
 1 file changed, 11 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index b4dd6a5a536f9..eb185dc2e59a0 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2856,12 +2856,15 @@ static void gen11_irq_reset(struct drm_i915_private *dev_priv)
 
 static void dg1_irq_reset(struct drm_i915_private *dev_priv)
 {
-	struct intel_gt *gt = to_gt(dev_priv);
-	struct intel_uncore *uncore = gt->uncore;
+	struct intel_uncore *uncore = to_gt(dev_priv)->uncore;
+	struct intel_gt *gt;
+	unsigned int i;
 
 	dg1_master_intr_disable(dev_priv->uncore.regs);
 
-	gen11_gt_irq_reset(gt);
+	for_each_gt(gt, dev_priv, i)
+		gen11_gt_irq_reset(gt);
+
 	gen11_display_irq_reset(dev_priv);
 
 	GEN3_IRQ_RESET(uncore, GEN11_GU_MISC_);
@@ -3643,11 +3646,13 @@ static void gen11_irq_postinstall(struct drm_i915_private *dev_priv)
 
 static void dg1_irq_postinstall(struct drm_i915_private *dev_priv)
 {
-	struct intel_gt *gt = to_gt(dev_priv);
-	struct intel_uncore *uncore = gt->uncore;
+	struct intel_uncore *uncore = to_gt(dev_priv)->uncore;
 	u32 gu_misc_masked = GEN11_GU_MISC_GSE;
+	struct intel_gt *gt;
+	unsigned int i;
 
-	gen11_gt_irq_postinstall(gt);
+	for_each_gt(gt, dev_priv, i)
+		gen11_gt_irq_postinstall(gt);
 
 	GEN3_IRQ_INIT(uncore, GEN11_GU_MISC_, ~gu_misc_masked, gu_misc_masked);
 
-- 
2.39.2


^ permalink raw reply related	[flat|nested] 5+ messages in thread
end of thread, other threads:[~2023-04-17 19:03 UTC | newest]

Thread overview: 5+ messages (download: mbox.gz follow: Atom feed
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2023-04-16 22:46 [Intel-gfx] [PATCH v3] drm/i915: Make IRQ reset and postinstall multi-gt aware Andi Shyti
2023-04-16 23:42 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Make IRQ reset and postinstall multi-gt aware (rev3) Patchwork
2023-04-17  1:51 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2023-04-17 13:22 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Make IRQ reset and postinstall multi-gt aware (rev4) Patchwork
2023-04-17 19:03 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Make IRQ reset and postinstall multi-gt aware (rev5) Patchwork

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