* [Intel-gfx] [PATCH v6 0/3] drm/i915/guc: Disable PL1 power limit when loading GuC firmware
@ 2023-04-20 16:40 Ashutosh Dixit
2023-04-20 16:40 ` [Intel-gfx] [PATCH 1/3] drm/i915/hwmon: Get mutex and rpm ref just once in hwm_power_max_write Ashutosh Dixit
` (5 more replies)
0 siblings, 6 replies; 13+ messages in thread
From: Ashutosh Dixit @ 2023-04-20 16:40 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel, Rodrigo Vivi
v6: Update Patch 3 to remove the timeout when blocked
v1-v5: Please see individual patches for revision history
Ashutosh Dixit (3):
drm/i915/hwmon: Get mutex and rpm ref just once in hwm_power_max_write
drm/i915/guc: Disable PL1 power limit when loading GuC firmware
drm/i915/hwmon: Block waiting for GuC reset to complete
drivers/gpu/drm/i915/gt/uc/intel_uc.c | 13 +++-
drivers/gpu/drm/i915/i915_hwmon.c | 87 +++++++++++++++++++++++----
drivers/gpu/drm/i915/i915_hwmon.h | 7 +++
3 files changed, 93 insertions(+), 14 deletions(-)
--
2.38.0
^ permalink raw reply [flat|nested] 13+ messages in thread* [Intel-gfx] [PATCH 1/3] drm/i915/hwmon: Get mutex and rpm ref just once in hwm_power_max_write 2023-04-20 16:40 [Intel-gfx] [PATCH v6 0/3] drm/i915/guc: Disable PL1 power limit when loading GuC firmware Ashutosh Dixit @ 2023-04-20 16:40 ` Ashutosh Dixit 2023-04-20 16:40 ` [Intel-gfx] [PATCH 2/3] drm/i915/guc: Disable PL1 power limit when loading GuC firmware Ashutosh Dixit ` (4 subsequent siblings) 5 siblings, 0 replies; 13+ messages in thread From: Ashutosh Dixit @ 2023-04-20 16:40 UTC (permalink / raw) To: intel-gfx; +Cc: dri-devel, Rodrigo Vivi In preparation for follow-on patches, refactor hwm_power_max_write to take hwmon_lock and runtime pm wakeref at start of the function and release them at the end, therefore acquiring these just once each. Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> --- drivers/gpu/drm/i915/i915_hwmon.c | 28 +++++++++++++++------------- 1 file changed, 15 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_hwmon.c b/drivers/gpu/drm/i915/i915_hwmon.c index 8e7dccc8d3a0e..7f44e809ca155 100644 --- a/drivers/gpu/drm/i915/i915_hwmon.c +++ b/drivers/gpu/drm/i915/i915_hwmon.c @@ -396,31 +396,33 @@ hwm_power_max_write(struct hwm_drvdata *ddat, long val) { struct i915_hwmon *hwmon = ddat->hwmon; intel_wakeref_t wakeref; + int ret = 0; u32 nval; + mutex_lock(&hwmon->hwmon_lock); + wakeref = intel_runtime_pm_get(ddat->uncore->rpm); + /* Disable PL1 limit and verify, because the limit cannot be disabled on all platforms */ if (val == PL1_DISABLE) { - mutex_lock(&hwmon->hwmon_lock); - with_intel_runtime_pm(ddat->uncore->rpm, wakeref) { - intel_uncore_rmw(ddat->uncore, hwmon->rg.pkg_rapl_limit, - PKG_PWR_LIM_1_EN, 0); - nval = intel_uncore_read(ddat->uncore, hwmon->rg.pkg_rapl_limit); - } - mutex_unlock(&hwmon->hwmon_lock); + intel_uncore_rmw(ddat->uncore, hwmon->rg.pkg_rapl_limit, + PKG_PWR_LIM_1_EN, 0); + nval = intel_uncore_read(ddat->uncore, hwmon->rg.pkg_rapl_limit); if (nval & PKG_PWR_LIM_1_EN) - return -ENODEV; - return 0; + ret = -ENODEV; + goto exit; } /* Computation in 64-bits to avoid overflow. Round to nearest. */ nval = DIV_ROUND_CLOSEST_ULL((u64)val << hwmon->scl_shift_power, SF_POWER); nval = PKG_PWR_LIM_1_EN | REG_FIELD_PREP(PKG_PWR_LIM_1, nval); - hwm_locked_with_pm_intel_uncore_rmw(ddat, hwmon->rg.pkg_rapl_limit, - PKG_PWR_LIM_1_EN | PKG_PWR_LIM_1, - nval); - return 0; + intel_uncore_rmw(ddat->uncore, hwmon->rg.pkg_rapl_limit, + PKG_PWR_LIM_1_EN | PKG_PWR_LIM_1, nval); +exit: + intel_runtime_pm_put(ddat->uncore->rpm, wakeref); + mutex_unlock(&hwmon->hwmon_lock); + return ret; } static int -- 2.38.0 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* [Intel-gfx] [PATCH 2/3] drm/i915/guc: Disable PL1 power limit when loading GuC firmware 2023-04-20 16:40 [Intel-gfx] [PATCH v6 0/3] drm/i915/guc: Disable PL1 power limit when loading GuC firmware Ashutosh Dixit 2023-04-20 16:40 ` [Intel-gfx] [PATCH 1/3] drm/i915/hwmon: Get mutex and rpm ref just once in hwm_power_max_write Ashutosh Dixit @ 2023-04-20 16:40 ` Ashutosh Dixit 2023-04-20 16:40 ` [Intel-gfx] [PATCH 3/3] drm/i915/hwmon: Block waiting for GuC reset to complete Ashutosh Dixit ` (3 subsequent siblings) 5 siblings, 0 replies; 13+ messages in thread From: Ashutosh Dixit @ 2023-04-20 16:40 UTC (permalink / raw) To: intel-gfx; +Cc: dri-devel, Rodrigo Vivi On dGfx, the PL1 power limit being enabled and set to a low value results in a low GPU operating freq. It also negates the freq raise operation which is done before GuC firmware load. As a result GuC firmware load can time out. Such timeouts were seen in the GL #8062 bug below (where the PL1 power limit was enabled and set to a low value). Therefore disable the PL1 power limit when allowed by HW when loading GuC firmware. v2: - Take mutex (to disallow writes to power1_max) across GuC reset/fw load - Add hwm_power_max_restore to error return code path v3 (Jani N): - Add/remove explanatory comments - Function renames - Type corrections - Locking annotation v4: - Don't hold the lock across GuC reset (Rodrigo) - New locking scheme (suggested by Rodrigo) - Eliminate rpm_get in power_max_disable/restore, not needed (Tvrtko) v5: - Fix uninitialized pl1en variable compile warning reported by kernel build robot by creating new err_rps label Link: https://gitlab.freedesktop.org/drm/intel/-/issues/8062 Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> --- drivers/gpu/drm/i915/gt/uc/intel_uc.c | 13 +++++++-- drivers/gpu/drm/i915/i915_hwmon.c | 40 +++++++++++++++++++++++++++ drivers/gpu/drm/i915/i915_hwmon.h | 7 +++++ 3 files changed, 58 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c b/drivers/gpu/drm/i915/gt/uc/intel_uc.c index 4ccb4be4c9cba..996168312340e 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c @@ -18,6 +18,7 @@ #include "intel_uc.h" #include "i915_drv.h" +#include "i915_hwmon.h" static const struct intel_uc_ops uc_ops_off; static const struct intel_uc_ops uc_ops_on; @@ -461,6 +462,7 @@ static int __uc_init_hw(struct intel_uc *uc) struct intel_guc *guc = &uc->guc; struct intel_huc *huc = &uc->huc; int ret, attempts; + bool pl1en; GEM_BUG_ON(!intel_uc_supports_guc(uc)); GEM_BUG_ON(!intel_uc_wants_guc(uc)); @@ -491,6 +493,9 @@ static int __uc_init_hw(struct intel_uc *uc) else attempts = 1; + /* Disable a potentially low PL1 power limit to allow freq to be raised */ + i915_hwmon_power_max_disable(gt->i915, &pl1en); + intel_rps_raise_unslice(&uc_to_gt(uc)->rps); while (attempts--) { @@ -500,7 +505,7 @@ static int __uc_init_hw(struct intel_uc *uc) */ ret = __uc_sanitize(uc); if (ret) - goto err_out; + goto err_rps; intel_huc_fw_upload(huc); intel_guc_ads_reset(guc); @@ -547,6 +552,8 @@ static int __uc_init_hw(struct intel_uc *uc) intel_rps_lower_unslice(&uc_to_gt(uc)->rps); } + i915_hwmon_power_max_restore(gt->i915, pl1en); + guc_info(guc, "submission %s\n", str_enabled_disabled(intel_uc_uses_guc_submission(uc))); guc_info(guc, "SLPC %s\n", str_enabled_disabled(intel_uc_uses_guc_slpc(uc))); @@ -559,10 +566,12 @@ static int __uc_init_hw(struct intel_uc *uc) intel_guc_submission_disable(guc); err_log_capture: __uc_capture_load_err_log(uc); -err_out: +err_rps: /* Return GT back to RPn */ intel_rps_lower_unslice(&uc_to_gt(uc)->rps); + i915_hwmon_power_max_restore(gt->i915, pl1en); +err_out: __uc_sanitize(uc); if (!ret) { diff --git a/drivers/gpu/drm/i915/i915_hwmon.c b/drivers/gpu/drm/i915/i915_hwmon.c index 7f44e809ca155..9ab8971679fe3 100644 --- a/drivers/gpu/drm/i915/i915_hwmon.c +++ b/drivers/gpu/drm/i915/i915_hwmon.c @@ -50,6 +50,7 @@ struct hwm_drvdata { struct hwm_energy_info ei; /* Energy info for energy1_input */ char name[12]; int gt_n; + bool reset_in_progress; }; struct i915_hwmon { @@ -400,6 +401,10 @@ hwm_power_max_write(struct hwm_drvdata *ddat, long val) u32 nval; mutex_lock(&hwmon->hwmon_lock); + if (hwmon->ddat.reset_in_progress) { + ret = -EAGAIN; + goto unlock; + } wakeref = intel_runtime_pm_get(ddat->uncore->rpm); /* Disable PL1 limit and verify, because the limit cannot be disabled on all platforms */ @@ -421,6 +426,7 @@ hwm_power_max_write(struct hwm_drvdata *ddat, long val) PKG_PWR_LIM_1_EN | PKG_PWR_LIM_1, nval); exit: intel_runtime_pm_put(ddat->uncore->rpm, wakeref); +unlock: mutex_unlock(&hwmon->hwmon_lock); return ret; } @@ -472,6 +478,40 @@ hwm_power_write(struct hwm_drvdata *ddat, u32 attr, int chan, long val) } } +void i915_hwmon_power_max_disable(struct drm_i915_private *i915, bool *old) +{ + struct i915_hwmon *hwmon = i915->hwmon; + u32 r; + + if (!hwmon || !i915_mmio_reg_valid(hwmon->rg.pkg_rapl_limit)) + return; + + mutex_lock(&hwmon->hwmon_lock); + + hwmon->ddat.reset_in_progress = true; + r = intel_uncore_rmw(hwmon->ddat.uncore, hwmon->rg.pkg_rapl_limit, + PKG_PWR_LIM_1_EN, 0); + *old = !!(r & PKG_PWR_LIM_1_EN); + + mutex_unlock(&hwmon->hwmon_lock); +} + +void i915_hwmon_power_max_restore(struct drm_i915_private *i915, bool old) +{ + struct i915_hwmon *hwmon = i915->hwmon; + + if (!hwmon || !i915_mmio_reg_valid(hwmon->rg.pkg_rapl_limit)) + return; + + mutex_lock(&hwmon->hwmon_lock); + + intel_uncore_rmw(hwmon->ddat.uncore, hwmon->rg.pkg_rapl_limit, + PKG_PWR_LIM_1_EN, old ? PKG_PWR_LIM_1_EN : 0); + hwmon->ddat.reset_in_progress = false; + + mutex_unlock(&hwmon->hwmon_lock); +} + static umode_t hwm_energy_is_visible(const struct hwm_drvdata *ddat, u32 attr) { diff --git a/drivers/gpu/drm/i915/i915_hwmon.h b/drivers/gpu/drm/i915/i915_hwmon.h index 7ca9cf2c34c96..0fcb7de844061 100644 --- a/drivers/gpu/drm/i915/i915_hwmon.h +++ b/drivers/gpu/drm/i915/i915_hwmon.h @@ -7,14 +7,21 @@ #ifndef __I915_HWMON_H__ #define __I915_HWMON_H__ +#include <linux/types.h> + struct drm_i915_private; +struct intel_gt; #if IS_REACHABLE(CONFIG_HWMON) void i915_hwmon_register(struct drm_i915_private *i915); void i915_hwmon_unregister(struct drm_i915_private *i915); +void i915_hwmon_power_max_disable(struct drm_i915_private *i915, bool *old); +void i915_hwmon_power_max_restore(struct drm_i915_private *i915, bool old); #else static inline void i915_hwmon_register(struct drm_i915_private *i915) { }; static inline void i915_hwmon_unregister(struct drm_i915_private *i915) { }; +static inline void i915_hwmon_power_max_disable(struct drm_i915_private *i915, bool *old) { }; +static inline void i915_hwmon_power_max_restore(struct drm_i915_private *i915, bool old) { }; #endif #endif /* __I915_HWMON_H__ */ -- 2.38.0 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* [Intel-gfx] [PATCH 3/3] drm/i915/hwmon: Block waiting for GuC reset to complete 2023-04-20 16:40 [Intel-gfx] [PATCH v6 0/3] drm/i915/guc: Disable PL1 power limit when loading GuC firmware Ashutosh Dixit 2023-04-20 16:40 ` [Intel-gfx] [PATCH 1/3] drm/i915/hwmon: Get mutex and rpm ref just once in hwm_power_max_write Ashutosh Dixit 2023-04-20 16:40 ` [Intel-gfx] [PATCH 2/3] drm/i915/guc: Disable PL1 power limit when loading GuC firmware Ashutosh Dixit @ 2023-04-20 16:40 ` Ashutosh Dixit 2023-04-20 17:26 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/guc: Disable PL1 power limit when loading GuC firmware Patchwork ` (2 subsequent siblings) 5 siblings, 0 replies; 13+ messages in thread From: Ashutosh Dixit @ 2023-04-20 16:40 UTC (permalink / raw) To: intel-gfx; +Cc: dri-devel, Rodrigo Vivi Instead of erroring out when GuC reset is in progress, block waiting for GuC reset to complete which is a more reasonable uapi behavior. v2: Avoid race between wake_up_all and waiting for wakeup (Rodrigo) v3: Remove timeout when blocked (Tvrtko) Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> --- drivers/gpu/drm/i915/i915_hwmon.c | 29 +++++++++++++++++++++++++---- 1 file changed, 25 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_hwmon.c b/drivers/gpu/drm/i915/i915_hwmon.c index 9ab8971679fe3..a3bdd9f68a458 100644 --- a/drivers/gpu/drm/i915/i915_hwmon.c +++ b/drivers/gpu/drm/i915/i915_hwmon.c @@ -51,6 +51,7 @@ struct hwm_drvdata { char name[12]; int gt_n; bool reset_in_progress; + wait_queue_head_t waitq; }; struct i915_hwmon { @@ -397,14 +398,32 @@ hwm_power_max_write(struct hwm_drvdata *ddat, long val) { struct i915_hwmon *hwmon = ddat->hwmon; intel_wakeref_t wakeref; + DEFINE_WAIT(wait); int ret = 0; u32 nval; - mutex_lock(&hwmon->hwmon_lock); - if (hwmon->ddat.reset_in_progress) { - ret = -EAGAIN; - goto unlock; + /* Block waiting for GuC reset to complete when needed */ + for (;;) { + mutex_lock(&hwmon->hwmon_lock); + + prepare_to_wait(&ddat->waitq, &wait, TASK_INTERRUPTIBLE); + + if (!hwmon->ddat.reset_in_progress) + break; + + if (signal_pending(current)) { + ret = -EINTR; + break; + } + + mutex_unlock(&hwmon->hwmon_lock); + + schedule(); } + finish_wait(&ddat->waitq, &wait); + if (ret) + goto unlock; + wakeref = intel_runtime_pm_get(ddat->uncore->rpm); /* Disable PL1 limit and verify, because the limit cannot be disabled on all platforms */ @@ -508,6 +527,7 @@ void i915_hwmon_power_max_restore(struct drm_i915_private *i915, bool old) intel_uncore_rmw(hwmon->ddat.uncore, hwmon->rg.pkg_rapl_limit, PKG_PWR_LIM_1_EN, old ? PKG_PWR_LIM_1_EN : 0); hwmon->ddat.reset_in_progress = false; + wake_up_all(&hwmon->ddat.waitq); mutex_unlock(&hwmon->hwmon_lock); } @@ -784,6 +804,7 @@ void i915_hwmon_register(struct drm_i915_private *i915) ddat->uncore = &i915->uncore; snprintf(ddat->name, sizeof(ddat->name), "i915"); ddat->gt_n = -1; + init_waitqueue_head(&ddat->waitq); for_each_gt(gt, i915, i) { ddat_gt = hwmon->ddat_gt + i; -- 2.38.0 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/guc: Disable PL1 power limit when loading GuC firmware 2023-04-20 16:40 [Intel-gfx] [PATCH v6 0/3] drm/i915/guc: Disable PL1 power limit when loading GuC firmware Ashutosh Dixit ` (2 preceding siblings ...) 2023-04-20 16:40 ` [Intel-gfx] [PATCH 3/3] drm/i915/hwmon: Block waiting for GuC reset to complete Ashutosh Dixit @ 2023-04-20 17:26 ` Patchwork 2023-04-20 17:37 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2023-04-21 0:08 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork 5 siblings, 0 replies; 13+ messages in thread From: Patchwork @ 2023-04-20 17:26 UTC (permalink / raw) To: Dixit, Ashutosh; +Cc: intel-gfx == Series Details == Series: drm/i915/guc: Disable PL1 power limit when loading GuC firmware URL : https://patchwork.freedesktop.org/series/116768/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:192:35: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:192:35: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:195:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:195:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:195:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:195:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:237:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:237:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:239:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:239:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:66:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:66:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:92:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:92:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:100:17: warning: unreplaced symbol 'old' +./include/asm-generic/bitops/generic-non-atomic.h:100:17: warning: unreplaced symbol 'old' +./include/asm-generic/bitops/generic-non-atomic.h:100:23: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:100:23: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:100:9: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:100:9: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:105:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:105:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:107:9: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:107:9: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:108:9: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:108:9: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:109:9: warning: unreplaced symbol 'old' +./include/asm-generic/bitops/generic-non-atomic.h:109:9: warning: unreplaced symbol 'old' +./include/asm-generic/bitops/generic-non-atomic.h:111:10: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:111:10: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:111:14: warning: unreplaced symbol 'old' +./include/asm-generic/bitops/generic-non-atomic.h:111:14: warning: unreplaced symbol 'old' +./include/asm-generic/bitops/generic-non-atomic.h:111:20: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:111:20: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:112:17: warning: unreplaced symbol 'old' +./include/asm-generic/bitops/generic-non-atomic.h:112:17: warning: unreplaced symbol 'old' +./include/asm-generic/bitops/generic-non-atomic.h:112:23: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:112:23: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:112:9: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:112:9: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:121:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:121:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:128:9: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:128:9: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:166:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:166:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:168:9: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:168:9: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:169:9: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:169:9: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:170:9: warning: unreplaced symbol 'val' +./include/asm-generic/bitops/generic-non-atomic.h:170:9: warning: unreplaced symbol 'val' +./include/asm-generic/bitops/generic-non-atomic.h:172:19: warning: unreplaced symbol 'val' +./include/asm-generic/bitops/generic-non-atomic.h:172:19: warning: unreplaced symbol 'val' +./include/asm-generic/bitops/generic-non-atomic.h:172:25: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:172:25: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:172:9: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:172:9: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:28:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:28:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:30:9: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:30:9: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:31:9: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:31:9: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:33:10: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:33:10: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:33:16: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:33:16: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:37:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:37:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:39:9: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:39:9: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:40:9: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:40:9: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:42:10: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:42:10: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:42:16: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:42:16: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:55:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:55:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:57:9: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:57:9: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:58:9: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:58:9: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:60:10: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:60:10: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:60:15: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:60:15: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:73:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:73:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:75:9: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:75:9: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:76:9: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:76:9: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:77:9: warning: unreplaced symbol 'old' +./include/asm-generic/bitops/generic-non-atomic.h:77:9: warning: unreplaced symbol 'old' +./include/asm-generic/bitops/generic-non-atomic.h:79:10: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:79:10: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:79:14: warning: unreplaced symbol 'old' +./include/asm-generic/bitops/generic-non-atomic.h:79:14: warning: unreplaced symbol 'old' +./include/asm-generic/bitops/generic-non-atomic.h:79:20: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:79:20: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:80:17: warning: unreplaced symbol 'old' +./include/asm-generic/bitops/generic-non-atomic.h:80:17: warning: unreplaced symbol 'old' +./include/asm-generic/bitops/generic-non-atomic.h:80:23: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:80:23: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:80:9: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:80:9: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:93:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:93:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:95:9: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:95:9: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:96:9: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:96:9: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:97:9: warning: unreplaced symbol 'old' +./include/asm-generic/bitops/generic-non-atomic.h:97:9: warning: unreplaced symbol 'old' +./include/asm-generic/bitops/generic-non-atomic.h:99:10: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:99:10: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:99:14: warning: unreplaced symbol 'old' +./include/asm-generic/bitops/generic-non-atomic.h:99:14: warning: unreplaced symbol 'old' +./include/asm-generic/bitops/generic-non-atomic.h:99:21: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:99:21: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/instrumented-non-atomic.h:100:9: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/instrumented-non-atomic.h:100:9: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/instrumented-non-atomic.h:112:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/instrumented-non-atomic.h:112:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/instrumented-non-atomic.h:115:9: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/instrumented-non-atomic.h:115:9: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/instrumented-non-atomic.h:127:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/instrumented-non-atomic.h:127:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/instrumented-non-atomic.h:130:9: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/instrumented-non-atomic.h:130:9: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/instrumented-non-atomic.h:139:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/instrumented-non-atomic.h:139:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/instrumented-non-atomic.h:142:9: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/instrumented-non-atomic.h:142:9: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/instrumented-non-atomic.h:26:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/instrumented-non-atomic.h:26:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/instrumented-non-atomic.h:42:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/instrumented-non-atomic.h:42:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/instrumented-non-atomic.h:58:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/instrumented-non-atomic.h:58:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/instrumented-non-atomic.h:97:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/instrumented-non-atomic.h:97:1: warning: unreplaced symbol 'return' ^ permalink raw reply [flat|nested] 13+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/guc: Disable PL1 power limit when loading GuC firmware 2023-04-20 16:40 [Intel-gfx] [PATCH v6 0/3] drm/i915/guc: Disable PL1 power limit when loading GuC firmware Ashutosh Dixit ` (3 preceding siblings ...) 2023-04-20 17:26 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/guc: Disable PL1 power limit when loading GuC firmware Patchwork @ 2023-04-20 17:37 ` Patchwork 2023-04-21 0:08 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork 5 siblings, 0 replies; 13+ messages in thread From: Patchwork @ 2023-04-20 17:37 UTC (permalink / raw) To: Dixit, Ashutosh; +Cc: intel-gfx [-- Attachment #1: Type: text/plain, Size: 2722 bytes --] == Series Details == Series: drm/i915/guc: Disable PL1 power limit when loading GuC firmware URL : https://patchwork.freedesktop.org/series/116768/ State : success == Summary == CI Bug Log - changes from CI_DRM_13034 -> Patchwork_116768v1 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116768v1/index.html Participating hosts (37 -> 35) ------------------------------ Missing (2): bat-mtlp-8 fi-snb-2520m Known issues ------------ Here are the changes found in Patchwork_116768v1 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@i915_selftest@live@requests: - bat-rpls-1: [PASS][1] -> [ABORT][2] ([i915#4983] / [i915#7911]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13034/bat-rpls-1/igt@i915_selftest@live@requests.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116768v1/bat-rpls-1/igt@i915_selftest@live@requests.html * igt@kms_chamelium_hpd@common-hpd-after-suspend: - bat-adlp-6: NOTRUN -> [SKIP][3] ([i915#7828]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116768v1/bat-adlp-6/igt@kms_chamelium_hpd@common-hpd-after-suspend.html #### Possible fixes #### * igt@i915_suspend@basic-s3-without-i915: - bat-adlp-6: [INCOMPLETE][4] ([i915#7443]) -> [PASS][5] [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13034/bat-adlp-6/igt@i915_suspend@basic-s3-without-i915.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116768v1/bat-adlp-6/igt@i915_suspend@basic-s3-without-i915.html [i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983 [i915#7443]: https://gitlab.freedesktop.org/drm/intel/issues/7443 [i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828 [i915#7911]: https://gitlab.freedesktop.org/drm/intel/issues/7911 Build changes ------------- * Linux: CI_DRM_13034 -> Patchwork_116768v1 CI-20190529: 20190529 CI_DRM_13034: bf6a3fbb5a6d7afbbaeb93043fd0001d6b83591b @ git://anongit.freedesktop.org/gfx-ci/linux IGT_7263: a6bd8f415c4ec41b5a014c7db47e46c81ffd0074 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_116768v1: bf6a3fbb5a6d7afbbaeb93043fd0001d6b83591b @ git://anongit.freedesktop.org/gfx-ci/linux ### Linux commits 39178baf855c drm/i915/hwmon: Block waiting for GuC reset to complete d6f8cf406cba drm/i915/guc: Disable PL1 power limit when loading GuC firmware 1341c465cd24 drm/i915/hwmon: Get mutex and rpm ref just once in hwm_power_max_write == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116768v1/index.html [-- Attachment #2: Type: text/html, Size: 3389 bytes --] ^ permalink raw reply [flat|nested] 13+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/guc: Disable PL1 power limit when loading GuC firmware 2023-04-20 16:40 [Intel-gfx] [PATCH v6 0/3] drm/i915/guc: Disable PL1 power limit when loading GuC firmware Ashutosh Dixit ` (4 preceding siblings ...) 2023-04-20 17:37 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork @ 2023-04-21 0:08 ` Patchwork 2023-04-25 0:26 ` Dixit, Ashutosh 5 siblings, 1 reply; 13+ messages in thread From: Patchwork @ 2023-04-21 0:08 UTC (permalink / raw) To: Dixit, Ashutosh; +Cc: intel-gfx [-- Attachment #1: Type: text/plain, Size: 12461 bytes --] == Series Details == Series: drm/i915/guc: Disable PL1 power limit when loading GuC firmware URL : https://patchwork.freedesktop.org/series/116768/ State : failure == Summary == CI Bug Log - changes from CI_DRM_13034_full -> Patchwork_116768v1_full ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_116768v1_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_116768v1_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (7 -> 7) ------------------------------ No changes in participating hosts Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_116768v1_full: ### IGT changes ### #### Possible regressions #### * igt@gem_ppgtt@blt-vs-render-ctx0: - shard-snb: [PASS][1] -> [DMESG-FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13034/shard-snb6/igt@gem_ppgtt@blt-vs-render-ctx0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116768v1/shard-snb6/igt@gem_ppgtt@blt-vs-render-ctx0.html #### Suppressed #### The following results come from untrusted machines, tests, or statuses. They do not affect the overall result. * igt@kms_flip@2x-flip-vs-fences-interruptible: - {shard-dg1}: NOTRUN -> [SKIP][3] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116768v1/shard-dg1-17/igt@kms_flip@2x-flip-vs-fences-interruptible.html Known issues ------------ Here are the changes found in Patchwork_116768v1_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt@gem_barrier_race@remote-request@rcs0: - shard-glk: [PASS][4] -> [ABORT][5] ([i915#8211]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13034/shard-glk9/igt@gem_barrier_race@remote-request@rcs0.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116768v1/shard-glk9/igt@gem_barrier_race@remote-request@rcs0.html * igt@kms_color@ctm-0-25@pipe-b-vga-1: - shard-snb: NOTRUN -> [SKIP][6] ([fdo#109271]) +8 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116768v1/shard-snb7/igt@kms_color@ctm-0-25@pipe-b-vga-1.html * igt@kms_flip@flip-vs-blocking-wf-vblank@c-hdmi-a2: - shard-glk: [PASS][7] -> [FAIL][8] ([i915#2122]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13034/shard-glk4/igt@kms_flip@flip-vs-blocking-wf-vblank@c-hdmi-a2.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116768v1/shard-glk1/igt@kms_flip@flip-vs-blocking-wf-vblank@c-hdmi-a2.html * igt@kms_flip@plain-flip-fb-recreate@b-dp1: - shard-apl: [PASS][9] -> [FAIL][10] ([i915#2122]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13034/shard-apl3/igt@kms_flip@plain-flip-fb-recreate@b-dp1.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116768v1/shard-apl2/igt@kms_flip@plain-flip-fb-recreate@b-dp1.html #### Possible fixes #### * igt@drm_fdinfo@most-busy-check-all@rcs0: - {shard-rkl}: [FAIL][11] ([i915#7742]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13034/shard-rkl-3/igt@drm_fdinfo@most-busy-check-all@rcs0.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116768v1/shard-rkl-7/igt@drm_fdinfo@most-busy-check-all@rcs0.html * igt@gem_barrier_race@remote-request@rcs0: - {shard-rkl}: [ABORT][13] ([i915#8211]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13034/shard-rkl-7/igt@gem_barrier_race@remote-request@rcs0.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116768v1/shard-rkl-4/igt@gem_barrier_race@remote-request@rcs0.html * igt@gem_exec_endless@dispatch@rcs0: - {shard-tglu}: [TIMEOUT][15] ([i915#3778]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13034/shard-tglu-8/igt@gem_exec_endless@dispatch@rcs0.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116768v1/shard-tglu-8/igt@gem_exec_endless@dispatch@rcs0.html * igt@gem_exec_fair@basic-none@vecs0: - {shard-rkl}: [FAIL][17] ([i915#2842]) -> [PASS][18] +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13034/shard-rkl-7/igt@gem_exec_fair@basic-none@vecs0.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116768v1/shard-rkl-6/igt@gem_exec_fair@basic-none@vecs0.html * igt@gem_exec_fair@basic-pace-solo@rcs0: - shard-apl: [FAIL][19] ([i915#2842]) -> [PASS][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13034/shard-apl2/igt@gem_exec_fair@basic-pace-solo@rcs0.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116768v1/shard-apl7/igt@gem_exec_fair@basic-pace-solo@rcs0.html * igt@i915_pm_rpm@modeset-lpsp: - {shard-rkl}: [SKIP][21] ([i915#1397]) -> [PASS][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13034/shard-rkl-1/igt@i915_pm_rpm@modeset-lpsp.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116768v1/shard-rkl-7/igt@i915_pm_rpm@modeset-lpsp.html * igt@i915_pm_rpm@modeset-non-lpsp: - {shard-dg1}: [SKIP][23] ([i915#1397]) -> [PASS][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13034/shard-dg1-14/igt@i915_pm_rpm@modeset-non-lpsp.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116768v1/shard-dg1-15/igt@i915_pm_rpm@modeset-non-lpsp.html * igt@i915_pm_rps@engine-order: - shard-apl: [FAIL][25] ([i915#6537]) -> [PASS][26] [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13034/shard-apl4/igt@i915_pm_rps@engine-order.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116768v1/shard-apl3/igt@i915_pm_rps@engine-order.html * igt@kms_cursor_legacy@forked-bo@pipe-b: - {shard-rkl}: [INCOMPLETE][27] ([i915#8011]) -> [PASS][28] [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13034/shard-rkl-7/igt@kms_cursor_legacy@forked-bo@pipe-b.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116768v1/shard-rkl-4/igt@kms_cursor_legacy@forked-bo@pipe-b.html * igt@kms_flip@flip-vs-expired-vblank@c-dp1: - shard-apl: [FAIL][29] ([i915#79]) -> [PASS][30] [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13034/shard-apl1/igt@kms_flip@flip-vs-expired-vblank@c-dp1.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116768v1/shard-apl6/igt@kms_flip@flip-vs-expired-vblank@c-dp1.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [IGT#2]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/2 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289 [fdo#109314]: https://bugs.freedesktop.org/show_bug.cgi?id=109314 [fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189 [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068 [fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615 [fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072 [i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397 [i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122 [i915#2433]: https://gitlab.freedesktop.org/drm/intel/issues/2433 [i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527 [i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575 [i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587 [i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672 [i915#284]: https://gitlab.freedesktop.org/drm/intel/issues/284 [i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842 [i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281 [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282 [i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297 [i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299 [i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359 [i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458 [i915#3528]: https://gitlab.freedesktop.org/drm/intel/issues/3528 [i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539 [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555 [i915#3591]: https://gitlab.freedesktop.org/drm/intel/issues/3591 [i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638 [i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689 [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708 [i915#3778]: https://gitlab.freedesktop.org/drm/intel/issues/3778 [i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886 [i915#3938]: https://gitlab.freedesktop.org/drm/intel/issues/3938 [i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955 [i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070 [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077 [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083 [i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212 [i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270 [i915#4391]: https://gitlab.freedesktop.org/drm/intel/issues/4391 [i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538 [i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579 [i915#4771]: https://gitlab.freedesktop.org/drm/intel/issues/4771 [i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812 [i915#4816]: https://gitlab.freedesktop.org/drm/intel/issues/4816 [i915#4833]: https://gitlab.freedesktop.org/drm/intel/issues/4833 [i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852 [i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860 [i915#4880]: https://gitlab.freedesktop.org/drm/intel/issues/4880 [i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176 [i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235 [i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286 [i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289 [i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325 [i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354 [i915#5563]: https://gitlab.freedesktop.org/drm/intel/issues/5563 [i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784 [i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095 [i915#6433]: https://gitlab.freedesktop.org/drm/intel/issues/6433 [i915#6493]: https://gitlab.freedesktop.org/drm/intel/issues/6493 [i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524 [i915#6537]: https://gitlab.freedesktop.org/drm/intel/issues/6537 [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658 [i915#7116]: https://gitlab.freedesktop.org/drm/intel/issues/7116 [i915#7561]: https://gitlab.freedesktop.org/drm/intel/issues/7561 [i915#7711]: https://gitlab.freedesktop.org/drm/intel/issues/7711 [i915#7742]: https://gitlab.freedesktop.org/drm/intel/issues/7742 [i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828 [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 [i915#7975]: https://gitlab.freedesktop.org/drm/intel/issues/7975 [i915#8011]: https://gitlab.freedesktop.org/drm/intel/issues/8011 [i915#8211]: https://gitlab.freedesktop.org/drm/intel/issues/8211 Build changes ------------- * Linux: CI_DRM_13034 -> Patchwork_116768v1 CI-20190529: 20190529 CI_DRM_13034: bf6a3fbb5a6d7afbbaeb93043fd0001d6b83591b @ git://anongit.freedesktop.org/gfx-ci/linux IGT_7263: a6bd8f415c4ec41b5a014c7db47e46c81ffd0074 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_116768v1: bf6a3fbb5a6d7afbbaeb93043fd0001d6b83591b @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116768v1/index.html [-- Attachment #2: Type: text/html, Size: 9407 bytes --] ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/guc: Disable PL1 power limit when loading GuC firmware 2023-04-21 0:08 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork @ 2023-04-25 0:26 ` Dixit, Ashutosh 0 siblings, 0 replies; 13+ messages in thread From: Dixit, Ashutosh @ 2023-04-25 0:26 UTC (permalink / raw) To: intel-gfx On Thu, 20 Apr 2023 17:08:42 -0700, Patchwork wrote: > > Patch Details > > Series: drm/i915/guc: Disable PL1 power limit when loading GuC firmware > URL: https://patchwork.freedesktop.org/series/116768/ > State: failure > Details: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116768v1/index.html > > CI Bug Log - changes from CI_DRM_13034_full -> Patchwork_116768v1_full > > Summary > > FAILURE > > Serious unknown changes coming with Patchwork_116768v1_full absolutely need to be > verified manually. > > If you think the reported changes have nothing to do with the changes > introduced in Patchwork_116768v1_full, please notify your bug team to allow them > to document this new failure mode, which will reduce false positives in CI. > > Participating hosts (7 -> 7) > > No changes in participating hosts > > Possible new issues > > Here are the unknown changes that may have been introduced in Patchwork_116768v1_full: > > IGT changes > > Possible regressions > > * igt@gem_ppgtt@blt-vs-render-ctx0: > > * shard-snb: PASS -> DMESG-FAIL This failure is unrelated to this series. The series has effect only for dGFX. Thanks. -- Ashutosh ^ permalink raw reply [flat|nested] 13+ messages in thread
* [Intel-gfx] [PATCH 0/3] drm/i915/guc: Disable PL1 power limit when loading GuC firmware @ 2023-04-10 22:35 Ashutosh Dixit 2023-04-10 22:35 ` [Intel-gfx] [PATCH 2/3] " Ashutosh Dixit 0 siblings, 1 reply; 13+ messages in thread From: Ashutosh Dixit @ 2023-04-10 22:35 UTC (permalink / raw) To: intel-gfx; +Cc: dri-devel, Rodrigo Vivi Updates to Patch 2/3 and Patch 3/3 in this version. Ashutosh Dixit (3): drm/i915/hwmon: Get mutex and rpm ref just once in hwm_power_max_write drm/i915/guc: Disable PL1 power limit when loading GuC firmware drm/i915/hwmon: Block waiting for GuC reset to complete drivers/gpu/drm/i915/gt/uc/intel_uc.c | 13 +++- drivers/gpu/drm/i915/i915_hwmon.c | 94 +++++++++++++++++++++++---- drivers/gpu/drm/i915/i915_hwmon.h | 7 ++ 3 files changed, 100 insertions(+), 14 deletions(-) -- 2.38.0 ^ permalink raw reply [flat|nested] 13+ messages in thread
* [Intel-gfx] [PATCH 2/3] drm/i915/guc: Disable PL1 power limit when loading GuC firmware 2023-04-10 22:35 [Intel-gfx] [PATCH 0/3] " Ashutosh Dixit @ 2023-04-10 22:35 ` Ashutosh Dixit 0 siblings, 0 replies; 13+ messages in thread From: Ashutosh Dixit @ 2023-04-10 22:35 UTC (permalink / raw) To: intel-gfx; +Cc: dri-devel, Rodrigo Vivi On dGfx, the PL1 power limit being enabled and set to a low value results in a low GPU operating freq. It also negates the freq raise operation which is done before GuC firmware load. As a result GuC firmware load can time out. Such timeouts were seen in the GL #8062 bug below (where the PL1 power limit was enabled and set to a low value). Therefore disable the PL1 power limit when allowed by HW when loading GuC firmware. v2: - Take mutex (to disallow writes to power1_max) across GuC reset/fw load - Add hwm_power_max_restore to error return code path v3 (Jani N): - Add/remove explanatory comments - Function renames - Type corrections - Locking annotation v4: - Don't hold the lock across GuC reset (Rodrigo) - New locking scheme (suggested by Rodrigo) - Eliminate rpm_get in power_max_disable/restore, not needed (Tvrtko) v5: - Fix uninitialized pl1en variable compile warning reported by kernel build robot by creating new err_rps label Link: https://gitlab.freedesktop.org/drm/intel/-/issues/8062 Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> --- drivers/gpu/drm/i915/gt/uc/intel_uc.c | 13 +++++++-- drivers/gpu/drm/i915/i915_hwmon.c | 40 +++++++++++++++++++++++++++ drivers/gpu/drm/i915/i915_hwmon.h | 7 +++++ 3 files changed, 58 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c b/drivers/gpu/drm/i915/gt/uc/intel_uc.c index 4ccb4be4c9cba..996168312340e 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c @@ -18,6 +18,7 @@ #include "intel_uc.h" #include "i915_drv.h" +#include "i915_hwmon.h" static const struct intel_uc_ops uc_ops_off; static const struct intel_uc_ops uc_ops_on; @@ -461,6 +462,7 @@ static int __uc_init_hw(struct intel_uc *uc) struct intel_guc *guc = &uc->guc; struct intel_huc *huc = &uc->huc; int ret, attempts; + bool pl1en; GEM_BUG_ON(!intel_uc_supports_guc(uc)); GEM_BUG_ON(!intel_uc_wants_guc(uc)); @@ -491,6 +493,9 @@ static int __uc_init_hw(struct intel_uc *uc) else attempts = 1; + /* Disable a potentially low PL1 power limit to allow freq to be raised */ + i915_hwmon_power_max_disable(gt->i915, &pl1en); + intel_rps_raise_unslice(&uc_to_gt(uc)->rps); while (attempts--) { @@ -500,7 +505,7 @@ static int __uc_init_hw(struct intel_uc *uc) */ ret = __uc_sanitize(uc); if (ret) - goto err_out; + goto err_rps; intel_huc_fw_upload(huc); intel_guc_ads_reset(guc); @@ -547,6 +552,8 @@ static int __uc_init_hw(struct intel_uc *uc) intel_rps_lower_unslice(&uc_to_gt(uc)->rps); } + i915_hwmon_power_max_restore(gt->i915, pl1en); + guc_info(guc, "submission %s\n", str_enabled_disabled(intel_uc_uses_guc_submission(uc))); guc_info(guc, "SLPC %s\n", str_enabled_disabled(intel_uc_uses_guc_slpc(uc))); @@ -559,10 +566,12 @@ static int __uc_init_hw(struct intel_uc *uc) intel_guc_submission_disable(guc); err_log_capture: __uc_capture_load_err_log(uc); -err_out: +err_rps: /* Return GT back to RPn */ intel_rps_lower_unslice(&uc_to_gt(uc)->rps); + i915_hwmon_power_max_restore(gt->i915, pl1en); +err_out: __uc_sanitize(uc); if (!ret) { diff --git a/drivers/gpu/drm/i915/i915_hwmon.c b/drivers/gpu/drm/i915/i915_hwmon.c index 7f44e809ca155..9ab8971679fe3 100644 --- a/drivers/gpu/drm/i915/i915_hwmon.c +++ b/drivers/gpu/drm/i915/i915_hwmon.c @@ -50,6 +50,7 @@ struct hwm_drvdata { struct hwm_energy_info ei; /* Energy info for energy1_input */ char name[12]; int gt_n; + bool reset_in_progress; }; struct i915_hwmon { @@ -400,6 +401,10 @@ hwm_power_max_write(struct hwm_drvdata *ddat, long val) u32 nval; mutex_lock(&hwmon->hwmon_lock); + if (hwmon->ddat.reset_in_progress) { + ret = -EAGAIN; + goto unlock; + } wakeref = intel_runtime_pm_get(ddat->uncore->rpm); /* Disable PL1 limit and verify, because the limit cannot be disabled on all platforms */ @@ -421,6 +426,7 @@ hwm_power_max_write(struct hwm_drvdata *ddat, long val) PKG_PWR_LIM_1_EN | PKG_PWR_LIM_1, nval); exit: intel_runtime_pm_put(ddat->uncore->rpm, wakeref); +unlock: mutex_unlock(&hwmon->hwmon_lock); return ret; } @@ -472,6 +478,40 @@ hwm_power_write(struct hwm_drvdata *ddat, u32 attr, int chan, long val) } } +void i915_hwmon_power_max_disable(struct drm_i915_private *i915, bool *old) +{ + struct i915_hwmon *hwmon = i915->hwmon; + u32 r; + + if (!hwmon || !i915_mmio_reg_valid(hwmon->rg.pkg_rapl_limit)) + return; + + mutex_lock(&hwmon->hwmon_lock); + + hwmon->ddat.reset_in_progress = true; + r = intel_uncore_rmw(hwmon->ddat.uncore, hwmon->rg.pkg_rapl_limit, + PKG_PWR_LIM_1_EN, 0); + *old = !!(r & PKG_PWR_LIM_1_EN); + + mutex_unlock(&hwmon->hwmon_lock); +} + +void i915_hwmon_power_max_restore(struct drm_i915_private *i915, bool old) +{ + struct i915_hwmon *hwmon = i915->hwmon; + + if (!hwmon || !i915_mmio_reg_valid(hwmon->rg.pkg_rapl_limit)) + return; + + mutex_lock(&hwmon->hwmon_lock); + + intel_uncore_rmw(hwmon->ddat.uncore, hwmon->rg.pkg_rapl_limit, + PKG_PWR_LIM_1_EN, old ? PKG_PWR_LIM_1_EN : 0); + hwmon->ddat.reset_in_progress = false; + + mutex_unlock(&hwmon->hwmon_lock); +} + static umode_t hwm_energy_is_visible(const struct hwm_drvdata *ddat, u32 attr) { diff --git a/drivers/gpu/drm/i915/i915_hwmon.h b/drivers/gpu/drm/i915/i915_hwmon.h index 7ca9cf2c34c96..0fcb7de844061 100644 --- a/drivers/gpu/drm/i915/i915_hwmon.h +++ b/drivers/gpu/drm/i915/i915_hwmon.h @@ -7,14 +7,21 @@ #ifndef __I915_HWMON_H__ #define __I915_HWMON_H__ +#include <linux/types.h> + struct drm_i915_private; +struct intel_gt; #if IS_REACHABLE(CONFIG_HWMON) void i915_hwmon_register(struct drm_i915_private *i915); void i915_hwmon_unregister(struct drm_i915_private *i915); +void i915_hwmon_power_max_disable(struct drm_i915_private *i915, bool *old); +void i915_hwmon_power_max_restore(struct drm_i915_private *i915, bool old); #else static inline void i915_hwmon_register(struct drm_i915_private *i915) { }; static inline void i915_hwmon_unregister(struct drm_i915_private *i915) { }; +static inline void i915_hwmon_power_max_disable(struct drm_i915_private *i915, bool *old) { }; +static inline void i915_hwmon_power_max_restore(struct drm_i915_private *i915, bool old) { }; #endif #endif /* __I915_HWMON_H__ */ -- 2.38.0 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* [Intel-gfx] [PATCH v4 0/3] drm/i915/guc: Disable PL1 power limit when loading GuC firmware @ 2023-04-06 4:45 Ashutosh Dixit 2023-04-06 4:45 ` [Intel-gfx] [PATCH 2/3] " Ashutosh Dixit 0 siblings, 1 reply; 13+ messages in thread From: Ashutosh Dixit @ 2023-04-06 4:45 UTC (permalink / raw) To: intel-gfx; +Cc: dri-devel, Rodrigo Vivi Split the v3 patch into 3 patches for easier review, can squash later if needed. Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> Ashutosh Dixit (3): drm/i915/hwmon: Get mutex and rpm ref just once in hwm_power_max_write drm/i915/guc: Disable PL1 power limit when loading GuC firmware drm/i915/hwmon: Block waiting for GuC reset to complete drivers/gpu/drm/i915/gt/uc/intel_uc.c | 9 ++++ drivers/gpu/drm/i915/i915_hwmon.c | 75 ++++++++++++++++++++++----- drivers/gpu/drm/i915/i915_hwmon.h | 7 +++ 3 files changed, 78 insertions(+), 13 deletions(-) -- 2.38.0 ^ permalink raw reply [flat|nested] 13+ messages in thread
* [Intel-gfx] [PATCH 2/3] drm/i915/guc: Disable PL1 power limit when loading GuC firmware 2023-04-06 4:45 [Intel-gfx] [PATCH v4 0/3] " Ashutosh Dixit @ 2023-04-06 4:45 ` Ashutosh Dixit 2023-04-06 9:16 ` kernel test robot 2023-04-07 11:08 ` Rodrigo Vivi 0 siblings, 2 replies; 13+ messages in thread From: Ashutosh Dixit @ 2023-04-06 4:45 UTC (permalink / raw) To: intel-gfx; +Cc: dri-devel, Rodrigo Vivi On dGfx, the PL1 power limit being enabled and set to a low value results in a low GPU operating freq. It also negates the freq raise operation which is done before GuC firmware load. As a result GuC firmware load can time out. Such timeouts were seen in the GL #8062 bug below (where the PL1 power limit was enabled and set to a low value). Therefore disable the PL1 power limit when allowed by HW when loading GuC firmware. v2: - Take mutex (to disallow writes to power1_max) across GuC reset/fw load - Add hwm_power_max_restore to error return code path v3 (Jani N): - Add/remove explanatory comments - Function renames - Type corrections - Locking annotation v4: - Don't hold the lock across GuC reset (Rodrigo) - New locking scheme (suggested by Rodrigo) - Eliminate rpm_get in power_max_disable/restore, not needed (Tvrtko) Link: https://gitlab.freedesktop.org/drm/intel/-/issues/8062 Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com> --- drivers/gpu/drm/i915/gt/uc/intel_uc.c | 9 ++++++ drivers/gpu/drm/i915/i915_hwmon.c | 40 +++++++++++++++++++++++++++ drivers/gpu/drm/i915/i915_hwmon.h | 7 +++++ 3 files changed, 56 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c b/drivers/gpu/drm/i915/gt/uc/intel_uc.c index 4ccb4be4c9cba..aa8e35a5636a0 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c @@ -18,6 +18,7 @@ #include "intel_uc.h" #include "i915_drv.h" +#include "i915_hwmon.h" static const struct intel_uc_ops uc_ops_off; static const struct intel_uc_ops uc_ops_on; @@ -461,6 +462,7 @@ static int __uc_init_hw(struct intel_uc *uc) struct intel_guc *guc = &uc->guc; struct intel_huc *huc = &uc->huc; int ret, attempts; + bool pl1en; GEM_BUG_ON(!intel_uc_supports_guc(uc)); GEM_BUG_ON(!intel_uc_wants_guc(uc)); @@ -491,6 +493,9 @@ static int __uc_init_hw(struct intel_uc *uc) else attempts = 1; + /* Disable a potentially low PL1 power limit to allow freq to be raised */ + i915_hwmon_power_max_disable(gt->i915, &pl1en); + intel_rps_raise_unslice(&uc_to_gt(uc)->rps); while (attempts--) { @@ -547,6 +552,8 @@ static int __uc_init_hw(struct intel_uc *uc) intel_rps_lower_unslice(&uc_to_gt(uc)->rps); } + i915_hwmon_power_max_restore(gt->i915, pl1en); + guc_info(guc, "submission %s\n", str_enabled_disabled(intel_uc_uses_guc_submission(uc))); guc_info(guc, "SLPC %s\n", str_enabled_disabled(intel_uc_uses_guc_slpc(uc))); @@ -563,6 +570,8 @@ static int __uc_init_hw(struct intel_uc *uc) /* Return GT back to RPn */ intel_rps_lower_unslice(&uc_to_gt(uc)->rps); + i915_hwmon_power_max_restore(gt->i915, pl1en); + __uc_sanitize(uc); if (!ret) { diff --git a/drivers/gpu/drm/i915/i915_hwmon.c b/drivers/gpu/drm/i915/i915_hwmon.c index 7f44e809ca155..9ab8971679fe3 100644 --- a/drivers/gpu/drm/i915/i915_hwmon.c +++ b/drivers/gpu/drm/i915/i915_hwmon.c @@ -50,6 +50,7 @@ struct hwm_drvdata { struct hwm_energy_info ei; /* Energy info for energy1_input */ char name[12]; int gt_n; + bool reset_in_progress; }; struct i915_hwmon { @@ -400,6 +401,10 @@ hwm_power_max_write(struct hwm_drvdata *ddat, long val) u32 nval; mutex_lock(&hwmon->hwmon_lock); + if (hwmon->ddat.reset_in_progress) { + ret = -EAGAIN; + goto unlock; + } wakeref = intel_runtime_pm_get(ddat->uncore->rpm); /* Disable PL1 limit and verify, because the limit cannot be disabled on all platforms */ @@ -421,6 +426,7 @@ hwm_power_max_write(struct hwm_drvdata *ddat, long val) PKG_PWR_LIM_1_EN | PKG_PWR_LIM_1, nval); exit: intel_runtime_pm_put(ddat->uncore->rpm, wakeref); +unlock: mutex_unlock(&hwmon->hwmon_lock); return ret; } @@ -472,6 +478,40 @@ hwm_power_write(struct hwm_drvdata *ddat, u32 attr, int chan, long val) } } +void i915_hwmon_power_max_disable(struct drm_i915_private *i915, bool *old) +{ + struct i915_hwmon *hwmon = i915->hwmon; + u32 r; + + if (!hwmon || !i915_mmio_reg_valid(hwmon->rg.pkg_rapl_limit)) + return; + + mutex_lock(&hwmon->hwmon_lock); + + hwmon->ddat.reset_in_progress = true; + r = intel_uncore_rmw(hwmon->ddat.uncore, hwmon->rg.pkg_rapl_limit, + PKG_PWR_LIM_1_EN, 0); + *old = !!(r & PKG_PWR_LIM_1_EN); + + mutex_unlock(&hwmon->hwmon_lock); +} + +void i915_hwmon_power_max_restore(struct drm_i915_private *i915, bool old) +{ + struct i915_hwmon *hwmon = i915->hwmon; + + if (!hwmon || !i915_mmio_reg_valid(hwmon->rg.pkg_rapl_limit)) + return; + + mutex_lock(&hwmon->hwmon_lock); + + intel_uncore_rmw(hwmon->ddat.uncore, hwmon->rg.pkg_rapl_limit, + PKG_PWR_LIM_1_EN, old ? PKG_PWR_LIM_1_EN : 0); + hwmon->ddat.reset_in_progress = false; + + mutex_unlock(&hwmon->hwmon_lock); +} + static umode_t hwm_energy_is_visible(const struct hwm_drvdata *ddat, u32 attr) { diff --git a/drivers/gpu/drm/i915/i915_hwmon.h b/drivers/gpu/drm/i915/i915_hwmon.h index 7ca9cf2c34c96..0fcb7de844061 100644 --- a/drivers/gpu/drm/i915/i915_hwmon.h +++ b/drivers/gpu/drm/i915/i915_hwmon.h @@ -7,14 +7,21 @@ #ifndef __I915_HWMON_H__ #define __I915_HWMON_H__ +#include <linux/types.h> + struct drm_i915_private; +struct intel_gt; #if IS_REACHABLE(CONFIG_HWMON) void i915_hwmon_register(struct drm_i915_private *i915); void i915_hwmon_unregister(struct drm_i915_private *i915); +void i915_hwmon_power_max_disable(struct drm_i915_private *i915, bool *old); +void i915_hwmon_power_max_restore(struct drm_i915_private *i915, bool old); #else static inline void i915_hwmon_register(struct drm_i915_private *i915) { }; static inline void i915_hwmon_unregister(struct drm_i915_private *i915) { }; +static inline void i915_hwmon_power_max_disable(struct drm_i915_private *i915, bool *old) { }; +static inline void i915_hwmon_power_max_restore(struct drm_i915_private *i915, bool old) { }; #endif #endif /* __I915_HWMON_H__ */ -- 2.38.0 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [Intel-gfx] [PATCH 2/3] drm/i915/guc: Disable PL1 power limit when loading GuC firmware 2023-04-06 4:45 ` [Intel-gfx] [PATCH 2/3] " Ashutosh Dixit @ 2023-04-06 9:16 ` kernel test robot 2023-04-07 11:08 ` Rodrigo Vivi 1 sibling, 0 replies; 13+ messages in thread From: kernel test robot @ 2023-04-06 9:16 UTC (permalink / raw) To: Ashutosh Dixit, intel-gfx; +Cc: Rodrigo Vivi, llvm, dri-devel, oe-kbuild-all Hi Ashutosh, kernel test robot noticed the following build warnings: [auto build test WARNING on drm-tip/drm-tip] url: https://github.com/intel-lab-lkp/linux/commits/Ashutosh-Dixit/drm-i915-hwmon-Get-mutex-and-rpm-ref-just-once-in-hwm_power_max_write/20230406-124659 base: git://anongit.freedesktop.org/drm/drm-tip drm-tip patch link: https://lore.kernel.org/r/20230406044522.3108359-3-ashutosh.dixit%40intel.com patch subject: [Intel-gfx] [PATCH 2/3] drm/i915/guc: Disable PL1 power limit when loading GuC firmware config: i386-randconfig-a002-20230403 (https://download.01.org/0day-ci/archive/20230406/202304061654.yjntbbxy-lkp@intel.com/config) compiler: clang version 14.0.6 (https://github.com/llvm/llvm-project f28c006a5895fc0e329fe15fead81e37457cb1d1) reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # https://github.com/intel-lab-lkp/linux/commit/b4aa935db7f0b46437cdaa39f0149ad835ceb73c git remote add linux-review https://github.com/intel-lab-lkp/linux git fetch --no-tags linux-review Ashutosh-Dixit/drm-i915-hwmon-Get-mutex-and-rpm-ref-just-once-in-hwm_power_max_write/20230406-124659 git checkout b4aa935db7f0b46437cdaa39f0149ad835ceb73c # save the config file mkdir build_dir && cp config build_dir/.config COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=i386 olddefconfig COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=i386 SHELL=/bin/bash drivers/gpu/drm/i915/ If you fix the issue, kindly add following tag where applicable | Reported-by: kernel test robot <lkp@intel.com> | Link: https://lore.kernel.org/oe-kbuild-all/202304061654.yjntbbxy-lkp@intel.com/ All warnings (new ones prefixed by >>): >> drivers/gpu/drm/i915/gt/uc/intel_uc.c:484:6: warning: variable 'pl1en' is used uninitialized whenever 'if' condition is true [-Wsometimes-uninitialized] if (ret) ^~~ drivers/gpu/drm/i915/gt/uc/intel_uc.c:573:41: note: uninitialized use occurs here i915_hwmon_power_max_restore(gt->i915, pl1en); ^~~~~ drivers/gpu/drm/i915/gt/uc/intel_uc.c:484:2: note: remove the 'if' if its condition is always false if (ret) ^~~~~~~~ drivers/gpu/drm/i915/gt/uc/intel_uc.c:475:6: warning: variable 'pl1en' is used uninitialized whenever 'if' condition is true [-Wsometimes-uninitialized] if (!intel_uc_fw_is_loadable(&guc->fw)) { ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/i915/gt/uc/intel_uc.c:573:41: note: uninitialized use occurs here i915_hwmon_power_max_restore(gt->i915, pl1en); ^~~~~ drivers/gpu/drm/i915/gt/uc/intel_uc.c:475:2: note: remove the 'if' if its condition is always false if (!intel_uc_fw_is_loadable(&guc->fw)) { ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/i915/gt/uc/intel_uc.c:465:12: note: initialize the variable 'pl1en' to silence this warning bool pl1en; ^ = 0 2 warnings generated. vim +484 drivers/gpu/drm/i915/gt/uc/intel_uc.c afd088ac05f120d drivers/gpu/drm/i915/gt/uc/intel_uc.c John Harrison 2022-01-06 457 6fbeda0bfd210f9 drivers/gpu/drm/i915/gt/uc/intel_uc.c Michal Wajdeczko 2020-01-10 458 static int __uc_init_hw(struct intel_uc *uc) 6fbeda0bfd210f9 drivers/gpu/drm/i915/gt/uc/intel_uc.c Michal Wajdeczko 2020-01-10 459 { 2f8c06cb6622b55 drivers/gpu/drm/i915/gt/uc/intel_uc.c Michal Wajdeczko 2023-01-28 460 struct intel_gt *gt = uc_to_gt(uc); 2f8c06cb6622b55 drivers/gpu/drm/i915/gt/uc/intel_uc.c Michal Wajdeczko 2023-01-28 461 struct drm_i915_private *i915 = gt->i915; 6fbeda0bfd210f9 drivers/gpu/drm/i915/gt/uc/intel_uc.c Michal Wajdeczko 2020-01-10 462 struct intel_guc *guc = &uc->guc; 6fbeda0bfd210f9 drivers/gpu/drm/i915/gt/uc/intel_uc.c Michal Wajdeczko 2020-01-10 463 struct intel_huc *huc = &uc->huc; 6fbeda0bfd210f9 drivers/gpu/drm/i915/gt/uc/intel_uc.c Michal Wajdeczko 2020-01-10 464 int ret, attempts; b4aa935db7f0b46 drivers/gpu/drm/i915/gt/uc/intel_uc.c Ashutosh Dixit 2023-04-05 465 bool pl1en; 6fbeda0bfd210f9 drivers/gpu/drm/i915/gt/uc/intel_uc.c Michal Wajdeczko 2020-01-10 466 6fbeda0bfd210f9 drivers/gpu/drm/i915/gt/uc/intel_uc.c Michal Wajdeczko 2020-01-10 467 GEM_BUG_ON(!intel_uc_supports_guc(uc)); bfe5a40a7b9a967 drivers/gpu/drm/i915/gt/uc/intel_uc.c Daniele Ceraolo Spurio 2020-02-18 468 GEM_BUG_ON(!intel_uc_wants_guc(uc)); 356c484822e6ac9 drivers/gpu/drm/i915/gt/uc/intel_uc.c Michal Wajdeczko 2019-08-16 469 2f8c06cb6622b55 drivers/gpu/drm/i915/gt/uc/intel_uc.c Michal Wajdeczko 2023-01-28 470 print_fw_ver(gt, &guc->fw); afd088ac05f120d drivers/gpu/drm/i915/gt/uc/intel_uc.c John Harrison 2022-01-06 471 afd088ac05f120d drivers/gpu/drm/i915/gt/uc/intel_uc.c John Harrison 2022-01-06 472 if (intel_uc_uses_huc(uc)) 2f8c06cb6622b55 drivers/gpu/drm/i915/gt/uc/intel_uc.c Michal Wajdeczko 2023-01-28 473 print_fw_ver(gt, &huc->fw); afd088ac05f120d drivers/gpu/drm/i915/gt/uc/intel_uc.c John Harrison 2022-01-06 474 42f96e5bd41e91f drivers/gpu/drm/i915/gt/uc/intel_uc.c Daniele Ceraolo Spurio 2020-02-18 475 if (!intel_uc_fw_is_loadable(&guc->fw)) { 6fbeda0bfd210f9 drivers/gpu/drm/i915/gt/uc/intel_uc.c Michal Wajdeczko 2020-01-10 476 ret = __uc_check_hw(uc) || ee402140274e870 drivers/gpu/drm/i915/gt/uc/intel_uc.c Michal Wajdeczko 2019-08-18 477 intel_uc_fw_is_overridden(&guc->fw) || 202c98e71692484 drivers/gpu/drm/i915/gt/uc/intel_uc.c Daniele Ceraolo Spurio 2020-02-18 478 intel_uc_wants_guc_submission(uc) ? ee402140274e870 drivers/gpu/drm/i915/gt/uc/intel_uc.c Michal Wajdeczko 2019-08-18 479 intel_uc_fw_status_to_error(guc->fw.status) : 0; ae7a3166a708bee drivers/gpu/drm/i915/gt/uc/intel_uc.c Michal Wajdeczko 2019-08-11 480 goto err_out; ae7a3166a708bee drivers/gpu/drm/i915/gt/uc/intel_uc.c Michal Wajdeczko 2019-08-11 481 } ae7a3166a708bee drivers/gpu/drm/i915/gt/uc/intel_uc.c Michal Wajdeczko 2019-08-11 482 63064d822c964c0 drivers/gpu/drm/i915/gt/uc/intel_uc.c Daniele Ceraolo Spurio 2019-07-30 483 ret = uc_init_wopcm(uc); 63064d822c964c0 drivers/gpu/drm/i915/gt/uc/intel_uc.c Daniele Ceraolo Spurio 2019-07-30 @484 if (ret) 63064d822c964c0 drivers/gpu/drm/i915/gt/uc/intel_uc.c Daniele Ceraolo Spurio 2019-07-30 485 goto err_out; 63064d822c964c0 drivers/gpu/drm/i915/gt/uc/intel_uc.c Daniele Ceraolo Spurio 2019-07-30 486 e5a1ad035938e60 drivers/gpu/drm/i915/gt/uc/intel_uc.c Matthew Brost 2021-07-26 487 intel_guc_reset_interrupts(guc); 61b5c1587dd82a8 drivers/gpu/drm/i915/intel_uc.c Michał Winiarski 2017-12-13 488 6cd5a72c357732e drivers/gpu/drm/i915/intel_uc.c Arkadiusz Hiler 2017-03-14 489 /* WaEnableuKernelHeaderValidFix:skl */ 6cd5a72c357732e drivers/gpu/drm/i915/intel_uc.c Arkadiusz Hiler 2017-03-14 490 /* WaEnableGuCBootHashCheckNotSet:skl,bxt,kbl */ c816723b6b8a627 drivers/gpu/drm/i915/gt/uc/intel_uc.c Lucas De Marchi 2021-06-05 491 if (GRAPHICS_VER(i915) == 9) 6cd5a72c357732e drivers/gpu/drm/i915/intel_uc.c Arkadiusz Hiler 2017-03-14 492 attempts = 3; 6cd5a72c357732e drivers/gpu/drm/i915/intel_uc.c Arkadiusz Hiler 2017-03-14 493 else 6cd5a72c357732e drivers/gpu/drm/i915/intel_uc.c Arkadiusz Hiler 2017-03-14 494 attempts = 1; 6cd5a72c357732e drivers/gpu/drm/i915/intel_uc.c Arkadiusz Hiler 2017-03-14 495 b4aa935db7f0b46 drivers/gpu/drm/i915/gt/uc/intel_uc.c Ashutosh Dixit 2023-04-05 496 /* Disable a potentially low PL1 power limit to allow freq to be raised */ b4aa935db7f0b46 drivers/gpu/drm/i915/gt/uc/intel_uc.c Ashutosh Dixit 2023-04-05 497 i915_hwmon_power_max_disable(gt->i915, &pl1en); b4aa935db7f0b46 drivers/gpu/drm/i915/gt/uc/intel_uc.c Ashutosh Dixit 2023-04-05 498 1c40d40f6835cde drivers/gpu/drm/i915/gt/uc/intel_uc.c Vinay Belgaumkar 2021-12-16 499 intel_rps_raise_unslice(&uc_to_gt(uc)->rps); 1c40d40f6835cde drivers/gpu/drm/i915/gt/uc/intel_uc.c Vinay Belgaumkar 2021-12-16 500 6cd5a72c357732e drivers/gpu/drm/i915/intel_uc.c Arkadiusz Hiler 2017-03-14 501 while (attempts--) { 6cd5a72c357732e drivers/gpu/drm/i915/intel_uc.c Arkadiusz Hiler 2017-03-14 502 /* 6cd5a72c357732e drivers/gpu/drm/i915/intel_uc.c Arkadiusz Hiler 2017-03-14 503 * Always reset the GuC just before (re)loading, so 6cd5a72c357732e drivers/gpu/drm/i915/intel_uc.c Arkadiusz Hiler 2017-03-14 504 * that the state and timing are fairly predictable 6cd5a72c357732e drivers/gpu/drm/i915/intel_uc.c Arkadiusz Hiler 2017-03-14 505 */ 771051eaa74661f drivers/gpu/drm/i915/gt/uc/intel_uc.c Michal Wajdeczko 2019-08-02 506 ret = __uc_sanitize(uc); 6cd5a72c357732e drivers/gpu/drm/i915/intel_uc.c Arkadiusz Hiler 2017-03-14 507 if (ret) 61b5c1587dd82a8 drivers/gpu/drm/i915/intel_uc.c Michał Winiarski 2017-12-13 508 goto err_out; 6cd5a72c357732e drivers/gpu/drm/i915/intel_uc.c Arkadiusz Hiler 2017-03-14 509 a8dc0f6d187bccc drivers/gpu/drm/i915/gt/uc/intel_uc.c Michal Wajdeczko 2019-08-18 510 intel_huc_fw_upload(huc); 386e300fe9fae7e drivers/gpu/drm/i915/intel_uc.c Michal Wajdeczko 2019-05-27 511 intel_guc_ads_reset(guc); 2bf8fb39eb70b6c drivers/gpu/drm/i915/gt/uc/intel_uc.c Daniele Ceraolo Spurio 2019-07-24 512 intel_guc_write_params(guc); e8668bbcb0f91c7 drivers/gpu/drm/i915/intel_uc.c Michal Wajdeczko 2017-10-16 513 ret = intel_guc_fw_upload(guc); 52b832606038c5b drivers/gpu/drm/i915/intel_uc.c Robert M. Fosha 2019-03-29 514 if (ret == 0) 6cd5a72c357732e drivers/gpu/drm/i915/intel_uc.c Arkadiusz Hiler 2017-03-14 515 break; 6cd5a72c357732e drivers/gpu/drm/i915/intel_uc.c Arkadiusz Hiler 2017-03-14 516 2f8c06cb6622b55 drivers/gpu/drm/i915/gt/uc/intel_uc.c Michal Wajdeczko 2023-01-28 517 gt_dbg(gt, "GuC fw load failed (%pe) will reset and retry %d more time(s)\n", 2f8c06cb6622b55 drivers/gpu/drm/i915/gt/uc/intel_uc.c Michal Wajdeczko 2023-01-28 518 ERR_PTR(ret), attempts); 6cd5a72c357732e drivers/gpu/drm/i915/intel_uc.c Arkadiusz Hiler 2017-03-14 519 } 6cd5a72c357732e drivers/gpu/drm/i915/intel_uc.c Arkadiusz Hiler 2017-03-14 520 6cd5a72c357732e drivers/gpu/drm/i915/intel_uc.c Arkadiusz Hiler 2017-03-14 521 /* Did we succeded or run out of retries? */ 6cd5a72c357732e drivers/gpu/drm/i915/intel_uc.c Arkadiusz Hiler 2017-03-14 522 if (ret) ac58d2ab0ad9c8b drivers/gpu/drm/i915/intel_uc.c Daniele Ceraolo Spurio 2017-05-22 523 goto err_log_capture; 6cd5a72c357732e drivers/gpu/drm/i915/intel_uc.c Arkadiusz Hiler 2017-03-14 524 789a625158b0c0c drivers/gpu/drm/i915/intel_uc.c Michal Wajdeczko 2017-05-02 525 ret = guc_enable_communication(guc); 789a625158b0c0c drivers/gpu/drm/i915/intel_uc.c Michal Wajdeczko 2017-05-02 526 if (ret) ac58d2ab0ad9c8b drivers/gpu/drm/i915/intel_uc.c Daniele Ceraolo Spurio 2017-05-22 527 goto err_log_capture; 789a625158b0c0c drivers/gpu/drm/i915/intel_uc.c Michal Wajdeczko 2017-05-02 528 6f67930af78f10a drivers/gpu/drm/i915/gt/uc/intel_uc.c Daniele Ceraolo Spurio 2022-05-04 529 /* 6f67930af78f10a drivers/gpu/drm/i915/gt/uc/intel_uc.c Daniele Ceraolo Spurio 2022-05-04 530 * GSC-loaded HuC is authenticated by the GSC, so we don't need to 6f67930af78f10a drivers/gpu/drm/i915/gt/uc/intel_uc.c Daniele Ceraolo Spurio 2022-05-04 531 * trigger the auth here. However, given that the HuC loaded this way 6f67930af78f10a drivers/gpu/drm/i915/gt/uc/intel_uc.c Daniele Ceraolo Spurio 2022-05-04 532 * survive GT reset, we still need to update our SW bookkeeping to make 6f67930af78f10a drivers/gpu/drm/i915/gt/uc/intel_uc.c Daniele Ceraolo Spurio 2022-05-04 533 * sure it reflects the correct HW status. 6f67930af78f10a drivers/gpu/drm/i915/gt/uc/intel_uc.c Daniele Ceraolo Spurio 2022-05-04 534 */ 6f67930af78f10a drivers/gpu/drm/i915/gt/uc/intel_uc.c Daniele Ceraolo Spurio 2022-05-04 535 if (intel_huc_is_loaded_by_gsc(huc)) 6f67930af78f10a drivers/gpu/drm/i915/gt/uc/intel_uc.c Daniele Ceraolo Spurio 2022-05-04 536 intel_huc_update_auth_status(huc); 6f67930af78f10a drivers/gpu/drm/i915/gt/uc/intel_uc.c Daniele Ceraolo Spurio 2022-05-04 537 else a8dc0f6d187bccc drivers/gpu/drm/i915/gt/uc/intel_uc.c Michal Wajdeczko 2019-08-18 538 intel_huc_auth(huc); 0dfa1cee613e03c drivers/gpu/drm/i915/intel_uc.c Michal Wajdeczko 2017-12-06 539 cd414f4f59f64d7 drivers/gpu/drm/i915/gt/uc/intel_uc.c John Harrison 2023-02-17 540 if (intel_uc_uses_guc_submission(uc)) { cd414f4f59f64d7 drivers/gpu/drm/i915/gt/uc/intel_uc.c John Harrison 2023-02-17 541 ret = intel_guc_submission_enable(guc); cd414f4f59f64d7 drivers/gpu/drm/i915/gt/uc/intel_uc.c John Harrison 2023-02-17 542 if (ret) cd414f4f59f64d7 drivers/gpu/drm/i915/gt/uc/intel_uc.c John Harrison 2023-02-17 543 goto err_log_capture; cd414f4f59f64d7 drivers/gpu/drm/i915/gt/uc/intel_uc.c John Harrison 2023-02-17 544 } 6cd5a72c357732e drivers/gpu/drm/i915/intel_uc.c Arkadiusz Hiler 2017-03-14 545 63c0eb30bfe9269 drivers/gpu/drm/i915/gt/uc/intel_uc.c Vinay Belgaumkar 2021-07-30 546 if (intel_uc_uses_guc_slpc(uc)) { 63c0eb30bfe9269 drivers/gpu/drm/i915/gt/uc/intel_uc.c Vinay Belgaumkar 2021-07-30 547 ret = intel_guc_slpc_enable(&guc->slpc); 63c0eb30bfe9269 drivers/gpu/drm/i915/gt/uc/intel_uc.c Vinay Belgaumkar 2021-07-30 548 if (ret) 63c0eb30bfe9269 drivers/gpu/drm/i915/gt/uc/intel_uc.c Vinay Belgaumkar 2021-07-30 549 goto err_submission; 1c40d40f6835cde drivers/gpu/drm/i915/gt/uc/intel_uc.c Vinay Belgaumkar 2021-12-16 550 } else { 1c40d40f6835cde drivers/gpu/drm/i915/gt/uc/intel_uc.c Vinay Belgaumkar 2021-12-16 551 /* Restore GT back to RPn for non-SLPC path */ 1c40d40f6835cde drivers/gpu/drm/i915/gt/uc/intel_uc.c Vinay Belgaumkar 2021-12-16 552 intel_rps_lower_unslice(&uc_to_gt(uc)->rps); 63c0eb30bfe9269 drivers/gpu/drm/i915/gt/uc/intel_uc.c Vinay Belgaumkar 2021-07-30 553 } 63c0eb30bfe9269 drivers/gpu/drm/i915/gt/uc/intel_uc.c Vinay Belgaumkar 2021-07-30 554 b4aa935db7f0b46 drivers/gpu/drm/i915/gt/uc/intel_uc.c Ashutosh Dixit 2023-04-05 555 i915_hwmon_power_max_restore(gt->i915, pl1en); b4aa935db7f0b46 drivers/gpu/drm/i915/gt/uc/intel_uc.c Ashutosh Dixit 2023-04-05 556 4fd4fde8e42e164 drivers/gpu/drm/i915/gt/uc/intel_uc.c John Harrison 2023-02-06 557 guc_info(guc, "submission %s\n", str_enabled_disabled(intel_uc_uses_guc_submission(uc))); 4fd4fde8e42e164 drivers/gpu/drm/i915/gt/uc/intel_uc.c John Harrison 2023-02-06 558 guc_info(guc, "SLPC %s\n", str_enabled_disabled(intel_uc_uses_guc_slpc(uc))); 63c0eb30bfe9269 drivers/gpu/drm/i915/gt/uc/intel_uc.c Vinay Belgaumkar 2021-07-30 559 6cd5a72c357732e drivers/gpu/drm/i915/intel_uc.c Arkadiusz Hiler 2017-03-14 560 return 0; 6cd5a72c357732e drivers/gpu/drm/i915/intel_uc.c Arkadiusz Hiler 2017-03-14 561 6cd5a72c357732e drivers/gpu/drm/i915/intel_uc.c Arkadiusz Hiler 2017-03-14 562 /* 6cd5a72c357732e drivers/gpu/drm/i915/intel_uc.c Arkadiusz Hiler 2017-03-14 563 * We've failed to load the firmware :( 6cd5a72c357732e drivers/gpu/drm/i915/intel_uc.c Arkadiusz Hiler 2017-03-14 564 */ 63c0eb30bfe9269 drivers/gpu/drm/i915/gt/uc/intel_uc.c Vinay Belgaumkar 2021-07-30 565 err_submission: 63c0eb30bfe9269 drivers/gpu/drm/i915/gt/uc/intel_uc.c Vinay Belgaumkar 2021-07-30 566 intel_guc_submission_disable(guc); ac58d2ab0ad9c8b drivers/gpu/drm/i915/intel_uc.c Daniele Ceraolo Spurio 2017-05-22 567 err_log_capture: 32ff76e80c2400c drivers/gpu/drm/i915/gt/uc/intel_uc.c Michal Wajdeczko 2019-08-02 568 __uc_capture_load_err_log(uc); 121981fafe699d9 drivers/gpu/drm/i915/intel_uc.c Michal Wajdeczko 2017-12-06 569 err_out: 1c40d40f6835cde drivers/gpu/drm/i915/gt/uc/intel_uc.c Vinay Belgaumkar 2021-12-16 570 /* Return GT back to RPn */ 1c40d40f6835cde drivers/gpu/drm/i915/gt/uc/intel_uc.c Vinay Belgaumkar 2021-12-16 571 intel_rps_lower_unslice(&uc_to_gt(uc)->rps); 1c40d40f6835cde drivers/gpu/drm/i915/gt/uc/intel_uc.c Vinay Belgaumkar 2021-12-16 572 b4aa935db7f0b46 drivers/gpu/drm/i915/gt/uc/intel_uc.c Ashutosh Dixit 2023-04-05 573 i915_hwmon_power_max_restore(gt->i915, pl1en); b4aa935db7f0b46 drivers/gpu/drm/i915/gt/uc/intel_uc.c Ashutosh Dixit 2023-04-05 574 ca7b2c1bbede618 drivers/gpu/drm/i915/gt/uc/intel_uc.c Daniele Ceraolo Spurio 2019-07-13 575 __uc_sanitize(uc); 89195bab5d8c540 drivers/gpu/drm/i915/intel_uc.c Michal Wajdeczko 2019-05-22 576 ee402140274e870 drivers/gpu/drm/i915/gt/uc/intel_uc.c Michal Wajdeczko 2019-08-18 577 if (!ret) { 2f8c06cb6622b55 drivers/gpu/drm/i915/gt/uc/intel_uc.c Michal Wajdeczko 2023-01-28 578 gt_notice(gt, "GuC is uninitialized\n"); ee402140274e870 drivers/gpu/drm/i915/gt/uc/intel_uc.c Michal Wajdeczko 2019-08-18 579 /* We want to run without GuC submission */ ee402140274e870 drivers/gpu/drm/i915/gt/uc/intel_uc.c Michal Wajdeczko 2019-08-18 580 return 0; ee402140274e870 drivers/gpu/drm/i915/gt/uc/intel_uc.c Michal Wajdeczko 2019-08-18 581 } ee402140274e870 drivers/gpu/drm/i915/gt/uc/intel_uc.c Michal Wajdeczko 2019-08-18 582 2f8c06cb6622b55 drivers/gpu/drm/i915/gt/uc/intel_uc.c Michal Wajdeczko 2023-01-28 583 gt_probe_error(gt, "GuC initialization failed %pe\n", ERR_PTR(ret)); a5f978c3609f02a drivers/gpu/drm/i915/gt/uc/intel_uc.c Michal Wajdeczko 2019-08-11 584 a5f978c3609f02a drivers/gpu/drm/i915/gt/uc/intel_uc.c Michal Wajdeczko 2019-08-11 585 /* We want to keep KMS alive */ a5f978c3609f02a drivers/gpu/drm/i915/gt/uc/intel_uc.c Michal Wajdeczko 2019-08-11 586 return -EIO; 6cd5a72c357732e drivers/gpu/drm/i915/intel_uc.c Arkadiusz Hiler 2017-03-14 587 } 6cd5a72c357732e drivers/gpu/drm/i915/intel_uc.c Arkadiusz Hiler 2017-03-14 588 -- 0-DAY CI Kernel Test Service https://github.com/intel/lkp-tests ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [Intel-gfx] [PATCH 2/3] drm/i915/guc: Disable PL1 power limit when loading GuC firmware 2023-04-06 4:45 ` [Intel-gfx] [PATCH 2/3] " Ashutosh Dixit 2023-04-06 9:16 ` kernel test robot @ 2023-04-07 11:08 ` Rodrigo Vivi 2023-04-10 22:17 ` Dixit, Ashutosh 1 sibling, 1 reply; 13+ messages in thread From: Rodrigo Vivi @ 2023-04-07 11:08 UTC (permalink / raw) To: Ashutosh Dixit; +Cc: intel-gfx, dri-devel On Wed, Apr 05, 2023 at 09:45:21PM -0700, Ashutosh Dixit wrote: > On dGfx, the PL1 power limit being enabled and set to a low value results > in a low GPU operating freq. It also negates the freq raise operation which > is done before GuC firmware load. As a result GuC firmware load can time > out. Such timeouts were seen in the GL #8062 bug below (where the PL1 power > limit was enabled and set to a low value). Therefore disable the PL1 power > limit when allowed by HW when loading GuC firmware. > > v2: > - Take mutex (to disallow writes to power1_max) across GuC reset/fw load > - Add hwm_power_max_restore to error return code path > > v3 (Jani N): > - Add/remove explanatory comments > - Function renames > - Type corrections > - Locking annotation > > v4: > - Don't hold the lock across GuC reset (Rodrigo) > - New locking scheme (suggested by Rodrigo) > - Eliminate rpm_get in power_max_disable/restore, not needed (Tvrtko) > > Link: https://gitlab.freedesktop.org/drm/intel/-/issues/8062 > Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com> > --- > drivers/gpu/drm/i915/gt/uc/intel_uc.c | 9 ++++++ > drivers/gpu/drm/i915/i915_hwmon.c | 40 +++++++++++++++++++++++++++ > drivers/gpu/drm/i915/i915_hwmon.h | 7 +++++ > 3 files changed, 56 insertions(+) > > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c b/drivers/gpu/drm/i915/gt/uc/intel_uc.c > index 4ccb4be4c9cba..aa8e35a5636a0 100644 > --- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c > +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c > @@ -18,6 +18,7 @@ > #include "intel_uc.h" > > #include "i915_drv.h" > +#include "i915_hwmon.h" > > static const struct intel_uc_ops uc_ops_off; > static const struct intel_uc_ops uc_ops_on; > @@ -461,6 +462,7 @@ static int __uc_init_hw(struct intel_uc *uc) > struct intel_guc *guc = &uc->guc; > struct intel_huc *huc = &uc->huc; > int ret, attempts; > + bool pl1en; we need to initialize this to make warn free builds happy... what's our default btw? false? true? we need to read it back? > > GEM_BUG_ON(!intel_uc_supports_guc(uc)); > GEM_BUG_ON(!intel_uc_wants_guc(uc)); > @@ -491,6 +493,9 @@ static int __uc_init_hw(struct intel_uc *uc) > else > attempts = 1; > > + /* Disable a potentially low PL1 power limit to allow freq to be raised */ > + i915_hwmon_power_max_disable(gt->i915, &pl1en); > + > intel_rps_raise_unslice(&uc_to_gt(uc)->rps); > > while (attempts--) { > @@ -547,6 +552,8 @@ static int __uc_init_hw(struct intel_uc *uc) > intel_rps_lower_unslice(&uc_to_gt(uc)->rps); > } > > + i915_hwmon_power_max_restore(gt->i915, pl1en); > + > guc_info(guc, "submission %s\n", str_enabled_disabled(intel_uc_uses_guc_submission(uc))); > guc_info(guc, "SLPC %s\n", str_enabled_disabled(intel_uc_uses_guc_slpc(uc))); > > @@ -563,6 +570,8 @@ static int __uc_init_hw(struct intel_uc *uc) > /* Return GT back to RPn */ > intel_rps_lower_unslice(&uc_to_gt(uc)->rps); > > + i915_hwmon_power_max_restore(gt->i915, pl1en); > + > __uc_sanitize(uc); > > if (!ret) { > diff --git a/drivers/gpu/drm/i915/i915_hwmon.c b/drivers/gpu/drm/i915/i915_hwmon.c > index 7f44e809ca155..9ab8971679fe3 100644 > --- a/drivers/gpu/drm/i915/i915_hwmon.c > +++ b/drivers/gpu/drm/i915/i915_hwmon.c > @@ -50,6 +50,7 @@ struct hwm_drvdata { > struct hwm_energy_info ei; /* Energy info for energy1_input */ > char name[12]; > int gt_n; > + bool reset_in_progress; > }; > > struct i915_hwmon { > @@ -400,6 +401,10 @@ hwm_power_max_write(struct hwm_drvdata *ddat, long val) > u32 nval; > > mutex_lock(&hwmon->hwmon_lock); > + if (hwmon->ddat.reset_in_progress) { > + ret = -EAGAIN; > + goto unlock; > + } > wakeref = intel_runtime_pm_get(ddat->uncore->rpm); > > /* Disable PL1 limit and verify, because the limit cannot be disabled on all platforms */ > @@ -421,6 +426,7 @@ hwm_power_max_write(struct hwm_drvdata *ddat, long val) > PKG_PWR_LIM_1_EN | PKG_PWR_LIM_1, nval); > exit: > intel_runtime_pm_put(ddat->uncore->rpm, wakeref); > +unlock: > mutex_unlock(&hwmon->hwmon_lock); > return ret; > } > @@ -472,6 +478,40 @@ hwm_power_write(struct hwm_drvdata *ddat, u32 attr, int chan, long val) > } > } > > +void i915_hwmon_power_max_disable(struct drm_i915_private *i915, bool *old) > +{ > + struct i915_hwmon *hwmon = i915->hwmon; > + u32 r; > + > + if (!hwmon || !i915_mmio_reg_valid(hwmon->rg.pkg_rapl_limit)) > + return; > + > + mutex_lock(&hwmon->hwmon_lock); > + > + hwmon->ddat.reset_in_progress = true; > + r = intel_uncore_rmw(hwmon->ddat.uncore, hwmon->rg.pkg_rapl_limit, > + PKG_PWR_LIM_1_EN, 0); > + *old = !!(r & PKG_PWR_LIM_1_EN); > + > + mutex_unlock(&hwmon->hwmon_lock); > +} > + > +void i915_hwmon_power_max_restore(struct drm_i915_private *i915, bool old) > +{ > + struct i915_hwmon *hwmon = i915->hwmon; > + > + if (!hwmon || !i915_mmio_reg_valid(hwmon->rg.pkg_rapl_limit)) > + return; > + > + mutex_lock(&hwmon->hwmon_lock); > + > + intel_uncore_rmw(hwmon->ddat.uncore, hwmon->rg.pkg_rapl_limit, > + PKG_PWR_LIM_1_EN, old ? PKG_PWR_LIM_1_EN : 0); > + hwmon->ddat.reset_in_progress = false; > + > + mutex_unlock(&hwmon->hwmon_lock); > +} you could have combined both functions in a i915_hwmon_power_max_set(struct drm_i915_private *i915, bool val, bool *old) then pass NULL to old on the restoration times and have if (old) *old = !!(r & PKG_PWR_LIM_1_EN); But really up to you here, the current code is clear to follow imho so, with the pl1en initialization fixed: Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> > + > static umode_t > hwm_energy_is_visible(const struct hwm_drvdata *ddat, u32 attr) > { > diff --git a/drivers/gpu/drm/i915/i915_hwmon.h b/drivers/gpu/drm/i915/i915_hwmon.h > index 7ca9cf2c34c96..0fcb7de844061 100644 > --- a/drivers/gpu/drm/i915/i915_hwmon.h > +++ b/drivers/gpu/drm/i915/i915_hwmon.h > @@ -7,14 +7,21 @@ > #ifndef __I915_HWMON_H__ > #define __I915_HWMON_H__ > > +#include <linux/types.h> > + > struct drm_i915_private; > +struct intel_gt; > > #if IS_REACHABLE(CONFIG_HWMON) > void i915_hwmon_register(struct drm_i915_private *i915); > void i915_hwmon_unregister(struct drm_i915_private *i915); > +void i915_hwmon_power_max_disable(struct drm_i915_private *i915, bool *old); > +void i915_hwmon_power_max_restore(struct drm_i915_private *i915, bool old); > #else > static inline void i915_hwmon_register(struct drm_i915_private *i915) { }; > static inline void i915_hwmon_unregister(struct drm_i915_private *i915) { }; > +static inline void i915_hwmon_power_max_disable(struct drm_i915_private *i915, bool *old) { }; > +static inline void i915_hwmon_power_max_restore(struct drm_i915_private *i915, bool old) { }; > #endif > > #endif /* __I915_HWMON_H__ */ > -- > 2.38.0 > ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [Intel-gfx] [PATCH 2/3] drm/i915/guc: Disable PL1 power limit when loading GuC firmware 2023-04-07 11:08 ` Rodrigo Vivi @ 2023-04-10 22:17 ` Dixit, Ashutosh 0 siblings, 0 replies; 13+ messages in thread From: Dixit, Ashutosh @ 2023-04-10 22:17 UTC (permalink / raw) To: Rodrigo Vivi; +Cc: intel-gfx, dri-devel On Fri, 07 Apr 2023 04:08:31 -0700, Rodrigo Vivi wrote: > Hi Rodrigo, > On Wed, Apr 05, 2023 at 09:45:21PM -0700, Ashutosh Dixit wrote: > > On dGfx, the PL1 power limit being enabled and set to a low value results > > in a low GPU operating freq. It also negates the freq raise operation which > > is done before GuC firmware load. As a result GuC firmware load can time > > out. Such timeouts were seen in the GL #8062 bug below (where the PL1 power > > limit was enabled and set to a low value). Therefore disable the PL1 power > > limit when allowed by HW when loading GuC firmware. > > > > v2: > > - Take mutex (to disallow writes to power1_max) across GuC reset/fw load > > - Add hwm_power_max_restore to error return code path > > > > v3 (Jani N): > > - Add/remove explanatory comments > > - Function renames > > - Type corrections > > - Locking annotation > > > > v4: > > - Don't hold the lock across GuC reset (Rodrigo) > > - New locking scheme (suggested by Rodrigo) > > - Eliminate rpm_get in power_max_disable/restore, not needed (Tvrtko) > > > > Link: https://gitlab.freedesktop.org/drm/intel/-/issues/8062 > > Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com> > > --- > > drivers/gpu/drm/i915/gt/uc/intel_uc.c | 9 ++++++ > > drivers/gpu/drm/i915/i915_hwmon.c | 40 +++++++++++++++++++++++++++ > > drivers/gpu/drm/i915/i915_hwmon.h | 7 +++++ > > 3 files changed, 56 insertions(+) > > > > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c b/drivers/gpu/drm/i915/gt/uc/intel_uc.c > > index 4ccb4be4c9cba..aa8e35a5636a0 100644 > > --- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c > > +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c > > @@ -18,6 +18,7 @@ > > #include "intel_uc.h" > > > > #include "i915_drv.h" > > +#include "i915_hwmon.h" > > > > static const struct intel_uc_ops uc_ops_off; > > static const struct intel_uc_ops uc_ops_on; > > @@ -461,6 +462,7 @@ static int __uc_init_hw(struct intel_uc *uc) > > struct intel_guc *guc = &uc->guc; > > struct intel_huc *huc = &uc->huc; > > int ret, attempts; > > + bool pl1en; > > we need to initialize this to make warn free builds happy... > what's our default btw? false? true? we need to read it back? Yes this was a real bug caught by the kernel build robot. We don't know the default till we read it back, which would mean exposing a new function. I have avoided exposing the new function, i.e. I have fixed this by creating a new (err_rps) label which will make sure that the variable is not used unless it is initialized. I am not expecting to see warnings from the build robot with this fix now. > > > > GEM_BUG_ON(!intel_uc_supports_guc(uc)); > > GEM_BUG_ON(!intel_uc_wants_guc(uc)); > > @@ -491,6 +493,9 @@ static int __uc_init_hw(struct intel_uc *uc) > > else > > attempts = 1; > > > > + /* Disable a potentially low PL1 power limit to allow freq to be raised */ > > + i915_hwmon_power_max_disable(gt->i915, &pl1en); > > + > > intel_rps_raise_unslice(&uc_to_gt(uc)->rps); > > > > while (attempts--) { > > @@ -547,6 +552,8 @@ static int __uc_init_hw(struct intel_uc *uc) > > intel_rps_lower_unslice(&uc_to_gt(uc)->rps); > > } > > > > + i915_hwmon_power_max_restore(gt->i915, pl1en); > > + > > guc_info(guc, "submission %s\n", str_enabled_disabled(intel_uc_uses_guc_submission(uc))); > > guc_info(guc, "SLPC %s\n", str_enabled_disabled(intel_uc_uses_guc_slpc(uc))); > > > > @@ -563,6 +570,8 @@ static int __uc_init_hw(struct intel_uc *uc) > > /* Return GT back to RPn */ > > intel_rps_lower_unslice(&uc_to_gt(uc)->rps); > > > > + i915_hwmon_power_max_restore(gt->i915, pl1en); > > + > > __uc_sanitize(uc); > > > > if (!ret) { > > diff --git a/drivers/gpu/drm/i915/i915_hwmon.c b/drivers/gpu/drm/i915/i915_hwmon.c > > index 7f44e809ca155..9ab8971679fe3 100644 > > --- a/drivers/gpu/drm/i915/i915_hwmon.c > > +++ b/drivers/gpu/drm/i915/i915_hwmon.c > > @@ -50,6 +50,7 @@ struct hwm_drvdata { > > struct hwm_energy_info ei; /* Energy info for energy1_input */ > > char name[12]; > > int gt_n; > > + bool reset_in_progress; > > }; > > > > struct i915_hwmon { > > @@ -400,6 +401,10 @@ hwm_power_max_write(struct hwm_drvdata *ddat, long val) > > u32 nval; > > > > mutex_lock(&hwmon->hwmon_lock); > > + if (hwmon->ddat.reset_in_progress) { > > + ret = -EAGAIN; > > + goto unlock; > > + } > > wakeref = intel_runtime_pm_get(ddat->uncore->rpm); > > > > /* Disable PL1 limit and verify, because the limit cannot be disabled on all platforms */ > > @@ -421,6 +426,7 @@ hwm_power_max_write(struct hwm_drvdata *ddat, long val) > > PKG_PWR_LIM_1_EN | PKG_PWR_LIM_1, nval); > > exit: > > intel_runtime_pm_put(ddat->uncore->rpm, wakeref); > > +unlock: > > mutex_unlock(&hwmon->hwmon_lock); > > return ret; > > } > > @@ -472,6 +478,40 @@ hwm_power_write(struct hwm_drvdata *ddat, u32 attr, int chan, long val) > > } > > } > > > > +void i915_hwmon_power_max_disable(struct drm_i915_private *i915, bool *old) > > +{ > > + struct i915_hwmon *hwmon = i915->hwmon; > > + u32 r; > > + > > + if (!hwmon || !i915_mmio_reg_valid(hwmon->rg.pkg_rapl_limit)) > > + return; > > + > > + mutex_lock(&hwmon->hwmon_lock); > > + > > + hwmon->ddat.reset_in_progress = true; > > + r = intel_uncore_rmw(hwmon->ddat.uncore, hwmon->rg.pkg_rapl_limit, > > + PKG_PWR_LIM_1_EN, 0); > > + *old = !!(r & PKG_PWR_LIM_1_EN); > > + > > + mutex_unlock(&hwmon->hwmon_lock); > > +} > > + > > +void i915_hwmon_power_max_restore(struct drm_i915_private *i915, bool old) > > +{ > > + struct i915_hwmon *hwmon = i915->hwmon; > > + > > + if (!hwmon || !i915_mmio_reg_valid(hwmon->rg.pkg_rapl_limit)) > > + return; > > + > > + mutex_lock(&hwmon->hwmon_lock); > > + > > + intel_uncore_rmw(hwmon->ddat.uncore, hwmon->rg.pkg_rapl_limit, > > + PKG_PWR_LIM_1_EN, old ? PKG_PWR_LIM_1_EN : 0); > > + hwmon->ddat.reset_in_progress = false; > > + > > + mutex_unlock(&hwmon->hwmon_lock); > > +} > > you could have combined both functions in a > i915_hwmon_power_max_set(struct drm_i915_private *i915, bool val, bool *old) > > then pass NULL to old on the restoration times > and have > if (old) > *old = !!(r & PKG_PWR_LIM_1_EN); > > But really up to you here, the current code is clear to follow imho > so, with the pl1en initialization fixed: Yes, left this as is. > > Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Have retained the R-b since the fix in __uc_init_hw is minor. Thanks! Ashutosh > > + > > static umode_t > > hwm_energy_is_visible(const struct hwm_drvdata *ddat, u32 attr) > > { > > diff --git a/drivers/gpu/drm/i915/i915_hwmon.h b/drivers/gpu/drm/i915/i915_hwmon.h > > index 7ca9cf2c34c96..0fcb7de844061 100644 > > --- a/drivers/gpu/drm/i915/i915_hwmon.h > > +++ b/drivers/gpu/drm/i915/i915_hwmon.h > > @@ -7,14 +7,21 @@ > > #ifndef __I915_HWMON_H__ > > #define __I915_HWMON_H__ > > > > +#include <linux/types.h> > > + > > struct drm_i915_private; > > +struct intel_gt; > > > > #if IS_REACHABLE(CONFIG_HWMON) > > void i915_hwmon_register(struct drm_i915_private *i915); > > void i915_hwmon_unregister(struct drm_i915_private *i915); > > +void i915_hwmon_power_max_disable(struct drm_i915_private *i915, bool *old); > > +void i915_hwmon_power_max_restore(struct drm_i915_private *i915, bool old); > > #else > > static inline void i915_hwmon_register(struct drm_i915_private *i915) { }; > > static inline void i915_hwmon_unregister(struct drm_i915_private *i915) { }; > > +static inline void i915_hwmon_power_max_disable(struct drm_i915_private *i915, bool *old) { }; > > +static inline void i915_hwmon_power_max_restore(struct drm_i915_private *i915, bool old) { }; > > #endif > > > > #endif /* __I915_HWMON_H__ */ > > -- > > 2.38.0 > > ^ permalink raw reply [flat|nested] 13+ messages in thread
end of thread, other threads:[~2023-04-25 0:26 UTC | newest] Thread overview: 13+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2023-04-20 16:40 [Intel-gfx] [PATCH v6 0/3] drm/i915/guc: Disable PL1 power limit when loading GuC firmware Ashutosh Dixit 2023-04-20 16:40 ` [Intel-gfx] [PATCH 1/3] drm/i915/hwmon: Get mutex and rpm ref just once in hwm_power_max_write Ashutosh Dixit 2023-04-20 16:40 ` [Intel-gfx] [PATCH 2/3] drm/i915/guc: Disable PL1 power limit when loading GuC firmware Ashutosh Dixit 2023-04-20 16:40 ` [Intel-gfx] [PATCH 3/3] drm/i915/hwmon: Block waiting for GuC reset to complete Ashutosh Dixit 2023-04-20 17:26 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/guc: Disable PL1 power limit when loading GuC firmware Patchwork 2023-04-20 17:37 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2023-04-21 0:08 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork 2023-04-25 0:26 ` Dixit, Ashutosh -- strict thread matches above, loose matches on Subject: below -- 2023-04-10 22:35 [Intel-gfx] [PATCH 0/3] " Ashutosh Dixit 2023-04-10 22:35 ` [Intel-gfx] [PATCH 2/3] " Ashutosh Dixit 2023-04-06 4:45 [Intel-gfx] [PATCH v4 0/3] " Ashutosh Dixit 2023-04-06 4:45 ` [Intel-gfx] [PATCH 2/3] " Ashutosh Dixit 2023-04-06 9:16 ` kernel test robot 2023-04-07 11:08 ` Rodrigo Vivi 2023-04-10 22:17 ` Dixit, Ashutosh
This is a public inbox, see mirroring instructions for how to clone and mirror all data and code used for this inbox