* [Intel-gfx] [PATCH v2 0/2] Use i915 instead of dev_priv
@ 2023-04-21 19:00 Andi Shyti
2023-04-21 19:00 ` [Intel-gfx] [PATCH v2 1/2] drm/i915/i915_drv: Use proper parameter naming in for_each_engine() Andi Shyti
` (5 more replies)
0 siblings, 6 replies; 7+ messages in thread
From: Andi Shyti @ 2023-04-21 19:00 UTC (permalink / raw)
To: Intel GFX, DRI Devel; +Cc: Andrzej Hajda, Rodrigo Vivi
Hi,
just another "Friday patch". While reviewing some patches from
Tejas I found a bit confusing the use of dev_priv__ inside the
for_each_engine(), perhaps it should be moved inside the gt/?
As I was at it I made the /dev_priv/i915/ change which is still
harmless. Next in queue is to change the i915_irq.h, which is a
bit tricky (but not much) as the "dev_priv" is hardcoded inside
some defines.
Thank you Andrzej and Rodrigo for your reviews.
Andi
Changelog
=========
v1 -> v2
- Fix double typo in the patch 1 commit:
/for_each_gt/for_each_engine/
- Phrase properly the commit of patch 2.
Andi Shyti (2):
drm/i915/i915_drv: Use proper parameter naming in for_each_engine()
drm/i915/i915_drv: Use i915 instead of dev_priv insied the file_priv
structure
drivers/gpu/drm/i915/i915_drv.h | 462 ++++++++++++++++----------------
1 file changed, 231 insertions(+), 231 deletions(-)
--
2.40.0
^ permalink raw reply [flat|nested] 7+ messages in thread* [Intel-gfx] [PATCH v2 1/2] drm/i915/i915_drv: Use proper parameter naming in for_each_engine() 2023-04-21 19:00 [Intel-gfx] [PATCH v2 0/2] Use i915 instead of dev_priv Andi Shyti @ 2023-04-21 19:00 ` Andi Shyti 2023-04-21 19:00 ` [Intel-gfx] [PATCH v2 2/2] drm/i915/i915_drv: Use i915 instead of dev_priv insied the file_priv structure Andi Shyti ` (4 subsequent siblings) 5 siblings, 0 replies; 7+ messages in thread From: Andi Shyti @ 2023-04-21 19:00 UTC (permalink / raw) To: Intel GFX, DRI Devel; +Cc: Andrzej Hajda, Rodrigo Vivi for_each_engine() loops through engines in the GT, not in dev_priv. Because it's misleading, call it "gt__" instead of "dev_priv__". Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index fe7eeafe9cff6..c16f8a3cd914f 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -381,11 +381,11 @@ static inline struct intel_gt *to_gt(struct drm_i915_private *i915) } /* Simple iterator over all initialised engines */ -#define for_each_engine(engine__, dev_priv__, id__) \ +#define for_each_engine(engine__, gt__, id__) \ for ((id__) = 0; \ (id__) < I915_NUM_ENGINES; \ (id__)++) \ - for_each_if ((engine__) = (dev_priv__)->engine[(id__)]) + for_each_if ((engine__) = (gt__)->engine[(id__)]) /* Iterator over subset of engines selected by mask */ #define for_each_engine_masked(engine__, gt__, mask__, tmp__) \ -- 2.40.0 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* [Intel-gfx] [PATCH v2 2/2] drm/i915/i915_drv: Use i915 instead of dev_priv insied the file_priv structure 2023-04-21 19:00 [Intel-gfx] [PATCH v2 0/2] Use i915 instead of dev_priv Andi Shyti 2023-04-21 19:00 ` [Intel-gfx] [PATCH v2 1/2] drm/i915/i915_drv: Use proper parameter naming in for_each_engine() Andi Shyti @ 2023-04-21 19:00 ` Andi Shyti 2023-04-21 22:29 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Use i915 instead of dev_priv (rev2) Patchwork ` (3 subsequent siblings) 5 siblings, 0 replies; 7+ messages in thread From: Andi Shyti @ 2023-04-21 19:00 UTC (permalink / raw) To: Intel GFX, DRI Devel; +Cc: Andrzej Hajda, Rodrigo Vivi In the process of renaming all instances of 'dev_priv' to 'i915', start using 'i915' within the i915_drv.h file. Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com> Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 458 ++++++++++++++++---------------- 1 file changed, 229 insertions(+), 229 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index c16f8a3cd914f..14c5338c96a6b 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -407,11 +407,11 @@ static inline struct intel_gt *to_gt(struct drm_i915_private *i915) (engine__) && (engine__)->uabi_class == (class__); \ (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node))) -#define INTEL_INFO(dev_priv) (&(dev_priv)->__info) -#define RUNTIME_INFO(dev_priv) (&(dev_priv)->__runtime) -#define DRIVER_CAPS(dev_priv) (&(dev_priv)->caps) +#define INTEL_INFO(i915) (&(i915)->__info) +#define RUNTIME_INFO(i915) (&(i915)->__runtime) +#define DRIVER_CAPS(i915) (&(i915)->caps) -#define INTEL_DEVID(dev_priv) (RUNTIME_INFO(dev_priv)->device_id) +#define INTEL_DEVID(i915) (RUNTIME_INFO(i915)->device_id) #define IP_VER(ver, rel) ((ver) << 8 | (rel)) @@ -431,7 +431,7 @@ static inline struct intel_gt *to_gt(struct drm_i915_private *i915) #define IS_DISPLAY_VER(i915, from, until) \ (DISPLAY_VER(i915) >= (from) && DISPLAY_VER(i915) <= (until)) -#define INTEL_REVID(dev_priv) (to_pci_dev((dev_priv)->drm.dev)->revision) +#define INTEL_REVID(i915) (to_pci_dev((i915)->drm.dev)->revision) #define INTEL_DISPLAY_STEP(__i915) (RUNTIME_INFO(__i915)->step.display_step) #define INTEL_GRAPHICS_STEP(__i915) (RUNTIME_INFO(__i915)->step.graphics_step) @@ -516,135 +516,135 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, return ((mask << (msb - pb)) & (mask << (msb - s))) & BIT(msb); } -#define IS_MOBILE(dev_priv) (INTEL_INFO(dev_priv)->is_mobile) -#define IS_DGFX(dev_priv) (INTEL_INFO(dev_priv)->is_dgfx) - -#define IS_I830(dev_priv) IS_PLATFORM(dev_priv, INTEL_I830) -#define IS_I845G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I845G) -#define IS_I85X(dev_priv) IS_PLATFORM(dev_priv, INTEL_I85X) -#define IS_I865G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I865G) -#define IS_I915G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915G) -#define IS_I915GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915GM) -#define IS_I945G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945G) -#define IS_I945GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945GM) -#define IS_I965G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965G) -#define IS_I965GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965GM) -#define IS_G45(dev_priv) IS_PLATFORM(dev_priv, INTEL_G45) -#define IS_GM45(dev_priv) IS_PLATFORM(dev_priv, INTEL_GM45) -#define IS_G4X(dev_priv) (IS_G45(dev_priv) || IS_GM45(dev_priv)) -#define IS_PINEVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_PINEVIEW) -#define IS_G33(dev_priv) IS_PLATFORM(dev_priv, INTEL_G33) -#define IS_IRONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IRONLAKE) -#define IS_IRONLAKE_M(dev_priv) \ - (IS_PLATFORM(dev_priv, INTEL_IRONLAKE) && IS_MOBILE(dev_priv)) -#define IS_SANDYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_SANDYBRIDGE) -#define IS_IVYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE) -#define IS_IVB_GT1(dev_priv) (IS_IVYBRIDGE(dev_priv) && \ - INTEL_INFO(dev_priv)->gt == 1) -#define IS_VALLEYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW) -#define IS_CHERRYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW) -#define IS_HASWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_HASWELL) -#define IS_BROADWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROADWELL) -#define IS_SKYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_SKYLAKE) -#define IS_BROXTON(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROXTON) -#define IS_KABYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_KABYLAKE) -#define IS_GEMINILAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_GEMINILAKE) -#define IS_COFFEELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COFFEELAKE) -#define IS_COMETLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COMETLAKE) -#define IS_ICELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ICELAKE) -#define IS_JSL_EHL(dev_priv) (IS_PLATFORM(dev_priv, INTEL_JASPERLAKE) || \ - IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE)) -#define IS_TIGERLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_TIGERLAKE) -#define IS_ROCKETLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ROCKETLAKE) -#define IS_DG1(dev_priv) IS_PLATFORM(dev_priv, INTEL_DG1) -#define IS_ALDERLAKE_S(dev_priv) IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_S) -#define IS_ALDERLAKE_P(dev_priv) IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_P) -#define IS_XEHPSDV(dev_priv) IS_PLATFORM(dev_priv, INTEL_XEHPSDV) -#define IS_DG2(dev_priv) IS_PLATFORM(dev_priv, INTEL_DG2) -#define IS_PONTEVECCHIO(dev_priv) IS_PLATFORM(dev_priv, INTEL_PONTEVECCHIO) -#define IS_METEORLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_METEORLAKE) - -#define IS_METEORLAKE_M(dev_priv) \ - IS_SUBPLATFORM(dev_priv, INTEL_METEORLAKE, INTEL_SUBPLATFORM_M) -#define IS_METEORLAKE_P(dev_priv) \ - IS_SUBPLATFORM(dev_priv, INTEL_METEORLAKE, INTEL_SUBPLATFORM_P) -#define IS_DG2_G10(dev_priv) \ - IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G10) -#define IS_DG2_G11(dev_priv) \ - IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G11) -#define IS_DG2_G12(dev_priv) \ - IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G12) -#define IS_ADLS_RPLS(dev_priv) \ - IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_S, INTEL_SUBPLATFORM_RPL) -#define IS_ADLP_N(dev_priv) \ - IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_N) -#define IS_ADLP_RPLP(dev_priv) \ - IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPL) -#define IS_ADLP_RPLU(dev_priv) \ - IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPLU) -#define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \ - (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00) -#define IS_BDW_ULT(dev_priv) \ - IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULT) -#define IS_BDW_ULX(dev_priv) \ - IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULX) -#define IS_BDW_GT3(dev_priv) (IS_BROADWELL(dev_priv) && \ - INTEL_INFO(dev_priv)->gt == 3) -#define IS_HSW_ULT(dev_priv) \ - IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULT) -#define IS_HSW_GT3(dev_priv) (IS_HASWELL(dev_priv) && \ - INTEL_INFO(dev_priv)->gt == 3) -#define IS_HSW_GT1(dev_priv) (IS_HASWELL(dev_priv) && \ - INTEL_INFO(dev_priv)->gt == 1) +#define IS_MOBILE(i915) (INTEL_INFO(i915)->is_mobile) +#define IS_DGFX(i915) (INTEL_INFO(i915)->is_dgfx) + +#define IS_I830(i915) IS_PLATFORM(i915, INTEL_I830) +#define IS_I845G(i915) IS_PLATFORM(i915, INTEL_I845G) +#define IS_I85X(i915) IS_PLATFORM(i915, INTEL_I85X) +#define IS_I865G(i915) IS_PLATFORM(i915, INTEL_I865G) +#define IS_I915G(i915) IS_PLATFORM(i915, INTEL_I915G) +#define IS_I915GM(i915) IS_PLATFORM(i915, INTEL_I915GM) +#define IS_I945G(i915) IS_PLATFORM(i915, INTEL_I945G) +#define IS_I945GM(i915) IS_PLATFORM(i915, INTEL_I945GM) +#define IS_I965G(i915) IS_PLATFORM(i915, INTEL_I965G) +#define IS_I965GM(i915) IS_PLATFORM(i915, INTEL_I965GM) +#define IS_G45(i915) IS_PLATFORM(i915, INTEL_G45) +#define IS_GM45(i915) IS_PLATFORM(i915, INTEL_GM45) +#define IS_G4X(i915) (IS_G45(i915) || IS_GM45(i915)) +#define IS_PINEVIEW(i915) IS_PLATFORM(i915, INTEL_PINEVIEW) +#define IS_G33(i915) IS_PLATFORM(i915, INTEL_G33) +#define IS_IRONLAKE(i915) IS_PLATFORM(i915, INTEL_IRONLAKE) +#define IS_IRONLAKE_M(i915) \ + (IS_PLATFORM(i915, INTEL_IRONLAKE) && IS_MOBILE(i915)) +#define IS_SANDYBRIDGE(i915) IS_PLATFORM(i915, INTEL_SANDYBRIDGE) +#define IS_IVYBRIDGE(i915) IS_PLATFORM(i915, INTEL_IVYBRIDGE) +#define IS_IVB_GT1(i915) (IS_IVYBRIDGE(i915) && \ + INTEL_INFO(i915)->gt == 1) +#define IS_VALLEYVIEW(i915) IS_PLATFORM(i915, INTEL_VALLEYVIEW) +#define IS_CHERRYVIEW(i915) IS_PLATFORM(i915, INTEL_CHERRYVIEW) +#define IS_HASWELL(i915) IS_PLATFORM(i915, INTEL_HASWELL) +#define IS_BROADWELL(i915) IS_PLATFORM(i915, INTEL_BROADWELL) +#define IS_SKYLAKE(i915) IS_PLATFORM(i915, INTEL_SKYLAKE) +#define IS_BROXTON(i915) IS_PLATFORM(i915, INTEL_BROXTON) +#define IS_KABYLAKE(i915) IS_PLATFORM(i915, INTEL_KABYLAKE) +#define IS_GEMINILAKE(i915) IS_PLATFORM(i915, INTEL_GEMINILAKE) +#define IS_COFFEELAKE(i915) IS_PLATFORM(i915, INTEL_COFFEELAKE) +#define IS_COMETLAKE(i915) IS_PLATFORM(i915, INTEL_COMETLAKE) +#define IS_ICELAKE(i915) IS_PLATFORM(i915, INTEL_ICELAKE) +#define IS_JSL_EHL(i915) (IS_PLATFORM(i915, INTEL_JASPERLAKE) || \ + IS_PLATFORM(i915, INTEL_ELKHARTLAKE)) +#define IS_TIGERLAKE(i915) IS_PLATFORM(i915, INTEL_TIGERLAKE) +#define IS_ROCKETLAKE(i915) IS_PLATFORM(i915, INTEL_ROCKETLAKE) +#define IS_DG1(i915) IS_PLATFORM(i915, INTEL_DG1) +#define IS_ALDERLAKE_S(i915) IS_PLATFORM(i915, INTEL_ALDERLAKE_S) +#define IS_ALDERLAKE_P(i915) IS_PLATFORM(i915, INTEL_ALDERLAKE_P) +#define IS_XEHPSDV(i915) IS_PLATFORM(i915, INTEL_XEHPSDV) +#define IS_DG2(i915) IS_PLATFORM(i915, INTEL_DG2) +#define IS_PONTEVECCHIO(i915) IS_PLATFORM(i915, INTEL_PONTEVECCHIO) +#define IS_METEORLAKE(i915) IS_PLATFORM(i915, INTEL_METEORLAKE) + +#define IS_METEORLAKE_M(i915) \ + IS_SUBPLATFORM(i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_M) +#define IS_METEORLAKE_P(i915) \ + IS_SUBPLATFORM(i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_P) +#define IS_DG2_G10(i915) \ + IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G10) +#define IS_DG2_G11(i915) \ + IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G11) +#define IS_DG2_G12(i915) \ + IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G12) +#define IS_ADLS_RPLS(i915) \ + IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_S, INTEL_SUBPLATFORM_RPL) +#define IS_ADLP_N(i915) \ + IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_N) +#define IS_ADLP_RPLP(i915) \ + IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPL) +#define IS_ADLP_RPLU(i915) \ + IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPLU) +#define IS_HSW_EARLY_SDV(i915) (IS_HASWELL(i915) && \ + (INTEL_DEVID(i915) & 0xFF00) == 0x0C00) +#define IS_BDW_ULT(i915) \ + IS_SUBPLATFORM(i915, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULT) +#define IS_BDW_ULX(i915) \ + IS_SUBPLATFORM(i915, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULX) +#define IS_BDW_GT3(i915) (IS_BROADWELL(i915) && \ + INTEL_INFO(i915)->gt == 3) +#define IS_HSW_ULT(i915) \ + IS_SUBPLATFORM(i915, INTEL_HASWELL, INTEL_SUBPLATFORM_ULT) +#define IS_HSW_GT3(i915) (IS_HASWELL(i915) && \ + INTEL_INFO(i915)->gt == 3) +#define IS_HSW_GT1(i915) (IS_HASWELL(i915) && \ + INTEL_INFO(i915)->gt == 1) /* ULX machines are also considered ULT. */ -#define IS_HSW_ULX(dev_priv) \ - IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULX) -#define IS_SKL_ULT(dev_priv) \ - IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULT) -#define IS_SKL_ULX(dev_priv) \ - IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULX) -#define IS_KBL_ULT(dev_priv) \ - IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT) -#define IS_KBL_ULX(dev_priv) \ - IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX) -#define IS_SKL_GT2(dev_priv) (IS_SKYLAKE(dev_priv) && \ - INTEL_INFO(dev_priv)->gt == 2) -#define IS_SKL_GT3(dev_priv) (IS_SKYLAKE(dev_priv) && \ - INTEL_INFO(dev_priv)->gt == 3) -#define IS_SKL_GT4(dev_priv) (IS_SKYLAKE(dev_priv) && \ - INTEL_INFO(dev_priv)->gt == 4) -#define IS_KBL_GT2(dev_priv) (IS_KABYLAKE(dev_priv) && \ - INTEL_INFO(dev_priv)->gt == 2) -#define IS_KBL_GT3(dev_priv) (IS_KABYLAKE(dev_priv) && \ - INTEL_INFO(dev_priv)->gt == 3) -#define IS_CFL_ULT(dev_priv) \ - IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULT) -#define IS_CFL_ULX(dev_priv) \ - IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULX) -#define IS_CFL_GT2(dev_priv) (IS_COFFEELAKE(dev_priv) && \ - INTEL_INFO(dev_priv)->gt == 2) -#define IS_CFL_GT3(dev_priv) (IS_COFFEELAKE(dev_priv) && \ - INTEL_INFO(dev_priv)->gt == 3) - -#define IS_CML_ULT(dev_priv) \ - IS_SUBPLATFORM(dev_priv, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULT) -#define IS_CML_ULX(dev_priv) \ - IS_SUBPLATFORM(dev_priv, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULX) -#define IS_CML_GT2(dev_priv) (IS_COMETLAKE(dev_priv) && \ - INTEL_INFO(dev_priv)->gt == 2) - -#define IS_ICL_WITH_PORT_F(dev_priv) \ - IS_SUBPLATFORM(dev_priv, INTEL_ICELAKE, INTEL_SUBPLATFORM_PORTF) - -#define IS_TGL_UY(dev_priv) \ - IS_SUBPLATFORM(dev_priv, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_UY) +#define IS_HSW_ULX(i915) \ + IS_SUBPLATFORM(i915, INTEL_HASWELL, INTEL_SUBPLATFORM_ULX) +#define IS_SKL_ULT(i915) \ + IS_SUBPLATFORM(i915, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULT) +#define IS_SKL_ULX(i915) \ + IS_SUBPLATFORM(i915, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULX) +#define IS_KBL_ULT(i915) \ + IS_SUBPLATFORM(i915, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT) +#define IS_KBL_ULX(i915) \ + IS_SUBPLATFORM(i915, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX) +#define IS_SKL_GT2(i915) (IS_SKYLAKE(i915) && \ + INTEL_INFO(i915)->gt == 2) +#define IS_SKL_GT3(i915) (IS_SKYLAKE(i915) && \ + INTEL_INFO(i915)->gt == 3) +#define IS_SKL_GT4(i915) (IS_SKYLAKE(i915) && \ + INTEL_INFO(i915)->gt == 4) +#define IS_KBL_GT2(i915) (IS_KABYLAKE(i915) && \ + INTEL_INFO(i915)->gt == 2) +#define IS_KBL_GT3(i915) (IS_KABYLAKE(i915) && \ + INTEL_INFO(i915)->gt == 3) +#define IS_CFL_ULT(i915) \ + IS_SUBPLATFORM(i915, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULT) +#define IS_CFL_ULX(i915) \ + IS_SUBPLATFORM(i915, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULX) +#define IS_CFL_GT2(i915) (IS_COFFEELAKE(i915) && \ + INTEL_INFO(i915)->gt == 2) +#define IS_CFL_GT3(i915) (IS_COFFEELAKE(i915) && \ + INTEL_INFO(i915)->gt == 3) + +#define IS_CML_ULT(i915) \ + IS_SUBPLATFORM(i915, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULT) +#define IS_CML_ULX(i915) \ + IS_SUBPLATFORM(i915, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULX) +#define IS_CML_GT2(i915) (IS_COMETLAKE(i915) && \ + INTEL_INFO(i915)->gt == 2) + +#define IS_ICL_WITH_PORT_F(i915) \ + IS_SUBPLATFORM(i915, INTEL_ICELAKE, INTEL_SUBPLATFORM_PORTF) + +#define IS_TGL_UY(i915) \ + IS_SUBPLATFORM(i915, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_UY) #define IS_SKL_GRAPHICS_STEP(p, since, until) (IS_SKYLAKE(p) && IS_GRAPHICS_STEP(p, since, until)) -#define IS_KBL_GRAPHICS_STEP(dev_priv, since, until) \ - (IS_KABYLAKE(dev_priv) && IS_GRAPHICS_STEP(dev_priv, since, until)) -#define IS_KBL_DISPLAY_STEP(dev_priv, since, until) \ - (IS_KABYLAKE(dev_priv) && IS_DISPLAY_STEP(dev_priv, since, until)) +#define IS_KBL_GRAPHICS_STEP(i915, since, until) \ + (IS_KABYLAKE(i915) && IS_GRAPHICS_STEP(i915, since, until)) +#define IS_KBL_DISPLAY_STEP(i915, since, until) \ + (IS_KABYLAKE(i915) && IS_DISPLAY_STEP(i915, since, until)) #define IS_JSL_EHL_GRAPHICS_STEP(p, since, until) \ (IS_JSL_EHL(p) && IS_GRAPHICS_STEP(p, since, until)) @@ -720,9 +720,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, (IS_PONTEVECCHIO(__i915) && \ IS_GRAPHICS_STEP(__i915, since, until)) -#define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp) -#define IS_GEN9_LP(dev_priv) (GRAPHICS_VER(dev_priv) == 9 && IS_LP(dev_priv)) -#define IS_GEN9_BC(dev_priv) (GRAPHICS_VER(dev_priv) == 9 && !IS_LP(dev_priv)) +#define IS_LP(i915) (INTEL_INFO(i915)->is_lp) +#define IS_GEN9_LP(i915) (GRAPHICS_VER(i915) == 9 && IS_LP(i915)) +#define IS_GEN9_BC(i915) (GRAPHICS_VER(i915) == 9 && !IS_LP(i915)) #define __HAS_ENGINE(engine_mask, id) ((engine_mask) & BIT(id)) #define HAS_ENGINE(gt, id) __HAS_ENGINE((gt)->info.engine_mask, id) @@ -747,180 +747,180 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, #define CCS_MASK(gt) \ ENGINE_INSTANCES_MASK(gt, CCS0, I915_MAX_CCS) -#define HAS_MEDIA_RATIO_MODE(dev_priv) (INTEL_INFO(dev_priv)->has_media_ratio_mode) +#define HAS_MEDIA_RATIO_MODE(i915) (INTEL_INFO(i915)->has_media_ratio_mode) /* * The Gen7 cmdparser copies the scanned buffer to the ggtt for execution * All later gens can run the final buffer from the ppgtt */ -#define CMDPARSER_USES_GGTT(dev_priv) (GRAPHICS_VER(dev_priv) == 7) +#define CMDPARSER_USES_GGTT(i915) (GRAPHICS_VER(i915) == 7) -#define HAS_LLC(dev_priv) (INTEL_INFO(dev_priv)->has_llc) -#define HAS_4TILE(dev_priv) (INTEL_INFO(dev_priv)->has_4tile) -#define HAS_SNOOP(dev_priv) (INTEL_INFO(dev_priv)->has_snoop) -#define HAS_EDRAM(dev_priv) ((dev_priv)->edram_size_mb) -#define HAS_SECURE_BATCHES(dev_priv) (GRAPHICS_VER(dev_priv) < 6) -#define HAS_WT(dev_priv) HAS_EDRAM(dev_priv) +#define HAS_LLC(i915) (INTEL_INFO(i915)->has_llc) +#define HAS_4TILE(i915) (INTEL_INFO(i915)->has_4tile) +#define HAS_SNOOP(i915) (INTEL_INFO(i915)->has_snoop) +#define HAS_EDRAM(i915) ((i915)->edram_size_mb) +#define HAS_SECURE_BATCHES(i915) (GRAPHICS_VER(i915) < 6) +#define HAS_WT(i915) HAS_EDRAM(i915) -#define HWS_NEEDS_PHYSICAL(dev_priv) (INTEL_INFO(dev_priv)->hws_needs_physical) +#define HWS_NEEDS_PHYSICAL(i915) (INTEL_INFO(i915)->hws_needs_physical) -#define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \ - (INTEL_INFO(dev_priv)->has_logical_ring_contexts) -#define HAS_LOGICAL_RING_ELSQ(dev_priv) \ - (INTEL_INFO(dev_priv)->has_logical_ring_elsq) +#define HAS_LOGICAL_RING_CONTEXTS(i915) \ + (INTEL_INFO(i915)->has_logical_ring_contexts) +#define HAS_LOGICAL_RING_ELSQ(i915) \ + (INTEL_INFO(i915)->has_logical_ring_elsq) -#define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv) +#define HAS_EXECLISTS(i915) HAS_LOGICAL_RING_CONTEXTS(i915) -#define INTEL_PPGTT(dev_priv) (RUNTIME_INFO(dev_priv)->ppgtt_type) -#define HAS_PPGTT(dev_priv) \ - (INTEL_PPGTT(dev_priv) != INTEL_PPGTT_NONE) -#define HAS_FULL_PPGTT(dev_priv) \ - (INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL) +#define INTEL_PPGTT(i915) (RUNTIME_INFO(i915)->ppgtt_type) +#define HAS_PPGTT(i915) \ + (INTEL_PPGTT(i915) != INTEL_PPGTT_NONE) +#define HAS_FULL_PPGTT(i915) \ + (INTEL_PPGTT(i915) >= INTEL_PPGTT_FULL) -#define HAS_PAGE_SIZES(dev_priv, sizes) ({ \ +#define HAS_PAGE_SIZES(i915, sizes) ({ \ GEM_BUG_ON((sizes) == 0); \ - ((sizes) & ~RUNTIME_INFO(dev_priv)->page_sizes) == 0; \ + ((sizes) & ~RUNTIME_INFO(i915)->page_sizes) == 0; \ }) -#define HAS_OVERLAY(dev_priv) (INTEL_INFO(dev_priv)->display.has_overlay) -#define OVERLAY_NEEDS_PHYSICAL(dev_priv) \ - (INTEL_INFO(dev_priv)->display.overlay_needs_physical) +#define HAS_OVERLAY(i915) (INTEL_INFO(i915)->display.has_overlay) +#define OVERLAY_NEEDS_PHYSICAL(i915) \ + (INTEL_INFO(i915)->display.overlay_needs_physical) /* Early gen2 have a totally busted CS tlb and require pinned batches. */ -#define HAS_BROKEN_CS_TLB(dev_priv) (IS_I830(dev_priv) || IS_I845G(dev_priv)) +#define HAS_BROKEN_CS_TLB(i915) (IS_I830(i915) || IS_I845G(i915)) -#define NEEDS_RC6_CTX_CORRUPTION_WA(dev_priv) \ - (IS_BROADWELL(dev_priv) || GRAPHICS_VER(dev_priv) == 9) +#define NEEDS_RC6_CTX_CORRUPTION_WA(i915) \ + (IS_BROADWELL(i915) || GRAPHICS_VER(i915) == 9) /* WaRsDisableCoarsePowerGating:skl,cnl */ -#define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \ - (IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv)) +#define NEEDS_WaRsDisableCoarsePowerGating(i915) \ + (IS_SKL_GT3(i915) || IS_SKL_GT4(i915)) -#define HAS_GMBUS_IRQ(dev_priv) (DISPLAY_VER(dev_priv) >= 4) -#define HAS_GMBUS_BURST_READ(dev_priv) (DISPLAY_VER(dev_priv) >= 11 || \ - IS_GEMINILAKE(dev_priv) || \ - IS_KABYLAKE(dev_priv)) +#define HAS_GMBUS_IRQ(i915) (DISPLAY_VER(i915) >= 4) +#define HAS_GMBUS_BURST_READ(i915) (DISPLAY_VER(i915) >= 11 || \ + IS_GEMINILAKE(i915) || \ + IS_KABYLAKE(i915)) /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte * rows, which changed the alignment requirements and fence programming. */ -#define HAS_128_BYTE_Y_TILING(dev_priv) (GRAPHICS_VER(dev_priv) != 2 && \ - !(IS_I915G(dev_priv) || IS_I915GM(dev_priv))) -#define SUPPORTS_TV(dev_priv) (INTEL_INFO(dev_priv)->display.supports_tv) -#define I915_HAS_HOTPLUG(dev_priv) (INTEL_INFO(dev_priv)->display.has_hotplug) +#define HAS_128_BYTE_Y_TILING(i915) (GRAPHICS_VER(i915) != 2 && \ + !(IS_I915G(i915) || IS_I915GM(i915))) +#define SUPPORTS_TV(i915) (INTEL_INFO(i915)->display.supports_tv) +#define I915_HAS_HOTPLUG(i915) (INTEL_INFO(i915)->display.has_hotplug) -#define HAS_FW_BLC(dev_priv) (DISPLAY_VER(dev_priv) > 2) -#define HAS_FBC(dev_priv) (RUNTIME_INFO(dev_priv)->fbc_mask != 0) -#define HAS_CUR_FBC(dev_priv) (!HAS_GMCH(dev_priv) && DISPLAY_VER(dev_priv) >= 7) +#define HAS_FW_BLC(i915) (DISPLAY_VER(i915) > 2) +#define HAS_FBC(i915) (RUNTIME_INFO(i915)->fbc_mask != 0) +#define HAS_CUR_FBC(i915) (!HAS_GMCH(i915) && DISPLAY_VER(i915) >= 7) -#define HAS_DPT(dev_priv) (DISPLAY_VER(dev_priv) >= 13) +#define HAS_DPT(i915) (DISPLAY_VER(i915) >= 13) -#define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv)) +#define HAS_IPS(i915) (IS_HSW_ULT(i915) || IS_BROADWELL(i915)) -#define HAS_DP_MST(dev_priv) (INTEL_INFO(dev_priv)->display.has_dp_mst) -#define HAS_DP20(dev_priv) (IS_DG2(dev_priv) || DISPLAY_VER(dev_priv) >= 14) +#define HAS_DP_MST(i915) (INTEL_INFO(i915)->display.has_dp_mst) +#define HAS_DP20(i915) (IS_DG2(i915) || DISPLAY_VER(i915) >= 14) -#define HAS_DOUBLE_BUFFERED_M_N(dev_priv) (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) +#define HAS_DOUBLE_BUFFERED_M_N(i915) (DISPLAY_VER(i915) >= 9 || IS_BROADWELL(i915)) -#define HAS_CDCLK_CRAWL(dev_priv) (INTEL_INFO(dev_priv)->display.has_cdclk_crawl) -#define HAS_CDCLK_SQUASH(dev_priv) (INTEL_INFO(dev_priv)->display.has_cdclk_squash) -#define HAS_DDI(dev_priv) (INTEL_INFO(dev_priv)->display.has_ddi) -#define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->display.has_fpga_dbg) -#define HAS_PSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_psr) -#define HAS_PSR_HW_TRACKING(dev_priv) \ - (INTEL_INFO(dev_priv)->display.has_psr_hw_tracking) -#define HAS_PSR2_SEL_FETCH(dev_priv) (DISPLAY_VER(dev_priv) >= 12) -#define HAS_TRANSCODER(dev_priv, trans) ((RUNTIME_INFO(dev_priv)->cpu_transcoder_mask & BIT(trans)) != 0) +#define HAS_CDCLK_CRAWL(i915) (INTEL_INFO(i915)->display.has_cdclk_crawl) +#define HAS_CDCLK_SQUASH(i915) (INTEL_INFO(i915)->display.has_cdclk_squash) +#define HAS_DDI(i915) (INTEL_INFO(i915)->display.has_ddi) +#define HAS_FPGA_DBG_UNCLAIMED(i915) (INTEL_INFO(i915)->display.has_fpga_dbg) +#define HAS_PSR(i915) (INTEL_INFO(i915)->display.has_psr) +#define HAS_PSR_HW_TRACKING(i915) \ + (INTEL_INFO(i915)->display.has_psr_hw_tracking) +#define HAS_PSR2_SEL_FETCH(i915) (DISPLAY_VER(i915) >= 12) +#define HAS_TRANSCODER(i915, trans) ((RUNTIME_INFO(i915)->cpu_transcoder_mask & BIT(trans)) != 0) -#define HAS_RC6(dev_priv) (INTEL_INFO(dev_priv)->has_rc6) -#define HAS_RC6p(dev_priv) (INTEL_INFO(dev_priv)->has_rc6p) -#define HAS_RC6pp(dev_priv) (false) /* HW was never validated */ +#define HAS_RC6(i915) (INTEL_INFO(i915)->has_rc6) +#define HAS_RC6p(i915) (INTEL_INFO(i915)->has_rc6p) +#define HAS_RC6pp(i915) (false) /* HW was never validated */ -#define HAS_RPS(dev_priv) (INTEL_INFO(dev_priv)->has_rps) +#define HAS_RPS(i915) (INTEL_INFO(i915)->has_rps) -#define HAS_DMC(dev_priv) (RUNTIME_INFO(dev_priv)->has_dmc) -#define HAS_DSB(dev_priv) (INTEL_INFO(dev_priv)->display.has_dsb) +#define HAS_DMC(i915) (RUNTIME_INFO(i915)->has_dmc) +#define HAS_DSB(i915) (INTEL_INFO(i915)->display.has_dsb) #define HAS_DSC(__i915) (RUNTIME_INFO(__i915)->has_dsc) #define HAS_HW_SAGV_WM(i915) (DISPLAY_VER(i915) >= 13 && !IS_DGFX(i915)) -#define HAS_HECI_PXP(dev_priv) \ - (INTEL_INFO(dev_priv)->has_heci_pxp) +#define HAS_HECI_PXP(i915) \ + (INTEL_INFO(i915)->has_heci_pxp) -#define HAS_HECI_GSCFI(dev_priv) \ - (INTEL_INFO(dev_priv)->has_heci_gscfi) +#define HAS_HECI_GSCFI(i915) \ + (INTEL_INFO(i915)->has_heci_gscfi) -#define HAS_HECI_GSC(dev_priv) (HAS_HECI_PXP(dev_priv) || HAS_HECI_GSCFI(dev_priv)) +#define HAS_HECI_GSC(i915) (HAS_HECI_PXP(i915) || HAS_HECI_GSCFI(i915)) #define HAS_MSO(i915) (DISPLAY_VER(i915) >= 12) -#define HAS_RUNTIME_PM(dev_priv) (INTEL_INFO(dev_priv)->has_runtime_pm) -#define HAS_64BIT_RELOC(dev_priv) (INTEL_INFO(dev_priv)->has_64bit_reloc) +#define HAS_RUNTIME_PM(i915) (INTEL_INFO(i915)->has_runtime_pm) +#define HAS_64BIT_RELOC(i915) (INTEL_INFO(i915)->has_64bit_reloc) -#define HAS_OA_BPC_REPORTING(dev_priv) \ - (INTEL_INFO(dev_priv)->has_oa_bpc_reporting) -#define HAS_OA_SLICE_CONTRIB_LIMITS(dev_priv) \ - (INTEL_INFO(dev_priv)->has_oa_slice_contrib_limits) -#define HAS_OAM(dev_priv) \ - (INTEL_INFO(dev_priv)->has_oam) +#define HAS_OA_BPC_REPORTING(i915) \ + (INTEL_INFO(i915)->has_oa_bpc_reporting) +#define HAS_OA_SLICE_CONTRIB_LIMITS(i915) \ + (INTEL_INFO(i915)->has_oa_slice_contrib_limits) +#define HAS_OAM(i915) \ + (INTEL_INFO(i915)->has_oam) /* * Set this flag, when platform requires 64K GTT page sizes or larger for * device local memory access. */ -#define HAS_64K_PAGES(dev_priv) (INTEL_INFO(dev_priv)->has_64k_pages) +#define HAS_64K_PAGES(i915) (INTEL_INFO(i915)->has_64k_pages) -#define HAS_IPC(dev_priv) (INTEL_INFO(dev_priv)->display.has_ipc) -#define HAS_SAGV(dev_priv) (DISPLAY_VER(dev_priv) >= 9 && !IS_LP(dev_priv)) +#define HAS_IPC(i915) (INTEL_INFO(i915)->display.has_ipc) +#define HAS_SAGV(i915) (DISPLAY_VER(i915) >= 9 && !IS_LP(i915)) #define HAS_REGION(i915, i) (RUNTIME_INFO(i915)->memory_regions & (i)) #define HAS_LMEM(i915) HAS_REGION(i915, REGION_LMEM) -#define HAS_EXTRA_GT_LIST(dev_priv) (INTEL_INFO(dev_priv)->extra_gt_list) +#define HAS_EXTRA_GT_LIST(i915) (INTEL_INFO(i915)->extra_gt_list) /* * Platform has the dedicated compression control state for each lmem surfaces * stored in lmem to support the 3D and media compression formats. */ -#define HAS_FLAT_CCS(dev_priv) (INTEL_INFO(dev_priv)->has_flat_ccs) +#define HAS_FLAT_CCS(i915) (INTEL_INFO(i915)->has_flat_ccs) -#define HAS_GT_UC(dev_priv) (INTEL_INFO(dev_priv)->has_gt_uc) +#define HAS_GT_UC(i915) (INTEL_INFO(i915)->has_gt_uc) -#define HAS_POOLED_EU(dev_priv) (RUNTIME_INFO(dev_priv)->has_pooled_eu) +#define HAS_POOLED_EU(i915) (RUNTIME_INFO(i915)->has_pooled_eu) -#define HAS_GLOBAL_MOCS_REGISTERS(dev_priv) (INTEL_INFO(dev_priv)->has_global_mocs) +#define HAS_GLOBAL_MOCS_REGISTERS(i915) (INTEL_INFO(i915)->has_global_mocs) -#define HAS_GMCH(dev_priv) (INTEL_INFO(dev_priv)->display.has_gmch) +#define HAS_GMCH(i915) (INTEL_INFO(i915)->display.has_gmch) #define HAS_GMD_ID(i915) (INTEL_INFO(i915)->has_gmd_id) -#define HAS_LSPCON(dev_priv) (IS_DISPLAY_VER(dev_priv, 9, 10)) +#define HAS_LSPCON(i915) (IS_DISPLAY_VER(i915, 9, 10)) #define HAS_L3_CCS_READ(i915) (INTEL_INFO(i915)->has_l3_ccs_read) /* DPF == dynamic parity feature */ -#define HAS_L3_DPF(dev_priv) (INTEL_INFO(dev_priv)->has_l3_dpf) -#define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \ - 2 : HAS_L3_DPF(dev_priv)) +#define HAS_L3_DPF(i915) (INTEL_INFO(i915)->has_l3_dpf) +#define NUM_L3_SLICES(i915) (IS_HSW_GT3(i915) ? \ + 2 : HAS_L3_DPF(i915)) -#define INTEL_NUM_PIPES(dev_priv) (hweight8(RUNTIME_INFO(dev_priv)->pipe_mask)) +#define INTEL_NUM_PIPES(i915) (hweight8(RUNTIME_INFO(i915)->pipe_mask)) -#define HAS_DISPLAY(dev_priv) (RUNTIME_INFO(dev_priv)->pipe_mask != 0) +#define HAS_DISPLAY(i915) (RUNTIME_INFO(i915)->pipe_mask != 0) #define HAS_VRR(i915) (DISPLAY_VER(i915) >= 11) #define HAS_ASYNC_FLIPS(i915) (DISPLAY_VER(i915) >= 5) /* Only valid when HAS_DISPLAY() is true */ -#define INTEL_DISPLAY_ENABLED(dev_priv) \ - (drm_WARN_ON(&(dev_priv)->drm, !HAS_DISPLAY(dev_priv)), \ - !(dev_priv)->params.disable_display && \ - !intel_opregion_headless_sku(dev_priv)) +#define INTEL_DISPLAY_ENABLED(i915) \ + (drm_WARN_ON(&(i915)->drm, !HAS_DISPLAY(i915)), \ + !(i915)->params.disable_display && \ + !intel_opregion_headless_sku(i915)) -#define HAS_GUC_DEPRIVILEGE(dev_priv) \ - (INTEL_INFO(dev_priv)->has_guc_deprivilege) +#define HAS_GUC_DEPRIVILEGE(i915) \ + (INTEL_INFO(i915)->has_guc_deprivilege) -#define HAS_D12_PLANE_MINIMIZATION(dev_priv) (IS_ROCKETLAKE(dev_priv) || \ - IS_ALDERLAKE_S(dev_priv)) +#define HAS_D12_PLANE_MINIMIZATION(i915) (IS_ROCKETLAKE(i915) || \ + IS_ALDERLAKE_S(i915)) #define HAS_MBUS_JOINING(i915) (IS_ALDERLAKE_P(i915) || DISPLAY_VER(i915) >= 14) -- 2.40.0 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Use i915 instead of dev_priv (rev2) 2023-04-21 19:00 [Intel-gfx] [PATCH v2 0/2] Use i915 instead of dev_priv Andi Shyti 2023-04-21 19:00 ` [Intel-gfx] [PATCH v2 1/2] drm/i915/i915_drv: Use proper parameter naming in for_each_engine() Andi Shyti 2023-04-21 19:00 ` [Intel-gfx] [PATCH v2 2/2] drm/i915/i915_drv: Use i915 instead of dev_priv insied the file_priv structure Andi Shyti @ 2023-04-21 22:29 ` Patchwork 2023-04-21 22:29 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork ` (2 subsequent siblings) 5 siblings, 0 replies; 7+ messages in thread From: Patchwork @ 2023-04-21 22:29 UTC (permalink / raw) To: Andi Shyti; +Cc: intel-gfx == Series Details == Series: Use i915 instead of dev_priv (rev2) URL : https://patchwork.freedesktop.org/series/116816/ State : warning == Summary == Error: dim checkpatch failed a9e68a5b12c6 drm/i915/i915_drv: Use proper parameter naming in for_each_engine() -:24: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses #24: FILE: drivers/gpu/drm/i915/i915_drv.h:384: +#define for_each_engine(engine__, gt__, id__) \ for ((id__) = 0; \ (id__) < I915_NUM_ENGINES; \ (id__)++) \ + for_each_if ((engine__) = (gt__)->engine[(id__)]) -:24: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'id__' - possible side-effects? #24: FILE: drivers/gpu/drm/i915/i915_drv.h:384: +#define for_each_engine(engine__, gt__, id__) \ for ((id__) = 0; \ (id__) < I915_NUM_ENGINES; \ (id__)++) \ + for_each_if ((engine__) = (gt__)->engine[(id__)]) -:29: WARNING:SPACING: space prohibited between function name and open parenthesis '(' #29: FILE: drivers/gpu/drm/i915/i915_drv.h:388: + for_each_if ((engine__) = (gt__)->engine[(id__)]) total: 1 errors, 1 warnings, 1 checks, 13 lines checked efd966c35aaa drm/i915/i915_drv: Use i915 instead of dev_priv insied the file_priv structure -:141: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible side-effects? #141: FILE: drivers/gpu/drm/i915/i915_drv.h:534: +#define IS_G4X(i915) (IS_G45(i915) || IS_GM45(i915)) -:145: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible side-effects? #145: FILE: drivers/gpu/drm/i915/i915_drv.h:538: +#define IS_IRONLAKE_M(i915) \ + (IS_PLATFORM(i915, INTEL_IRONLAKE) && IS_MOBILE(i915)) -:149: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible side-effects? #149: FILE: drivers/gpu/drm/i915/i915_drv.h:542: +#define IS_IVB_GT1(i915) (IS_IVYBRIDGE(i915) && \ + INTEL_INFO(i915)->gt == 1) -:162: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible side-effects? #162: FILE: drivers/gpu/drm/i915/i915_drv.h:555: +#define IS_JSL_EHL(i915) (IS_PLATFORM(i915, INTEL_JASPERLAKE) || \ + IS_PLATFORM(i915, INTEL_ELKHARTLAKE)) -:192: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible side-effects? #192: FILE: drivers/gpu/drm/i915/i915_drv.h:585: +#define IS_HSW_EARLY_SDV(i915) (IS_HASWELL(i915) && \ + (INTEL_DEVID(i915) & 0xFF00) == 0x0C00) -:198: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible side-effects? #198: FILE: drivers/gpu/drm/i915/i915_drv.h:591: +#define IS_BDW_GT3(i915) (IS_BROADWELL(i915) && \ + INTEL_INFO(i915)->gt == 3) -:202: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible side-effects? #202: FILE: drivers/gpu/drm/i915/i915_drv.h:595: +#define IS_HSW_GT3(i915) (IS_HASWELL(i915) && \ + INTEL_INFO(i915)->gt == 3) -:204: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible side-effects? #204: FILE: drivers/gpu/drm/i915/i915_drv.h:597: +#define IS_HSW_GT1(i915) (IS_HASWELL(i915) && \ + INTEL_INFO(i915)->gt == 1) -:258: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible side-effects? #258: FILE: drivers/gpu/drm/i915/i915_drv.h:610: +#define IS_SKL_GT2(i915) (IS_SKYLAKE(i915) && \ + INTEL_INFO(i915)->gt == 2) -:260: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible side-effects? #260: FILE: drivers/gpu/drm/i915/i915_drv.h:612: +#define IS_SKL_GT3(i915) (IS_SKYLAKE(i915) && \ + INTEL_INFO(i915)->gt == 3) -:262: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible side-effects? #262: FILE: drivers/gpu/drm/i915/i915_drv.h:614: +#define IS_SKL_GT4(i915) (IS_SKYLAKE(i915) && \ + INTEL_INFO(i915)->gt == 4) -:264: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible side-effects? #264: FILE: drivers/gpu/drm/i915/i915_drv.h:616: +#define IS_KBL_GT2(i915) (IS_KABYLAKE(i915) && \ + INTEL_INFO(i915)->gt == 2) -:266: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible side-effects? #266: FILE: drivers/gpu/drm/i915/i915_drv.h:618: +#define IS_KBL_GT3(i915) (IS_KABYLAKE(i915) && \ + INTEL_INFO(i915)->gt == 3) -:272: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible side-effects? #272: FILE: drivers/gpu/drm/i915/i915_drv.h:624: +#define IS_CFL_GT2(i915) (IS_COFFEELAKE(i915) && \ + INTEL_INFO(i915)->gt == 2) -:274: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible side-effects? #274: FILE: drivers/gpu/drm/i915/i915_drv.h:626: +#define IS_CFL_GT3(i915) (IS_COFFEELAKE(i915) && \ + INTEL_INFO(i915)->gt == 3) -:281: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible side-effects? #281: FILE: drivers/gpu/drm/i915/i915_drv.h:633: +#define IS_CML_GT2(i915) (IS_COMETLAKE(i915) && \ + INTEL_INFO(i915)->gt == 2) -:296: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible side-effects? #296: FILE: drivers/gpu/drm/i915/i915_drv.h:644: +#define IS_KBL_GRAPHICS_STEP(i915, since, until) \ + (IS_KABYLAKE(i915) && IS_GRAPHICS_STEP(i915, since, until)) -:298: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible side-effects? #298: FILE: drivers/gpu/drm/i915/i915_drv.h:646: +#define IS_KBL_DISPLAY_STEP(i915, since, until) \ + (IS_KABYLAKE(i915) && IS_DISPLAY_STEP(i915, since, until)) -:311: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible side-effects? #311: FILE: drivers/gpu/drm/i915/i915_drv.h:724: +#define IS_GEN9_LP(i915) (GRAPHICS_VER(i915) == 9 && IS_LP(i915)) -:312: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible side-effects? #312: FILE: drivers/gpu/drm/i915/i915_drv.h:725: +#define IS_GEN9_BC(i915) (GRAPHICS_VER(i915) == 9 && !IS_LP(i915)) -:370: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'sizes' - possible side-effects? #370: FILE: drivers/gpu/drm/i915/i915_drv.h:780: +#define HAS_PAGE_SIZES(i915, sizes) ({ \ GEM_BUG_ON((sizes) == 0); \ + ((sizes) & ~RUNTIME_INFO(i915)->page_sizes) == 0; \ }) -:385: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible side-effects? #385: FILE: drivers/gpu/drm/i915/i915_drv.h:790: +#define HAS_BROKEN_CS_TLB(i915) (IS_I830(i915) || IS_I845G(i915)) -:389: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible side-effects? #389: FILE: drivers/gpu/drm/i915/i915_drv.h:792: +#define NEEDS_RC6_CTX_CORRUPTION_WA(i915) \ + (IS_BROADWELL(i915) || GRAPHICS_VER(i915) == 9) -:395: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible side-effects? #395: FILE: drivers/gpu/drm/i915/i915_drv.h:796: +#define NEEDS_WaRsDisableCoarsePowerGating(i915) \ + (IS_SKL_GT3(i915) || IS_SKL_GT4(i915)) -:403: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible side-effects? #403: FILE: drivers/gpu/drm/i915/i915_drv.h:800: +#define HAS_GMBUS_BURST_READ(i915) (DISPLAY_VER(i915) >= 11 || \ + IS_GEMINILAKE(i915) || \ + IS_KABYLAKE(i915)) -:414: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible side-effects? #414: FILE: drivers/gpu/drm/i915/i915_drv.h:807: +#define HAS_128_BYTE_Y_TILING(i915) (GRAPHICS_VER(i915) != 2 && \ + !(IS_I915G(i915) || IS_I915GM(i915))) -:424: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible side-effects? #424: FILE: drivers/gpu/drm/i915/i915_drv.h:814: +#define HAS_CUR_FBC(i915) (!HAS_GMCH(i915) && DISPLAY_VER(i915) >= 7) -:430: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible side-effects? #430: FILE: drivers/gpu/drm/i915/i915_drv.h:818: +#define HAS_IPS(i915) (IS_HSW_ULT(i915) || IS_BROADWELL(i915)) -:435: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible side-effects? #435: FILE: drivers/gpu/drm/i915/i915_drv.h:821: +#define HAS_DP20(i915) (IS_DG2(i915) || DISPLAY_VER(i915) >= 14) -:438: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible side-effects? #438: FILE: drivers/gpu/drm/i915/i915_drv.h:823: +#define HAS_DOUBLE_BUFFERED_M_N(i915) (DISPLAY_VER(i915) >= 9 || IS_BROADWELL(i915)) -:457: WARNING:LONG_LINE: line length of 102 exceeds 100 columns #457: FILE: drivers/gpu/drm/i915/i915_drv.h:833: +#define HAS_TRANSCODER(i915, trans) ((RUNTIME_INFO(i915)->cpu_transcoder_mask & BIT(trans)) != 0) -:487: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible side-effects? #487: FILE: drivers/gpu/drm/i915/i915_drv.h:852: +#define HAS_HECI_GSC(i915) (HAS_HECI_PXP(i915) || HAS_HECI_GSCFI(i915)) -:519: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible side-effects? #519: FILE: drivers/gpu/drm/i915/i915_drv.h:873: +#define HAS_SAGV(i915) (DISPLAY_VER(i915) >= 9 && !IS_LP(i915)) -:558: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible side-effects? #558: FILE: drivers/gpu/drm/i915/i915_drv.h:902: +#define NUM_L3_SLICES(i915) (IS_HSW_GT3(i915) ? \ + 2 : HAS_L3_DPF(i915)) -:576: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible side-effects? #576: FILE: drivers/gpu/drm/i915/i915_drv.h:914: +#define INTEL_DISPLAY_ENABLED(i915) \ + (drm_WARN_ON(&(i915)->drm, !HAS_DISPLAY(i915)), \ + !(i915)->params.disable_display && \ + !intel_opregion_headless_sku(i915)) -:588: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible side-effects? #588: FILE: drivers/gpu/drm/i915/i915_drv.h:922: +#define HAS_D12_PLANE_MINIMIZATION(i915) (IS_ROCKETLAKE(i915) || \ + IS_ALDERLAKE_S(i915)) total: 0 errors, 1 warnings, 35 checks, 571 lines checked ^ permalink raw reply [flat|nested] 7+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Use i915 instead of dev_priv (rev2) 2023-04-21 19:00 [Intel-gfx] [PATCH v2 0/2] Use i915 instead of dev_priv Andi Shyti ` (2 preceding siblings ...) 2023-04-21 22:29 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Use i915 instead of dev_priv (rev2) Patchwork @ 2023-04-21 22:29 ` Patchwork 2023-04-21 22:41 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2023-04-22 9:43 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork 5 siblings, 0 replies; 7+ messages in thread From: Patchwork @ 2023-04-21 22:29 UTC (permalink / raw) To: Andi Shyti; +Cc: intel-gfx == Series Details == Series: Use i915 instead of dev_priv (rev2) URL : https://patchwork.freedesktop.org/series/116816/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. ^ permalink raw reply [flat|nested] 7+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for Use i915 instead of dev_priv (rev2) 2023-04-21 19:00 [Intel-gfx] [PATCH v2 0/2] Use i915 instead of dev_priv Andi Shyti ` (3 preceding siblings ...) 2023-04-21 22:29 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork @ 2023-04-21 22:41 ` Patchwork 2023-04-22 9:43 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork 5 siblings, 0 replies; 7+ messages in thread From: Patchwork @ 2023-04-21 22:41 UTC (permalink / raw) To: Andi Shyti; +Cc: intel-gfx [-- Attachment #1: Type: text/plain, Size: 4399 bytes --] == Series Details == Series: Use i915 instead of dev_priv (rev2) URL : https://patchwork.freedesktop.org/series/116816/ State : success == Summary == CI Bug Log - changes from CI_DRM_13043 -> Patchwork_116816v2 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116816v2/index.html Participating hosts (36 -> 36) ------------------------------ Additional (1): bat-mtlp-8 Missing (1): fi-snb-2520m Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_116816v2: ### IGT changes ### #### Suppressed #### The following results come from untrusted machines, tests, or statuses. They do not affect the overall result. * igt@i915_selftest@live@gem: - {bat-mtlp-8}: NOTRUN -> [DMESG-FAIL][1] +2 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116816v2/bat-mtlp-8/igt@i915_selftest@live@gem.html Known issues ------------ Here are the changes found in Patchwork_116816v2 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@kms_pipe_crc_basic@suspend-read-crc@pipe-a-hdmi-a-1: - fi-rkl-11600: [PASS][2] -> [FAIL][3] ([fdo#103375]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13043/fi-rkl-11600/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-a-hdmi-a-1.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116816v2/fi-rkl-11600/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-a-hdmi-a-1.html #### Possible fixes #### * igt@i915_selftest@live@slpc: - bat-rpls-1: [DMESG-FAIL][4] ([i915#6367] / [i915#7996]) -> [PASS][5] [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13043/bat-rpls-1/igt@i915_selftest@live@slpc.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116816v2/bat-rpls-1/igt@i915_selftest@live@slpc.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375 [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285 [i915#3595]: https://gitlab.freedesktop.org/drm/intel/issues/3595 [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708 [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077 [i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079 [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083 [i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212 [i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213 [i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579 [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613 [i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190 [i915#5274]: https://gitlab.freedesktop.org/drm/intel/issues/5274 [i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367 [i915#6645]: https://gitlab.freedesktop.org/drm/intel/issues/6645 [i915#7456]: https://gitlab.freedesktop.org/drm/intel/issues/7456 [i915#7699]: https://gitlab.freedesktop.org/drm/intel/issues/7699 [i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828 [i915#7996]: https://gitlab.freedesktop.org/drm/intel/issues/7996 [i915#8346]: https://gitlab.freedesktop.org/drm/intel/issues/8346 [i915#8368]: https://gitlab.freedesktop.org/drm/intel/issues/8368 [i915#8369]: https://gitlab.freedesktop.org/drm/intel/issues/8369 [i915#8379]: https://gitlab.freedesktop.org/drm/intel/issues/8379 Build changes ------------- * Linux: CI_DRM_13043 -> Patchwork_116816v2 CI-20190529: 20190529 CI_DRM_13043: 2fa9c266135355c9993507d7c27cc6722956bfec @ git://anongit.freedesktop.org/gfx-ci/linux IGT_7264: 2f0a07378e58e5c7d7b589b39ace7e3a2317f6b2 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_116816v2: 2fa9c266135355c9993507d7c27cc6722956bfec @ git://anongit.freedesktop.org/gfx-ci/linux ### Linux commits 2a9c436a72a6 drm/i915/i915_drv: Use i915 instead of dev_priv insied the file_priv structure 4b2e8a9001db drm/i915/i915_drv: Use proper parameter naming in for_each_engine() == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116816v2/index.html [-- Attachment #2: Type: text/html, Size: 3708 bytes --] ^ permalink raw reply [flat|nested] 7+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for Use i915 instead of dev_priv (rev2) 2023-04-21 19:00 [Intel-gfx] [PATCH v2 0/2] Use i915 instead of dev_priv Andi Shyti ` (4 preceding siblings ...) 2023-04-21 22:41 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork @ 2023-04-22 9:43 ` Patchwork 5 siblings, 0 replies; 7+ messages in thread From: Patchwork @ 2023-04-22 9:43 UTC (permalink / raw) To: Andi Shyti; +Cc: intel-gfx [-- Attachment #1: Type: text/plain, Size: 13538 bytes --] == Series Details == Series: Use i915 instead of dev_priv (rev2) URL : https://patchwork.freedesktop.org/series/116816/ State : success == Summary == CI Bug Log - changes from CI_DRM_13043_full -> Patchwork_116816v2_full ==================================================== Summary ------- **SUCCESS** No regressions found. Participating hosts (7 -> 7) ------------------------------ No changes in participating hosts Known issues ------------ Here are the changes found in Patchwork_116816v2_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt@gem_exec_fair@basic-pace-solo@rcs0: - shard-apl: [PASS][1] -> [FAIL][2] ([i915#2842]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13043/shard-apl4/igt@gem_exec_fair@basic-pace-solo@rcs0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116816v2/shard-apl3/igt@gem_exec_fair@basic-pace-solo@rcs0.html * igt@i915_pm_rps@reset: - shard-snb: [PASS][3] -> [INCOMPLETE][4] ([i915#7790]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13043/shard-snb4/igt@i915_pm_rps@reset.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116816v2/shard-snb2/igt@i915_pm_rps@reset.html * igt@kms_async_flips@alternate-sync-async-flip@pipe-b-dp-1: - shard-apl: [PASS][5] -> [FAIL][6] ([i915#2521]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13043/shard-apl6/igt@kms_async_flips@alternate-sync-async-flip@pipe-b-dp-1.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116816v2/shard-apl7/igt@kms_async_flips@alternate-sync-async-flip@pipe-b-dp-1.html * igt@kms_color@ctm-green-to-red@pipe-a-hdmi-a-1: - shard-snb: NOTRUN -> [SKIP][7] ([fdo#109271]) +26 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116816v2/shard-snb1/igt@kms_color@ctm-green-to-red@pipe-a-hdmi-a-1.html * igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-render: - shard-apl: NOTRUN -> [SKIP][8] ([fdo#109271]) +3 similar issues [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116816v2/shard-apl2/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-render.html #### Possible fixes #### * igt@gem_exec_endless@dispatch@vecs0: - {shard-tglu}: [TIMEOUT][9] ([i915#3778]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13043/shard-tglu-10/igt@gem_exec_endless@dispatch@vecs0.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116816v2/shard-tglu-5/igt@gem_exec_endless@dispatch@vecs0.html * igt@gem_exec_fair@basic-pace-share@rcs0: - {shard-tglu}: [FAIL][11] ([i915#2842]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13043/shard-tglu-4/igt@gem_exec_fair@basic-pace-share@rcs0.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116816v2/shard-tglu-9/igt@gem_exec_fair@basic-pace-share@rcs0.html * igt@gem_exec_fair@basic-pace@vcs0: - shard-glk: [FAIL][13] ([i915#2842]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13043/shard-glk8/igt@gem_exec_fair@basic-pace@vcs0.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116816v2/shard-glk2/igt@gem_exec_fair@basic-pace@vcs0.html * igt@gem_exec_schedule@smoketest@rcs0: - shard-glk: [DMESG-WARN][15] ([i915#118]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13043/shard-glk4/igt@gem_exec_schedule@smoketest@rcs0.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116816v2/shard-glk8/igt@gem_exec_schedule@smoketest@rcs0.html * igt@gen9_exec_parse@allowed-all: - shard-apl: [ABORT][17] ([i915#5566]) -> [PASS][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13043/shard-apl7/igt@gen9_exec_parse@allowed-all.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116816v2/shard-apl2/igt@gen9_exec_parse@allowed-all.html * igt@i915_pm_rc6_residency@rc6-idle@vcs0: - {shard-dg1}: [FAIL][19] ([i915#3591]) -> [PASS][20] +1 similar issue [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13043/shard-dg1-18/igt@i915_pm_rc6_residency@rc6-idle@vcs0.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116816v2/shard-dg1-16/igt@i915_pm_rc6_residency@rc6-idle@vcs0.html * igt@i915_pm_rpm@dpms-non-lpsp: - {shard-rkl}: [SKIP][21] ([i915#1397]) -> [PASS][22] +2 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13043/shard-rkl-7/igt@i915_pm_rpm@dpms-non-lpsp.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116816v2/shard-rkl-3/igt@i915_pm_rpm@dpms-non-lpsp.html * igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic: - shard-glk: [FAIL][23] ([i915#72]) -> [PASS][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13043/shard-glk4/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116816v2/shard-glk8/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions: - shard-apl: [FAIL][25] ([i915#2346]) -> [PASS][26] [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13043/shard-apl1/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116816v2/shard-apl7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html * igt@kms_cursor_legacy@single-move@pipe-b: - {shard-rkl}: [INCOMPLETE][27] ([i915#8011]) -> [PASS][28] +1 similar issue [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13043/shard-rkl-7/igt@kms_cursor_legacy@single-move@pipe-b.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116816v2/shard-rkl-3/igt@kms_cursor_legacy@single-move@pipe-b.html * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-mmap-cpu: - shard-snb: [SKIP][29] ([fdo#109271]) -> [PASS][30] [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13043/shard-snb2/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-mmap-cpu.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116816v2/shard-snb1/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-mmap-cpu.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274 [fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280 [fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283 [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285 [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289 [fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291 [fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295 [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315 [fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506 [fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189 [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068 [fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614 [fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615 [fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [fdo#112054]: https://bugs.freedesktop.org/show_bug.cgi?id=112054 [fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283 [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397 [i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839 [i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346 [i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521 [i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527 [i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575 [i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587 [i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658 [i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672 [i915#2681]: https://gitlab.freedesktop.org/drm/intel/issues/2681 [i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842 [i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281 [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282 [i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297 [i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301 [i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359 [i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458 [i915#3469]: https://gitlab.freedesktop.org/drm/intel/issues/3469 [i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539 [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555 [i915#3591]: https://gitlab.freedesktop.org/drm/intel/issues/3591 [i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637 [i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638 [i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689 [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708 [i915#3742]: https://gitlab.freedesktop.org/drm/intel/issues/3742 [i915#3778]: https://gitlab.freedesktop.org/drm/intel/issues/3778 [i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840 [i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886 [i915#4036]: https://gitlab.freedesktop.org/drm/intel/issues/4036 [i915#404]: https://gitlab.freedesktop.org/drm/intel/issues/404 [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077 [i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079 [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083 [i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098 [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103 [i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212 [i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213 [i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270 [i915#4349]: https://gitlab.freedesktop.org/drm/intel/issues/4349 [i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538 [i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579 [i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812 [i915#4833]: https://gitlab.freedesktop.org/drm/intel/issues/4833 [i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852 [i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860 [i915#4936]: https://gitlab.freedesktop.org/drm/intel/issues/4936 [i915#4958]: https://gitlab.freedesktop.org/drm/intel/issues/4958 [i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176 [i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235 [i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286 [i915#5288]: https://gitlab.freedesktop.org/drm/intel/issues/5288 [i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325 [i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354 [i915#5493]: https://gitlab.freedesktop.org/drm/intel/issues/5493 [i915#5563]: https://gitlab.freedesktop.org/drm/intel/issues/5563 [i915#5566]: https://gitlab.freedesktop.org/drm/intel/issues/5566 [i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095 [i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268 [i915#6433]: https://gitlab.freedesktop.org/drm/intel/issues/6433 [i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524 [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658 [i915#6590]: https://gitlab.freedesktop.org/drm/intel/issues/6590 [i915#6946]: https://gitlab.freedesktop.org/drm/intel/issues/6946 [i915#7116]: https://gitlab.freedesktop.org/drm/intel/issues/7116 [i915#72]: https://gitlab.freedesktop.org/drm/intel/issues/72 [i915#7561]: https://gitlab.freedesktop.org/drm/intel/issues/7561 [i915#7697]: https://gitlab.freedesktop.org/drm/intel/issues/7697 [i915#7707]: https://gitlab.freedesktop.org/drm/intel/issues/7707 [i915#7711]: https://gitlab.freedesktop.org/drm/intel/issues/7711 [i915#7742]: https://gitlab.freedesktop.org/drm/intel/issues/7742 [i915#7790]: https://gitlab.freedesktop.org/drm/intel/issues/7790 [i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828 [i915#8011]: https://gitlab.freedesktop.org/drm/intel/issues/8011 [i915#8381]: https://gitlab.freedesktop.org/drm/intel/issues/8381 Build changes ------------- * Linux: CI_DRM_13043 -> Patchwork_116816v2 CI-20190529: 20190529 CI_DRM_13043: 2fa9c266135355c9993507d7c27cc6722956bfec @ git://anongit.freedesktop.org/gfx-ci/linux IGT_7264: 2f0a07378e58e5c7d7b589b39ace7e3a2317f6b2 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_116816v2: 2fa9c266135355c9993507d7c27cc6722956bfec @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116816v2/index.html [-- Attachment #2: Type: text/html, Size: 9170 bytes --] ^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2023-04-22 9:44 UTC | newest] Thread overview: 7+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2023-04-21 19:00 [Intel-gfx] [PATCH v2 0/2] Use i915 instead of dev_priv Andi Shyti 2023-04-21 19:00 ` [Intel-gfx] [PATCH v2 1/2] drm/i915/i915_drv: Use proper parameter naming in for_each_engine() Andi Shyti 2023-04-21 19:00 ` [Intel-gfx] [PATCH v2 2/2] drm/i915/i915_drv: Use i915 instead of dev_priv insied the file_priv structure Andi Shyti 2023-04-21 22:29 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Use i915 instead of dev_priv (rev2) Patchwork 2023-04-21 22:29 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork 2023-04-21 22:41 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2023-04-22 9:43 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
This is a public inbox, see mirroring instructions for how to clone and mirror all data and code used for this inbox