* [Intel-gfx] [PATCH 0/2] Restore MTL boot
@ 2023-04-24 16:09 Andi Shyti
2023-04-24 16:09 ` [Intel-gfx] [PATCH 1/2] Revert "drm/i915/mtl: fix mocs selftest" Andi Shyti
` (5 more replies)
0 siblings, 6 replies; 9+ messages in thread
From: Andi Shyti @ 2023-04-24 16:09 UTC (permalink / raw)
To: Intel GFX, DRI Devel, Fei Yang
Cc: Andrzej Hajda, Lucas Martins De Marchi, Andi Shyti, Matt Roper,
Nirmoy Das
Hi,
The two patches reverted in this series are, together, preventing
MTL from booting.
Revert them until the fix is deployed.
Andi
Andi Shyti (2):
Revert "drm/i915/mtl: fix mocs selftest"
Revert "drm/i915/mtl: Define MOCS and PAT tables for MTL"
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 6 +--
drivers/gpu/drm/i915/gt/intel_gtt.c | 47 +----------------
drivers/gpu/drm/i915/gt/intel_gtt.h | 8 ---
drivers/gpu/drm/i915/gt/intel_mocs.c | 70 +------------------------
drivers/gpu/drm/i915/gt/selftest_mocs.c | 3 +-
5 files changed, 4 insertions(+), 130 deletions(-)
--
2.40.0
^ permalink raw reply [flat|nested] 9+ messages in thread* [Intel-gfx] [PATCH 1/2] Revert "drm/i915/mtl: fix mocs selftest" 2023-04-24 16:09 [Intel-gfx] [PATCH 0/2] Restore MTL boot Andi Shyti @ 2023-04-24 16:09 ` Andi Shyti 2023-04-25 6:25 ` Andrzej Hajda 2023-04-24 16:09 ` [Intel-gfx] [PATCH 2/2] Revert "drm/i915/mtl: Define MOCS and PAT tables for MTL" Andi Shyti ` (4 subsequent siblings) 5 siblings, 1 reply; 9+ messages in thread From: Andi Shyti @ 2023-04-24 16:09 UTC (permalink / raw) To: Intel GFX, DRI Devel, Fei Yang Cc: Andrzej Hajda, Lucas Martins De Marchi, Andi Shyti, Matt Roper, Nirmoy Das This reverts commit faca6aaa4838c3c234caa619d3c7d1f09da0d303. This patch, in series with the next "Define MOCS and PAT tables for MTL" are causing boot failures for MTL. Revert them both. Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com> Cc: Fei Yang <fei.yang@intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> --- drivers/gpu/drm/i915/gt/selftest_mocs.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/selftest_mocs.c b/drivers/gpu/drm/i915/gt/selftest_mocs.c index a8446ab825012..ca009a6a13bdb 100644 --- a/drivers/gpu/drm/i915/gt/selftest_mocs.c +++ b/drivers/gpu/drm/i915/gt/selftest_mocs.c @@ -131,14 +131,13 @@ static int read_mocs_table(struct i915_request *rq, const struct drm_i915_mocs_table *table, u32 *offset) { - struct intel_gt *gt = rq->engine->gt; u32 addr; if (!table) return 0; if (HAS_GLOBAL_MOCS_REGISTERS(rq->engine->i915)) - addr = global_mocs_offset() + gt->uncore->gsi_offset; + addr = global_mocs_offset(); else addr = mocs_offset(rq->engine); -- 2.40.0 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [Intel-gfx] [PATCH 1/2] Revert "drm/i915/mtl: fix mocs selftest" 2023-04-24 16:09 ` [Intel-gfx] [PATCH 1/2] Revert "drm/i915/mtl: fix mocs selftest" Andi Shyti @ 2023-04-25 6:25 ` Andrzej Hajda 0 siblings, 0 replies; 9+ messages in thread From: Andrzej Hajda @ 2023-04-25 6:25 UTC (permalink / raw) To: Andi Shyti, Intel GFX, DRI Devel, Fei Yang Cc: Matt Roper, Lucas Martins De Marchi, Andi Shyti, Nirmoy Das On 24.04.2023 18:09, Andi Shyti wrote: > This reverts commit faca6aaa4838c3c234caa619d3c7d1f09da0d303. > > This patch, in series with the next "Define MOCS and PAT tables > for MTL" are causing boot failures for MTL. > > Revert them both. > > Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com> > Cc: Fei Yang <fei.yang@intel.com> > Cc: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com> Regards Andrzej > --- > drivers/gpu/drm/i915/gt/selftest_mocs.c | 3 +-- > 1 file changed, 1 insertion(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/selftest_mocs.c b/drivers/gpu/drm/i915/gt/selftest_mocs.c > index a8446ab825012..ca009a6a13bdb 100644 > --- a/drivers/gpu/drm/i915/gt/selftest_mocs.c > +++ b/drivers/gpu/drm/i915/gt/selftest_mocs.c > @@ -131,14 +131,13 @@ static int read_mocs_table(struct i915_request *rq, > const struct drm_i915_mocs_table *table, > u32 *offset) > { > - struct intel_gt *gt = rq->engine->gt; > u32 addr; > > if (!table) > return 0; > > if (HAS_GLOBAL_MOCS_REGISTERS(rq->engine->i915)) > - addr = global_mocs_offset() + gt->uncore->gsi_offset; > + addr = global_mocs_offset(); > else > addr = mocs_offset(rq->engine); > ^ permalink raw reply [flat|nested] 9+ messages in thread
* [Intel-gfx] [PATCH 2/2] Revert "drm/i915/mtl: Define MOCS and PAT tables for MTL" 2023-04-24 16:09 [Intel-gfx] [PATCH 0/2] Restore MTL boot Andi Shyti 2023-04-24 16:09 ` [Intel-gfx] [PATCH 1/2] Revert "drm/i915/mtl: fix mocs selftest" Andi Shyti @ 2023-04-24 16:09 ` Andi Shyti 2023-04-25 6:25 ` Andrzej Hajda 2023-04-24 16:16 ` [Intel-gfx] [PATCH 0/2] Restore MTL boot Das, Nirmoy ` (3 subsequent siblings) 5 siblings, 1 reply; 9+ messages in thread From: Andi Shyti @ 2023-04-24 16:09 UTC (permalink / raw) To: Intel GFX, DRI Devel, Fei Yang Cc: Andrzej Hajda, Lucas Martins De Marchi, Andi Shyti, Matt Roper, Nirmoy Das This reverts commit b76c0deef6273609c02ed5053209f6397cd1b0fb. This patch is causing boot failures for MTL. Revert it. Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Aravind Iddamsetty <aravind.iddamsetty@intel.com> Cc: Nirmoy Das <nirmoy.das@intel.com> Cc: Fei Yang <fei.yang@intel.com> Cc: Andrzej Hajda <andrzej.hajda@intel.com> --- drivers/gpu/drm/i915/gt/intel_gt_regs.h | 6 +-- drivers/gpu/drm/i915/gt/intel_gtt.c | 47 +---------------- drivers/gpu/drm/i915/gt/intel_gtt.h | 8 --- drivers/gpu/drm/i915/gt/intel_mocs.c | 70 +------------------------ 4 files changed, 3 insertions(+), 128 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h index e8c3b762a92a3..fd1f9cd35e9d7 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h @@ -356,11 +356,7 @@ #define GEN7_TLB_RD_ADDR _MMIO(0x4700) #define GEN12_PAT_INDEX(index) _MMIO(0x4800 + (index) * 4) -#define _PAT_INDEX(index) _PICK_EVEN_2RANGES(index, 8, \ - 0x4800, 0x4804, \ - 0x4848, 0x484c) -#define XEHP_PAT_INDEX(index) MCR_REG(_PAT_INDEX(index)) -#define XELPMP_PAT_INDEX(index) _MMIO(_PAT_INDEX(index)) +#define XEHP_PAT_INDEX(index) MCR_REG(0x4800 + (index) * 4) #define XEHP_TILE0_ADDR_RANGE MCR_REG(0x4900) #define XEHP_TILE_LMEM_RANGE_SHIFT 8 diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c b/drivers/gpu/drm/i915/gt/intel_gtt.c index 2f6a9be0ffe61..4f436ba7a3c83 100644 --- a/drivers/gpu/drm/i915/gt/intel_gtt.c +++ b/drivers/gpu/drm/i915/gt/intel_gtt.c @@ -468,44 +468,6 @@ void gtt_write_workarounds(struct intel_gt *gt) } } -static void xelpmp_setup_private_ppat(struct intel_uncore *uncore) -{ - intel_uncore_write(uncore, XELPMP_PAT_INDEX(0), - MTL_PPAT_L4_0_WB); - intel_uncore_write(uncore, XELPMP_PAT_INDEX(1), - MTL_PPAT_L4_1_WT); - intel_uncore_write(uncore, XELPMP_PAT_INDEX(2), - MTL_PPAT_L4_3_UC); - intel_uncore_write(uncore, XELPMP_PAT_INDEX(3), - MTL_PPAT_L4_0_WB | MTL_2_COH_1W); - intel_uncore_write(uncore, XELPMP_PAT_INDEX(4), - MTL_PPAT_L4_0_WB | MTL_3_COH_2W); - - /* - * Remaining PAT entries are left at the hardware-default - * fully-cached setting - */ -} - -static void xelpg_setup_private_ppat(struct intel_gt *gt) -{ - intel_gt_mcr_multicast_write(gt, XEHP_PAT_INDEX(0), - MTL_PPAT_L4_0_WB); - intel_gt_mcr_multicast_write(gt, XEHP_PAT_INDEX(1), - MTL_PPAT_L4_1_WT); - intel_gt_mcr_multicast_write(gt, XEHP_PAT_INDEX(2), - MTL_PPAT_L4_3_UC); - intel_gt_mcr_multicast_write(gt, XEHP_PAT_INDEX(3), - MTL_PPAT_L4_0_WB | MTL_2_COH_1W); - intel_gt_mcr_multicast_write(gt, XEHP_PAT_INDEX(4), - MTL_PPAT_L4_0_WB | MTL_3_COH_2W); - - /* - * Remaining PAT entries are left at the hardware-default - * fully-cached setting - */ -} - static void tgl_setup_private_ppat(struct intel_uncore *uncore) { /* TGL doesn't support LLC or AGE settings */ @@ -641,14 +603,7 @@ void setup_private_pat(struct intel_gt *gt) GEM_BUG_ON(GRAPHICS_VER(i915) < 8); - if (gt->type == GT_MEDIA) { - xelpmp_setup_private_ppat(gt->uncore); - return; - } - - if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) - xelpg_setup_private_ppat(gt); - else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) + if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) xehp_setup_private_ppat(gt); else if (GRAPHICS_VER(i915) >= 12) tgl_setup_private_ppat(uncore); diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h b/drivers/gpu/drm/i915/gt/intel_gtt.h index ea17849e7a5c8..69ce55f517f56 100644 --- a/drivers/gpu/drm/i915/gt/intel_gtt.h +++ b/drivers/gpu/drm/i915/gt/intel_gtt.h @@ -147,14 +147,6 @@ typedef u64 gen8_pte_t; #define GEN8_PDE_IPS_64K BIT(11) #define GEN8_PDE_PS_2M BIT(7) -#define MTL_PPAT_L4_CACHE_POLICY_MASK REG_GENMASK(3, 2) -#define MTL_PAT_INDEX_COH_MODE_MASK REG_GENMASK(1, 0) -#define MTL_PPAT_L4_3_UC REG_FIELD_PREP(MTL_PPAT_L4_CACHE_POLICY_MASK, 3) -#define MTL_PPAT_L4_1_WT REG_FIELD_PREP(MTL_PPAT_L4_CACHE_POLICY_MASK, 1) -#define MTL_PPAT_L4_0_WB REG_FIELD_PREP(MTL_PPAT_L4_CACHE_POLICY_MASK, 0) -#define MTL_3_COH_2W REG_FIELD_PREP(MTL_PAT_INDEX_COH_MODE_MASK, 3) -#define MTL_2_COH_1W REG_FIELD_PREP(MTL_PAT_INDEX_COH_MODE_MASK, 2) - enum i915_cache_level; struct drm_i915_gem_object; diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c index 2c014407225cc..69b489e8dfeda 100644 --- a/drivers/gpu/drm/i915/gt/intel_mocs.c +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c @@ -40,10 +40,6 @@ struct drm_i915_mocs_table { #define LE_COS(value) ((value) << 15) #define LE_SSE(value) ((value) << 17) -/* Defines for the tables (GLOB_MOCS_0 - GLOB_MOCS_16) */ -#define _L4_CACHEABILITY(value) ((value) << 2) -#define IG_PAT(value) ((value) << 8) - /* Defines for the tables (LNCFMOCS0 - LNCFMOCS31) - two entries per word */ #define L3_ESC(value) ((value) << 0) #define L3_SCC(value) ((value) << 1) @@ -54,7 +50,6 @@ struct drm_i915_mocs_table { /* Helper defines */ #define GEN9_NUM_MOCS_ENTRIES 64 /* 63-64 are reserved, but configured. */ #define PVC_NUM_MOCS_ENTRIES 3 -#define MTL_NUM_MOCS_ENTRIES 16 /* (e)LLC caching options */ /* @@ -78,12 +73,6 @@ struct drm_i915_mocs_table { #define L3_2_RESERVED _L3_CACHEABILITY(2) #define L3_3_WB _L3_CACHEABILITY(3) -/* L4 caching options */ -#define L4_0_WB _L4_CACHEABILITY(0) -#define L4_1_WT _L4_CACHEABILITY(1) -#define L4_2_RESERVED _L4_CACHEABILITY(2) -#define L4_3_UC _L4_CACHEABILITY(3) - #define MOCS_ENTRY(__idx, __control_value, __l3cc_value) \ [__idx] = { \ .control_value = __control_value, \ @@ -427,57 +416,6 @@ static const struct drm_i915_mocs_entry pvc_mocs_table[] = { MOCS_ENTRY(2, 0, L3_3_WB), }; -static const struct drm_i915_mocs_entry mtl_mocs_table[] = { - /* Error - Reserved for Non-Use */ - MOCS_ENTRY(0, - IG_PAT(0), - L3_LKUP(1) | L3_3_WB), - /* Cached - L3 + L4 */ - MOCS_ENTRY(1, - IG_PAT(1), - L3_LKUP(1) | L3_3_WB), - /* L4 - GO:L3 */ - MOCS_ENTRY(2, - IG_PAT(1), - L3_LKUP(1) | L3_1_UC), - /* Uncached - GO:L3 */ - MOCS_ENTRY(3, - IG_PAT(1) | L4_3_UC, - L3_LKUP(1) | L3_1_UC), - /* L4 - GO:Mem */ - MOCS_ENTRY(4, - IG_PAT(1), - L3_LKUP(1) | L3_GLBGO(1) | L3_1_UC), - /* Uncached - GO:Mem */ - MOCS_ENTRY(5, - IG_PAT(1) | L4_3_UC, - L3_LKUP(1) | L3_GLBGO(1) | L3_1_UC), - /* L4 - L3:NoLKUP; GO:L3 */ - MOCS_ENTRY(6, - IG_PAT(1), - L3_1_UC), - /* Uncached - L3:NoLKUP; GO:L3 */ - MOCS_ENTRY(7, - IG_PAT(1) | L4_3_UC, - L3_1_UC), - /* L4 - L3:NoLKUP; GO:Mem */ - MOCS_ENTRY(8, - IG_PAT(1), - L3_GLBGO(1) | L3_1_UC), - /* Uncached - L3:NoLKUP; GO:Mem */ - MOCS_ENTRY(9, - IG_PAT(1) | L4_3_UC, - L3_GLBGO(1) | L3_1_UC), - /* Display - L3; L4:WT */ - MOCS_ENTRY(14, - IG_PAT(1) | L4_1_WT, - L3_LKUP(1) | L3_3_WB), - /* CCS - Non-Displayable */ - MOCS_ENTRY(15, - IG_PAT(1), - L3_GLBGO(1) | L3_1_UC), -}; - enum { HAS_GLOBAL_MOCS = BIT(0), HAS_ENGINE_MOCS = BIT(1), @@ -507,13 +445,7 @@ static unsigned int get_mocs_settings(const struct drm_i915_private *i915, memset(table, 0, sizeof(struct drm_i915_mocs_table)); table->unused_entries_index = I915_MOCS_PTE; - if (IS_METEORLAKE(i915)) { - table->size = ARRAY_SIZE(mtl_mocs_table); - table->table = mtl_mocs_table; - table->n_entries = MTL_NUM_MOCS_ENTRIES; - table->uc_index = 9; - table->unused_entries_index = 1; - } else if (IS_PONTEVECCHIO(i915)) { + if (IS_PONTEVECCHIO(i915)) { table->size = ARRAY_SIZE(pvc_mocs_table); table->table = pvc_mocs_table; table->n_entries = PVC_NUM_MOCS_ENTRIES; -- 2.40.0 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [Intel-gfx] [PATCH 2/2] Revert "drm/i915/mtl: Define MOCS and PAT tables for MTL" 2023-04-24 16:09 ` [Intel-gfx] [PATCH 2/2] Revert "drm/i915/mtl: Define MOCS and PAT tables for MTL" Andi Shyti @ 2023-04-25 6:25 ` Andrzej Hajda 0 siblings, 0 replies; 9+ messages in thread From: Andrzej Hajda @ 2023-04-25 6:25 UTC (permalink / raw) To: Andi Shyti, Intel GFX, DRI Devel, Fei Yang Cc: Matt Roper, Lucas Martins De Marchi, Andi Shyti, Nirmoy Das On 24.04.2023 18:09, Andi Shyti wrote: > This reverts commit b76c0deef6273609c02ed5053209f6397cd1b0fb. > > This patch is causing boot failures for MTL. > > Revert it. > > Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com> > Cc: Matt Roper <matthew.d.roper@intel.com> > Cc: Lucas De Marchi <lucas.demarchi@intel.com> > Cc: Aravind Iddamsetty <aravind.iddamsetty@intel.com> > Cc: Nirmoy Das <nirmoy.das@intel.com> > Cc: Fei Yang <fei.yang@intel.com> > Cc: Andrzej Hajda <andrzej.hajda@intel.com> Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com> Regards Andrzej > --- > drivers/gpu/drm/i915/gt/intel_gt_regs.h | 6 +-- > drivers/gpu/drm/i915/gt/intel_gtt.c | 47 +---------------- > drivers/gpu/drm/i915/gt/intel_gtt.h | 8 --- > drivers/gpu/drm/i915/gt/intel_mocs.c | 70 +------------------------ > 4 files changed, 3 insertions(+), 128 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > index e8c3b762a92a3..fd1f9cd35e9d7 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h > +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > @@ -356,11 +356,7 @@ > #define GEN7_TLB_RD_ADDR _MMIO(0x4700) > > #define GEN12_PAT_INDEX(index) _MMIO(0x4800 + (index) * 4) > -#define _PAT_INDEX(index) _PICK_EVEN_2RANGES(index, 8, \ > - 0x4800, 0x4804, \ > - 0x4848, 0x484c) > -#define XEHP_PAT_INDEX(index) MCR_REG(_PAT_INDEX(index)) > -#define XELPMP_PAT_INDEX(index) _MMIO(_PAT_INDEX(index)) > +#define XEHP_PAT_INDEX(index) MCR_REG(0x4800 + (index) * 4) > > #define XEHP_TILE0_ADDR_RANGE MCR_REG(0x4900) > #define XEHP_TILE_LMEM_RANGE_SHIFT 8 > diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c b/drivers/gpu/drm/i915/gt/intel_gtt.c > index 2f6a9be0ffe61..4f436ba7a3c83 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gtt.c > +++ b/drivers/gpu/drm/i915/gt/intel_gtt.c > @@ -468,44 +468,6 @@ void gtt_write_workarounds(struct intel_gt *gt) > } > } > > -static void xelpmp_setup_private_ppat(struct intel_uncore *uncore) > -{ > - intel_uncore_write(uncore, XELPMP_PAT_INDEX(0), > - MTL_PPAT_L4_0_WB); > - intel_uncore_write(uncore, XELPMP_PAT_INDEX(1), > - MTL_PPAT_L4_1_WT); > - intel_uncore_write(uncore, XELPMP_PAT_INDEX(2), > - MTL_PPAT_L4_3_UC); > - intel_uncore_write(uncore, XELPMP_PAT_INDEX(3), > - MTL_PPAT_L4_0_WB | MTL_2_COH_1W); > - intel_uncore_write(uncore, XELPMP_PAT_INDEX(4), > - MTL_PPAT_L4_0_WB | MTL_3_COH_2W); > - > - /* > - * Remaining PAT entries are left at the hardware-default > - * fully-cached setting > - */ > -} > - > -static void xelpg_setup_private_ppat(struct intel_gt *gt) > -{ > - intel_gt_mcr_multicast_write(gt, XEHP_PAT_INDEX(0), > - MTL_PPAT_L4_0_WB); > - intel_gt_mcr_multicast_write(gt, XEHP_PAT_INDEX(1), > - MTL_PPAT_L4_1_WT); > - intel_gt_mcr_multicast_write(gt, XEHP_PAT_INDEX(2), > - MTL_PPAT_L4_3_UC); > - intel_gt_mcr_multicast_write(gt, XEHP_PAT_INDEX(3), > - MTL_PPAT_L4_0_WB | MTL_2_COH_1W); > - intel_gt_mcr_multicast_write(gt, XEHP_PAT_INDEX(4), > - MTL_PPAT_L4_0_WB | MTL_3_COH_2W); > - > - /* > - * Remaining PAT entries are left at the hardware-default > - * fully-cached setting > - */ > -} > - > static void tgl_setup_private_ppat(struct intel_uncore *uncore) > { > /* TGL doesn't support LLC or AGE settings */ > @@ -641,14 +603,7 @@ void setup_private_pat(struct intel_gt *gt) > > GEM_BUG_ON(GRAPHICS_VER(i915) < 8); > > - if (gt->type == GT_MEDIA) { > - xelpmp_setup_private_ppat(gt->uncore); > - return; > - } > - > - if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) > - xelpg_setup_private_ppat(gt); > - else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) > + if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) > xehp_setup_private_ppat(gt); > else if (GRAPHICS_VER(i915) >= 12) > tgl_setup_private_ppat(uncore); > diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h b/drivers/gpu/drm/i915/gt/intel_gtt.h > index ea17849e7a5c8..69ce55f517f56 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gtt.h > +++ b/drivers/gpu/drm/i915/gt/intel_gtt.h > @@ -147,14 +147,6 @@ typedef u64 gen8_pte_t; > #define GEN8_PDE_IPS_64K BIT(11) > #define GEN8_PDE_PS_2M BIT(7) > > -#define MTL_PPAT_L4_CACHE_POLICY_MASK REG_GENMASK(3, 2) > -#define MTL_PAT_INDEX_COH_MODE_MASK REG_GENMASK(1, 0) > -#define MTL_PPAT_L4_3_UC REG_FIELD_PREP(MTL_PPAT_L4_CACHE_POLICY_MASK, 3) > -#define MTL_PPAT_L4_1_WT REG_FIELD_PREP(MTL_PPAT_L4_CACHE_POLICY_MASK, 1) > -#define MTL_PPAT_L4_0_WB REG_FIELD_PREP(MTL_PPAT_L4_CACHE_POLICY_MASK, 0) > -#define MTL_3_COH_2W REG_FIELD_PREP(MTL_PAT_INDEX_COH_MODE_MASK, 3) > -#define MTL_2_COH_1W REG_FIELD_PREP(MTL_PAT_INDEX_COH_MODE_MASK, 2) > - > enum i915_cache_level; > > struct drm_i915_gem_object; > diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c > index 2c014407225cc..69b489e8dfeda 100644 > --- a/drivers/gpu/drm/i915/gt/intel_mocs.c > +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c > @@ -40,10 +40,6 @@ struct drm_i915_mocs_table { > #define LE_COS(value) ((value) << 15) > #define LE_SSE(value) ((value) << 17) > > -/* Defines for the tables (GLOB_MOCS_0 - GLOB_MOCS_16) */ > -#define _L4_CACHEABILITY(value) ((value) << 2) > -#define IG_PAT(value) ((value) << 8) > - > /* Defines for the tables (LNCFMOCS0 - LNCFMOCS31) - two entries per word */ > #define L3_ESC(value) ((value) << 0) > #define L3_SCC(value) ((value) << 1) > @@ -54,7 +50,6 @@ struct drm_i915_mocs_table { > /* Helper defines */ > #define GEN9_NUM_MOCS_ENTRIES 64 /* 63-64 are reserved, but configured. */ > #define PVC_NUM_MOCS_ENTRIES 3 > -#define MTL_NUM_MOCS_ENTRIES 16 > > /* (e)LLC caching options */ > /* > @@ -78,12 +73,6 @@ struct drm_i915_mocs_table { > #define L3_2_RESERVED _L3_CACHEABILITY(2) > #define L3_3_WB _L3_CACHEABILITY(3) > > -/* L4 caching options */ > -#define L4_0_WB _L4_CACHEABILITY(0) > -#define L4_1_WT _L4_CACHEABILITY(1) > -#define L4_2_RESERVED _L4_CACHEABILITY(2) > -#define L4_3_UC _L4_CACHEABILITY(3) > - > #define MOCS_ENTRY(__idx, __control_value, __l3cc_value) \ > [__idx] = { \ > .control_value = __control_value, \ > @@ -427,57 +416,6 @@ static const struct drm_i915_mocs_entry pvc_mocs_table[] = { > MOCS_ENTRY(2, 0, L3_3_WB), > }; > > -static const struct drm_i915_mocs_entry mtl_mocs_table[] = { > - /* Error - Reserved for Non-Use */ > - MOCS_ENTRY(0, > - IG_PAT(0), > - L3_LKUP(1) | L3_3_WB), > - /* Cached - L3 + L4 */ > - MOCS_ENTRY(1, > - IG_PAT(1), > - L3_LKUP(1) | L3_3_WB), > - /* L4 - GO:L3 */ > - MOCS_ENTRY(2, > - IG_PAT(1), > - L3_LKUP(1) | L3_1_UC), > - /* Uncached - GO:L3 */ > - MOCS_ENTRY(3, > - IG_PAT(1) | L4_3_UC, > - L3_LKUP(1) | L3_1_UC), > - /* L4 - GO:Mem */ > - MOCS_ENTRY(4, > - IG_PAT(1), > - L3_LKUP(1) | L3_GLBGO(1) | L3_1_UC), > - /* Uncached - GO:Mem */ > - MOCS_ENTRY(5, > - IG_PAT(1) | L4_3_UC, > - L3_LKUP(1) | L3_GLBGO(1) | L3_1_UC), > - /* L4 - L3:NoLKUP; GO:L3 */ > - MOCS_ENTRY(6, > - IG_PAT(1), > - L3_1_UC), > - /* Uncached - L3:NoLKUP; GO:L3 */ > - MOCS_ENTRY(7, > - IG_PAT(1) | L4_3_UC, > - L3_1_UC), > - /* L4 - L3:NoLKUP; GO:Mem */ > - MOCS_ENTRY(8, > - IG_PAT(1), > - L3_GLBGO(1) | L3_1_UC), > - /* Uncached - L3:NoLKUP; GO:Mem */ > - MOCS_ENTRY(9, > - IG_PAT(1) | L4_3_UC, > - L3_GLBGO(1) | L3_1_UC), > - /* Display - L3; L4:WT */ > - MOCS_ENTRY(14, > - IG_PAT(1) | L4_1_WT, > - L3_LKUP(1) | L3_3_WB), > - /* CCS - Non-Displayable */ > - MOCS_ENTRY(15, > - IG_PAT(1), > - L3_GLBGO(1) | L3_1_UC), > -}; > - > enum { > HAS_GLOBAL_MOCS = BIT(0), > HAS_ENGINE_MOCS = BIT(1), > @@ -507,13 +445,7 @@ static unsigned int get_mocs_settings(const struct drm_i915_private *i915, > memset(table, 0, sizeof(struct drm_i915_mocs_table)); > > table->unused_entries_index = I915_MOCS_PTE; > - if (IS_METEORLAKE(i915)) { > - table->size = ARRAY_SIZE(mtl_mocs_table); > - table->table = mtl_mocs_table; > - table->n_entries = MTL_NUM_MOCS_ENTRIES; > - table->uc_index = 9; > - table->unused_entries_index = 1; > - } else if (IS_PONTEVECCHIO(i915)) { > + if (IS_PONTEVECCHIO(i915)) { > table->size = ARRAY_SIZE(pvc_mocs_table); > table->table = pvc_mocs_table; > table->n_entries = PVC_NUM_MOCS_ENTRIES; ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [Intel-gfx] [PATCH 0/2] Restore MTL boot 2023-04-24 16:09 [Intel-gfx] [PATCH 0/2] Restore MTL boot Andi Shyti 2023-04-24 16:09 ` [Intel-gfx] [PATCH 1/2] Revert "drm/i915/mtl: fix mocs selftest" Andi Shyti 2023-04-24 16:09 ` [Intel-gfx] [PATCH 2/2] Revert "drm/i915/mtl: Define MOCS and PAT tables for MTL" Andi Shyti @ 2023-04-24 16:16 ` Das, Nirmoy 2023-04-24 23:47 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Restore MTL boot (rev2) Patchwork ` (2 subsequent siblings) 5 siblings, 0 replies; 9+ messages in thread From: Das, Nirmoy @ 2023-04-24 16:16 UTC (permalink / raw) To: Andi Shyti, Intel GFX, DRI Devel, Fei Yang Cc: Lucas Martins De Marchi, Matt Roper, Andrzej Hajda, Andi Shyti On 4/24/2023 6:09 PM, Andi Shyti wrote: > Hi, > > The two patches reverted in this series are, together, preventing > MTL from booting. > > Revert them until the fix is deployed. > > Andi > > Andi Shyti (2): > Revert "drm/i915/mtl: fix mocs selftest" > Revert "drm/i915/mtl: Define MOCS and PAT tables for MTL" Series is Reviewed-by: Nirmoy Das <nirmoy.das@intel.com> > > drivers/gpu/drm/i915/gt/intel_gt_regs.h | 6 +-- > drivers/gpu/drm/i915/gt/intel_gtt.c | 47 +---------------- > drivers/gpu/drm/i915/gt/intel_gtt.h | 8 --- > drivers/gpu/drm/i915/gt/intel_mocs.c | 70 +------------------------ > drivers/gpu/drm/i915/gt/selftest_mocs.c | 3 +- > 5 files changed, 4 insertions(+), 130 deletions(-) > ^ permalink raw reply [flat|nested] 9+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Restore MTL boot (rev2) 2023-04-24 16:09 [Intel-gfx] [PATCH 0/2] Restore MTL boot Andi Shyti ` (2 preceding siblings ...) 2023-04-24 16:16 ` [Intel-gfx] [PATCH 0/2] Restore MTL boot Das, Nirmoy @ 2023-04-24 23:47 ` Patchwork 2023-04-25 0:01 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2023-04-25 6:19 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork 5 siblings, 0 replies; 9+ messages in thread From: Patchwork @ 2023-04-24 23:47 UTC (permalink / raw) To: Andi Shyti; +Cc: intel-gfx == Series Details == Series: Restore MTL boot (rev2) URL : https://patchwork.freedesktop.org/series/116894/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. ^ permalink raw reply [flat|nested] 9+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for Restore MTL boot (rev2) 2023-04-24 16:09 [Intel-gfx] [PATCH 0/2] Restore MTL boot Andi Shyti ` (3 preceding siblings ...) 2023-04-24 23:47 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Restore MTL boot (rev2) Patchwork @ 2023-04-25 0:01 ` Patchwork 2023-04-25 6:19 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork 5 siblings, 0 replies; 9+ messages in thread From: Patchwork @ 2023-04-25 0:01 UTC (permalink / raw) To: Andi Shyti; +Cc: intel-gfx [-- Attachment #1: Type: text/plain, Size: 6058 bytes --] == Series Details == Series: Restore MTL boot (rev2) URL : https://patchwork.freedesktop.org/series/116894/ State : success == Summary == CI Bug Log - changes from CI_DRM_13056 -> Patchwork_116894v2 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116894v2/index.html Participating hosts (39 -> 37) ------------------------------ Missing (2): fi-kbl-soraka fi-snb-2520m Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_116894v2: ### IGT changes ### #### Suppressed #### The following results come from untrusted machines, tests, or statuses. They do not affect the overall result. * igt@i915_selftest@live@hugepages: - {bat-mtlp-8}: NOTRUN -> [DMESG-FAIL][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116894v2/bat-mtlp-8/igt@i915_selftest@live@hugepages.html * igt@kms_pipe_crc_basic@suspend-read-crc@pipe-c-edp-1: - {bat-mtlp-8}: NOTRUN -> [SKIP][2] +1 similar issue [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116894v2/bat-mtlp-8/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-c-edp-1.html Known issues ------------ Here are the changes found in Patchwork_116894v2 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@i915_selftest@live@gt_heartbeat: - fi-apl-guc: [PASS][3] -> [DMESG-FAIL][4] ([i915#5334]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13056/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116894v2/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html * igt@i915_selftest@live@requests: - bat-rpls-1: [PASS][5] -> [ABORT][6] ([i915#4983] / [i915#7911]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13056/bat-rpls-1/igt@i915_selftest@live@requests.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116894v2/bat-rpls-1/igt@i915_selftest@live@requests.html * igt@kms_pipe_crc_basic@nonblocking-crc@pipe-d-dp-1: - bat-dg2-8: [PASS][7] -> [FAIL][8] ([i915#7932]) +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13056/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc@pipe-d-dp-1.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116894v2/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc@pipe-d-dp-1.html #### Possible fixes #### * igt@i915_module_load@load: - {bat-mtlp-8}: [ABORT][9] ([i915#8361]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13056/bat-mtlp-8/igt@i915_module_load@load.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116894v2/bat-mtlp-8/igt@i915_module_load@load.html * igt@i915_selftest@live@gt_heartbeat: - fi-glk-j4005: [DMESG-FAIL][11] ([i915#5334]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13056/fi-glk-j4005/igt@i915_selftest@live@gt_heartbeat.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116894v2/fi-glk-j4005/igt@i915_selftest@live@gt_heartbeat.html * igt@i915_selftest@live@migrate: - bat-atsm-1: [DMESG-FAIL][13] ([i915#7699]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13056/bat-atsm-1/igt@i915_selftest@live@migrate.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116894v2/bat-atsm-1/igt@i915_selftest@live@migrate.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285 [i915#3595]: https://gitlab.freedesktop.org/drm/intel/issues/3595 [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708 [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077 [i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079 [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083 [i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212 [i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213 [i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579 [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613 [i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983 [i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190 [i915#5274]: https://gitlab.freedesktop.org/drm/intel/issues/5274 [i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334 [i915#6645]: https://gitlab.freedesktop.org/drm/intel/issues/6645 [i915#7456]: https://gitlab.freedesktop.org/drm/intel/issues/7456 [i915#7699]: https://gitlab.freedesktop.org/drm/intel/issues/7699 [i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828 [i915#7911]: https://gitlab.freedesktop.org/drm/intel/issues/7911 [i915#7932]: https://gitlab.freedesktop.org/drm/intel/issues/7932 [i915#8346]: https://gitlab.freedesktop.org/drm/intel/issues/8346 [i915#8361]: https://gitlab.freedesktop.org/drm/intel/issues/8361 [i915#8368]: https://gitlab.freedesktop.org/drm/intel/issues/8368 [i915#8369]: https://gitlab.freedesktop.org/drm/intel/issues/8369 [i915#8379]: https://gitlab.freedesktop.org/drm/intel/issues/8379 Build changes ------------- * Linux: CI_DRM_13056 -> Patchwork_116894v2 CI-20190529: 20190529 CI_DRM_13056: 308c0163d9e46238948942260e6d2abcad3d8bff @ git://anongit.freedesktop.org/gfx-ci/linux IGT_7267: a267f0236e06fc282e3dc3b8c7d76f9ed6088d9b @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_116894v2: 308c0163d9e46238948942260e6d2abcad3d8bff @ git://anongit.freedesktop.org/gfx-ci/linux ### Linux commits 2565120ae169 Revert "drm/i915/mtl: Define MOCS and PAT tables for MTL" 8ff95062e6a8 Revert "drm/i915/mtl: fix mocs selftest" == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116894v2/index.html [-- Attachment #2: Type: text/html, Size: 5662 bytes --] ^ permalink raw reply [flat|nested] 9+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for Restore MTL boot (rev2) 2023-04-24 16:09 [Intel-gfx] [PATCH 0/2] Restore MTL boot Andi Shyti ` (4 preceding siblings ...) 2023-04-25 0:01 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork @ 2023-04-25 6:19 ` Patchwork 5 siblings, 0 replies; 9+ messages in thread From: Patchwork @ 2023-04-25 6:19 UTC (permalink / raw) To: Andi Shyti; +Cc: intel-gfx [-- Attachment #1: Type: text/plain, Size: 13496 bytes --] == Series Details == Series: Restore MTL boot (rev2) URL : https://patchwork.freedesktop.org/series/116894/ State : success == Summary == CI Bug Log - changes from CI_DRM_13056_full -> Patchwork_116894v2_full ==================================================== Summary ------- **SUCCESS** No regressions found. Participating hosts (7 -> 7) ------------------------------ No changes in participating hosts Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_116894v2_full: ### IGT changes ### #### Suppressed #### The following results come from untrusted machines, tests, or statuses. They do not affect the overall result. * igt@gem_workarounds@basic-read-context: - {shard-dg1}: [PASS][1] -> [DMESG-WARN][2] +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13056/shard-dg1-15/igt@gem_workarounds@basic-read-context.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116894v2/shard-dg1-14/igt@gem_workarounds@basic-read-context.html Known issues ------------ Here are the changes found in Patchwork_116894v2_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt@gem_barrier_race@remote-request@rcs0: - shard-apl: [PASS][3] -> [ABORT][4] ([i915#8211] / [i915#8234]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13056/shard-apl2/igt@gem_barrier_race@remote-request@rcs0.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116894v2/shard-apl3/igt@gem_barrier_race@remote-request@rcs0.html * igt@gem_exec_fair@basic-deadline: - shard-glk: [PASS][5] -> [FAIL][6] ([i915#2846]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13056/shard-glk8/igt@gem_exec_fair@basic-deadline.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116894v2/shard-glk3/igt@gem_exec_fair@basic-deadline.html * igt@kms_color@ctm-max@pipe-b-dp-1: - shard-apl: [PASS][7] -> [DMESG-WARN][8] ([i915#62]) +8 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13056/shard-apl1/igt@kms_color@ctm-max@pipe-b-dp-1.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116894v2/shard-apl1/igt@kms_color@ctm-max@pipe-b-dp-1.html * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size: - shard-apl: [PASS][9] -> [FAIL][10] ([i915#2346]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13056/shard-apl6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116894v2/shard-apl6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html * igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-1: - shard-glk: NOTRUN -> [SKIP][11] ([fdo#109271]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116894v2/shard-glk3/igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-1.html * igt@kms_flip@plain-flip-ts-check-interruptible@c-dp1: - shard-apl: [PASS][12] -> [FAIL][13] ([i915#2122]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13056/shard-apl2/igt@kms_flip@plain-flip-ts-check-interruptible@c-dp1.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116894v2/shard-apl6/igt@kms_flip@plain-flip-ts-check-interruptible@c-dp1.html * igt@kms_frontbuffer_tracking@fbc-badstride: - shard-snb: [PASS][14] -> [SKIP][15] ([fdo#109271]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13056/shard-snb5/igt@kms_frontbuffer_tracking@fbc-badstride.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116894v2/shard-snb6/igt@kms_frontbuffer_tracking@fbc-badstride.html #### Possible fixes #### * igt@gem_barrier_race@remote-request@rcs0: - {shard-tglu}: [ABORT][16] ([i915#8211]) -> [PASS][17] [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13056/shard-tglu-6/igt@gem_barrier_race@remote-request@rcs0.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116894v2/shard-tglu-7/igt@gem_barrier_race@remote-request@rcs0.html * igt@gem_exec_fair@basic-pace-solo@rcs0: - {shard-rkl}: [FAIL][18] ([i915#2842]) -> [PASS][19] [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13056/shard-rkl-7/igt@gem_exec_fair@basic-pace-solo@rcs0.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116894v2/shard-rkl-4/igt@gem_exec_fair@basic-pace-solo@rcs0.html * igt@gem_ppgtt@blt-vs-render-ctxn: - shard-snb: [FAIL][20] ([i915#8295]) -> [PASS][21] [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13056/shard-snb1/igt@gem_ppgtt@blt-vs-render-ctxn.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116894v2/shard-snb1/igt@gem_ppgtt@blt-vs-render-ctxn.html * igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a: - {shard-dg1}: [SKIP][22] ([i915#1937]) -> [PASS][23] [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13056/shard-dg1-15/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116894v2/shard-dg1-14/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a.html * igt@i915_pm_rpm@modeset-lpsp-stress-no-wait: - {shard-dg1}: [SKIP][24] ([i915#1397]) -> [PASS][25] [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13056/shard-dg1-15/igt@i915_pm_rpm@modeset-lpsp-stress-no-wait.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116894v2/shard-dg1-14/igt@i915_pm_rpm@modeset-lpsp-stress-no-wait.html * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions: - shard-apl: [FAIL][26] ([i915#2346]) -> [PASS][27] [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13056/shard-apl7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116894v2/shard-apl7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html * igt@kms_cursor_legacy@forked-move@pipe-b: - {shard-dg1}: [INCOMPLETE][28] ([i915#8011] / [i915#8347]) -> [PASS][29] [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13056/shard-dg1-14/igt@kms_cursor_legacy@forked-move@pipe-b.html [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116894v2/shard-dg1-17/igt@kms_cursor_legacy@forked-move@pipe-b.html * igt@kms_flip@2x-flip-vs-expired-vblank@ac-hdmi-a1-hdmi-a2: - shard-glk: [FAIL][30] ([i915#79]) -> [PASS][31] [30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13056/shard-glk4/igt@kms_flip@2x-flip-vs-expired-vblank@ac-hdmi-a1-hdmi-a2.html [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116894v2/shard-glk9/igt@kms_flip@2x-flip-vs-expired-vblank@ac-hdmi-a1-hdmi-a2.html * igt@kms_flip@flip-vs-expired-vblank-interruptible@c-dp1: - shard-apl: [FAIL][32] ([i915#79]) -> [PASS][33] [32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13056/shard-apl1/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-dp1.html [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116894v2/shard-apl1/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-dp1.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280 [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289 [fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291 [fdo#109302]: https://bugs.freedesktop.org/show_bug.cgi?id=109302 [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315 [fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189 [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068 [fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614 [fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615 [fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072 [i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397 [i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839 [i915#1937]: https://gitlab.freedesktop.org/drm/intel/issues/1937 [i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122 [i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346 [i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437 [i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527 [i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575 [i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587 [i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672 [i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842 [i915#2846]: https://gitlab.freedesktop.org/drm/intel/issues/2846 [i915#315]: https://gitlab.freedesktop.org/drm/intel/issues/315 [i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281 [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282 [i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297 [i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359 [i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458 [i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539 [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555 [i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638 [i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689 [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708 [i915#3804]: https://gitlab.freedesktop.org/drm/intel/issues/3804 [i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886 [i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955 [i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070 [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077 [i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078 [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083 [i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212 [i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215 [i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270 [i915#4387]: https://gitlab.freedesktop.org/drm/intel/issues/4387 [i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538 [i915#4565]: https://gitlab.freedesktop.org/drm/intel/issues/4565 [i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579 [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613 [i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812 [i915#4816]: https://gitlab.freedesktop.org/drm/intel/issues/4816 [i915#4833]: https://gitlab.freedesktop.org/drm/intel/issues/4833 [i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852 [i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860 [i915#4879]: https://gitlab.freedesktop.org/drm/intel/issues/4879 [i915#4881]: https://gitlab.freedesktop.org/drm/intel/issues/4881 [i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983 [i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176 [i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235 [i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286 [i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289 [i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354 [i915#5563]: https://gitlab.freedesktop.org/drm/intel/issues/5563 [i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268 [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658 [i915#7116]: https://gitlab.freedesktop.org/drm/intel/issues/7116 [i915#7561]: https://gitlab.freedesktop.org/drm/intel/issues/7561 [i915#7701]: https://gitlab.freedesktop.org/drm/intel/issues/7701 [i915#7711]: https://gitlab.freedesktop.org/drm/intel/issues/7711 [i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828 [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 [i915#8011]: https://gitlab.freedesktop.org/drm/intel/issues/8011 [i915#8211]: https://gitlab.freedesktop.org/drm/intel/issues/8211 [i915#8234]: https://gitlab.freedesktop.org/drm/intel/issues/8234 [i915#8295]: https://gitlab.freedesktop.org/drm/intel/issues/8295 [i915#8311]: https://gitlab.freedesktop.org/drm/intel/issues/8311 [i915#8347]: https://gitlab.freedesktop.org/drm/intel/issues/8347 [i915#8381]: https://gitlab.freedesktop.org/drm/intel/issues/8381 Build changes ------------- * Linux: CI_DRM_13056 -> Patchwork_116894v2 CI-20190529: 20190529 CI_DRM_13056: 308c0163d9e46238948942260e6d2abcad3d8bff @ git://anongit.freedesktop.org/gfx-ci/linux IGT_7267: a267f0236e06fc282e3dc3b8c7d76f9ed6088d9b @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_116894v2: 308c0163d9e46238948942260e6d2abcad3d8bff @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116894v2/index.html [-- Attachment #2: Type: text/html, Size: 10168 bytes --] ^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2023-04-25 6:25 UTC | newest] Thread overview: 9+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2023-04-24 16:09 [Intel-gfx] [PATCH 0/2] Restore MTL boot Andi Shyti 2023-04-24 16:09 ` [Intel-gfx] [PATCH 1/2] Revert "drm/i915/mtl: fix mocs selftest" Andi Shyti 2023-04-25 6:25 ` Andrzej Hajda 2023-04-24 16:09 ` [Intel-gfx] [PATCH 2/2] Revert "drm/i915/mtl: Define MOCS and PAT tables for MTL" Andi Shyti 2023-04-25 6:25 ` Andrzej Hajda 2023-04-24 16:16 ` [Intel-gfx] [PATCH 0/2] Restore MTL boot Das, Nirmoy 2023-04-24 23:47 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Restore MTL boot (rev2) Patchwork 2023-04-25 0:01 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2023-04-25 6:19 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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