* [Intel-gfx] [PATCH v2 0/4] Improvements to GuC error capture
@ 2023-04-28 18:56 John.C.Harrison
2023-04-28 18:56 ` [Intel-gfx] [PATCH v2 1/4] drm/i915/guc: Don't capture Gen8 regs on Xe devices John.C.Harrison
` (6 more replies)
0 siblings, 7 replies; 10+ messages in thread
From: John.C.Harrison @ 2023-04-28 18:56 UTC (permalink / raw)
To: Intel-GFX; +Cc: DRI-Devel
From: John Harrison <John.C.Harrison@Intel.com>
The GuC error capture list creation was including Gen8 registers on Xe
platforms. While fixing that, it was noticed that there were other
issues. The platform naming was wrong, the naming of lists was
misleading, the steered register code was duplicated and steered
registers were not included on all supported platforms.
Separately, it was noticed that the capture list search was broken for
virtual engines. So fix that up too.
v2: Swuash the split patches into a single patch ready for merge.
Also include an extra patch about capture lists and virtual engines.
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
John Harrison (4):
drm/i915/guc: Don't capture Gen8 regs on Xe devices
drm/i915/guc: Consolidate duplicated capture list code
drm/i915/guc: Capture list naming clean up
drm/i915/guc: Fix error capture for virtual engines
.../gpu/drm/i915/gt/uc/intel_guc_capture.c | 242 ++++++++----------
.../gpu/drm/i915/gt/uc/intel_guc_capture.h | 3 +
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 32 ++-
drivers/gpu/drm/i915/i915_gpu_error.c | 11 +-
4 files changed, 149 insertions(+), 139 deletions(-)
--
2.39.1
^ permalink raw reply [flat|nested] 10+ messages in thread* [Intel-gfx] [PATCH v2 1/4] drm/i915/guc: Don't capture Gen8 regs on Xe devices 2023-04-28 18:56 [Intel-gfx] [PATCH v2 0/4] Improvements to GuC error capture John.C.Harrison @ 2023-04-28 18:56 ` John.C.Harrison 2023-04-28 18:56 ` [Intel-gfx] [PATCH v2 2/4] drm/i915/guc: Consolidate duplicated capture list code John.C.Harrison ` (5 subsequent siblings) 6 siblings, 0 replies; 10+ messages in thread From: John.C.Harrison @ 2023-04-28 18:56 UTC (permalink / raw) To: Intel-GFX Cc: Balasubramani Vivekanandan, Alan Previn, Jani Nikula, Matt Roper, Lucas De Marchi, DRI-Devel From: John Harrison <John.C.Harrison@Intel.com> A pair of pre-Xe registers were being included in the Xe capture list. GuC was rejecting those as being invalid and logging errors about them. So, stop doing it. Signed-off-by: John Harrison <John.C.Harrison@Intel.com> Reviewed-by: Alan Previn <alan.previn.teres.alexis@intel.com> Fixes: dce2bd542337 ("drm/i915/guc: Add Gen9 registers for GuC error state capture.") Cc: Alan Previn <alan.previn.teres.alexis@intel.com> Cc: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: John Harrison <John.C.Harrison@Intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> --- drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c index cf49188db6a6e..e0e793167d61b 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c @@ -31,12 +31,14 @@ { FORCEWAKE_MT, 0, 0, "FORCEWAKE" } #define COMMON_GEN9BASE_GLOBAL \ - { GEN8_FAULT_TLB_DATA0, 0, 0, "GEN8_FAULT_TLB_DATA0" }, \ - { GEN8_FAULT_TLB_DATA1, 0, 0, "GEN8_FAULT_TLB_DATA1" }, \ { ERROR_GEN6, 0, 0, "ERROR_GEN6" }, \ { DONE_REG, 0, 0, "DONE_REG" }, \ { HSW_GTT_CACHE_EN, 0, 0, "HSW_GTT_CACHE_EN" } +#define GEN9_GLOBAL \ + { GEN8_FAULT_TLB_DATA0, 0, 0, "GEN8_FAULT_TLB_DATA0" }, \ + { GEN8_FAULT_TLB_DATA1, 0, 0, "GEN8_FAULT_TLB_DATA1" } + #define COMMON_GEN12BASE_GLOBAL \ { GEN12_FAULT_TLB_DATA0, 0, 0, "GEN12_FAULT_TLB_DATA0" }, \ { GEN12_FAULT_TLB_DATA1, 0, 0, "GEN12_FAULT_TLB_DATA1" }, \ @@ -142,6 +144,7 @@ static const struct __guc_mmio_reg_descr xe_lpd_gsc_inst_regs[] = { static const struct __guc_mmio_reg_descr default_global_regs[] = { COMMON_BASE_GLOBAL, COMMON_GEN9BASE_GLOBAL, + GEN9_GLOBAL, }; static const struct __guc_mmio_reg_descr default_rc_class_regs[] = { -- 2.39.1 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* [Intel-gfx] [PATCH v2 2/4] drm/i915/guc: Consolidate duplicated capture list code 2023-04-28 18:56 [Intel-gfx] [PATCH v2 0/4] Improvements to GuC error capture John.C.Harrison 2023-04-28 18:56 ` [Intel-gfx] [PATCH v2 1/4] drm/i915/guc: Don't capture Gen8 regs on Xe devices John.C.Harrison @ 2023-04-28 18:56 ` John.C.Harrison 2023-04-28 18:56 ` [Intel-gfx] [PATCH v2 3/4] drm/i915/guc: Capture list naming clean up John.C.Harrison ` (4 subsequent siblings) 6 siblings, 0 replies; 10+ messages in thread From: John.C.Harrison @ 2023-04-28 18:56 UTC (permalink / raw) To: Intel-GFX; +Cc: Alan Previn, DRI-Devel From: John Harrison <John.C.Harrison@Intel.com> Remove 99% duplicated steered register list code. Also, include the pre-Xe steered registers in the pre-Xe list generation. Signed-off-by: John Harrison <John.C.Harrison@Intel.com> Reviewed-by: Alan Previn <alan.previn.teres.alexis@intel.com> --- .../gpu/drm/i915/gt/uc/intel_guc_capture.c | 112 +++++------------- 1 file changed, 29 insertions(+), 83 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c index e0e793167d61b..9184d2595e4ce 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c @@ -260,11 +260,15 @@ struct __ext_steer_reg { i915_mcr_reg_t reg; }; -static const struct __ext_steer_reg xe_extregs[] = { +static const struct __ext_steer_reg gen8_extregs[] = { {"GEN8_SAMPLER_INSTDONE", GEN8_SAMPLER_INSTDONE}, {"GEN8_ROW_INSTDONE", GEN8_ROW_INSTDONE} }; +static const struct __ext_steer_reg xehpg_extregs[] = { + {"XEHPG_INSTDONE_GEOM_SVG", XEHPG_INSTDONE_GEOM_SVG} +}; + static void __fill_ext_reg(struct __guc_mmio_reg_descr *ext, const struct __ext_steer_reg *extlist, int slice_id, int subslice_id) @@ -295,8 +299,8 @@ __alloc_ext_regs(struct __guc_mmio_reg_descr_group *newlist, } static void -guc_capture_alloc_steered_lists_xe_lpd(struct intel_guc *guc, - const struct __guc_mmio_reg_descr_group *lists) +guc_capture_alloc_steered_lists(struct intel_guc *guc, + const struct __guc_mmio_reg_descr_group *lists) { struct intel_gt *gt = guc_to_gt(guc); int slice, subslice, iter, i, num_steer_regs, num_tot_regs = 0; @@ -304,74 +308,19 @@ guc_capture_alloc_steered_lists_xe_lpd(struct intel_guc *guc, struct __guc_mmio_reg_descr_group *extlists; struct __guc_mmio_reg_descr *extarray; struct sseu_dev_info *sseu; + bool has_xehpg_extregs; - /* In XE_LPD we only have steered registers for the render-class */ + /* steered registers currently only exist for the render-class */ list = guc_capture_get_one_list(lists, GUC_CAPTURE_LIST_INDEX_PF, GUC_CAPTURE_LIST_TYPE_ENGINE_CLASS, GUC_RENDER_CLASS); /* skip if extlists was previously allocated */ if (!list || guc->capture->extlists) return; - num_steer_regs = ARRAY_SIZE(xe_extregs); - - sseu = >->info.sseu; - for_each_ss_steering(iter, gt, slice, subslice) - num_tot_regs += num_steer_regs; - - if (!num_tot_regs) - return; - - /* allocate an extra for an end marker */ - extlists = kcalloc(2, sizeof(struct __guc_mmio_reg_descr_group), GFP_KERNEL); - if (!extlists) - return; - - if (__alloc_ext_regs(&extlists[0], list, num_tot_regs)) { - kfree(extlists); - return; - } - - extarray = extlists[0].extlist; - for_each_ss_steering(iter, gt, slice, subslice) { - for (i = 0; i < num_steer_regs; ++i) { - __fill_ext_reg(extarray, &xe_extregs[i], slice, subslice); - ++extarray; - } - } - - guc->capture->extlists = extlists; -} - -static const struct __ext_steer_reg xehpg_extregs[] = { - {"XEHPG_INSTDONE_GEOM_SVG", XEHPG_INSTDONE_GEOM_SVG} -}; - -static bool __has_xehpg_extregs(u32 ipver) -{ - return (ipver >= IP_VER(12, 55)); -} - -static void -guc_capture_alloc_steered_lists_xe_hpg(struct intel_guc *guc, - const struct __guc_mmio_reg_descr_group *lists, - u32 ipver) -{ - struct intel_gt *gt = guc_to_gt(guc); - struct sseu_dev_info *sseu; - int slice, subslice, i, iter, num_steer_regs, num_tot_regs = 0; - const struct __guc_mmio_reg_descr_group *list; - struct __guc_mmio_reg_descr_group *extlists; - struct __guc_mmio_reg_descr *extarray; - - /* In XE_LP / HPG we only have render-class steering registers during error-capture */ - list = guc_capture_get_one_list(lists, GUC_CAPTURE_LIST_INDEX_PF, - GUC_CAPTURE_LIST_TYPE_ENGINE_CLASS, GUC_RENDER_CLASS); - /* skip if extlists was previously allocated */ - if (!list || guc->capture->extlists) - return; + has_xehpg_extregs = GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 55); - num_steer_regs = ARRAY_SIZE(xe_extregs); - if (__has_xehpg_extregs(ipver)) + num_steer_regs = ARRAY_SIZE(gen8_extregs); + if (has_xehpg_extregs) num_steer_regs += ARRAY_SIZE(xehpg_extregs); sseu = >->info.sseu; @@ -393,11 +342,12 @@ guc_capture_alloc_steered_lists_xe_hpg(struct intel_guc *guc, extarray = extlists[0].extlist; for_each_ss_steering(iter, gt, slice, subslice) { - for (i = 0; i < ARRAY_SIZE(xe_extregs); ++i) { - __fill_ext_reg(extarray, &xe_extregs[i], slice, subslice); + for (i = 0; i < ARRAY_SIZE(gen8_extregs); ++i) { + __fill_ext_reg(extarray, &gen8_extregs[i], slice, subslice); ++extarray; } - if (__has_xehpg_extregs(ipver)) { + + if (has_xehpg_extregs) { for (i = 0; i < ARRAY_SIZE(xehpg_extregs); ++i) { __fill_ext_reg(extarray, &xehpg_extregs[i], slice, subslice); ++extarray; @@ -413,26 +363,22 @@ static const struct __guc_mmio_reg_descr_group * guc_capture_get_device_reglist(struct intel_guc *guc) { struct drm_i915_private *i915 = guc_to_gt(guc)->i915; + const struct __guc_mmio_reg_descr_group *lists; - if (GRAPHICS_VER(i915) > 11) { - /* - * For certain engine classes, there are slice and subslice - * level registers requiring steering. We allocate and populate - * these at init time based on hw config add it as an extension - * list at the end of the pre-populated render list. - */ - if (IS_DG2(i915)) - guc_capture_alloc_steered_lists_xe_hpg(guc, xe_lpd_lists, IP_VER(12, 55)); - else if (IS_XEHPSDV(i915)) - guc_capture_alloc_steered_lists_xe_hpg(guc, xe_lpd_lists, IP_VER(12, 50)); - else - guc_capture_alloc_steered_lists_xe_lpd(guc, xe_lpd_lists); + if (GRAPHICS_VER(i915) >= 12) + lists = xe_lpd_lists; + else + lists = default_lists; - return xe_lpd_lists; - } + /* + * For certain engine classes, there are slice and subslice + * level registers requiring steering. We allocate and populate + * these at init time based on hw config add it as an extension + * list at the end of the pre-populated render list. + */ + guc_capture_alloc_steered_lists(guc, lists); - /* if GuC submission is enabled on a non-POR platform, just use a common baseline */ - return default_lists; + return lists; } static const char * -- 2.39.1 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* [Intel-gfx] [PATCH v2 3/4] drm/i915/guc: Capture list naming clean up 2023-04-28 18:56 [Intel-gfx] [PATCH v2 0/4] Improvements to GuC error capture John.C.Harrison 2023-04-28 18:56 ` [Intel-gfx] [PATCH v2 1/4] drm/i915/guc: Don't capture Gen8 regs on Xe devices John.C.Harrison 2023-04-28 18:56 ` [Intel-gfx] [PATCH v2 2/4] drm/i915/guc: Consolidate duplicated capture list code John.C.Harrison @ 2023-04-28 18:56 ` John.C.Harrison 2023-05-03 17:54 ` Teres Alexis, Alan Previn 2023-04-28 18:56 ` [Intel-gfx] [PATCH v2 4/4] drm/i915/guc: Fix error capture for virtual engines John.C.Harrison ` (3 subsequent siblings) 6 siblings, 1 reply; 10+ messages in thread From: John.C.Harrison @ 2023-04-28 18:56 UTC (permalink / raw) To: Intel-GFX; +Cc: DRI-Devel From: John Harrison <John.C.Harrison@Intel.com> Don't use 'xe_lp*' prefixes for register lists that are common with Gen8. Don't add Xe only GSC registers to pre-Xe devices that don't even have a GSC engine. Fix Xe_LP name. Don't use GEN9 as a prefix for register lists that contain all GEN8 registers. Rename the 'default_' register list prefix to 'gen8_' as that is the more accurate name. Signed-off-by: John Harrison <John.C.Harrison@Intel.com> --- .../gpu/drm/i915/gt/uc/intel_guc_capture.c | 100 +++++++++--------- 1 file changed, 49 insertions(+), 51 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c index 9184d2595e4ce..729a8fcf20dda 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c @@ -30,12 +30,12 @@ #define COMMON_BASE_GLOBAL \ { FORCEWAKE_MT, 0, 0, "FORCEWAKE" } -#define COMMON_GEN9BASE_GLOBAL \ +#define COMMON_GEN8BASE_GLOBAL \ { ERROR_GEN6, 0, 0, "ERROR_GEN6" }, \ { DONE_REG, 0, 0, "DONE_REG" }, \ { HSW_GTT_CACHE_EN, 0, 0, "HSW_GTT_CACHE_EN" } -#define GEN9_GLOBAL \ +#define GEN8_GLOBAL \ { GEN8_FAULT_TLB_DATA0, 0, 0, "GEN8_FAULT_TLB_DATA0" }, \ { GEN8_FAULT_TLB_DATA1, 0, 0, "GEN8_FAULT_TLB_DATA1" } @@ -96,67 +96,65 @@ { GEN12_SFC_DONE(2), 0, 0, "SFC_DONE[2]" }, \ { GEN12_SFC_DONE(3), 0, 0, "SFC_DONE[3]" } -/* XE_LPD - Global */ -static const struct __guc_mmio_reg_descr xe_lpd_global_regs[] = { +/* XE_LP Global */ +static const struct __guc_mmio_reg_descr xe_lp_global_regs[] = { COMMON_BASE_GLOBAL, - COMMON_GEN9BASE_GLOBAL, + COMMON_GEN8BASE_GLOBAL, COMMON_GEN12BASE_GLOBAL, }; -/* XE_LPD - Render / Compute Per-Class */ -static const struct __guc_mmio_reg_descr xe_lpd_rc_class_regs[] = { +/* XE_LP Render / Compute Per-Class */ +static const struct __guc_mmio_reg_descr xe_lp_rc_class_regs[] = { COMMON_BASE_HAS_EU, COMMON_BASE_RENDER, COMMON_GEN12BASE_RENDER, }; -/* GEN9/XE_LPD - Render / Compute Per-Engine-Instance */ -static const struct __guc_mmio_reg_descr xe_lpd_rc_inst_regs[] = { +/* GEN8+ Render / Compute Per-Engine-Instance */ +static const struct __guc_mmio_reg_descr gen8_rc_inst_regs[] = { COMMON_BASE_ENGINE_INSTANCE, }; -/* GEN9/XE_LPD - Media Decode/Encode Per-Engine-Instance */ -static const struct __guc_mmio_reg_descr xe_lpd_vd_inst_regs[] = { +/* GEN8+ Media Decode/Encode Per-Engine-Instance */ +static const struct __guc_mmio_reg_descr gen8_vd_inst_regs[] = { COMMON_BASE_ENGINE_INSTANCE, }; -/* XE_LPD - Video Enhancement Per-Class */ -static const struct __guc_mmio_reg_descr xe_lpd_vec_class_regs[] = { +/* XE_LP Video Enhancement Per-Class */ +static const struct __guc_mmio_reg_descr xe_lp_vec_class_regs[] = { COMMON_GEN12BASE_VEC, }; -/* GEN9/XE_LPD - Video Enhancement Per-Engine-Instance */ -static const struct __guc_mmio_reg_descr xe_lpd_vec_inst_regs[] = { +/* GEN8+ Video Enhancement Per-Engine-Instance */ +static const struct __guc_mmio_reg_descr gen8_vec_inst_regs[] = { COMMON_BASE_ENGINE_INSTANCE, }; -/* GEN9/XE_LPD - Blitter Per-Engine-Instance */ -static const struct __guc_mmio_reg_descr xe_lpd_blt_inst_regs[] = { +/* GEN8+ Blitter Per-Engine-Instance */ +static const struct __guc_mmio_reg_descr gen8_blt_inst_regs[] = { COMMON_BASE_ENGINE_INSTANCE, }; -/* XE_LPD - GSC Per-Engine-Instance */ -static const struct __guc_mmio_reg_descr xe_lpd_gsc_inst_regs[] = { +/* XE_LP - GSC Per-Engine-Instance */ +static const struct __guc_mmio_reg_descr xe_lp_gsc_inst_regs[] = { COMMON_BASE_ENGINE_INSTANCE, }; -/* GEN9 - Global */ -static const struct __guc_mmio_reg_descr default_global_regs[] = { +/* GEN8 - Global */ +static const struct __guc_mmio_reg_descr gen8_global_regs[] = { COMMON_BASE_GLOBAL, - COMMON_GEN9BASE_GLOBAL, - GEN9_GLOBAL, + COMMON_GEN8BASE_GLOBAL, + GEN8_GLOBAL, }; -static const struct __guc_mmio_reg_descr default_rc_class_regs[] = { +static const struct __guc_mmio_reg_descr gen8_rc_class_regs[] = { COMMON_BASE_HAS_EU, COMMON_BASE_RENDER, }; /* - * Empty lists: - * GEN9/XE_LPD - Blitter Per-Class - * GEN9/XE_LPD - Media Decode/Encode Per-Class - * GEN9 - VEC Class + * Empty list to prevent warnings about unknown class/instance types + * as not all class/instanace types have entries on all platforms. */ static const struct __guc_mmio_reg_descr empty_regs_list[] = { }; @@ -174,37 +172,37 @@ static const struct __guc_mmio_reg_descr empty_regs_list[] = { } /* List of lists */ -static const struct __guc_mmio_reg_descr_group default_lists[] = { - MAKE_REGLIST(default_global_regs, PF, GLOBAL, 0), - MAKE_REGLIST(default_rc_class_regs, PF, ENGINE_CLASS, GUC_RENDER_CLASS), - MAKE_REGLIST(xe_lpd_rc_inst_regs, PF, ENGINE_INSTANCE, GUC_RENDER_CLASS), - MAKE_REGLIST(default_rc_class_regs, PF, ENGINE_CLASS, GUC_COMPUTE_CLASS), - MAKE_REGLIST(xe_lpd_rc_inst_regs, PF, ENGINE_INSTANCE, GUC_COMPUTE_CLASS), +static const struct __guc_mmio_reg_descr_group gen8_lists[] = { + MAKE_REGLIST(gen8_global_regs, PF, GLOBAL, 0), + MAKE_REGLIST(gen8_rc_class_regs, PF, ENGINE_CLASS, GUC_RENDER_CLASS), + MAKE_REGLIST(gen8_rc_inst_regs, PF, ENGINE_INSTANCE, GUC_RENDER_CLASS), + MAKE_REGLIST(gen8_rc_class_regs, PF, ENGINE_CLASS, GUC_COMPUTE_CLASS), + MAKE_REGLIST(gen8_rc_inst_regs, PF, ENGINE_INSTANCE, GUC_COMPUTE_CLASS), MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_VIDEO_CLASS), - MAKE_REGLIST(xe_lpd_vd_inst_regs, PF, ENGINE_INSTANCE, GUC_VIDEO_CLASS), + MAKE_REGLIST(gen8_vd_inst_regs, PF, ENGINE_INSTANCE, GUC_VIDEO_CLASS), MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_VIDEOENHANCE_CLASS), - MAKE_REGLIST(xe_lpd_vec_inst_regs, PF, ENGINE_INSTANCE, GUC_VIDEOENHANCE_CLASS), + MAKE_REGLIST(gen8_vec_inst_regs, PF, ENGINE_INSTANCE, GUC_VIDEOENHANCE_CLASS), MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_BLITTER_CLASS), - MAKE_REGLIST(xe_lpd_blt_inst_regs, PF, ENGINE_INSTANCE, GUC_BLITTER_CLASS), + MAKE_REGLIST(gen8_blt_inst_regs, PF, ENGINE_INSTANCE, GUC_BLITTER_CLASS), MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_GSC_OTHER_CLASS), - MAKE_REGLIST(xe_lpd_gsc_inst_regs, PF, ENGINE_INSTANCE, GUC_GSC_OTHER_CLASS), + MAKE_REGLIST(empty_regs_list, PF, ENGINE_INSTANCE, GUC_GSC_OTHER_CLASS), {} }; -static const struct __guc_mmio_reg_descr_group xe_lpd_lists[] = { - MAKE_REGLIST(xe_lpd_global_regs, PF, GLOBAL, 0), - MAKE_REGLIST(xe_lpd_rc_class_regs, PF, ENGINE_CLASS, GUC_RENDER_CLASS), - MAKE_REGLIST(xe_lpd_rc_inst_regs, PF, ENGINE_INSTANCE, GUC_RENDER_CLASS), - MAKE_REGLIST(xe_lpd_rc_class_regs, PF, ENGINE_CLASS, GUC_COMPUTE_CLASS), - MAKE_REGLIST(xe_lpd_rc_inst_regs, PF, ENGINE_INSTANCE, GUC_COMPUTE_CLASS), +static const struct __guc_mmio_reg_descr_group xe_lp_lists[] = { + MAKE_REGLIST(xe_lp_global_regs, PF, GLOBAL, 0), + MAKE_REGLIST(xe_lp_rc_class_regs, PF, ENGINE_CLASS, GUC_RENDER_CLASS), + MAKE_REGLIST(gen8_rc_inst_regs, PF, ENGINE_INSTANCE, GUC_RENDER_CLASS), + MAKE_REGLIST(xe_lp_rc_class_regs, PF, ENGINE_CLASS, GUC_COMPUTE_CLASS), + MAKE_REGLIST(gen8_rc_inst_regs, PF, ENGINE_INSTANCE, GUC_COMPUTE_CLASS), MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_VIDEO_CLASS), - MAKE_REGLIST(xe_lpd_vd_inst_regs, PF, ENGINE_INSTANCE, GUC_VIDEO_CLASS), - MAKE_REGLIST(xe_lpd_vec_class_regs, PF, ENGINE_CLASS, GUC_VIDEOENHANCE_CLASS), - MAKE_REGLIST(xe_lpd_vec_inst_regs, PF, ENGINE_INSTANCE, GUC_VIDEOENHANCE_CLASS), + MAKE_REGLIST(gen8_vd_inst_regs, PF, ENGINE_INSTANCE, GUC_VIDEO_CLASS), + MAKE_REGLIST(xe_lp_vec_class_regs, PF, ENGINE_CLASS, GUC_VIDEOENHANCE_CLASS), + MAKE_REGLIST(gen8_vec_inst_regs, PF, ENGINE_INSTANCE, GUC_VIDEOENHANCE_CLASS), MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_BLITTER_CLASS), - MAKE_REGLIST(xe_lpd_blt_inst_regs, PF, ENGINE_INSTANCE, GUC_BLITTER_CLASS), + MAKE_REGLIST(gen8_blt_inst_regs, PF, ENGINE_INSTANCE, GUC_BLITTER_CLASS), MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_GSC_OTHER_CLASS), - MAKE_REGLIST(xe_lpd_gsc_inst_regs, PF, ENGINE_INSTANCE, GUC_GSC_OTHER_CLASS), + MAKE_REGLIST(xe_lp_gsc_inst_regs, PF, ENGINE_INSTANCE, GUC_GSC_OTHER_CLASS), {} }; @@ -366,9 +364,9 @@ guc_capture_get_device_reglist(struct intel_guc *guc) const struct __guc_mmio_reg_descr_group *lists; if (GRAPHICS_VER(i915) >= 12) - lists = xe_lpd_lists; + lists = xe_lp_lists; else - lists = default_lists; + lists = gen8_lists; /* * For certain engine classes, there are slice and subslice -- 2.39.1 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [Intel-gfx] [PATCH v2 3/4] drm/i915/guc: Capture list naming clean up 2023-04-28 18:56 ` [Intel-gfx] [PATCH v2 3/4] drm/i915/guc: Capture list naming clean up John.C.Harrison @ 2023-05-03 17:54 ` Teres Alexis, Alan Previn 0 siblings, 0 replies; 10+ messages in thread From: Teres Alexis, Alan Previn @ 2023-05-03 17:54 UTC (permalink / raw) To: Harrison, John C, Intel-GFX@Lists.FreeDesktop.Org Cc: DRI-Devel@Lists.FreeDesktop.Org LGTM: Reviewed-by: Alan Previn <alan.previn.teres.alexis@intel.com> On Fri, 2023-04-28 at 11:56 -0700, John.C.Harrison@Intel.com wrote: > From: John Harrison <John.C.Harrison@Intel.com> > > Don't use 'xe_lp*' prefixes for register lists that are common with > Gen8. > > Don't add Xe only GSC registers to pre-Xe devices that don't > even have a GSC engine. > > Fix Xe_LP name. > > Don't use GEN9 as a prefix for register lists that contain all GEN8 > registers. > > Rename the 'default_' register list prefix to 'gen8_' as that is the > more accurate name. alan:snip ^ permalink raw reply [flat|nested] 10+ messages in thread
* [Intel-gfx] [PATCH v2 4/4] drm/i915/guc: Fix error capture for virtual engines 2023-04-28 18:56 [Intel-gfx] [PATCH v2 0/4] Improvements to GuC error capture John.C.Harrison ` (2 preceding siblings ...) 2023-04-28 18:56 ` [Intel-gfx] [PATCH v2 3/4] drm/i915/guc: Capture list naming clean up John.C.Harrison @ 2023-04-28 18:56 ` John.C.Harrison 2023-04-28 20:22 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Improvements to GuC error capture Patchwork ` (2 subsequent siblings) 6 siblings, 0 replies; 10+ messages in thread From: John.C.Harrison @ 2023-04-28 18:56 UTC (permalink / raw) To: Intel-GFX; +Cc: Alan Previn, DRI-Devel From: John Harrison <John.C.Harrison@Intel.com> GuC based register dumps in error capture logs were basically broken for virtual engines. This can be seen in igt@gem_exec_balancer@hang: [IGT] gem_exec_balancer: starting subtest hang [drm] GPU HANG: ecode 12:4:e1524110, in gem_exec_balanc [6388] [drm] GT0: GUC: No register capture node found for 0x1005 / 0xFEDC311D [drm] GPU HANG: ecode 12:4:00000000, in gem_exec_balanc [6388] [IGT] gem_exec_balancer: exiting, ret=0 The test causes a hang on both engines of a virtual engine context. The engine instance zero hang gets a valid error capture but the non-instance-zero hang does not. Fix that by scanning through the list of pending register captures when a hang notification for a virtual engine is received. That way, the hang can be assigned to the correct physical engine prior to starting the error capture process. So later on, when the error capture handler tries to find the engine register list, it looks for one on the correct engine. Also, sneak in a missing blank line before a comment in the node search code. v2: Fix null pointer deref on non-GuC platforms. Signed-off-by: John Harrison <John.C.Harrison@Intel.com> Reviewed-by: Alan Previn <alan.previn.teres.alexis@intel.com> --- .../gpu/drm/i915/gt/uc/intel_guc_capture.c | 31 ++++++++++++++++++ .../gpu/drm/i915/gt/uc/intel_guc_capture.h | 3 ++ .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 32 ++++++++++++++++--- drivers/gpu/drm/i915/i915_gpu_error.c | 11 +++++-- 4 files changed, 70 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c index 729a8fcf20dda..1def0b6467c79 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c @@ -1540,6 +1540,36 @@ void intel_guc_capture_free_node(struct intel_engine_coredump *ee) ee->guc_capture_node = NULL; } +bool intel_guc_capture_is_matching_engine(struct intel_gt *gt, + struct intel_context *ce, + struct intel_engine_cs *engine) +{ + struct __guc_capture_parsed_output *n; + struct intel_guc *guc; + + if (!gt || !ce || !engine) + return false; + + guc = >->uc.guc; + if (!guc->capture) + return false; + + /* + * Look for a matching GuC reported error capture node from + * the internal output link-list based on lrca, guc-id and engine + * identification. + */ + list_for_each_entry(n, &guc->capture->outlist, link) { + if (n->eng_inst == GUC_ID_TO_ENGINE_INSTANCE(engine->guc_id) && + n->eng_class == GUC_ID_TO_ENGINE_CLASS(engine->guc_id) && + n->guc_id == ce->guc_id.id && + (n->lrca & CTX_GTT_ADDRESS_MASK) == (ce->lrc.lrca & CTX_GTT_ADDRESS_MASK)) + return true; + } + + return false; +} + void intel_guc_capture_get_matching_node(struct intel_gt *gt, struct intel_engine_coredump *ee, struct intel_context *ce) @@ -1555,6 +1585,7 @@ void intel_guc_capture_get_matching_node(struct intel_gt *gt, return; GEM_BUG_ON(ee->guc_capture_node); + /* * Look for a matching GuC reported error capture node from * the internal output link-list based on lrca, guc-id and engine diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.h index fbd3713c7832d..302256d45431d 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.h +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.h @@ -11,6 +11,7 @@ struct drm_i915_error_state_buf; struct guc_gt_system_info; struct intel_engine_coredump; +struct intel_engine_cs; struct intel_context; struct intel_gt; struct intel_guc; @@ -20,6 +21,8 @@ int intel_guc_capture_print_engine_node(struct drm_i915_error_state_buf *m, const struct intel_engine_coredump *ee); void intel_guc_capture_get_matching_node(struct intel_gt *gt, struct intel_engine_coredump *ee, struct intel_context *ce); +bool intel_guc_capture_is_matching_engine(struct intel_gt *gt, struct intel_context *ce, + struct intel_engine_cs *engine); void intel_guc_capture_process(struct intel_guc *guc); int intel_guc_capture_getlist(struct intel_guc *guc, u32 owner, u32 type, u32 classid, void **outptr); diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c index ee3e8352637f2..b93fe27b4eaae 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c @@ -4697,13 +4697,37 @@ static void capture_error_state(struct intel_guc *guc, { struct intel_gt *gt = guc_to_gt(guc); struct drm_i915_private *i915 = gt->i915; - struct intel_engine_cs *engine = __context_to_physical_engine(ce); intel_wakeref_t wakeref; + intel_engine_mask_t engine_mask; + + if (intel_engine_is_virtual(ce->engine)) { + struct intel_engine_cs *e; + intel_engine_mask_t tmp, virtual_mask = ce->engine->mask; + + engine_mask = 0; + for_each_engine_masked(e, ce->engine->gt, virtual_mask, tmp) { + bool match = intel_guc_capture_is_matching_engine(gt, ce, e); + + if (match) { + intel_engine_set_hung_context(e, ce); + engine_mask |= e->mask; + atomic_inc(&i915->gpu_error.reset_engine_count[e->uabi_class]); + } + } + + if (!engine_mask) { + guc_warn(guc, "No matching physical engine capture for virtual engine context 0x%04X / %s", + ce->guc_id.id, ce->engine->name); + engine_mask = ~0U; + } + } else { + intel_engine_set_hung_context(ce->engine, ce); + engine_mask = ce->engine->mask; + atomic_inc(&i915->gpu_error.reset_engine_count[ce->engine->uabi_class]); + } - intel_engine_set_hung_context(engine, ce); with_intel_runtime_pm(&i915->runtime_pm, wakeref) - i915_capture_error_state(gt, engine->mask, CORE_DUMP_FLAG_IS_GUC_CAPTURE); - atomic_inc(&i915->gpu_error.reset_engine_count[engine->uabi_class]); + i915_capture_error_state(gt, engine_mask, CORE_DUMP_FLAG_IS_GUC_CAPTURE); } static void guc_context_replay(struct intel_context *ce) diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c index f020c0086fbcd..7360046b99455 100644 --- a/drivers/gpu/drm/i915/i915_gpu_error.c +++ b/drivers/gpu/drm/i915/i915_gpu_error.c @@ -808,10 +808,15 @@ static void err_print_gt_engines(struct drm_i915_error_state_buf *m, for (ee = gt->engine; ee; ee = ee->next) { const struct i915_vma_coredump *vma; - if (ee->guc_capture_node) - intel_guc_capture_print_engine_node(m, ee); - else + if (gt->uc && gt->uc->guc.is_guc_capture) { + if (ee->guc_capture_node) + intel_guc_capture_print_engine_node(m, ee); + else + err_printf(m, " Missing GuC capture node for %s\n", + ee->engine->name); + } else { error_print_engine(m, ee); + } err_printf(m, " hung: %u\n", ee->hung); err_printf(m, " engine reset count: %u\n", ee->reset_count); -- 2.39.1 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Improvements to GuC error capture 2023-04-28 18:56 [Intel-gfx] [PATCH v2 0/4] Improvements to GuC error capture John.C.Harrison ` (3 preceding siblings ...) 2023-04-28 18:56 ` [Intel-gfx] [PATCH v2 4/4] drm/i915/guc: Fix error capture for virtual engines John.C.Harrison @ 2023-04-28 20:22 ` Patchwork 2023-04-28 20:33 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2023-04-29 6:49 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork 6 siblings, 0 replies; 10+ messages in thread From: Patchwork @ 2023-04-28 20:22 UTC (permalink / raw) To: john.c.harrison; +Cc: intel-gfx == Series Details == Series: Improvements to GuC error capture URL : https://patchwork.freedesktop.org/series/117120/ State : warning == Summary == Error: dim checkpatch failed 2a554128572f drm/i915/guc: Don't capture Gen8 regs on Xe devices -:36: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses #36: FILE: drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c:38: +#define GEN9_GLOBAL \ + { GEN8_FAULT_TLB_DATA0, 0, 0, "GEN8_FAULT_TLB_DATA0" }, \ + { GEN8_FAULT_TLB_DATA1, 0, 0, "GEN8_FAULT_TLB_DATA1" } total: 1 errors, 0 warnings, 0 checks, 23 lines checked 1aec011e7466 drm/i915/guc: Consolidate duplicated capture list code 265a61afba27 drm/i915/guc: Capture list naming clean up -:31: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses #31: FILE: drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c:33: +#define COMMON_GEN8BASE_GLOBAL \ { ERROR_GEN6, 0, 0, "ERROR_GEN6" }, \ { DONE_REG, 0, 0, "DONE_REG" }, \ { HSW_GTT_CACHE_EN, 0, 0, "HSW_GTT_CACHE_EN" } -:37: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses #37: FILE: drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c:38: +#define GEN8_GLOBAL \ { GEN8_FAULT_TLB_DATA0, 0, 0, "GEN8_FAULT_TLB_DATA0" }, \ { GEN8_FAULT_TLB_DATA1, 0, 0, "GEN8_FAULT_TLB_DATA1" } total: 2 errors, 0 warnings, 0 checks, 174 lines checked 0dddb3302a00 drm/i915/guc: Fix error capture for virtual engines ^ permalink raw reply [flat|nested] 10+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for Improvements to GuC error capture 2023-04-28 18:56 [Intel-gfx] [PATCH v2 0/4] Improvements to GuC error capture John.C.Harrison ` (4 preceding siblings ...) 2023-04-28 20:22 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Improvements to GuC error capture Patchwork @ 2023-04-28 20:33 ` Patchwork 2023-04-29 6:49 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork 6 siblings, 0 replies; 10+ messages in thread From: Patchwork @ 2023-04-28 20:33 UTC (permalink / raw) To: john.c.harrison; +Cc: intel-gfx [-- Attachment #1: Type: text/plain, Size: 4163 bytes --] == Series Details == Series: Improvements to GuC error capture URL : https://patchwork.freedesktop.org/series/117120/ State : success == Summary == CI Bug Log - changes from CI_DRM_13074 -> Patchwork_117120v1 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117120v1/index.html Participating hosts (39 -> 36) ------------------------------ Missing (3): fi-kbl-soraka fi-snb-2520m fi-elk-e7500 Known issues ------------ Here are the changes found in Patchwork_117120v1 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@kms_chamelium_hpd@common-hpd-after-suspend: - fi-bsw-n3050: NOTRUN -> [SKIP][1] ([fdo#109271]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117120v1/fi-bsw-n3050/igt@kms_chamelium_hpd@common-hpd-after-suspend.html * igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence: - bat-dg2-11: NOTRUN -> [SKIP][2] ([i915#1845] / [i915#5354]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117120v1/bat-dg2-11/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence.html #### Possible fixes #### * igt@i915_selftest@live@execlists: - fi-bsw-n3050: [ABORT][3] ([i915#7911] / [i915#7913]) -> [PASS][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13074/fi-bsw-n3050/igt@i915_selftest@live@execlists.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117120v1/fi-bsw-n3050/igt@i915_selftest@live@execlists.html * igt@i915_selftest@live@requests: - {bat-mtlp-6}: [ABORT][5] ([i915#4983] / [i915#7920]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13074/bat-mtlp-6/igt@i915_selftest@live@requests.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117120v1/bat-mtlp-6/igt@i915_selftest@live@requests.html * igt@kms_pipe_crc_basic@nonblocking-crc@pipe-d-dp-1: - bat-dg2-8: [FAIL][7] ([i915#7932]) -> [PASS][8] +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13074/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc@pipe-d-dp-1.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117120v1/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc@pipe-d-dp-1.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845 [i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078 [i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983 [i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354 [i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367 [i915#6645]: https://gitlab.freedesktop.org/drm/intel/issues/6645 [i915#7699]: https://gitlab.freedesktop.org/drm/intel/issues/7699 [i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828 [i915#7911]: https://gitlab.freedesktop.org/drm/intel/issues/7911 [i915#7913]: https://gitlab.freedesktop.org/drm/intel/issues/7913 [i915#7920]: https://gitlab.freedesktop.org/drm/intel/issues/7920 [i915#7932]: https://gitlab.freedesktop.org/drm/intel/issues/7932 Build changes ------------- * Linux: CI_DRM_13074 -> Patchwork_117120v1 CI-20190529: 20190529 CI_DRM_13074: 29e53d3ca48aa5fcb6bcf8d1624c829b7838e242 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_7277: 1cb3507f3ff28d11bd5cfabcde576fe78ddab571 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_117120v1: 29e53d3ca48aa5fcb6bcf8d1624c829b7838e242 @ git://anongit.freedesktop.org/gfx-ci/linux ### Linux commits f8bcc661b30b drm/i915/guc: Fix error capture for virtual engines ceaddfc9c109 drm/i915/guc: Capture list naming clean up 6b7158bb7935 drm/i915/guc: Consolidate duplicated capture list code de24f07fdf8e drm/i915/guc: Don't capture Gen8 regs on Xe devices == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117120v1/index.html [-- Attachment #2: Type: text/html, Size: 4565 bytes --] ^ permalink raw reply [flat|nested] 10+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for Improvements to GuC error capture 2023-04-28 18:56 [Intel-gfx] [PATCH v2 0/4] Improvements to GuC error capture John.C.Harrison ` (5 preceding siblings ...) 2023-04-28 20:33 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork @ 2023-04-29 6:49 ` Patchwork 2023-05-03 18:25 ` John Harrison 6 siblings, 1 reply; 10+ messages in thread From: Patchwork @ 2023-04-29 6:49 UTC (permalink / raw) To: John Harrison; +Cc: intel-gfx [-- Attachment #1: Type: text/plain, Size: 13233 bytes --] == Series Details == Series: Improvements to GuC error capture URL : https://patchwork.freedesktop.org/series/117120/ State : failure == Summary == CI Bug Log - changes from CI_DRM_13074_full -> Patchwork_117120v1_full ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_117120v1_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_117120v1_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (7 -> 8) ------------------------------ Additional (1): shard-rkl0 Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_117120v1_full: ### IGT changes ### #### Possible regressions #### * igt@kms_flip@flip-vs-suspend-interruptible@a-dp1: - shard-apl: [PASS][1] -> [ABORT][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13074/shard-apl2/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117120v1/shard-apl7/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html #### Suppressed #### The following results come from untrusted machines, tests, or statuses. They do not affect the overall result. * igt@gem_ctx_freq@sysfs: - {shard-dg1}: [PASS][3] -> [FAIL][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13074/shard-dg1-13/igt@gem_ctx_freq@sysfs.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117120v1/shard-dg1-15/igt@gem_ctx_freq@sysfs.html * igt@gem_exec_schedule@wide@vcs1: - {shard-tglu}: [PASS][5] -> [INCOMPLETE][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13074/shard-tglu-10/igt@gem_exec_schedule@wide@vcs1.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117120v1/shard-tglu-2/igt@gem_exec_schedule@wide@vcs1.html Known issues ------------ Here are the changes found in Patchwork_117120v1_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt@i915_selftest@live@dmabuf: - shard-apl: [PASS][7] -> [DMESG-FAIL][8] ([i915#7562]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13074/shard-apl4/igt@i915_selftest@live@dmabuf.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117120v1/shard-apl4/igt@i915_selftest@live@dmabuf.html * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions: - shard-glk: [PASS][9] -> [FAIL][10] ([i915#2346]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13074/shard-glk6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117120v1/shard-glk3/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size: - shard-apl: [PASS][11] -> [FAIL][12] ([i915#2346]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13074/shard-apl3/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117120v1/shard-apl6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html * igt@kms_flip@2x-flip-vs-expired-vblank@bc-hdmi-a1-hdmi-a2: - shard-glk: [PASS][13] -> [FAIL][14] ([i915#79]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13074/shard-glk8/igt@kms_flip@2x-flip-vs-expired-vblank@bc-hdmi-a1-hdmi-a2.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117120v1/shard-glk4/igt@kms_flip@2x-flip-vs-expired-vblank@bc-hdmi-a1-hdmi-a2.html * igt@kms_flip@flip-vs-expired-vblank-interruptible@b-dp1: - shard-apl: [PASS][15] -> [FAIL][16] ([i915#79]) +2 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13074/shard-apl7/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-dp1.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117120v1/shard-apl4/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-dp1.html * igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-0-25@pipe-a-hdmi-a-1: - shard-snb: NOTRUN -> [SKIP][17] ([fdo#109271]) +33 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117120v1/shard-snb1/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-0-25@pipe-a-hdmi-a-1.html * igt@kms_setmode@basic@pipe-a-vga-1: - shard-snb: NOTRUN -> [FAIL][18] ([i915#5465]) +1 similar issue [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117120v1/shard-snb4/igt@kms_setmode@basic@pipe-a-vga-1.html #### Possible fixes #### * igt@gem_exec_balancer@hang: - {shard-dg1}: [DMESG-WARN][19] ([i915#8150]) -> [PASS][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13074/shard-dg1-17/igt@gem_exec_balancer@hang.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117120v1/shard-dg1-12/igt@gem_exec_balancer@hang.html * igt@gem_exec_fair@basic-pace-solo@rcs0: - shard-apl: [FAIL][21] ([i915#2842]) -> [PASS][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13074/shard-apl1/igt@gem_exec_fair@basic-pace-solo@rcs0.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117120v1/shard-apl3/igt@gem_exec_fair@basic-pace-solo@rcs0.html * igt@gem_exec_suspend@basic-s4-devices@lmem0: - {shard-dg1}: [ABORT][23] ([i915#7975] / [i915#8213]) -> [PASS][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13074/shard-dg1-14/igt@gem_exec_suspend@basic-s4-devices@lmem0.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117120v1/shard-dg1-17/igt@gem_exec_suspend@basic-s4-devices@lmem0.html * igt@gem_ppgtt@blt-vs-render-ctx0: - shard-snb: [DMESG-FAIL][25] ([i915#8295]) -> [PASS][26] [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13074/shard-snb6/igt@gem_ppgtt@blt-vs-render-ctx0.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117120v1/shard-snb1/igt@gem_ppgtt@blt-vs-render-ctx0.html * igt@i915_pm_rpm@modeset-non-lpsp-stress: - {shard-rkl}: [SKIP][27] ([i915#1397]) -> [PASS][28] [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13074/shard-rkl-7/igt@i915_pm_rpm@modeset-non-lpsp-stress.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117120v1/shard-rkl-1/igt@i915_pm_rpm@modeset-non-lpsp-stress.html * igt@kms_cursor_legacy@forked-bo@pipe-b: - {shard-rkl}: [INCOMPLETE][29] ([i915#8011]) -> [PASS][30] [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13074/shard-rkl-7/igt@kms_cursor_legacy@forked-bo@pipe-b.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117120v1/shard-rkl-1/igt@kms_cursor_legacy@forked-bo@pipe-b.html * igt@kms_plane_scaling@plane-upscale-with-modifiers-factor-0-25@pipe-b-hdmi-a-2: - {shard-rkl}: [ABORT][31] ([i915#8311]) -> [PASS][32] [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13074/shard-rkl-6/igt@kms_plane_scaling@plane-upscale-with-modifiers-factor-0-25@pipe-b-hdmi-a-2.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117120v1/shard-rkl-2/igt@kms_plane_scaling@plane-upscale-with-modifiers-factor-0-25@pipe-b-hdmi-a-2.html * igt@perf_pmu@idle@rcs0: - {shard-rkl}: [FAIL][33] ([i915#4349]) -> [PASS][34] [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13074/shard-rkl-7/igt@perf_pmu@idle@rcs0.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117120v1/shard-rkl-1/igt@perf_pmu@idle@rcs0.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285 [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289 [fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295 [fdo#109300]: https://bugs.freedesktop.org/show_bug.cgi?id=109300 [fdo#109307]: https://bugs.freedesktop.org/show_bug.cgi?id=109307 [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315 [fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506 [fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189 [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068 [fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614 [fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615 [fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072 [i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397 [i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825 [i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346 [i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527 [i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575 [i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587 [i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672 [i915#2681]: https://gitlab.freedesktop.org/drm/intel/issues/2681 [i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842 [i915#315]: https://gitlab.freedesktop.org/drm/intel/issues/315 [i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281 [i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291 [i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458 [i915#3591]: https://gitlab.freedesktop.org/drm/intel/issues/3591 [i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638 [i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689 [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708 [i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734 [i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886 [i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955 [i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070 [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077 [i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078 [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083 [i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098 [i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270 [i915#4349]: https://gitlab.freedesktop.org/drm/intel/issues/4349 [i915#4565]: https://gitlab.freedesktop.org/drm/intel/issues/4565 [i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579 [i915#4816]: https://gitlab.freedesktop.org/drm/intel/issues/4816 [i915#4833]: https://gitlab.freedesktop.org/drm/intel/issues/4833 [i915#4873]: https://gitlab.freedesktop.org/drm/intel/issues/4873 [i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176 [i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235 [i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286 [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533 [i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354 [i915#5465]: https://gitlab.freedesktop.org/drm/intel/issues/5465 [i915#5563]: https://gitlab.freedesktop.org/drm/intel/issues/5563 [i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095 [i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268 [i915#6301]: https://gitlab.freedesktop.org/drm/intel/issues/6301 [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658 [i915#6768]: https://gitlab.freedesktop.org/drm/intel/issues/6768 [i915#7116]: https://gitlab.freedesktop.org/drm/intel/issues/7116 [i915#7562]: https://gitlab.freedesktop.org/drm/intel/issues/7562 [i915#7711]: https://gitlab.freedesktop.org/drm/intel/issues/7711 [i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828 [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 [i915#7975]: https://gitlab.freedesktop.org/drm/intel/issues/7975 [i915#8011]: https://gitlab.freedesktop.org/drm/intel/issues/8011 [i915#8150]: https://gitlab.freedesktop.org/drm/intel/issues/8150 [i915#8213]: https://gitlab.freedesktop.org/drm/intel/issues/8213 [i915#8295]: https://gitlab.freedesktop.org/drm/intel/issues/8295 [i915#8311]: https://gitlab.freedesktop.org/drm/intel/issues/8311 Build changes ------------- * Linux: CI_DRM_13074 -> Patchwork_117120v1 CI-20190529: 20190529 CI_DRM_13074: 29e53d3ca48aa5fcb6bcf8d1624c829b7838e242 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_7277: 1cb3507f3ff28d11bd5cfabcde576fe78ddab571 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_117120v1: 29e53d3ca48aa5fcb6bcf8d1624c829b7838e242 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117120v1/index.html [-- Attachment #2: Type: text/html, Size: 10647 bytes --] ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for Improvements to GuC error capture 2023-04-29 6:49 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork @ 2023-05-03 18:25 ` John Harrison 0 siblings, 0 replies; 10+ messages in thread From: John Harrison @ 2023-05-03 18:25 UTC (permalink / raw) To: intel-gfx [-- Attachment #1: Type: text/plain, Size: 9876 bytes --] On 4/28/2023 23:49, Patchwork wrote: > Project List - Patchwork *Patch Details* > *Series:* Improvements to GuC error capture > *URL:* https://patchwork.freedesktop.org/series/117120/ > *State:* failure > *Details:* > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117120v1/index.html > > > CI Bug Log - changes from CI_DRM_13074_full -> Patchwork_117120v1_full > > > Summary > > *FAILURE* > > Serious unknown changes coming with Patchwork_117120v1_full absolutely > need to be > verified manually. > > If you think the reported changes have nothing to do with the changes > introduced in Patchwork_117120v1_full, please notify your bug team to > allow them > to document this new failure mode, which will reduce false positives > in CI. > > > Participating hosts (7 -> 8) > > Additional (1): shard-rkl0 > > > Possible new issues > > Here are the unknown changes that may have been introduced in > Patchwork_117120v1_full: > > > IGT changes > > > Possible regressions > > * igt@kms_flip@flip-vs-suspend-interruptible@a-dp1: > o shard-apl: PASS > <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13074/shard-apl2/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html> > -> ABORT > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117120v1/shard-apl7/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html> > Display code went boom. Not related to error capture with GuC submission. John. > * > > > Suppressed > > The following results come from untrusted machines, tests, or statuses. > They do not affect the overall result. > > * > > igt@gem_ctx_freq@sysfs: > > o {shard-dg1}: PASS > <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13074/shard-dg1-13/igt@gem_ctx_freq@sysfs.html> > -> FAIL > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117120v1/shard-dg1-15/igt@gem_ctx_freq@sysfs.html> > * > > igt@gem_exec_schedule@wide@vcs1: > > o {shard-tglu}: PASS > <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13074/shard-tglu-10/igt@gem_exec_schedule@wide@vcs1.html> > -> INCOMPLETE > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117120v1/shard-tglu-2/igt@gem_exec_schedule@wide@vcs1.html> > > > Known issues > > Here are the changes found in Patchwork_117120v1_full that come from > known issues: > > > IGT changes > > > Issues hit > > * > > igt@i915_selftest@live@dmabuf: > > o shard-apl: PASS > <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13074/shard-apl4/igt@i915_selftest@live@dmabuf.html> > -> DMESG-FAIL > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117120v1/shard-apl4/igt@i915_selftest@live@dmabuf.html> > (i915#7562 <https://gitlab.freedesktop.org/drm/intel/issues/7562>) > * > > igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions: > > o shard-glk: PASS > <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13074/shard-glk6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html> > -> FAIL > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117120v1/shard-glk3/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html> > (i915#2346 <https://gitlab.freedesktop.org/drm/intel/issues/2346>) > * > > igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size: > > o shard-apl: PASS > <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13074/shard-apl3/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html> > -> FAIL > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117120v1/shard-apl6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html> > (i915#2346 <https://gitlab.freedesktop.org/drm/intel/issues/2346>) > * > > igt@kms_flip@2x-flip-vs-expired-vblank@bc-hdmi-a1-hdmi-a2: > > o shard-glk: PASS > <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13074/shard-glk8/igt@kms_flip@2x-flip-vs-expired-vblank@bc-hdmi-a1-hdmi-a2.html> > -> FAIL > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117120v1/shard-glk4/igt@kms_flip@2x-flip-vs-expired-vblank@bc-hdmi-a1-hdmi-a2.html> > (i915#79 <https://gitlab.freedesktop.org/drm/intel/issues/79>) > * > > igt@kms_flip@flip-vs-expired-vblank-interruptible@b-dp1: > > o shard-apl: PASS > <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13074/shard-apl7/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-dp1.html> > -> FAIL > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117120v1/shard-apl4/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-dp1.html> > (i915#79 <https://gitlab.freedesktop.org/drm/intel/issues/79>) > +2 similar issues > * > > igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-0-25@pipe-a-hdmi-a-1: > > o shard-snb: NOTRUN -> SKIP > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117120v1/shard-snb1/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-0-25@pipe-a-hdmi-a-1.html> > (fdo#109271 > <https://bugs.freedesktop.org/show_bug.cgi?id=109271>) +33 > similar issues > * > > igt@kms_setmode@basic@pipe-a-vga-1: > > o shard-snb: NOTRUN -> FAIL > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117120v1/shard-snb4/igt@kms_setmode@basic@pipe-a-vga-1.html> > (i915#5465 > <https://gitlab.freedesktop.org/drm/intel/issues/5465>) +1 > similar issue > > > Possible fixes > > * > > igt@gem_exec_balancer@hang: > > o {shard-dg1}: DMESG-WARN > <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13074/shard-dg1-17/igt@gem_exec_balancer@hang.html> > (i915#8150 > <https://gitlab.freedesktop.org/drm/intel/issues/8150>) -> > PASS > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117120v1/shard-dg1-12/igt@gem_exec_balancer@hang.html> > * > > igt@gem_exec_fair@basic-pace-solo@rcs0: > > o shard-apl: FAIL > <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13074/shard-apl1/igt@gem_exec_fair@basic-pace-solo@rcs0.html> > (i915#2842 > <https://gitlab.freedesktop.org/drm/intel/issues/2842>) -> > PASS > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117120v1/shard-apl3/igt@gem_exec_fair@basic-pace-solo@rcs0.html> > * > > igt@gem_exec_suspend@basic-s4-devices@lmem0: > > o {shard-dg1}: ABORT > <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13074/shard-dg1-14/igt@gem_exec_suspend@basic-s4-devices@lmem0.html> > (i915#7975 > <https://gitlab.freedesktop.org/drm/intel/issues/7975> / > i915#8213 > <https://gitlab.freedesktop.org/drm/intel/issues/8213>) -> > PASS > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117120v1/shard-dg1-17/igt@gem_exec_suspend@basic-s4-devices@lmem0.html> > * > > igt@gem_ppgtt@blt-vs-render-ctx0: > > o shard-snb: DMESG-FAIL > <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13074/shard-snb6/igt@gem_ppgtt@blt-vs-render-ctx0.html> > (i915#8295 > <https://gitlab.freedesktop.org/drm/intel/issues/8295>) -> > PASS > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117120v1/shard-snb1/igt@gem_ppgtt@blt-vs-render-ctx0.html> > * > > igt@i915_pm_rpm@modeset-non-lpsp-stress: > > o {shard-rkl}: SKIP > <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13074/shard-rkl-7/igt@i915_pm_rpm@modeset-non-lpsp-stress.html> > (i915#1397 > <https://gitlab.freedesktop.org/drm/intel/issues/1397>) -> > PASS > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117120v1/shard-rkl-1/igt@i915_pm_rpm@modeset-non-lpsp-stress.html> > * > > igt@kms_cursor_legacy@forked-bo@pipe-b: > > o {shard-rkl}: INCOMPLETE > <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13074/shard-rkl-7/igt@kms_cursor_legacy@forked-bo@pipe-b.html> > (i915#8011 > <https://gitlab.freedesktop.org/drm/intel/issues/8011>) -> > PASS > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117120v1/shard-rkl-1/igt@kms_cursor_legacy@forked-bo@pipe-b.html> > * > > igt@kms_plane_scaling@plane-upscale-with-modifiers-factor-0-25@pipe-b-hdmi-a-2: > > o {shard-rkl}: ABORT > <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13074/shard-rkl-6/igt@kms_plane_scaling@plane-upscale-with-modifiers-factor-0-25@pipe-b-hdmi-a-2.html> > (i915#8311 > <https://gitlab.freedesktop.org/drm/intel/issues/8311>) -> > PASS > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117120v1/shard-rkl-2/igt@kms_plane_scaling@plane-upscale-with-modifiers-factor-0-25@pipe-b-hdmi-a-2.html> > * > > igt@perf_pmu@idle@rcs0: > > o {shard-rkl}: FAIL > <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13074/shard-rkl-7/igt@perf_pmu@idle@rcs0.html> > (i915#4349 > <https://gitlab.freedesktop.org/drm/intel/issues/4349>) -> > PASS > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117120v1/shard-rkl-1/igt@perf_pmu@idle@rcs0.html> > > {name}: This element is suppressed. This means it is ignored when > computing > the status of the difference (SUCCESS, WARNING, or FAILURE). > > > Build changes > > * Linux: CI_DRM_13074 -> Patchwork_117120v1 > > CI-20190529: 20190529 > CI_DRM_13074: 29e53d3ca48aa5fcb6bcf8d1624c829b7838e242 @ > git://anongit.freedesktop.org/gfx-ci/linux > IGT_7277: 1cb3507f3ff28d11bd5cfabcde576fe78ddab571 @ > https://gitlab.freedesktop.org/drm/igt-gpu-tools.git > Patchwork_117120v1: 29e53d3ca48aa5fcb6bcf8d1624c829b7838e242 @ > git://anongit.freedesktop.org/gfx-ci/linux > piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ > git://anongit.freedesktop.org/piglit > [-- Attachment #2: Type: text/html, Size: 14159 bytes --] ^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2023-05-03 18:30 UTC | newest] Thread overview: 10+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2023-04-28 18:56 [Intel-gfx] [PATCH v2 0/4] Improvements to GuC error capture John.C.Harrison 2023-04-28 18:56 ` [Intel-gfx] [PATCH v2 1/4] drm/i915/guc: Don't capture Gen8 regs on Xe devices John.C.Harrison 2023-04-28 18:56 ` [Intel-gfx] [PATCH v2 2/4] drm/i915/guc: Consolidate duplicated capture list code John.C.Harrison 2023-04-28 18:56 ` [Intel-gfx] [PATCH v2 3/4] drm/i915/guc: Capture list naming clean up John.C.Harrison 2023-05-03 17:54 ` Teres Alexis, Alan Previn 2023-04-28 18:56 ` [Intel-gfx] [PATCH v2 4/4] drm/i915/guc: Fix error capture for virtual engines John.C.Harrison 2023-04-28 20:22 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Improvements to GuC error capture Patchwork 2023-04-28 20:33 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2023-04-29 6:49 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork 2023-05-03 18:25 ` John Harrison
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