From: Anusha Srivatsa <anusha.srivatsa@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH 1/5] drm/i915/adlp: s/ADLP/ALDERLAKE_P for display and graphics step
Date: Tue, 30 May 2023 11:55:25 -0700 [thread overview]
Message-ID: <20230530185529.3378520-2-anusha.srivatsa@intel.com> (raw)
In-Reply-To: <20230530185529.3378520-1-anusha.srivatsa@intel.com>
Driver refers to the platfrom Alderlake P as ADLP in places
and ALDERLAKE_P in some. Making the consistent change
to avoid confusion of the right naming convention for
the platform.
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 2 +-
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 2 +-
drivers/gpu/drm/i915/display/intel_psr.c | 8 ++++----
drivers/gpu/drm/i915/display/skl_universal_plane.c | 4 ++--
drivers/gpu/drm/i915/i915_drv.h | 4 ++--
5 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 6bed75f1541a..013678caaca8 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -3541,7 +3541,7 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
} else if (IS_ALDERLAKE_P(dev_priv)) {
dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
/* Wa_22011320316:adl-p[a0] */
- if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
+ if (IS_ALDERLAKE_P_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
dev_priv->display.cdclk.table = adlp_a_step_cdclk_table;
else if (IS_ADLP_RPLU(dev_priv))
dev_priv->display.cdclk.table = rplu_cdclk_table;
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 6b2d8a1e2aa9..81f3ce5a0a1e 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -3781,7 +3781,7 @@ static void adlp_cmtg_clock_gating_wa(struct drm_i915_private *i915, struct inte
{
u32 val;
- if (!IS_ADLP_DISPLAY_STEP(i915, STEP_A0, STEP_B0) ||
+ if (!IS_ALDERLAKE_P_DISPLAY_STEP(i915, STEP_A0, STEP_B0) ||
pll->info->id != DPLL_ID_ICL_DPLL0)
return;
/*
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index ea0389c5f656..c25457dae315 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -639,7 +639,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
}
/* Wa_22012278275:adl-p */
- if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_E0)) {
+ if (IS_ALDERLAKE_P_DISPLAY_STEP(dev_priv, STEP_A0, STEP_E0)) {
static const u8 map[] = {
2, /* 5 lines */
1, /* 6 lines */
@@ -807,7 +807,7 @@ tgl_dc3co_exitline_compute_config(struct intel_dp *intel_dp,
return;
/* Wa_16011303918:adl-p */
- if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
+ if (IS_ALDERLAKE_P_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
return;
/*
@@ -975,7 +975,7 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
return false;
}
- if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) {
+ if (IS_ALDERLAKE_P_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) {
drm_dbg_kms(&dev_priv->drm, "PSR2 not completely functional in this stepping\n");
return false;
}
@@ -1033,7 +1033,7 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
/* Wa_16011303918:adl-p */
if (crtc_state->vrr.enable &&
- IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) {
+ IS_ALDERLAKE_P_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) {
drm_dbg_kms(&dev_priv->drm,
"PSR2 not enabled, not compatible with HW stepping + VRR\n");
return false;
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 36070d86550f..2019e0a87bd3 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -2174,7 +2174,7 @@ static bool skl_plane_has_rc_ccs(struct drm_i915_private *i915,
return false;
/* Wa_22011186057 */
- if (IS_ADLP_DISPLAY_STEP(i915, STEP_A0, STEP_B0))
+ if (IS_ALDERLAKE_P_DISPLAY_STEP(i915, STEP_A0, STEP_B0))
return false;
if (DISPLAY_VER(i915) >= 11)
@@ -2200,7 +2200,7 @@ static bool gen12_plane_has_mc_ccs(struct drm_i915_private *i915,
return false;
/* Wa_22011186057 */
- if (IS_ADLP_DISPLAY_STEP(i915, STEP_A0, STEP_B0))
+ if (IS_ALDERLAKE_P_DISPLAY_STEP(i915, STEP_A0, STEP_B0))
return false;
/* Wa_14013215631 */
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f1205ed3ba71..1a50b8b2f00d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -669,11 +669,11 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
(IS_ALDERLAKE_S(__i915) && \
IS_GRAPHICS_STEP(__i915, since, until))
-#define IS_ADLP_DISPLAY_STEP(__i915, since, until) \
+#define IS_ALDERLAKE_P_DISPLAY_STEP(__i915, since, until) \
(IS_ALDERLAKE_P(__i915) && \
IS_DISPLAY_STEP(__i915, since, until))
-#define IS_ADLP_GRAPHICS_STEP(__i915, since, until) \
+#define IS_ALDERLAKE_P_GRAPHICS_STEP(__i915, since, until) \
(IS_ALDERLAKE_P(__i915) && \
IS_GRAPHICS_STEP(__i915, since, until))
--
2.25.1
next prev parent reply other threads:[~2023-05-30 18:54 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-30 18:55 [Intel-gfx] [PATCH 0/5] s/ADL/ALDERLAKE Anusha Srivatsa
2023-05-30 18:55 ` Anusha Srivatsa [this message]
2023-06-05 15:13 ` [Intel-gfx] [PATCH 1/5] drm/i915/adlp: s/ADLP/ALDERLAKE_P for display and graphics step Jani Nikula
2023-06-05 18:20 ` Srivatsa, Anusha
2023-06-05 18:29 ` Jani Nikula
2023-06-05 20:40 ` Srivatsa, Anusha
2023-05-30 18:55 ` [Intel-gfx] [PATCH 2/5] drm/i915/rplp: s/ADLP/ALDERLAKE_P for RPLP defines Anusha Srivatsa
2023-06-05 15:16 ` Jani Nikula
2023-05-30 18:55 ` [Intel-gfx] [PATCH 3/5] drm/i915/rplu: s/ADLP/ALDERLAKE_P in RPLU defines Anusha Srivatsa
2023-05-30 18:55 ` [Intel-gfx] [PATCH 4/5] drm/i915/adln: s/ADLP/ALDERLAKE_P in ADLN defines Anusha Srivatsa
2023-05-30 18:55 ` [Intel-gfx] [PATCH 5/5] drm/i915/adls: s/ADLS/ALDERLAKE_S in platform and subplatform defines Anusha Srivatsa
2023-05-31 16:26 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for s/ADL/ALDERLAKE Patchwork
2023-05-31 16:26 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-05-31 16:40 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-06-02 4:35 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2023-06-05 15:19 ` [Intel-gfx] [PATCH 0/5] s/ADL/ALDERLAKE Jani Nikula
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