From: Anusha Srivatsa <anusha.srivatsa@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH 3/5] drm/i915/rplu: s/ADLP/ALDERLAKE_P in RPLU defines
Date: Tue, 30 May 2023 11:55:27 -0700 [thread overview]
Message-ID: <20230530185529.3378520-4-anusha.srivatsa@intel.com> (raw)
In-Reply-To: <20230530185529.3378520-1-anusha.srivatsa@intel.com>
Follow consistent naming convention. Replace ADLP with
ALDERLAKE_P
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 013678caaca8..4420de5ffe9c 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -3543,7 +3543,7 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
/* Wa_22011320316:adl-p[a0] */
if (IS_ALDERLAKE_P_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
dev_priv->display.cdclk.table = adlp_a_step_cdclk_table;
- else if (IS_ADLP_RPLU(dev_priv))
+ else if (IS_ALDERLAKE_P_RPLU(dev_priv))
dev_priv->display.cdclk.table = rplu_cdclk_table;
else
dev_priv->display.cdclk.table = adlp_cdclk_table;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 43414cdc137c..d400cecb318b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -583,7 +583,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_N)
#define IS_ALDERLAKE_P_RPLP(i915) \
IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPL)
-#define IS_ADLP_RPLU(i915) \
+#define IS_ALDERLAKE_P_RPLU(i915) \
IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPLU)
#define IS_HSW_EARLY_SDV(i915) (IS_HASWELL(i915) && \
(INTEL_DEVID(i915) & 0xFF00) == 0x0C00)
--
2.25.1
next prev parent reply other threads:[~2023-05-30 18:54 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-30 18:55 [Intel-gfx] [PATCH 0/5] s/ADL/ALDERLAKE Anusha Srivatsa
2023-05-30 18:55 ` [Intel-gfx] [PATCH 1/5] drm/i915/adlp: s/ADLP/ALDERLAKE_P for display and graphics step Anusha Srivatsa
2023-06-05 15:13 ` Jani Nikula
2023-06-05 18:20 ` Srivatsa, Anusha
2023-06-05 18:29 ` Jani Nikula
2023-06-05 20:40 ` Srivatsa, Anusha
2023-05-30 18:55 ` [Intel-gfx] [PATCH 2/5] drm/i915/rplp: s/ADLP/ALDERLAKE_P for RPLP defines Anusha Srivatsa
2023-06-05 15:16 ` Jani Nikula
2023-05-30 18:55 ` Anusha Srivatsa [this message]
2023-05-30 18:55 ` [Intel-gfx] [PATCH 4/5] drm/i915/adln: s/ADLP/ALDERLAKE_P in ADLN defines Anusha Srivatsa
2023-05-30 18:55 ` [Intel-gfx] [PATCH 5/5] drm/i915/adls: s/ADLS/ALDERLAKE_S in platform and subplatform defines Anusha Srivatsa
2023-05-31 16:26 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for s/ADL/ALDERLAKE Patchwork
2023-05-31 16:26 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-05-31 16:40 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-06-02 4:35 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2023-06-05 15:19 ` [Intel-gfx] [PATCH 0/5] s/ADL/ALDERLAKE Jani Nikula
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