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* [Intel-gfx] [PATCH] drm/i915: Extend Wa_14015795083 platforms
@ 2023-06-02 22:55 Matt Roper
  2023-06-03  1:03 ` [Intel-gfx] ✗ Fi.CI.DOCS: warning for " Patchwork
  2023-06-03  1:18 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
  0 siblings, 2 replies; 4+ messages in thread
From: Matt Roper @ 2023-06-02 22:55 UTC (permalink / raw)
  To: intel-gfx; +Cc: matthew.d.roper

This workaround was already implemented for DG2, PVC, and some steppings
of MTL, but the workaround database has now been updated to extend this
workaround to TGL, RKL, DG1, and ADL.

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 4d2dece96011..95d6f23b2605 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1485,6 +1485,9 @@ gen12_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
 
 	/* Wa_14011059788:tgl,rkl,adl-s,dg1,adl-p */
 	wa_mcr_write_or(wal, GEN10_DFR_RATIO_EN_AND_CHICKEN, DFR_DISABLE);
+
+	/* Wa_14015795083 */
+	wa_write_clr(wal, GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE);
 }
 
 static void
-- 
2.40.1


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end of thread, other threads:[~2023-06-03  3:27 UTC | newest]

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2023-06-02 22:55 [Intel-gfx] [PATCH] drm/i915: Extend Wa_14015795083 platforms Matt Roper
2023-06-03  1:03 ` [Intel-gfx] ✗ Fi.CI.DOCS: warning for " Patchwork
2023-06-03  1:18 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2023-06-03  3:27   ` Matt Roper

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