[Intel-gfx] [PATCH 00/11] Replace acronym with full platform name in defines.

[Intel-gfx] [PATCH 00/11] Replace acronym with full platform name in defines.

[Dnyaneshwar Bhadane]

Replace all occurences of ADL with ALDERLAKE, TGL with TIGERLAKE, 
MTL with METEORLAKE, RKL with ROCKETLAKE, JSL with JASPERLAKE, 
KBL with KABYLAKE and SKL with SKYLAKE in platform and subplatform
defines. This way there is a consistent pattern to how platforms 
are referred. While the change is minor and could be combined to 
have lesser patches, splitting to per subpaltform for easier 
cherrypicks, if needed.


Anusha Srivatsa (5):
  drm/i915/adlp: s/ADLP/ALDERLAKE_P for display and graphics step
  drm/i915/rplp: s/ADLP/ALDERLAKE_P for RPLP defines
  drm/i915/adln: s/ADLP/ALDERLAKE_P in ADLN defines
  drm/i915/adls: s/ADLS/ALDERLAKE_S in platform and subplatform defines
  drm/i915/rplu: s/ADLP/ALDERLAKE_P in RPLU defines

Dnyaneshwar Bhadane (6):
  drm/i915/TGL: s/TGL/TIGERLAKE for platform/subplatform defines
  drm/i915/MTL: s/MTL/METEORLAKE for platform/subplatform defines
  drm/i915/TGL: s/RKL/ROCKETLAKE for platform/subplatform defines
  drm/i915/JSL: s/JSL/JASPERLAKE for platform/subplatform defines
  drm/i915/KBL: s/KBL/KABYLAKE for platform/subplatform defines
  drm/i915/SKL: s/SKL/SKYLAKE for platform/subplatform defines

 drivers/gpu/drm/i915/display/icl_dsi.c        |  4 +-
 drivers/gpu/drm/i915/display/intel_cdclk.c    |  8 +--
 .../gpu/drm/i915/display/intel_combo_phy.c    |  6 +-
 drivers/gpu/drm/i915/display/intel_ddi.c      |  6 +-
 .../drm/i915/display/intel_ddi_buf_trans.c    | 10 +--
 drivers/gpu/drm/i915/display/intel_display.c  |  6 +-
 .../drm/i915/display/intel_display_device.c   |  2 +-
 .../drm/i915/display/intel_display_power.c    |  2 +-
 drivers/gpu/drm/i915/display/intel_dp.c       |  2 +-
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 20 +++---
 drivers/gpu/drm/i915/display/intel_fbc.c      |  2 +-
 drivers/gpu/drm/i915/display/intel_hdmi.c     |  2 +-
 drivers/gpu/drm/i915/display/intel_pmdemand.c |  2 +-
 drivers/gpu/drm/i915/display/intel_psr.c      | 20 +++---
 .../drm/i915/display/skl_universal_plane.c    | 10 +--
 drivers/gpu/drm/i915/gem/i915_gem_object.c    |  2 +-
 drivers/gpu/drm/i915/gt/gen8_engine_cs.c      | 10 +--
 drivers/gpu/drm/i915/gt/intel_engine_cs.c     |  2 +-
 .../drm/i915/gt/intel_execlists_submission.c  |  2 +-
 drivers/gpu/drm/i915/gt/intel_gt_mcr.c        |  4 +-
 drivers/gpu/drm/i915/gt/intel_lrc.c           |  4 +-
 drivers/gpu/drm/i915/gt/intel_rc6.c           |  2 +-
 drivers/gpu/drm/i915/gt/intel_sseu.c          |  2 +-
 drivers/gpu/drm/i915/gt/intel_workarounds.c   | 54 ++++++++--------
 drivers/gpu/drm/i915/gt/uc/intel_guc.c        |  4 +-
 .../gpu/drm/i915/gt/uc/intel_guc_hwconfig.c   |  2 +-
 .../gpu/drm/i915/gt/uc/intel_guc_submission.c |  4 +-
 drivers/gpu/drm/i915/gt/uc/intel_uc.c         |  2 +-
 drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c      |  2 +-
 drivers/gpu/drm/i915/i915_drv.h               | 64 +++++++++----------
 drivers/gpu/drm/i915/i915_perf.c              |  4 +-
 drivers/gpu/drm/i915/intel_clock_gating.c     |  4 +-
 drivers/gpu/drm/i915/intel_step.c             | 10 +--
 drivers/gpu/drm/i915/soc/intel_pch.c          |  6 +-
 34 files changed, 143 insertions(+), 143 deletions(-)

-- 
2.34.1

[Intel-gfx] [PATCH 01/11] drm/i915/TGL: s/TGL/TIGERLAKE for platform/subplatform defines

[Dnyaneshwar Bhadane]

Follow consistent naming convention. Replace TGL with
TIGERLAKE.

Signed-off-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c | 2 +-
 drivers/gpu/drm/i915/display/skl_universal_plane.c | 2 +-
 drivers/gpu/drm/i915/i915_drv.h                    | 4 ++--
 drivers/gpu/drm/i915/intel_step.c                  | 2 +-
 4 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
index b7d20485bde5..9e34cc103aeb 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
@@ -1390,7 +1390,7 @@ tgl_get_combo_buf_trans_dp(struct intel_encoder *encoder,
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 
 	if (crtc_state->port_clock > 270000) {
-		if (IS_TGL_UY(dev_priv)) {
+		if (IS_TIGERLAKE_UY(dev_priv)) {
 			return intel_get_buf_trans(&tgl_uy_combo_phy_trans_dp_hbr2,
 						   n_entries);
 		} else {
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 6b01a0b68b97..26def9cb86e4 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -2196,7 +2196,7 @@ static bool gen12_plane_has_mc_ccs(struct drm_i915_private *i915,
 
 	/* Wa_14010477008 */
 	if (IS_DG1(i915) || IS_ROCKETLAKE(i915) ||
-	    IS_TGL_DISPLAY_STEP(i915, STEP_A0, STEP_D0))
+	    IS_TIGERLAKE_DISPLAY_STEP(i915, STEP_A0, STEP_D0))
 		return false;
 
 	/* Wa_22011186057 */
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b4cf6f0f636d..0f30dc890209 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -647,7 +647,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define IS_ICL_WITH_PORT_F(i915) \
 	IS_SUBPLATFORM(i915, INTEL_ICELAKE, INTEL_SUBPLATFORM_PORTF)
 
-#define IS_TGL_UY(i915) \
+#define IS_TIGERLAKE_UY(i915) \
 	IS_SUBPLATFORM(i915, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_UY)
 
 #define IS_SKL_GRAPHICS_STEP(p, since, until) (IS_SKYLAKE(p) && IS_GRAPHICS_STEP(p, since, until))
@@ -662,7 +662,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define IS_JSL_EHL_DISPLAY_STEP(p, since, until) \
 	(IS_JSL_EHL(p) && IS_DISPLAY_STEP(p, since, until))
 
-#define IS_TGL_DISPLAY_STEP(__i915, since, until) \
+#define IS_TIGERLAKE_DISPLAY_STEP(__i915, since, until) \
 	(IS_TIGERLAKE(__i915) && \
 	 IS_DISPLAY_STEP(__i915, since, until))
 
diff --git a/drivers/gpu/drm/i915/intel_step.c b/drivers/gpu/drm/i915/intel_step.c
index 8a9ff6227e53..67054c87bb5f 100644
--- a/drivers/gpu/drm/i915/intel_step.c
+++ b/drivers/gpu/drm/i915/intel_step.c
@@ -213,7 +213,7 @@ void intel_step_init(struct drm_i915_private *i915)
 	} else if (IS_ROCKETLAKE(i915)) {
 		revids = rkl_revids;
 		size = ARRAY_SIZE(rkl_revids);
-	} else if (IS_TGL_UY(i915)) {
+	} else if (IS_TIGERLAKE_UY(i915)) {
 		revids = tgl_uy_revids;
 		size = ARRAY_SIZE(tgl_uy_revids);
 	} else if (IS_TIGERLAKE(i915)) {
-- 
2.34.1

[Intel-gfx] [PATCH 02/11] drm/i915/MTL: s/MTL/METEORLAKE for platform/subplatform defines

[Dnyaneshwar Bhadane]

Follow consistent naming convention. Replace MTL with
METEORLAKE

Signed-off-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>
---
 drivers/gpu/drm/i915/display/intel_fbc.c      |  2 +-
 drivers/gpu/drm/i915/display/intel_pmdemand.c |  2 +-
 drivers/gpu/drm/i915/display/intel_psr.c      | 10 ++---
 .../drm/i915/display/skl_universal_plane.c    |  4 +-
 drivers/gpu/drm/i915/gt/gen8_engine_cs.c      |  8 ++--
 drivers/gpu/drm/i915/gt/intel_engine_cs.c     |  2 +-
 .../drm/i915/gt/intel_execlists_submission.c  |  2 +-
 drivers/gpu/drm/i915/gt/intel_gt_mcr.c        |  4 +-
 drivers/gpu/drm/i915/gt/intel_lrc.c           |  4 +-
 drivers/gpu/drm/i915/gt/intel_rc6.c           |  2 +-
 drivers/gpu/drm/i915/gt/intel_workarounds.c   | 44 +++++++++----------
 drivers/gpu/drm/i915/gt/uc/intel_guc.c        |  4 +-
 .../gpu/drm/i915/gt/uc/intel_guc_submission.c |  4 +-
 drivers/gpu/drm/i915/i915_drv.h               |  6 +--
 drivers/gpu/drm/i915/i915_perf.c              |  4 +-
 15 files changed, 51 insertions(+), 51 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index 7f8b2d7713c7..6358a8b26172 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -1093,7 +1093,7 @@ static int intel_fbc_check_plane(struct intel_atomic_state *state,
 
 	/* Wa_14016291713 */
 	if ((IS_DISPLAY_VER(i915, 12, 13) ||
-	     IS_MTL_DISPLAY_STEP(i915, STEP_A0, STEP_C0)) &&
+	     IS_METEORLAKE_DISPLAY_STEP(i915, STEP_A0, STEP_C0)) &&
 	    crtc_state->has_psr) {
 		plane_state->no_fbc_reason = "PSR1 enabled (Wa_14016291713)";
 		return 0;
diff --git a/drivers/gpu/drm/i915/display/intel_pmdemand.c b/drivers/gpu/drm/i915/display/intel_pmdemand.c
index f7608d363634..8c3158b188ef 100644
--- a/drivers/gpu/drm/i915/display/intel_pmdemand.c
+++ b/drivers/gpu/drm/i915/display/intel_pmdemand.c
@@ -92,7 +92,7 @@ int intel_pmdemand_init(struct drm_i915_private *i915)
 				     &pmdemand_state->base,
 				     &intel_pmdemand_funcs);
 
-	if (IS_MTL_DISPLAY_STEP(i915, STEP_A0, STEP_C0))
+	if (IS_METEORLAKE_DISPLAY_STEP(i915, STEP_A0, STEP_C0))
 		/* Wa_14016740474 */
 		intel_de_rmw(i915, XELPD_CHICKEN_DCPR_3, 0, DMD_RSP_TIMEOUT_DISABLE);
 
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index d58ed9b62e67..06b464229efe 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1247,7 +1247,7 @@ static void wm_optimization_wa(struct intel_dp *intel_dp,
 	bool set_wa_bit = false;
 
 	/* Wa_14015648006 */
-	if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
+	if (IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
 	    IS_DISPLAY_VER(dev_priv, 11, 13))
 		set_wa_bit |= crtc_state->wm_level_disabled;
 
@@ -1320,7 +1320,7 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
 		 * All supported adlp panels have 1-based X granularity, this may
 		 * cause issues if non-supported panels are used.
 		 */
-		if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
+		if (IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
 			intel_de_rmw(dev_priv, MTL_CHICKEN_TRANS(cpu_transcoder), 0,
 				     ADLP_1_BASED_X_GRANULARITY);
 		else if (IS_ALDERLAKE_P(dev_priv))
@@ -1328,7 +1328,7 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
 				     ADLP_1_BASED_X_GRANULARITY);
 
 		/* Wa_16012604467:adlp,mtl[a0,b0] */
-		if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
+		if (IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
 			intel_de_rmw(dev_priv,
 				     MTL_CLKGATE_DIS_TRANS(cpu_transcoder), 0,
 				     MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS);
@@ -1489,7 +1489,7 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
 
 	if (intel_dp->psr.psr2_enabled) {
 		/* Wa_16012604467:adlp,mtl[a0,b0] */
-		if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
+		if (IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
 			intel_de_rmw(dev_priv,
 				     MTL_CLKGATE_DIS_TRANS(cpu_transcoder),
 				     MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS, 0);
@@ -1963,7 +1963,7 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
 		goto skip_sel_fetch_set_loop;
 
 	/* Wa_14014971492 */
-	if ((IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
+	if ((IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
 	     IS_ALDERLAKE_P(dev_priv) || IS_TIGERLAKE(dev_priv)) &&
 	    crtc_state->splitter.enable)
 		pipe_clip.y1 = 0;
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 26def9cb86e4..25b06ced9ce7 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -2169,8 +2169,8 @@ static bool skl_plane_has_rc_ccs(struct drm_i915_private *i915,
 				 enum pipe pipe, enum plane_id plane_id)
 {
 	/* Wa_14017240301 */
-	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
-	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
+	if (IS_METEORLAKE_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
+	    IS_METEORLAKE_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
 		return false;
 
 	/* Wa_22011186057 */
diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
index 23857cc08eca..eb72610a8588 100644
--- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
@@ -180,8 +180,8 @@ u32 *gen12_emit_aux_table_inv(struct intel_gt *gt, u32 *cs, const i915_reg_t inv
 static int mtl_dummy_pipe_control(struct i915_request *rq)
 {
 	/* Wa_14016712196 */
-	if (IS_MTL_GRAPHICS_STEP(rq->engine->i915, M, STEP_A0, STEP_B0) ||
-	    IS_MTL_GRAPHICS_STEP(rq->engine->i915, P, STEP_A0, STEP_B0)) {
+	if (IS_METEORLAKE_GRAPHICS_STEP(rq->engine->i915, M, STEP_A0, STEP_B0) ||
+	    IS_METEORLAKE_GRAPHICS_STEP(rq->engine->i915, P, STEP_A0, STEP_B0)) {
 		u32 *cs;
 
 		/* dummy PIPE_CONTROL + depth flush */
@@ -765,8 +765,8 @@ u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
 		     PIPE_CONTROL_FLUSH_ENABLE);
 
 	/* Wa_14016712196 */
-	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
-	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
+	if (IS_METEORLAKE_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
+	    IS_METEORLAKE_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
 		/* dummy PIPE_CONTROL + depth flush */
 		cs = gen12_emit_pipe_control(cs, 0,
 					     PIPE_CONTROL_DEPTH_CACHE_FLUSH, 0);
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 0aff5bb13c53..f9af6b1a7c01 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -1616,7 +1616,7 @@ static int __intel_engine_stop_cs(struct intel_engine_cs *engine,
 	 * Wa_22011802037: Prior to doing a reset, ensure CS is
 	 * stopped, set ring stop bit and prefetch disable bit to halt CS
 	 */
-	if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
+	if (IS_METEORLAKE_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
 	    (GRAPHICS_VER(engine->i915) >= 11 &&
 	    GRAPHICS_VER_FULL(engine->i915) < IP_VER(12, 70)))
 		intel_uncore_write_fw(uncore, RING_MODE_GEN7(engine->mmio_base),
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 2ebd937f3b4c..901ecd59afbc 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -3001,7 +3001,7 @@ static void execlists_reset_prepare(struct intel_engine_cs *engine)
 	 * Wa_22011802037: In addition to stopping the cs, we need
 	 * to wait for any pending mi force wakeups
 	 */
-	if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
+	if (IS_METEORLAKE_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
 	    (GRAPHICS_VER(engine->i915) >= 11 &&
 	    GRAPHICS_VER_FULL(engine->i915) < IP_VER(12, 70)))
 		intel_engine_wait_for_pending_mi_fw(engine);
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
index 0b414eae1683..1dc7180eeb27 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
@@ -166,8 +166,8 @@ void intel_gt_mcr_init(struct intel_gt *gt)
 		gt->steering_table[OADDRM] = xelpmp_oaddrm_steering_table;
 	} else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) {
 		/* Wa_14016747170 */
-		if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
-		    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
+		if (IS_METEORLAKE_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
+		    IS_METEORLAKE_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
 			fuse = REG_FIELD_GET(MTL_GT_L3_EXC_MASK,
 					     intel_uncore_read(gt->uncore,
 							       MTL_GT_ACTIVITY_FACTOR));
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index a4ec20aaafe2..cd9a76f048f3 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -1370,8 +1370,8 @@ gen12_emit_indirect_ctx_rcs(const struct intel_context *ce, u32 *cs)
 					      cs, GEN12_GFX_CCS_AUX_NV);
 
 	/* Wa_16014892111 */
-	if (IS_MTL_GRAPHICS_STEP(ce->engine->i915, M, STEP_A0, STEP_B0) ||
-	    IS_MTL_GRAPHICS_STEP(ce->engine->i915, P, STEP_A0, STEP_B0) ||
+	if (IS_METEORLAKE_GRAPHICS_STEP(ce->engine->i915, M, STEP_A0, STEP_B0) ||
+	    IS_METEORLAKE_GRAPHICS_STEP(ce->engine->i915, P, STEP_A0, STEP_B0) ||
 	    IS_DG2(ce->engine->i915))
 		cs = dg2_emit_draw_watermark_setting(cs);
 
diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c
index 58bb1c55294c..cc8b09b8a7fa 100644
--- a/drivers/gpu/drm/i915/gt/intel_rc6.c
+++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
@@ -526,7 +526,7 @@ static bool rc6_supported(struct intel_rc6 *rc6)
 		return false;
 	}
 
-	if (IS_MTL_MEDIA_STEP(gt->i915, STEP_A0, STEP_B0) &&
+	if (IS_METEORLAKE_MEDIA_STEP(gt->i915, STEP_A0, STEP_B0) &&
 	    gt->type == GT_MEDIA) {
 		drm_notice(&i915->drm,
 			   "Media RC6 disabled on A step\n");
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 4d2dece96011..a109ecd54944 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -819,8 +819,8 @@ static void mtl_ctx_gt_tuning_init(struct intel_engine_cs *engine,
 
 	dg2_ctx_gt_tuning_init(engine, wal);
 
-	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_B0, STEP_FOREVER) ||
-	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_B0, STEP_FOREVER))
+	if (IS_METEORLAKE_GRAPHICS_STEP(i915, M, STEP_B0, STEP_FOREVER) ||
+	    IS_METEORLAKE_GRAPHICS_STEP(i915, P, STEP_B0, STEP_FOREVER))
 		wa_add(wal, DRAW_WATERMARK, VERT_WM_VAL, 0x3FF, 0, false);
 }
 
@@ -831,8 +831,8 @@ static void mtl_ctx_workarounds_init(struct intel_engine_cs *engine,
 
 	mtl_ctx_gt_tuning_init(engine, wal);
 
-	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
-	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) {
+	if (IS_METEORLAKE_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
+	    IS_METEORLAKE_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) {
 		/* Wa_14014947963 */
 		wa_masked_field_set(wal, VF_PREEMPTION,
 				    PREEMPTION_VERTEX_COUNT, 0x4000);
@@ -1716,8 +1716,8 @@ xelpg_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
 	/* Wa_22016670082 */
 	wa_write_or(wal, GEN12_SQCNT1, GEN12_STRICT_RAR_ENABLE);
 
-	if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
-	    IS_MTL_GRAPHICS_STEP(gt->i915, P, STEP_A0, STEP_B0)) {
+	if (IS_METEORLAKE_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
+	    IS_METEORLAKE_GRAPHICS_STEP(gt->i915, P, STEP_A0, STEP_B0)) {
 		/* Wa_14014830051 */
 		wa_mcr_write_clr(wal, SARB_CHICKEN1, COMP_CKN_IN);
 
@@ -2413,15 +2413,15 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
 {
 	struct drm_i915_private *i915 = engine->i915;
 
-	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
-	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) {
+	if (IS_METEORLAKE_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
+	    IS_METEORLAKE_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) {
 		/* Wa_22014600077 */
 		wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS,
 				 ENABLE_EU_COUNT_FOR_TDL_FLUSH);
 	}
 
-	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
-	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
+	if (IS_METEORLAKE_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
+	    IS_METEORLAKE_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
 	    IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
 	    IS_DG2_G11(i915) || IS_DG2_G12(i915)) {
 		/* Wa_1509727124 */
@@ -2431,7 +2431,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
 
 	if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
 	    IS_DG2_G11(i915) || IS_DG2_G12(i915) ||
-	    IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0)) {
+	    IS_METEORLAKE_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0)) {
 		/* Wa_22012856258 */
 		wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2,
 				 GEN12_DISABLE_READ_SUPPRESSION);
@@ -3016,13 +3016,13 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
 				 GEN11_INDIRECT_STATE_BASE_ADDR_OVERRIDE);
 	}
 
-	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_B0, STEP_FOREVER) ||
-	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_B0, STEP_FOREVER))
+	if (IS_METEORLAKE_GRAPHICS_STEP(i915, M, STEP_B0, STEP_FOREVER) ||
+	    IS_METEORLAKE_GRAPHICS_STEP(i915, P, STEP_B0, STEP_FOREVER))
 		/* Wa_14017856879 */
 		wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN3, MTL_DISABLE_FIX_FOR_EOT_FLUSH);
 
-	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
-	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
+	if (IS_METEORLAKE_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
+	    IS_METEORLAKE_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
 		/*
 		 * Wa_14017066071
 		 * Wa_14017654203
@@ -3030,13 +3030,13 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
 		wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE,
 				 MTL_DISABLE_SAMPLER_SC_OOO);
 
-	if (IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
+	if (IS_METEORLAKE_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
 		/* Wa_22015279794 */
 		wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS,
 				 DISABLE_PREFETCH_INTO_IC);
 
-	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
-	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
+	if (IS_METEORLAKE_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
+	    IS_METEORLAKE_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
 	    IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
 	    IS_DG2_G11(i915) || IS_DG2_G12(i915)) {
 		/* Wa_22013037850 */
@@ -3044,16 +3044,16 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
 				DISABLE_128B_EVICTION_COMMAND_UDW);
 	}
 
-	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
-	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
+	if (IS_METEORLAKE_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
+	    IS_METEORLAKE_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
 	    IS_PONTEVECCHIO(i915) ||
 	    IS_DG2(i915)) {
 		/* Wa_22014226127 */
 		wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE);
 	}
 
-	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
-	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
+	if (IS_METEORLAKE_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
+	    IS_METEORLAKE_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
 	    IS_DG2(i915)) {
 		/* Wa_18017747507 */
 		wa_masked_en(wal, VFG_PREEMPTION_CHICKEN, POLYGON_TRIFAN_LINELOOP_DISABLE);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index 2eb891b270ae..3af0fcd7dd57 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -277,7 +277,7 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc)
 		flags |= GUC_WA_GAM_CREDITS;
 
 	/* Wa_14014475959 */
-	if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
+	if (IS_METEORLAKE_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
 	    IS_DG2(gt->i915))
 		flags |= GUC_WA_HOLD_CCS_SWITCHOUT;
 
@@ -292,7 +292,7 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc)
 		flags |= GUC_WA_DUAL_QUEUE;
 
 	/* Wa_22011802037: graphics version 11/12 */
-	if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
+	if (IS_METEORLAKE_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
 	    (GRAPHICS_VER(gt->i915) >= 11 &&
 	    GRAPHICS_VER_FULL(gt->i915) < IP_VER(12, 70)))
 		flags |= GUC_WA_PRE_PARSER;
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index a0e3ef1c65d2..5914c7348aba 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -1658,7 +1658,7 @@ static void guc_engine_reset_prepare(struct intel_engine_cs *engine)
 	 * Wa_22011802037: In addition to stopping the cs, we need
 	 * to wait for any pending mi force wakeups
 	 */
-	if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
+	if (IS_METEORLAKE_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
 	    (GRAPHICS_VER(engine->i915) >= 11 &&
 	     GRAPHICS_VER_FULL(engine->i915) < IP_VER(12, 70))) {
 		intel_engine_stop_cs(engine);
@@ -4267,7 +4267,7 @@ static void guc_default_vfuncs(struct intel_engine_cs *engine)
 
 	/* Wa_14014475959:dg2 */
 	if (engine->class == COMPUTE_CLASS)
-		if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
+		if (IS_METEORLAKE_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
 		    IS_DG2(engine->i915))
 			engine->flags |= I915_ENGINE_USES_WA_HOLD_CCS_SWITCHOUT;
 
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 0f30dc890209..472a36cf1a72 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -688,15 +688,15 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define IS_XEHPSDV_GRAPHICS_STEP(__i915, since, until) \
 	(IS_XEHPSDV(__i915) && IS_GRAPHICS_STEP(__i915, since, until))
 
-#define IS_MTL_GRAPHICS_STEP(__i915, variant, since, until) \
+#define IS_METEORLAKE_GRAPHICS_STEP(__i915, variant, since, until) \
 	(IS_SUBPLATFORM(__i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_##variant) && \
 	 IS_GRAPHICS_STEP(__i915, since, until))
 
-#define IS_MTL_DISPLAY_STEP(__i915, since, until) \
+#define IS_METEORLAKE_DISPLAY_STEP(__i915, since, until) \
 	(IS_METEORLAKE(__i915) && \
 	 IS_DISPLAY_STEP(__i915, since, until))
 
-#define IS_MTL_MEDIA_STEP(__i915, since, until) \
+#define IS_METEORLAKE_MEDIA_STEP(__i915, since, until) \
 	(IS_METEORLAKE(__i915) && \
 	 IS_MEDIA_STEP(__i915, since, until))
 
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 0a111b281578..e943ffbaecbc 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -4214,7 +4214,7 @@ static int read_properties_unlocked(struct i915_perf *perf,
 	 * C6 disable in BIOS. Fail if Media C6 is enabled on steppings where OAM
 	 * does not work as expected.
 	 */
-	if (IS_MTL_MEDIA_STEP(props->engine->i915, STEP_A0, STEP_C0) &&
+	if (IS_METEORLAKE_MEDIA_STEP(props->engine->i915, STEP_A0, STEP_C0) &&
 	    props->engine->oa_group->type == TYPE_OAM &&
 	    intel_check_bios_c6_setup(&props->engine->gt->rc6)) {
 		drm_dbg(&perf->i915->drm,
@@ -5322,7 +5322,7 @@ int i915_perf_ioctl_version(struct drm_i915_private *i915)
 	 * C6 disable in BIOS. If Media C6 is enabled in BIOS, return version 6
 	 * to indicate that OA media is not supported.
 	 */
-	if (IS_MTL_MEDIA_STEP(i915, STEP_A0, STEP_C0)) {
+	if (IS_METEORLAKE_MEDIA_STEP(i915, STEP_A0, STEP_C0)) {
 		struct intel_gt *gt;
 		int i;
 
-- 
2.34.1

[Intel-gfx] [PATCH 03/11] drm/i915/TGL: s/RKL/ROCKETLAKE for platform/subplatform defines

[Dnyaneshwar Bhadane]

Follow consistent naming convention. Replace RKL with
ROCKETLAKE.

Signed-off-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_power.c | 2 +-
 drivers/gpu/drm/i915/i915_drv.h                    | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index db5437043904..c65505b82065 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -1586,7 +1586,7 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv)
 		return;
 
 	if (IS_ALDERLAKE_S(dev_priv) ||
-	    IS_RKL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
+	    IS_ROCKETLAKE_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
 		/* Wa_1409767108 */
 		table = wa_1409767108_buddy_page_masks;
 	else
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 472a36cf1a72..3e9567f9ad15 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -666,7 +666,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 	(IS_TIGERLAKE(__i915) && \
 	 IS_DISPLAY_STEP(__i915, since, until))
 
-#define IS_RKL_DISPLAY_STEP(p, since, until) \
+#define IS_ROCKETLAKE_DISPLAY_STEP(p, since, until) \
 	(IS_ROCKETLAKE(p) && IS_DISPLAY_STEP(p, since, until))
 
 #define IS_ADLS_DISPLAY_STEP(__i915, since, until) \
-- 
2.34.1

[Intel-gfx] [PATCH 04/11] drm/i915/JSL: s/JSL/JASPERLAKE for platform/subplatform defines

[Dnyaneshwar Bhadane]

Follow consistent naming convention. Replace JSL with
JASPERLAKE.

Signed-off-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>
---
 drivers/gpu/drm/i915/display/icl_dsi.c         |  4 ++--
 drivers/gpu/drm/i915/display/intel_cdclk.c     |  4 ++--
 drivers/gpu/drm/i915/display/intel_combo_phy.c |  6 +++---
 drivers/gpu/drm/i915/display/intel_ddi.c       |  6 +++---
 drivers/gpu/drm/i915/display/intel_display.c   |  6 +++---
 drivers/gpu/drm/i915/display/intel_dp.c        |  2 +-
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c  | 18 +++++++++---------
 drivers/gpu/drm/i915/display/intel_hdmi.c      |  2 +-
 drivers/gpu/drm/i915/display/intel_psr.c       |  2 +-
 drivers/gpu/drm/i915/gem/i915_gem_object.c     |  2 +-
 drivers/gpu/drm/i915/gt/intel_sseu.c           |  2 +-
 drivers/gpu/drm/i915/gt/intel_workarounds.c    |  2 +-
 drivers/gpu/drm/i915/i915_drv.h                | 10 +++++-----
 drivers/gpu/drm/i915/intel_step.c              |  2 +-
 drivers/gpu/drm/i915/soc/intel_pch.c           |  6 +++---
 15 files changed, 37 insertions(+), 37 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index 59a2a289d9be..70f045da3bac 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -444,7 +444,7 @@ static void gen11_dsi_config_phy_lanes_sequence(struct intel_encoder *encoder)
 		intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), tmp);
 
 		/* For EHL, TGL, set latency optimization for PCS_DW1 lanes */
-		if (IS_JSL_EHL(dev_priv) || (DISPLAY_VER(dev_priv) >= 12)) {
+		if (IS_JASPERLAKE_EHL(dev_priv) || (DISPLAY_VER(dev_priv) >= 12)) {
 			intel_de_rmw(dev_priv, ICL_PORT_PCS_DW1_AUX(phy),
 				     LATENCY_OPTIM_MASK, LATENCY_OPTIM_VAL(0));
 
@@ -553,7 +553,7 @@ gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder,
 		}
 	}
 
-	if (IS_JSL_EHL(dev_priv)) {
+	if (IS_JASPERLAKE_EHL(dev_priv)) {
 		for_each_dsi_phy(phy, intel_dsi->phys)
 			intel_de_rmw(dev_priv, ICL_DPHY_CHKN(phy),
 				     0, ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP);
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 4207863b7b2a..2acfa0435675 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -3147,7 +3147,7 @@ static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
  */
 void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
 {
-	if (IS_JSL_EHL(dev_priv)) {
+	if (IS_JASPERLAKE_EHL(dev_priv)) {
 		if (dev_priv->display.cdclk.hw.ref == 24000)
 			dev_priv->display.cdclk.max_cdclk_freq = 552000;
 		else
@@ -3575,7 +3575,7 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
 	} else if (DISPLAY_VER(dev_priv) >= 12) {
 		dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
 		dev_priv->display.cdclk.table = icl_cdclk_table;
-	} else if (IS_JSL_EHL(dev_priv)) {
+	} else if (IS_JASPERLAKE_EHL(dev_priv)) {
 		dev_priv->display.funcs.cdclk = &ehl_cdclk_funcs;
 		dev_priv->display.cdclk.table = icl_cdclk_table;
 	} else if (DISPLAY_VER(dev_priv) >= 11) {
diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c b/drivers/gpu/drm/i915/display/intel_combo_phy.c
index 922a6d87b553..37bd6d31ced1 100644
--- a/drivers/gpu/drm/i915/display/intel_combo_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c
@@ -141,7 +141,7 @@ static bool has_phy_misc(struct drm_i915_private *i915, enum phy phy)
 
 	if (IS_ALDERLAKE_S(i915))
 		return phy == PHY_A;
-	else if (IS_JSL_EHL(i915) ||
+	else if (IS_JASPERLAKE_EHL(i915) ||
 		 IS_ROCKETLAKE(i915) ||
 		 IS_DG1(i915))
 		return phy < PHY_C;
@@ -242,7 +242,7 @@ static bool icl_combo_phy_verify_state(struct drm_i915_private *dev_priv,
 		ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW8(phy),
 				     IREFGEN, IREFGEN);
 
-		if (IS_JSL_EHL(dev_priv)) {
+		if (IS_JASPERLAKE_EHL(dev_priv)) {
 			if (ehl_vbt_ddi_d_present(dev_priv))
 				expected_val = ICL_PHY_MISC_MUX_DDID;
 
@@ -333,7 +333,7 @@ static void icl_combo_phys_init(struct drm_i915_private *dev_priv)
 		 * "internal" child devices.
 		 */
 		val = intel_de_read(dev_priv, ICL_PHY_MISC(phy));
-		if (IS_JSL_EHL(dev_priv) && phy == PHY_A) {
+		if (IS_JASPERLAKE_EHL(dev_priv) && phy == PHY_A) {
 			val &= ~ICL_PHY_MISC_MUX_DDID;
 
 			if (ehl_vbt_ddi_d_present(dev_priv))
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 090f242e610c..106387ff3658 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3582,7 +3582,7 @@ void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
 {
 	if (DISPLAY_VER(dev_priv) >= 12 && crtc_state->port_clock > 594000)
 		crtc_state->min_voltage_level = 2;
-	else if (IS_JSL_EHL(dev_priv) && crtc_state->port_clock > 594000)
+	else if (IS_JASPERLAKE_EHL(dev_priv) && crtc_state->port_clock > 594000)
 		crtc_state->min_voltage_level = 3;
 	else if (DISPLAY_VER(dev_priv) >= 11 && crtc_state->port_clock > 594000)
 		crtc_state->min_voltage_level = 1;
@@ -4801,7 +4801,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
 		encoder->disable_clock = dg1_ddi_disable_clock;
 		encoder->is_clock_enabled = dg1_ddi_is_clock_enabled;
 		encoder->get_config = dg1_ddi_get_config;
-	} else if (IS_JSL_EHL(dev_priv)) {
+	} else if (IS_JASPERLAKE_EHL(dev_priv)) {
 		if (intel_ddi_is_tc(dev_priv, port)) {
 			encoder->enable_clock = jsl_ddi_tc_enable_clock;
 			encoder->disable_clock = jsl_ddi_tc_disable_clock;
@@ -4872,7 +4872,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
 		encoder->hpd_pin = rkl_hpd_pin(dev_priv, port);
 	else if (DISPLAY_VER(dev_priv) >= 12)
 		encoder->hpd_pin = tgl_hpd_pin(dev_priv, port);
-	else if (IS_JSL_EHL(dev_priv))
+	else if (IS_JASPERLAKE_EHL(dev_priv))
 		encoder->hpd_pin = ehl_hpd_pin(dev_priv, port);
 	else if (DISPLAY_VER(dev_priv) == 11)
 		encoder->hpd_pin = icl_hpd_pin(dev_priv, port);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index d8533603ad05..e659f8abaec8 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1750,7 +1750,7 @@ bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
 		return phy <= PHY_E;
 	else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
 		return phy <= PHY_D;
-	else if (IS_JSL_EHL(dev_priv))
+	else if (IS_JASPERLAKE_EHL(dev_priv))
 		return phy <= PHY_C;
 	else if (IS_ALDERLAKE_P(dev_priv) || IS_DISPLAY_VER(dev_priv, 11, 12))
 		return phy <= PHY_B;
@@ -1802,7 +1802,7 @@ enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port)
 		return PHY_B + port - PORT_TC1;
 	else if ((IS_DG1(i915) || IS_ROCKETLAKE(i915)) && port >= PORT_TC1)
 		return PHY_C + port - PORT_TC1;
-	else if (IS_JSL_EHL(i915) && port == PORT_D)
+	else if (IS_JASPERLAKE_EHL(i915) && port == PORT_D)
 		return PHY_A;
 
 	return PHY_A + port - PORT_A;
@@ -7440,7 +7440,7 @@ void intel_setup_outputs(struct drm_i915_private *dev_priv)
 		intel_ddi_init(dev_priv, PORT_TC5);
 		intel_ddi_init(dev_priv, PORT_TC6);
 		icl_dsi_init(dev_priv);
-	} else if (IS_JSL_EHL(dev_priv)) {
+	} else if (IS_JASPERLAKE_EHL(dev_priv)) {
 		intel_ddi_init(dev_priv, PORT_A);
 		intel_ddi_init(dev_priv, PORT_B);
 		intel_ddi_init(dev_priv, PORT_C);
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 09dc6c88ad28..da9962b914f4 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -500,7 +500,7 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
 		else if (IS_ALDERLAKE_P(dev_priv) || IS_ALDERLAKE_S(dev_priv) ||
 			 IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
 			max_rate = 810000;
-		else if (IS_JSL_EHL(dev_priv))
+		else if (IS_JASPERLAKE_EHL(dev_priv))
 			max_rate = ehl_max_source_rate(intel_dp);
 		else
 			max_rate = icl_max_source_rate(intel_dp);
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 6b2d8a1e2aa9..c6d376d414b8 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -191,7 +191,7 @@ intel_combo_pll_enable_reg(struct drm_i915_private *i915,
 {
 	if (IS_DG1(i915))
 		return DG1_DPLL_ENABLE(pll->info->id);
-	else if (IS_JSL_EHL(i915) && (pll->info->id == DPLL_ID_EHL_DPLL4))
+	else if (IS_JASPERLAKE_EHL(i915) && (pll->info->id == DPLL_ID_EHL_DPLL4))
 		return MG_PLL_ENABLE(0);
 
 	return ICL_DPLL_ENABLE(pll->info->id);
@@ -2461,7 +2461,7 @@ static bool
 ehl_combo_pll_div_frac_wa_needed(struct drm_i915_private *i915)
 {
 	return ((IS_PLATFORM(i915, INTEL_ELKHARTLAKE) &&
-		 IS_JSL_EHL_DISPLAY_STEP(i915, STEP_B0, STEP_FOREVER)) ||
+		 IS_JASPERLAKE_EHL_DISPLAY_STEP(i915, STEP_B0, STEP_FOREVER)) ||
 		 IS_TIGERLAKE(i915) || IS_ALDERLAKE_S(i915) || IS_ALDERLAKE_P(i915)) &&
 		 i915->display.dpll.ref_clks.nssc == 38400;
 }
@@ -3226,7 +3226,7 @@ static int icl_get_combo_phy_dpll(struct intel_atomic_state *state,
 			BIT(DPLL_ID_EHL_DPLL4) |
 			BIT(DPLL_ID_ICL_DPLL1) |
 			BIT(DPLL_ID_ICL_DPLL0);
-	} else if (IS_JSL_EHL(dev_priv) && port != PORT_A) {
+	} else if (IS_JASPERLAKE_EHL(dev_priv) && port != PORT_A) {
 		dpll_mask =
 			BIT(DPLL_ID_EHL_DPLL4) |
 			BIT(DPLL_ID_ICL_DPLL1) |
@@ -3567,7 +3567,7 @@ static bool icl_pll_get_hw_state(struct drm_i915_private *dev_priv,
 			hw_state->div0 &= TGL_DPLL0_DIV0_AFC_STARTUP_MASK;
 		}
 	} else {
-		if (IS_JSL_EHL(dev_priv) && id == DPLL_ID_EHL_DPLL4) {
+		if (IS_JASPERLAKE_EHL(dev_priv) && id == DPLL_ID_EHL_DPLL4) {
 			hw_state->cfgcr0 = intel_de_read(dev_priv,
 							 ICL_DPLL_CFGCR0(4));
 			hw_state->cfgcr1 = intel_de_read(dev_priv,
@@ -3623,7 +3623,7 @@ static void icl_dpll_write(struct drm_i915_private *dev_priv,
 		cfgcr1_reg = TGL_DPLL_CFGCR1(id);
 		div0_reg = TGL_DPLL0_DIV0(id);
 	} else {
-		if (IS_JSL_EHL(dev_priv) && id == DPLL_ID_EHL_DPLL4) {
+		if (IS_JASPERLAKE_EHL(dev_priv) && id == DPLL_ID_EHL_DPLL4) {
 			cfgcr0_reg = ICL_DPLL_CFGCR0(4);
 			cfgcr1_reg = ICL_DPLL_CFGCR1(4);
 		} else {
@@ -3806,7 +3806,7 @@ static void combo_pll_enable(struct drm_i915_private *dev_priv,
 {
 	i915_reg_t enable_reg = intel_combo_pll_enable_reg(dev_priv, pll);
 
-	if (IS_JSL_EHL(dev_priv) &&
+	if (IS_JASPERLAKE_EHL(dev_priv) &&
 	    pll->info->id == DPLL_ID_EHL_DPLL4) {
 
 		/*
@@ -3914,7 +3914,7 @@ static void combo_pll_disable(struct drm_i915_private *dev_priv,
 
 	icl_pll_disable(dev_priv, pll, enable_reg);
 
-	if (IS_JSL_EHL(dev_priv) &&
+	if (IS_JASPERLAKE_EHL(dev_priv) &&
 	    pll->info->id == DPLL_ID_EHL_DPLL4)
 		intel_display_power_put(dev_priv, POWER_DOMAIN_DC_OFF,
 					pll->wakeref);
@@ -4150,7 +4150,7 @@ void intel_shared_dpll_init(struct drm_i915_private *dev_priv)
 		dpll_mgr = &rkl_pll_mgr;
 	else if (DISPLAY_VER(dev_priv) >= 12)
 		dpll_mgr = &tgl_pll_mgr;
-	else if (IS_JSL_EHL(dev_priv))
+	else if (IS_JASPERLAKE_EHL(dev_priv))
 		dpll_mgr = &ehl_pll_mgr;
 	else if (DISPLAY_VER(dev_priv) >= 11)
 		dpll_mgr = &icl_pll_mgr;
@@ -4335,7 +4335,7 @@ static void readout_dpll_hw_state(struct drm_i915_private *i915,
 
 	pll->on = intel_dpll_get_hw_state(i915, pll, &pll->state.hw_state);
 
-	if (IS_JSL_EHL(i915) && pll->on &&
+	if (IS_JASPERLAKE_EHL(i915) && pll->on &&
 	    pll->info->id == DPLL_ID_EHL_DPLL4) {
 		pll->wakeref = intel_display_power_get(i915,
 						       POWER_DOMAIN_DC_OFF);
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 7ac5e6c5e00d..4e557594ba62 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -2903,7 +2903,7 @@ static u8 intel_hdmi_ddc_pin(struct intel_encoder *encoder)
 		ddc_pin = rkl_port_to_ddc_pin(dev_priv, port);
 	else if (DISPLAY_VER(dev_priv) == 9 && HAS_PCH_TGP(dev_priv))
 		ddc_pin = gen9bc_tgp_port_to_ddc_pin(dev_priv, port);
-	else if (IS_JSL_EHL(dev_priv) && HAS_PCH_TGP(dev_priv))
+	else if (IS_JASPERLAKE_EHL(dev_priv) && HAS_PCH_TGP(dev_priv))
 		ddc_pin = mcc_port_to_ddc_pin(dev_priv, port);
 	else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
 		ddc_pin = icl_port_to_ddc_pin(dev_priv, port);
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 06b464229efe..f61d39d2b0fc 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -963,7 +963,7 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
 		return false;
 
 	/* JSL and EHL only supports eDP 1.3 */
-	if (IS_JSL_EHL(dev_priv)) {
+	if (IS_JASPERLAKE_EHL(dev_priv)) {
 		drm_dbg_kms(&dev_priv->drm, "PSR2 not supported by phy\n");
 		return false;
 	}
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.c b/drivers/gpu/drm/i915/gem/i915_gem_object.c
index 97ac6fb37958..0b34518d051c 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.c
@@ -226,7 +226,7 @@ bool i915_gem_object_can_bypass_llc(struct drm_i915_gem_object *obj)
 	 * it, but since i915 takes the stance of always zeroing memory before
 	 * handing it to userspace, we need to prevent this.
 	 */
-	return IS_JSL_EHL(i915);
+	return IS_JASPERLAKE_EHL(i915);
 }
 
 static void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file)
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c
index 1141f875f5bd..6945a0bc9778 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
@@ -302,7 +302,7 @@ static void gen11_sseu_info_init(struct intel_gt *gt)
 	u8 eu_en;
 	u8 s_en;
 
-	if (IS_JSL_EHL(gt->i915))
+	if (IS_JASPERLAKE_EHL(gt->i915))
 		intel_sseu_set_info(sseu, 1, 4, 8);
 	else
 		intel_sseu_set_info(sseu, 1, 8, 8);
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index a109ecd54944..a62dcbc2f901 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1441,7 +1441,7 @@ icl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
 
 	/* Wa_1607087056:icl,ehl,jsl */
 	if (IS_ICELAKE(i915) ||
-	    IS_JSL_EHL_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
+	    IS_JASPERLAKE_EHL_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
 		wa_write_or(wal,
 			    GEN11_SLICE_UNIT_LEVEL_CLKGATE,
 			    L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 3e9567f9ad15..3981b890f053 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -563,7 +563,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define IS_COFFEELAKE(i915)	IS_PLATFORM(i915, INTEL_COFFEELAKE)
 #define IS_COMETLAKE(i915)	IS_PLATFORM(i915, INTEL_COMETLAKE)
 #define IS_ICELAKE(i915)	IS_PLATFORM(i915, INTEL_ICELAKE)
-#define IS_JSL_EHL(i915)	(IS_PLATFORM(i915, INTEL_JASPERLAKE) || \
+#define IS_JASPERLAKE_EHL(i915)	(IS_PLATFORM(i915, INTEL_JASPERLAKE) || \
 				IS_PLATFORM(i915, INTEL_ELKHARTLAKE))
 #define IS_TIGERLAKE(i915)	IS_PLATFORM(i915, INTEL_TIGERLAKE)
 #define IS_ROCKETLAKE(i915)	IS_PLATFORM(i915, INTEL_ROCKETLAKE)
@@ -657,10 +657,10 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define IS_KBL_DISPLAY_STEP(i915, since, until) \
 	(IS_KABYLAKE(i915) && IS_DISPLAY_STEP(i915, since, until))
 
-#define IS_JSL_EHL_GRAPHICS_STEP(p, since, until) \
-	(IS_JSL_EHL(p) && IS_GRAPHICS_STEP(p, since, until))
-#define IS_JSL_EHL_DISPLAY_STEP(p, since, until) \
-	(IS_JSL_EHL(p) && IS_DISPLAY_STEP(p, since, until))
+#define IS_JASPERLAKE_EHL_GRAPHICS_STEP(p, since, until) \
+	(IS_JASPERLAKE_EHL(p) && IS_GRAPHICS_STEP(p, since, until))
+#define IS_JASPERLAKE_EHL_DISPLAY_STEP(p, since, until) \
+	(IS_JASPERLAKE_EHL(p) && IS_DISPLAY_STEP(p, since, until))
 
 #define IS_TIGERLAKE_DISPLAY_STEP(__i915, since, until) \
 	(IS_TIGERLAKE(__i915) && \
diff --git a/drivers/gpu/drm/i915/intel_step.c b/drivers/gpu/drm/i915/intel_step.c
index 67054c87bb5f..847c7de50e1f 100644
--- a/drivers/gpu/drm/i915/intel_step.c
+++ b/drivers/gpu/drm/i915/intel_step.c
@@ -219,7 +219,7 @@ void intel_step_init(struct drm_i915_private *i915)
 	} else if (IS_TIGERLAKE(i915)) {
 		revids = tgl_revids;
 		size = ARRAY_SIZE(tgl_revids);
-	} else if (IS_JSL_EHL(i915)) {
+	} else if (IS_JASPERLAKE_EHL(i915)) {
 		revids = jsl_ehl_revids;
 		size = ARRAY_SIZE(jsl_ehl_revids);
 	} else if (IS_ICELAKE(i915)) {
diff --git a/drivers/gpu/drm/i915/soc/intel_pch.c b/drivers/gpu/drm/i915/soc/intel_pch.c
index ba9843cb1b13..2e78b17843da 100644
--- a/drivers/gpu/drm/i915/soc/intel_pch.c
+++ b/drivers/gpu/drm/i915/soc/intel_pch.c
@@ -115,7 +115,7 @@ intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id)
 		return PCH_ICP;
 	case INTEL_PCH_MCC_DEVICE_ID_TYPE:
 		drm_dbg_kms(&dev_priv->drm, "Found Mule Creek Canyon PCH\n");
-		drm_WARN_ON(&dev_priv->drm, !IS_JSL_EHL(dev_priv));
+		drm_WARN_ON(&dev_priv->drm, !IS_JASPERLAKE_EHL(dev_priv));
 		/* MCC is TGP compatible */
 		return PCH_TGP;
 	case INTEL_PCH_TGP_DEVICE_ID_TYPE:
@@ -127,7 +127,7 @@ intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id)
 		return PCH_TGP;
 	case INTEL_PCH_JSP_DEVICE_ID_TYPE:
 		drm_dbg_kms(&dev_priv->drm, "Found Jasper Lake PCH\n");
-		drm_WARN_ON(&dev_priv->drm, !IS_JSL_EHL(dev_priv));
+		drm_WARN_ON(&dev_priv->drm, !IS_JASPERLAKE_EHL(dev_priv));
 		/* JSP is ICP compatible */
 		return PCH_ICP;
 	case INTEL_PCH_ADP_DEVICE_ID_TYPE:
@@ -177,7 +177,7 @@ intel_virt_detect_pch(const struct drm_i915_private *dev_priv,
 		id = INTEL_PCH_ADP_DEVICE_ID_TYPE;
 	else if (IS_TIGERLAKE(dev_priv) || IS_ROCKETLAKE(dev_priv))
 		id = INTEL_PCH_TGP_DEVICE_ID_TYPE;
-	else if (IS_JSL_EHL(dev_priv))
+	else if (IS_JASPERLAKE_EHL(dev_priv))
 		id = INTEL_PCH_MCC_DEVICE_ID_TYPE;
 	else if (IS_ICELAKE(dev_priv))
 		id = INTEL_PCH_ICP_DEVICE_ID_TYPE;
-- 
2.34.1

[Intel-gfx] [PATCH 05/11] drm/i915/KBL: s/KBL/KABYLAKE for platform/subplatform defines

[Dnyaneshwar Bhadane]

Follow consistent naming convention. Replace KBL with
KABYLAKE.

Signed-off-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c |  4 ++--
 drivers/gpu/drm/i915/gt/gen8_engine_cs.c           |  2 +-
 drivers/gpu/drm/i915/gt/intel_workarounds.c        |  6 +++---
 drivers/gpu/drm/i915/i915_drv.h                    | 12 ++++++------
 drivers/gpu/drm/i915/intel_clock_gating.c          |  4 ++--
 5 files changed, 14 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
index 9e34cc103aeb..84b09d188d2a 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
@@ -1718,9 +1718,9 @@ void intel_ddi_buf_trans_init(struct intel_encoder *encoder)
 			encoder->get_buf_trans = icl_get_mg_buf_trans;
 	} else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) {
 		encoder->get_buf_trans = bxt_get_buf_trans;
-	} else if (IS_CML_ULX(i915) || IS_CFL_ULX(i915) || IS_KBL_ULX(i915)) {
+	} else if (IS_CML_ULX(i915) || IS_CFL_ULX(i915) || IS_KABYLAKE_ULX(i915)) {
 		encoder->get_buf_trans = kbl_y_get_buf_trans;
-	} else if (IS_CML_ULT(i915) || IS_CFL_ULT(i915) || IS_KBL_ULT(i915)) {
+	} else if (IS_CML_ULT(i915) || IS_CFL_ULT(i915) || IS_KABYLAKE_ULT(i915)) {
 		encoder->get_buf_trans = kbl_u_get_buf_trans;
 	} else if (IS_COMETLAKE(i915) || IS_COFFEELAKE(i915) || IS_KABYLAKE(i915)) {
 		encoder->get_buf_trans = kbl_get_buf_trans;
diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
index eb72610a8588..ec0771dc662a 100644
--- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
@@ -43,7 +43,7 @@ int gen8_emit_flush_rcs(struct i915_request *rq, u32 mode)
 			vf_flush_wa = true;
 
 		/* WaForGAMHang:kbl */
-		if (IS_KBL_GRAPHICS_STEP(rq->engine->i915, 0, STEP_C0))
+		if (IS_KABYLAKE_GRAPHICS_STEP(rq->engine->i915, 0, STEP_C0))
 			dc_flush_wa = true;
 	}
 
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index a62dcbc2f901..b632fb5592a8 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -584,7 +584,7 @@ static void kbl_ctx_workarounds_init(struct intel_engine_cs *engine,
 	gen9_ctx_workarounds_init(engine, wal);
 
 	/* WaToEnableHwFixForPushConstHWBug:kbl */
-	if (IS_KBL_GRAPHICS_STEP(i915, STEP_C0, STEP_FOREVER))
+	if (IS_KABYLAKE_GRAPHICS_STEP(i915, STEP_C0, STEP_FOREVER))
 		wa_masked_en(wal, COMMON_SLICE_CHICKEN2,
 			     GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
 
@@ -1185,7 +1185,7 @@ kbl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
 	gen9_gt_workarounds_init(gt, wal);
 
 	/* WaDisableDynamicCreditSharing:kbl */
-	if (IS_KBL_GRAPHICS_STEP(gt->i915, 0, STEP_C0))
+	if (IS_KABYLAKE_GRAPHICS_STEP(gt->i915, 0, STEP_C0))
 		wa_write_or(wal,
 			    GAMT_CHKN_BIT_REG,
 			    GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING);
@@ -2933,7 +2933,7 @@ xcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
 	struct drm_i915_private *i915 = engine->i915;
 
 	/* WaKBLVECSSemaphoreWaitPoll:kbl */
-	if (IS_KBL_GRAPHICS_STEP(i915, STEP_A0, STEP_F0)) {
+	if (IS_KABYLAKE_GRAPHICS_STEP(i915, STEP_A0, STEP_F0)) {
 		wa_write(wal,
 			 RING_SEMA_WAIT_POLL(engine->mmio_base),
 			 1);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 3981b890f053..f19915115cff 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -614,9 +614,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 	IS_SUBPLATFORM(i915, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULT)
 #define IS_SKL_ULX(i915) \
 	IS_SUBPLATFORM(i915, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULX)
-#define IS_KBL_ULT(i915) \
+#define IS_KABYLAKE_ULT(i915) \
 	IS_SUBPLATFORM(i915, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT)
-#define IS_KBL_ULX(i915) \
+#define IS_KABYLAKE_ULX(i915) \
 	IS_SUBPLATFORM(i915, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX)
 #define IS_SKL_GT2(i915)	(IS_SKYLAKE(i915) && \
 				 INTEL_INFO(i915)->gt == 2)
@@ -624,9 +624,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 				 INTEL_INFO(i915)->gt == 3)
 #define IS_SKL_GT4(i915)	(IS_SKYLAKE(i915) && \
 				 INTEL_INFO(i915)->gt == 4)
-#define IS_KBL_GT2(i915)	(IS_KABYLAKE(i915) && \
+#define IS_KABYLAKE_GT2(i915)	(IS_KABYLAKE(i915) && \
 				 INTEL_INFO(i915)->gt == 2)
-#define IS_KBL_GT3(i915)	(IS_KABYLAKE(i915) && \
+#define IS_KABYLAKE_GT3(i915)	(IS_KABYLAKE(i915) && \
 				 INTEL_INFO(i915)->gt == 3)
 #define IS_CFL_ULT(i915) \
 	IS_SUBPLATFORM(i915, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULT)
@@ -652,9 +652,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 
 #define IS_SKL_GRAPHICS_STEP(p, since, until) (IS_SKYLAKE(p) && IS_GRAPHICS_STEP(p, since, until))
 
-#define IS_KBL_GRAPHICS_STEP(i915, since, until) \
+#define IS_KABYLAKE_GRAPHICS_STEP(i915, since, until) \
 	(IS_KABYLAKE(i915) && IS_GRAPHICS_STEP(i915, since, until))
-#define IS_KBL_DISPLAY_STEP(i915, since, until) \
+#define IS_KABYLAKE_DISPLAY_STEP(i915, since, until) \
 	(IS_KABYLAKE(i915) && IS_DISPLAY_STEP(i915, since, until))
 
 #define IS_JASPERLAKE_EHL_GRAPHICS_STEP(p, since, until) \
diff --git a/drivers/gpu/drm/i915/intel_clock_gating.c b/drivers/gpu/drm/i915/intel_clock_gating.c
index a27600bc5976..bb349043522c 100644
--- a/drivers/gpu/drm/i915/intel_clock_gating.c
+++ b/drivers/gpu/drm/i915/intel_clock_gating.c
@@ -456,12 +456,12 @@ static void kbl_init_clock_gating(struct drm_i915_private *i915)
 	intel_uncore_rmw(&i915->uncore, FBC_LLC_READ_CTRL, 0, FBC_LLC_FULLY_OPEN);
 
 	/* WaDisableSDEUnitClockGating:kbl */
-	if (IS_KBL_GRAPHICS_STEP(i915, 0, STEP_C0))
+	if (IS_KABYLAKE_GRAPHICS_STEP(i915, 0, STEP_C0))
 		intel_uncore_rmw(&i915->uncore, GEN8_UCGCTL6,
 				 0, GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
 
 	/* WaDisableGamClockGating:kbl */
-	if (IS_KBL_GRAPHICS_STEP(i915, 0, STEP_C0))
+	if (IS_KABYLAKE_GRAPHICS_STEP(i915, 0, STEP_C0))
 		intel_uncore_rmw(&i915->uncore, GEN6_UCGCTL1,
 				 0, GEN6_GAMUNIT_CLOCK_GATE_DISABLE);
 
-- 
2.34.1

[Intel-gfx] [PATCH 06/11] drm/i915/SKL: s/SKL/SKYLAKE for platform/subplatform defines

[Dnyaneshwar Bhadane]

Follow consistent naming convention. Replace SKL with
SKYLAKE.

Signed-off-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c |  4 ++--
 drivers/gpu/drm/i915/gt/intel_workarounds.c        |  2 +-
 drivers/gpu/drm/i915/i915_drv.h                    | 14 +++++++-------
 3 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
index 84b09d188d2a..ab84d003232c 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
@@ -1724,9 +1724,9 @@ void intel_ddi_buf_trans_init(struct intel_encoder *encoder)
 		encoder->get_buf_trans = kbl_u_get_buf_trans;
 	} else if (IS_COMETLAKE(i915) || IS_COFFEELAKE(i915) || IS_KABYLAKE(i915)) {
 		encoder->get_buf_trans = kbl_get_buf_trans;
-	} else if (IS_SKL_ULX(i915)) {
+	} else if (IS_SKYLAKE_ULX(i915)) {
 		encoder->get_buf_trans = skl_y_get_buf_trans;
-	} else if (IS_SKL_ULT(i915)) {
+	} else if (IS_SKYLAKE_ULT(i915)) {
 		encoder->get_buf_trans = skl_u_get_buf_trans;
 	} else if (IS_SKYLAKE(i915)) {
 		encoder->get_buf_trans = skl_get_buf_trans;
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index b632fb5592a8..10a4e0fc23ec 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1173,7 +1173,7 @@ skl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
 		    GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE);
 
 	/* WaInPlaceDecompressionHang:skl */
-	if (IS_SKL_GRAPHICS_STEP(gt->i915, STEP_A0, STEP_H0))
+	if (IS_SKYLAKE_GRAPHICS_STEP(gt->i915, STEP_A0, STEP_H0))
 		wa_write_or(wal,
 			    GEN9_GAMT_ECO_REG_RW_IA,
 			    GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f19915115cff..3c4a66f1a7ba 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -610,19 +610,19 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 /* ULX machines are also considered ULT. */
 #define IS_HSW_ULX(i915) \
 	IS_SUBPLATFORM(i915, INTEL_HASWELL, INTEL_SUBPLATFORM_ULX)
-#define IS_SKL_ULT(i915) \
+#define IS_SKYLAKE_ULT(i915) \
 	IS_SUBPLATFORM(i915, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULT)
-#define IS_SKL_ULX(i915) \
+#define IS_SKYLAKE_ULX(i915) \
 	IS_SUBPLATFORM(i915, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULX)
 #define IS_KABYLAKE_ULT(i915) \
 	IS_SUBPLATFORM(i915, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT)
 #define IS_KABYLAKE_ULX(i915) \
 	IS_SUBPLATFORM(i915, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX)
-#define IS_SKL_GT2(i915)	(IS_SKYLAKE(i915) && \
+#define IS_SKYLAKE_GT2(i915)	(IS_SKYLAKE(i915) && \
 				 INTEL_INFO(i915)->gt == 2)
-#define IS_SKL_GT3(i915)	(IS_SKYLAKE(i915) && \
+#define IS_SKYLAKE_GT3(i915)	(IS_SKYLAKE(i915) && \
 				 INTEL_INFO(i915)->gt == 3)
-#define IS_SKL_GT4(i915)	(IS_SKYLAKE(i915) && \
+#define IS_SKYLAKE_GT4(i915)	(IS_SKYLAKE(i915) && \
 				 INTEL_INFO(i915)->gt == 4)
 #define IS_KABYLAKE_GT2(i915)	(IS_KABYLAKE(i915) && \
 				 INTEL_INFO(i915)->gt == 2)
@@ -650,7 +650,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define IS_TIGERLAKE_UY(i915) \
 	IS_SUBPLATFORM(i915, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_UY)
 
-#define IS_SKL_GRAPHICS_STEP(p, since, until) (IS_SKYLAKE(p) && IS_GRAPHICS_STEP(p, since, until))
+#define IS_SKYLAKE_GRAPHICS_STEP(p, since, until) (IS_SKYLAKE(p) && IS_GRAPHICS_STEP(p, since, until))
 
 #define IS_KABYLAKE_GRAPHICS_STEP(i915, since, until) \
 	(IS_KABYLAKE(i915) && IS_GRAPHICS_STEP(i915, since, until))
@@ -801,7 +801,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 
 /* WaRsDisableCoarsePowerGating:skl,cnl */
 #define NEEDS_WaRsDisableCoarsePowerGating(i915)			\
-	(IS_SKL_GT3(i915) || IS_SKL_GT4(i915))
+	(IS_SKYLAKE_GT3(i915) || IS_SKYLAKE_GT4(i915))
 
 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
  * rows, which changed the alignment requirements and fence programming.
-- 
2.34.1

[Intel-gfx] [PATCH 07/11] drm/i915/adlp: s/ADLP/ALDERLAKE_P for display and graphics step

[Dnyaneshwar Bhadane]

From: Anusha Srivatsa <anusha.srivatsa@intel.com>

Driver refers to the platfrom Alderlake P as ADLP in places
and ALDERLAKE_P in some. Making the consistent change
to avoid confusion of the right naming convention for
the platform.

Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c         | 2 +-
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c      | 2 +-
 drivers/gpu/drm/i915/display/intel_psr.c           | 8 ++++----
 drivers/gpu/drm/i915/display/skl_universal_plane.c | 4 ++--
 drivers/gpu/drm/i915/i915_drv.h                    | 4 ++--
 5 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 2acfa0435675..831d1258ea3f 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -3559,7 +3559,7 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
 		dev_priv->display.cdclk.table = dg2_cdclk_table;
 	} else if (IS_ALDERLAKE_P(dev_priv)) {
 		/* Wa_22011320316:adl-p[a0] */
-		if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) {
+		if (IS_ALDERLAKE_P_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
 			dev_priv->display.cdclk.table = adlp_a_step_cdclk_table;
 			dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
 		} else if (IS_ADLP_RPLU(dev_priv)) {
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index c6d376d414b8..47fe8311067e 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -3781,7 +3781,7 @@ static void adlp_cmtg_clock_gating_wa(struct drm_i915_private *i915, struct inte
 {
 	u32 val;
 
-	if (!IS_ADLP_DISPLAY_STEP(i915, STEP_A0, STEP_B0) ||
+	if (!IS_ALDERLAKE_P_DISPLAY_STEP(i915, STEP_A0, STEP_B0) ||
 	    pll->info->id != DPLL_ID_ICL_DPLL0)
 		return;
 	/*
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index f61d39d2b0fc..00c98c2b4324 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -639,7 +639,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
 	}
 
 	/* Wa_22012278275:adl-p */
-	if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_E0)) {
+	if (IS_ALDERLAKE_P_DISPLAY_STEP(dev_priv, STEP_A0, STEP_E0)) {
 		static const u8 map[] = {
 			2, /* 5 lines */
 			1, /* 6 lines */
@@ -807,7 +807,7 @@ tgl_dc3co_exitline_compute_config(struct intel_dp *intel_dp,
 		return;
 
 	/* Wa_16011303918:adl-p */
-	if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
+	if (IS_ALDERLAKE_P_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
 		return;
 
 	/*
@@ -975,7 +975,7 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
 		return false;
 	}
 
-	if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) {
+	if (IS_ALDERLAKE_P_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) {
 		drm_dbg_kms(&dev_priv->drm, "PSR2 not completely functional in this stepping\n");
 		return false;
 	}
@@ -1033,7 +1033,7 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
 
 	/* Wa_16011303918:adl-p */
 	if (crtc_state->vrr.enable &&
-	    IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) {
+	    IS_ALDERLAKE_P_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) {
 		drm_dbg_kms(&dev_priv->drm,
 			    "PSR2 not enabled, not compatible with HW stepping + VRR\n");
 		return false;
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 25b06ced9ce7..2458a9ea25ba 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -2174,7 +2174,7 @@ static bool skl_plane_has_rc_ccs(struct drm_i915_private *i915,
 		return false;
 
 	/* Wa_22011186057 */
-	if (IS_ADLP_DISPLAY_STEP(i915, STEP_A0, STEP_B0))
+	if (IS_ALDERLAKE_P_DISPLAY_STEP(i915, STEP_A0, STEP_B0))
 		return false;
 
 	if (DISPLAY_VER(i915) >= 11)
@@ -2200,7 +2200,7 @@ static bool gen12_plane_has_mc_ccs(struct drm_i915_private *i915,
 		return false;
 
 	/* Wa_22011186057 */
-	if (IS_ADLP_DISPLAY_STEP(i915, STEP_A0, STEP_B0))
+	if (IS_ALDERLAKE_P_DISPLAY_STEP(i915, STEP_A0, STEP_B0))
 		return false;
 
 	/* Wa_14013215631 */
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 3c4a66f1a7ba..08e14cf225b5 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -677,11 +677,11 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 	(IS_ALDERLAKE_S(__i915) && \
 	 IS_GRAPHICS_STEP(__i915, since, until))
 
-#define IS_ADLP_DISPLAY_STEP(__i915, since, until) \
+#define IS_ALDERLAKE_P_DISPLAY_STEP(__i915, since, until) \
 	(IS_ALDERLAKE_P(__i915) && \
 	 IS_DISPLAY_STEP(__i915, since, until))
 
-#define IS_ADLP_GRAPHICS_STEP(__i915, since, until) \
+#define IS_ALDERLAKE_P_GRAPHICS_STEP(__i915, since, until) \
 	(IS_ALDERLAKE_P(__i915) && \
 	 IS_GRAPHICS_STEP(__i915, since, until))
 
-- 
2.34.1

[Intel-gfx] [PATCH 08/11] drm/i915/rplp: s/ADLP/ALDERLAKE_P for RPLP defines

[Dnyaneshwar Bhadane]

From: Anusha Srivatsa <anusha.srivatsa@intel.com>

Follow consistent naming convention. Replace ADLP with
ALDERLAKE_P.

Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h   | 2 +-
 drivers/gpu/drm/i915/intel_step.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 08e14cf225b5..bff9218b9f78 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -589,7 +589,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 	IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_S, INTEL_SUBPLATFORM_RPL)
 #define IS_ADLP_N(i915) \
 	IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_N)
-#define IS_ADLP_RPLP(i915) \
+#define IS_ALDERLAKE_P_RPLP(i915) \
 	IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPL)
 #define IS_ADLP_RPLU(i915) \
 	IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPLU)
diff --git a/drivers/gpu/drm/i915/intel_step.c b/drivers/gpu/drm/i915/intel_step.c
index 847c7de50e1f..9072f4ccd3c1 100644
--- a/drivers/gpu/drm/i915/intel_step.c
+++ b/drivers/gpu/drm/i915/intel_step.c
@@ -195,7 +195,7 @@ void intel_step_init(struct drm_i915_private *i915)
 	} else if (IS_ADLP_N(i915)) {
 		revids = adlp_n_revids;
 		size = ARRAY_SIZE(adlp_n_revids);
-	} else if (IS_ADLP_RPLP(i915)) {
+	} else if (IS_ALDERLAKE_P_RPLP(i915)) {
 		revids = adlp_rplp_revids;
 		size = ARRAY_SIZE(adlp_rplp_revids);
 	} else if (IS_ALDERLAKE_P(i915)) {
-- 
2.34.1

[Intel-gfx] [PATCH 09/11] drm/i915/adln: s/ADLP/ALDERLAKE_P in ADLN defines

[Dnyaneshwar Bhadane]

From: Anusha Srivatsa <anusha.srivatsa@intel.com>

Follow consistent naming convention. Replace ADLP with
ALDERLAKE_P

Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
 drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c | 2 +-
 drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c        | 2 +-
 drivers/gpu/drm/i915/i915_drv.h                 | 2 +-
 drivers/gpu/drm/i915/intel_step.c               | 2 +-
 4 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c
index 852bea0208ce..cc9569af7f0c 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c
@@ -94,7 +94,7 @@ static int guc_hwconfig_fill_buffer(struct intel_guc *guc, struct intel_hwconfig
 
 static bool has_table(struct drm_i915_private *i915)
 {
-	if (IS_ALDERLAKE_P(i915) && !IS_ADLP_N(i915))
+	if (IS_ALDERLAKE_P(i915) && !IS_ALDERLAKE_P_N(i915))
 		return true;
 	if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55))
 		return true;
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
index d408856ae4c0..dfb2837a3ed4 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
@@ -279,7 +279,7 @@ __uc_fw_auto_select(struct drm_i915_private *i915, struct intel_uc_fw *uc_fw)
 	 * ADL-S, otherwise the GuC might attempt to fetch a config table that
 	 * does not exist.
 	 */
-	if (IS_ADLP_N(i915))
+	if (IS_ALDERLAKE_P_N(i915))
 		p = INTEL_ALDERLAKE_S;
 
 	GEM_BUG_ON(uc_fw->type >= ARRAY_SIZE(blobs_all));
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index bff9218b9f78..d3ce6ed3be86 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -587,7 +587,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 	IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G12)
 #define IS_ADLS_RPLS(i915) \
 	IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_S, INTEL_SUBPLATFORM_RPL)
-#define IS_ADLP_N(i915) \
+#define IS_ALDERLAKE_P_N(i915) \
 	IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_N)
 #define IS_ALDERLAKE_P_RPLP(i915) \
 	IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPL)
diff --git a/drivers/gpu/drm/i915/intel_step.c b/drivers/gpu/drm/i915/intel_step.c
index 9072f4ccd3c1..fe447063a064 100644
--- a/drivers/gpu/drm/i915/intel_step.c
+++ b/drivers/gpu/drm/i915/intel_step.c
@@ -192,7 +192,7 @@ void intel_step_init(struct drm_i915_private *i915)
 	} else if (IS_XEHPSDV(i915)) {
 		revids = xehpsdv_revids;
 		size = ARRAY_SIZE(xehpsdv_revids);
-	} else if (IS_ADLP_N(i915)) {
+	} else if (IS_ALDERLAKE_P_N(i915)) {
 		revids = adlp_n_revids;
 		size = ARRAY_SIZE(adlp_n_revids);
 	} else if (IS_ALDERLAKE_P_RPLP(i915)) {
-- 
2.34.1

[Intel-gfx] [PATCH 10/11] drm/i915/adls: s/ADLS/ALDERLAKE_S in platform and subplatform defines

[Dnyaneshwar Bhadane]

From: Anusha Srivatsa <anusha.srivatsa@intel.com>

Driver refers to the platfrom Alderlake S as ADLS in places
and ALDERLAKE_S in some. Making the consistent change
to avoid confusion of the right naming convention for
the platform.

Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_device.c | 2 +-
 drivers/gpu/drm/i915/gt/uc/intel_uc.c               | 2 +-
 drivers/gpu/drm/i915/i915_drv.h                     | 6 +++---
 drivers/gpu/drm/i915/intel_step.c                   | 2 +-
 4 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c
index 3fd30e7f0062..f3090b8afc60 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.c
+++ b/drivers/gpu/drm/i915/display/intel_display_device.c
@@ -797,7 +797,7 @@ void intel_display_device_info_runtime_init(struct drm_i915_private *i915)
 	enum pipe pipe;
 
 	/* Wa_14011765242: adl-s A0,A1 */
-	if (IS_ADLS_DISPLAY_STEP(i915, STEP_A0, STEP_A2))
+	if (IS_ALDERLAKE_S_DISPLAY_STEP(i915, STEP_A0, STEP_A2))
 		for_each_pipe(i915, pipe)
 			display_runtime->num_scalers[pipe] = 0;
 	else if (DISPLAY_VER(i915) >= 11) {
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
index 18250fb64bd8..eb28705b88bd 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
@@ -43,7 +43,7 @@ static void uc_expand_default_options(struct intel_uc *uc)
 	}
 
 	/* Intermediate platforms are HuC authentication only */
-	if (IS_ALDERLAKE_S(i915) && !IS_ADLS_RPLS(i915)) {
+	if (IS_ALDERLAKE_S(i915) && !IS_ALDERLAKE_S_RPLS(i915)) {
 		i915->params.enable_guc = ENABLE_GUC_LOAD_HUC;
 		return;
 	}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index d3ce6ed3be86..1dad0c9b4f30 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -585,7 +585,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 	IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G11)
 #define IS_DG2_G12(i915) \
 	IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G12)
-#define IS_ADLS_RPLS(i915) \
+#define IS_ALDERLAKE_S_RPLS(i915) \
 	IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_S, INTEL_SUBPLATFORM_RPL)
 #define IS_ALDERLAKE_P_N(i915) \
 	IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_N)
@@ -669,11 +669,11 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define IS_ROCKETLAKE_DISPLAY_STEP(p, since, until) \
 	(IS_ROCKETLAKE(p) && IS_DISPLAY_STEP(p, since, until))
 
-#define IS_ADLS_DISPLAY_STEP(__i915, since, until) \
+#define IS_ALDERLAKE_S_DISPLAY_STEP(__i915, since, until) \
 	(IS_ALDERLAKE_S(__i915) && \
 	 IS_DISPLAY_STEP(__i915, since, until))
 
-#define IS_ADLS_GRAPHICS_STEP(__i915, since, until) \
+#define IS_ALDERLAKE_GRAPHICS_STEP(__i915, since, until) \
 	(IS_ALDERLAKE_S(__i915) && \
 	 IS_GRAPHICS_STEP(__i915, since, until))
 
diff --git a/drivers/gpu/drm/i915/intel_step.c b/drivers/gpu/drm/i915/intel_step.c
index fe447063a064..f410aa2a8077 100644
--- a/drivers/gpu/drm/i915/intel_step.c
+++ b/drivers/gpu/drm/i915/intel_step.c
@@ -201,7 +201,7 @@ void intel_step_init(struct drm_i915_private *i915)
 	} else if (IS_ALDERLAKE_P(i915)) {
 		revids = adlp_revids;
 		size = ARRAY_SIZE(adlp_revids);
-	} else if (IS_ADLS_RPLS(i915)) {
+	} else if (IS_ALDERLAKE_S_RPLS(i915)) {
 		revids = adls_rpls_revids;
 		size = ARRAY_SIZE(adls_rpls_revids);
 	} else if (IS_ALDERLAKE_S(i915)) {
-- 
2.34.1

[Intel-gfx] [PATCH 11/11] drm/i915/rplu: s/ADLP/ALDERLAKE_P in RPLU defines

[Dnyaneshwar Bhadane]

From: Anusha Srivatsa <anusha.srivatsa@intel.com>

Follow consistent naming convention. Replace ADLP with
ALDERLAKE_P

Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 2 +-
 drivers/gpu/drm/i915/i915_drv.h            | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 831d1258ea3f..d4d4bf72bc6d 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -3562,7 +3562,7 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
 		if (IS_ALDERLAKE_P_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
 			dev_priv->display.cdclk.table = adlp_a_step_cdclk_table;
 			dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
-		} else if (IS_ADLP_RPLU(dev_priv)) {
+		} else if (IS_ALDERLAKE_RPLU(dev_priv)) {
 			dev_priv->display.cdclk.table = rplu_cdclk_table;
 			dev_priv->display.funcs.cdclk = &rplu_cdclk_funcs;
 		} else {
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 1dad0c9b4f30..c6ad78381dd1 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -591,7 +591,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 	IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_N)
 #define IS_ALDERLAKE_P_RPLP(i915) \
 	IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPL)
-#define IS_ADLP_RPLU(i915) \
+#define IS_ALDERLAKE_RPLU(i915) \
 	IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPLU)
 #define IS_HSW_EARLY_SDV(i915) (IS_HASWELL(i915) && \
 				    (INTEL_DEVID(i915) & 0xFF00) == 0x0C00)
-- 
2.34.1

[Intel-gfx] ✗ Fi.CI.BUILD: failure for Replace acronym with full platform name in defines.

[Patchwork]

== Series Details ==

Series: Replace acronym with full platform name in defines.
URL   : https://patchwork.freedesktop.org/series/119361/
State : failure

== Summary ==

Error: make failed
  CALL    scripts/checksyscalls.sh
  DESCEND objtool
  INSTALL libsubcmd_headers
  CC [M]  drivers/gpu/drm/i915/display/intel_cdclk.o
drivers/gpu/drm/i915/display/intel_cdclk.c: In function ‘intel_init_cdclk_hooks’:
drivers/gpu/drm/i915/display/intel_cdclk.c:3562:3: error: this ‘if’ clause does not guard... [-Werror=misleading-indentation]
 3562 |   if (IS_ALDERLAKE_P_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
      |   ^~
drivers/gpu/drm/i915/display/intel_cdclk.c:3564:4: note: ...this statement, but the latter is misleadingly indented as if it were guarded by the ‘if’
 3564 |    dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
      |    ^~~~~~~~
drivers/gpu/drm/i915/display/intel_cdclk.c: At top level:
drivers/gpu/drm/i915/display/intel_cdclk.c:3572:4: error: expected identifier or ‘(’ before ‘else’
 3572 |  } else if (IS_ROCKETLAKE(dev_priv)) {
      |    ^~~~
drivers/gpu/drm/i915/display/intel_cdclk.c:3575:4: error: expected identifier or ‘(’ before ‘else’
 3575 |  } else if (DISPLAY_VER(dev_priv) >= 12) {
      |    ^~~~
drivers/gpu/drm/i915/display/intel_cdclk.c:3578:4: error: expected identifier or ‘(’ before ‘else’
 3578 |  } else if (IS_JASPERLAKE_EHL(dev_priv)) {
      |    ^~~~
drivers/gpu/drm/i915/display/intel_cdclk.c:3581:4: error: expected identifier or ‘(’ before ‘else’
 3581 |  } else if (DISPLAY_VER(dev_priv) >= 11) {
      |    ^~~~
drivers/gpu/drm/i915/display/intel_cdclk.c:3584:4: error: expected identifier or ‘(’ before ‘else’
 3584 |  } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
      |    ^~~~
drivers/gpu/drm/i915/display/intel_cdclk.c:3590:4: error: expected identifier or ‘(’ before ‘else’
 3590 |  } else if (DISPLAY_VER(dev_priv) == 9) {
      |    ^~~~
drivers/gpu/drm/i915/display/intel_cdclk.c:3592:4: error: expected identifier or ‘(’ before ‘else’
 3592 |  } else if (IS_BROADWELL(dev_priv)) {
      |    ^~~~
drivers/gpu/drm/i915/display/intel_cdclk.c:3594:4: error: expected identifier or ‘(’ before ‘else’
 3594 |  } else if (IS_HASWELL(dev_priv)) {
      |    ^~~~
drivers/gpu/drm/i915/display/intel_cdclk.c:3596:4: error: expected identifier or ‘(’ before ‘else’
 3596 |  } else if (IS_CHERRYVIEW(dev_priv)) {
      |    ^~~~
drivers/gpu/drm/i915/display/intel_cdclk.c:3598:4: error: expected identifier or ‘(’ before ‘else’
 3598 |  } else if (IS_VALLEYVIEW(dev_priv)) {
      |    ^~~~
drivers/gpu/drm/i915/display/intel_cdclk.c:3600:4: error: expected identifier or ‘(’ before ‘else’
 3600 |  } else if (IS_SANDYBRIDGE(dev_priv) || IS_IVYBRIDGE(dev_priv)) {
      |    ^~~~
drivers/gpu/drm/i915/display/intel_cdclk.c:3602:4: error: expected identifier or ‘(’ before ‘else’
 3602 |  } else if (IS_IRONLAKE(dev_priv)) {
      |    ^~~~
drivers/gpu/drm/i915/display/intel_cdclk.c:3604:4: error: expected identifier or ‘(’ before ‘else’
 3604 |  } else if (IS_GM45(dev_priv)) {
      |    ^~~~
drivers/gpu/drm/i915/display/intel_cdclk.c:3606:4: error: expected identifier or ‘(’ before ‘else’
 3606 |  } else if (IS_G45(dev_priv)) {
      |    ^~~~
drivers/gpu/drm/i915/display/intel_cdclk.c:3608:4: error: expected identifier or ‘(’ before ‘else’
 3608 |  } else if (IS_I965GM(dev_priv)) {
      |    ^~~~
drivers/gpu/drm/i915/display/intel_cdclk.c:3610:4: error: expected identifier or ‘(’ before ‘else’
 3610 |  } else if (IS_I965G(dev_priv)) {
      |    ^~~~
drivers/gpu/drm/i915/display/intel_cdclk.c:3612:4: error: expected identifier or ‘(’ before ‘else’
 3612 |  } else if (IS_PINEVIEW(dev_priv)) {
      |    ^~~~
drivers/gpu/drm/i915/display/intel_cdclk.c:3614:4: error: expected identifier or ‘(’ before ‘else’
 3614 |  } else if (IS_G33(dev_priv)) {
      |    ^~~~
drivers/gpu/drm/i915/display/intel_cdclk.c:3616:4: error: expected identifier or ‘(’ before ‘else’
 3616 |  } else if (IS_I945GM(dev_priv)) {
      |    ^~~~
drivers/gpu/drm/i915/display/intel_cdclk.c:3618:4: error: expected identifier or ‘(’ before ‘else’
 3618 |  } else if (IS_I945G(dev_priv)) {
      |    ^~~~
drivers/gpu/drm/i915/display/intel_cdclk.c:3620:4: error: expected identifier or ‘(’ before ‘else’
 3620 |  } else if (IS_I915GM(dev_priv)) {
      |    ^~~~
drivers/gpu/drm/i915/display/intel_cdclk.c:3622:4: error: expected identifier or ‘(’ before ‘else’
 3622 |  } else if (IS_I915G(dev_priv)) {
      |    ^~~~
drivers/gpu/drm/i915/display/intel_cdclk.c:3624:4: error: expected identifier or ‘(’ before ‘else’
 3624 |  } else if (IS_I865G(dev_priv)) {
      |    ^~~~
drivers/gpu/drm/i915/display/intel_cdclk.c:3626:4: error: expected identifier or ‘(’ before ‘else’
 3626 |  } else if (IS_I85X(dev_priv)) {
      |    ^~~~
drivers/gpu/drm/i915/display/intel_cdclk.c:3628:4: error: expected identifier or ‘(’ before ‘else’
 3628 |  } else if (IS_I845G(dev_priv)) {
      |    ^~~~
drivers/gpu/drm/i915/display/intel_cdclk.c:3630:4: error: expected identifier or ‘(’ before ‘else’
 3630 |  } else if (IS_I830(dev_priv)) {
      |    ^~~~
drivers/gpu/drm/i915/display/intel_cdclk.c:3634:2: error: expected identifier or ‘(’ before ‘if’
 3634 |  if (drm_WARN(&dev_priv->drm, !dev_priv->display.funcs.cdclk,
      |  ^~
In file included from ./arch/x86/include/asm/bug.h:87,
                 from ./include/linux/bug.h:5,
                 from ./include/linux/cpumask.h:14,
                 from ./arch/x86/include/asm/cpumask.h:5,
                 from ./arch/x86/include/asm/msr.h:11,
                 from ./arch/x86/include/asm/processor.h:23,
                 from ./arch/x86/include/asm/timex.h:5,
                 from ./include/linux/timex.h:67,
                 from ./include/linux/time32.h:13,
                 from ./include/linux/time.h:60,
                 from drivers/gpu/drm/i915/display/intel_cdclk.c:24:
./include/asm-generic/bug.h:135:2: error: expected identifier or ‘(’ before ‘)’ token
  135 | })
      |  ^
./include/drm/drm_print.h:620:2: note: in expansion of macro ‘WARN’
  620 |  WARN(condition, "%s %s: " format,    \
      |  ^~~~
drivers/gpu/drm/i915/display/intel_cdclk.c:3634:6: note: in expansion of macro ‘drm_WARN’
 3634 |  if (drm_WARN(&dev_priv->drm, !dev_priv->display.funcs.cdclk,
      |      ^~~~~~~~
drivers/gpu/drm/i915/display/intel_cdclk.c:3637:1: error: expected identifier or ‘(’ before ‘}’ token
 3637 | }
      | ^
drivers/gpu/drm/i915/display/intel_cdclk.c:3543:39: error: ‘i830_cdclk_funcs’ defined but not used [-Werror=unused-const-variable=]
 3543 | static const struct intel_cdclk_funcs i830_cdclk_funcs = {
      |                                       ^~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/display/intel_cdclk.c:3538:39: error: ‘i845g_cdclk_funcs’ defined but not used [-Werror=unused-const-variable=]
 3538 | static const struct intel_cdclk_funcs i845g_cdclk_funcs = {
      |                                       ^~~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/display/intel_cdclk.c:3533:39: error: ‘i85x_cdclk_funcs’ defined but not used [-Werror=unused-const-variable=]
 3533 | static const struct intel_cdclk_funcs i85x_cdclk_funcs = {
      |                                       ^~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/display/intel_cdclk.c:3528:39: error: ‘i865g_cdclk_funcs’ defined but not used [-Werror=unused-const-variable=]
 3528 | static const struct intel_cdclk_funcs i865g_cdclk_funcs = {
      |                                       ^~~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/display/intel_cdclk.c:3523:39: error: ‘i915g_cdclk_funcs’ defined but not used [-Werror=unused-const-variable=]
 3523 | static const struct intel_cdclk_funcs i915g_cdclk_funcs = {
      |                                       ^~~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/display/intel_cdclk.c:3518:39: error: ‘i915gm_cdclk_funcs’ defined but not used [-Werror=unused-const-variable=]
 3518 | static const struct intel_cdclk_funcs i915gm_cdclk_funcs = {
      |                                       ^~~~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/display/intel_cdclk.c:3511:39: error: ‘i945gm_cdclk_funcs’ defined but not used [-Werror=unused-const-variable=]
 3511 | static const struct intel_cdclk_funcs i945gm_cdclk_funcs = {
      |                                       ^~~~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/display/intel_cdclk.c:3506:39: error: ‘g33_cdclk_funcs’ defined but not used [-Werror=unused-const-variable=]
 3506 | static const struct intel_cdclk_funcs g33_cdclk_funcs = {
      |                                       ^~~~~~~~~~~~~~~
drivers/gpu/drm/i915/display/intel_cdclk.c:3501:39: error: ‘pnv_cdclk_funcs’ defined but not used [-Werror=unused-const-variable=]
 3501 | static const struct intel_cdclk_funcs pnv_cdclk_funcs = {
      |                                       ^~~~~~~~~~~~~~~
drivers/gpu/drm/i915/display/intel_cdclk.c:3494:39: error: ‘i965gm_cdclk_funcs’ defined but not used [-Werror=unused-const-variable=]
 3494 | static const struct intel_cdclk_funcs i965gm_cdclk_funcs = {
      |                                       ^~~~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/display/intel_cdclk.c:3487:39: error: ‘gm45_cdclk_funcs’ defined but not used [-Werror=unused-const-variable=]
 3487 | static const struct intel_cdclk_funcs gm45_cdclk_funcs = {
      |                                       ^~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/display/intel_cdclk.c:3482:39: error: ‘ilk_cdclk_funcs’ defined but not used [-Werror=unused-const-variable=]
 3482 | static const struct intel_cdclk_funcs ilk_cdclk_funcs = {
      |                                       ^~~~~~~~~~~~~~~
drivers/gpu/drm/i915/display/intel_cdclk.c:3477:39: error: ‘fixed_400mhz_cdclk_funcs’ defined but not used [-Werror=unused-const-variable=]
 3477 | static const struct intel_cdclk_funcs fixed_400mhz_cdclk_funcs = {
      |                                       ^~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/display/intel_cdclk.c:3471:39: error: ‘hsw_cdclk_funcs’ defined but not used [-Werror=unused-const-variable=]
 3471 | static const struct intel_cdclk_funcs hsw_cdclk_funcs = {
      |                                       ^~~~~~~~~~~~~~~
drivers/gpu/drm/i915/display/intel_cdclk.c:3465:39: error: ‘vlv_cdclk_funcs’ defined but not used [-Werror=unused-const-variable=]
 3465 | static const struct intel_cdclk_funcs vlv_cdclk_funcs = {
      |                                       ^~~~~~~~~~~~~~~
drivers/gpu/drm/i915/display/intel_cdclk.c:3459:39: error: ‘chv_cdclk_funcs’ defined but not used [-Werror=unused-const-variable=]
 3459 | static const struct intel_cdclk_funcs chv_cdclk_funcs = {
      |                                       ^~~~~~~~~~~~~~~
drivers/gpu/drm/i915/display/intel_cdclk.c:3453:39: error: ‘bdw_cdclk_funcs’ defined but not used [-Werror=unused-const-variable=]
 3453 | static const struct intel_cdclk_funcs bdw_cdclk_funcs = {
      |                                       ^~~~~~~~~~~~~~~
drivers/gpu/drm/i915/display/intel_cdclk.c:3447:39: error: ‘skl_cdclk_funcs’ defined but not used [-Werror=unused-const-variable=]
 3447 | static const struct intel_cdclk_funcs skl_cdclk_funcs = {
      |                                       ^~~~~~~~~~~~~~~
drivers/gpu/drm/i915/display/intel_cdclk.c:3440:39: error: ‘bxt_cdclk_funcs’ defined but not used [-Werror=unused-const-variable=]
 3440 | static const struct intel_cdclk_funcs bxt_cdclk_funcs = {
      |                                       ^~~~~~~~~~~~~~~
drivers/gpu/drm/i915/display/intel_cdclk.c:3433:39: error: ‘icl_cdclk_funcs’ defined but not used [-Werror=unused-const-variable=]
 3433 | static const struct intel_cdclk_funcs icl_cdclk_funcs = {
      |                                       ^~~~~~~~~~~~~~~
drivers/gpu/drm/i915/display/intel_cdclk.c:3426:39: error: ‘ehl_cdclk_funcs’ defined but not used [-Werror=unused-const-variable=]
 3426 | static const struct intel_cdclk_funcs ehl_cdclk_funcs = {
      |                                       ^~~~~~~~~~~~~~~
drivers/gpu/drm/i915/display/intel_cdclk.c:1272:38: error: ‘rkl_cdclk_table’ defined but not used [-Werror=unused-const-variable=]
 1272 | static const struct intel_cdclk_vals rkl_cdclk_table[] = {
      |                                      ^~~~~~~~~~~~~~~
drivers/gpu/drm/i915/display/intel_cdclk.c:1248:38: error: ‘icl_cdclk_table’ defined but not used [-Werror=unused-const-variable=]
 1248 | static const struct intel_cdclk_vals icl_cdclk_table[] = {
      |                                      ^~~~~~~~~~~~~~~
drivers/gpu/drm/i915/display/intel_cdclk.c:1241:38: error: ‘glk_cdclk_table’ defined but not used [-Werror=unused-const-variable=]
 1241 | static const struct intel_cdclk_vals glk_cdclk_table[] = {
      |                                      ^~~~~~~~~~~~~~~
drivers/gpu/drm/i915/display/intel_cdclk.c:1232:38: error: ‘bxt_cdclk_table’ defined but not used [-Werror=unused-const-variable=]
 1232 | static const struct intel_cdclk_vals bxt_cdclk_table[] = {
      |                                      ^~~~~~~~~~~~~~~
cc1: all warnings being treated as errors
make[5]: *** [scripts/Makefile.build:252: drivers/gpu/drm/i915/display/intel_cdclk.o] Error 1
make[4]: *** [scripts/Makefile.build:494: drivers/gpu/drm/i915] Error 2
make[3]: *** [scripts/Makefile.build:494: drivers/gpu/drm] Error 2
make[2]: *** [scripts/Makefile.build:494: drivers/gpu] Error 2
make[1]: *** [scripts/Makefile.build:494: drivers] Error 2
make: *** [Makefile:2026: .] Error 2
Build failed, no error log produced

Re: [Intel-gfx] [PATCH 07/11] drm/i915/adlp: s/ADLP/ALDERLAKE_P for display and graphics step

[kernel test robot]

Hi Dnyaneshwar,

kernel test robot noticed the following build errors:

[auto build test ERROR on drm-tip/drm-tip]

url:    https://github.com/intel-lab-lkp/linux/commits/Dnyaneshwar-Bhadane/drm-i915-TGL-s-TGL-TIGERLAKE-for-platform-subplatform-defines/20230615-130242
base:   git://anongit.freedesktop.org/drm/drm-tip drm-tip
patch link:    https://lore.kernel.org/r/20230615050015.3105902-8-dnyaneshwar.bhadane%40intel.com
patch subject: [Intel-gfx] [PATCH 07/11] drm/i915/adlp: s/ADLP/ALDERLAKE_P for display and graphics step
config: i386-defconfig (https://download.01.org/0day-ci/archive/20230615/202306151559.EK0S8n5W-lkp@intel.com/config)
compiler: gcc-12 (Debian 12.2.0-14) 12.2.0
reproduce (this is a W=1 build):
        git remote add drm-tip git://anongit.freedesktop.org/drm/drm-tip
        git fetch drm-tip drm-tip
        git checkout drm-tip/drm-tip
        b4 shazam https://lore.kernel.org/r/20230615050015.3105902-8-dnyaneshwar.bhadane@intel.com
        # save the config file
        mkdir build_dir && cp config build_dir/.config
        make W=1 O=build_dir ARCH=i386 olddefconfig
        make W=1 O=build_dir ARCH=i386 SHELL=/bin/bash drivers/gpu/drm/i915/

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202306151559.EK0S8n5W-lkp@intel.com/

All errors (new ones prefixed by >>):

   drivers/gpu/drm/i915/display/intel_cdclk.c: In function 'intel_init_cdclk_hooks':
>> drivers/gpu/drm/i915/display/intel_cdclk.c:3562:17: error: this 'if' clause does not guard... [-Werror=misleading-indentation]
    3562 |                 if (IS_ALDERLAKE_P_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
         |                 ^~
   drivers/gpu/drm/i915/display/intel_cdclk.c:3564:25: note: ...this statement, but the latter is misleadingly indented as if it were guarded by the 'if'
    3564 |                         dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
         |                         ^~~~~~~~
   drivers/gpu/drm/i915/display/intel_cdclk.c: At top level:
>> drivers/gpu/drm/i915/display/intel_cdclk.c:3572:11: error: expected identifier or '(' before 'else'
    3572 |         } else if (IS_ROCKETLAKE(dev_priv)) {
         |           ^~~~
   drivers/gpu/drm/i915/display/intel_cdclk.c:3575:11: error: expected identifier or '(' before 'else'
    3575 |         } else if (DISPLAY_VER(dev_priv) >= 12) {
         |           ^~~~
   drivers/gpu/drm/i915/display/intel_cdclk.c:3578:11: error: expected identifier or '(' before 'else'
    3578 |         } else if (IS_JASPERLAKE_EHL(dev_priv)) {
         |           ^~~~
   drivers/gpu/drm/i915/display/intel_cdclk.c:3581:11: error: expected identifier or '(' before 'else'
    3581 |         } else if (DISPLAY_VER(dev_priv) >= 11) {
         |           ^~~~
   drivers/gpu/drm/i915/display/intel_cdclk.c:3584:11: error: expected identifier or '(' before 'else'
    3584 |         } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
         |           ^~~~
   drivers/gpu/drm/i915/display/intel_cdclk.c:3590:11: error: expected identifier or '(' before 'else'
    3590 |         } else if (DISPLAY_VER(dev_priv) == 9) {
         |           ^~~~
   drivers/gpu/drm/i915/display/intel_cdclk.c:3592:11: error: expected identifier or '(' before 'else'
    3592 |         } else if (IS_BROADWELL(dev_priv)) {
         |           ^~~~
   drivers/gpu/drm/i915/display/intel_cdclk.c:3594:11: error: expected identifier or '(' before 'else'
    3594 |         } else if (IS_HASWELL(dev_priv)) {
         |           ^~~~
   drivers/gpu/drm/i915/display/intel_cdclk.c:3596:11: error: expected identifier or '(' before 'else'
    3596 |         } else if (IS_CHERRYVIEW(dev_priv)) {
         |           ^~~~
   drivers/gpu/drm/i915/display/intel_cdclk.c:3598:11: error: expected identifier or '(' before 'else'
    3598 |         } else if (IS_VALLEYVIEW(dev_priv)) {
         |           ^~~~
   drivers/gpu/drm/i915/display/intel_cdclk.c:3600:11: error: expected identifier or '(' before 'else'
    3600 |         } else if (IS_SANDYBRIDGE(dev_priv) || IS_IVYBRIDGE(dev_priv)) {
         |           ^~~~
   drivers/gpu/drm/i915/display/intel_cdclk.c:3602:11: error: expected identifier or '(' before 'else'
    3602 |         } else if (IS_IRONLAKE(dev_priv)) {
         |           ^~~~
   drivers/gpu/drm/i915/display/intel_cdclk.c:3604:11: error: expected identifier or '(' before 'else'
    3604 |         } else if (IS_GM45(dev_priv)) {
         |           ^~~~
   drivers/gpu/drm/i915/display/intel_cdclk.c:3606:11: error: expected identifier or '(' before 'else'
    3606 |         } else if (IS_G45(dev_priv)) {
         |           ^~~~
   drivers/gpu/drm/i915/display/intel_cdclk.c:3608:11: error: expected identifier or '(' before 'else'
    3608 |         } else if (IS_I965GM(dev_priv)) {
         |           ^~~~
   drivers/gpu/drm/i915/display/intel_cdclk.c:3610:11: error: expected identifier or '(' before 'else'
    3610 |         } else if (IS_I965G(dev_priv)) {
         |           ^~~~
   drivers/gpu/drm/i915/display/intel_cdclk.c:3612:11: error: expected identifier or '(' before 'else'
    3612 |         } else if (IS_PINEVIEW(dev_priv)) {
         |           ^~~~
   drivers/gpu/drm/i915/display/intel_cdclk.c:3614:11: error: expected identifier or '(' before 'else'
    3614 |         } else if (IS_G33(dev_priv)) {
         |           ^~~~
   drivers/gpu/drm/i915/display/intel_cdclk.c:3616:11: error: expected identifier or '(' before 'else'
    3616 |         } else if (IS_I945GM(dev_priv)) {
         |           ^~~~
   drivers/gpu/drm/i915/display/intel_cdclk.c:3618:11: error: expected identifier or '(' before 'else'
    3618 |         } else if (IS_I945G(dev_priv)) {
         |           ^~~~
   drivers/gpu/drm/i915/display/intel_cdclk.c:3620:11: error: expected identifier or '(' before 'else'
    3620 |         } else if (IS_I915GM(dev_priv)) {
         |           ^~~~
   drivers/gpu/drm/i915/display/intel_cdclk.c:3622:11: error: expected identifier or '(' before 'else'
    3622 |         } else if (IS_I915G(dev_priv)) {
         |           ^~~~
   drivers/gpu/drm/i915/display/intel_cdclk.c:3624:11: error: expected identifier or '(' before 'else'
    3624 |         } else if (IS_I865G(dev_priv)) {
         |           ^~~~
   drivers/gpu/drm/i915/display/intel_cdclk.c:3626:11: error: expected identifier or '(' before 'else'
    3626 |         } else if (IS_I85X(dev_priv)) {
         |           ^~~~
   drivers/gpu/drm/i915/display/intel_cdclk.c:3628:11: error: expected identifier or '(' before 'else'
    3628 |         } else if (IS_I845G(dev_priv)) {
         |           ^~~~
   drivers/gpu/drm/i915/display/intel_cdclk.c:3630:11: error: expected identifier or '(' before 'else'
    3630 |         } else if (IS_I830(dev_priv)) {
         |           ^~~~
>> drivers/gpu/drm/i915/display/intel_cdclk.c:3634:9: error: expected identifier or '(' before 'if'
    3634 |         if (drm_WARN(&dev_priv->drm, !dev_priv->display.funcs.cdclk,
         |         ^~
   In file included from arch/x86/include/asm/bug.h:87,
                    from include/linux/bug.h:5,
                    from include/linux/cpumask.h:14,
                    from arch/x86/include/asm/cpumask.h:5,
                    from arch/x86/include/asm/msr.h:11,
                    from arch/x86/include/asm/processor.h:23,
                    from arch/x86/include/asm/timex.h:5,
                    from include/linux/timex.h:67,
                    from include/linux/time32.h:13,
                    from include/linux/time.h:60,
                    from drivers/gpu/drm/i915/display/intel_cdclk.c:24:
>> include/asm-generic/bug.h:135:2: error: expected identifier or '(' before ')' token
     135 | })
         |  ^
   include/drm/drm_print.h:620:9: note: in expansion of macro 'WARN'
     620 |         WARN(condition, "%s %s: " format,                               \
         |         ^~~~
   drivers/gpu/drm/i915/display/intel_cdclk.c:3634:13: note: in expansion of macro 'drm_WARN'
    3634 |         if (drm_WARN(&dev_priv->drm, !dev_priv->display.funcs.cdclk,
         |             ^~~~~~~~
>> drivers/gpu/drm/i915/display/intel_cdclk.c:3637:1: error: expected identifier or '(' before '}' token
    3637 | }
         | ^
>> drivers/gpu/drm/i915/display/intel_cdclk.c:3543:39: error: 'i830_cdclk_funcs' defined but not used [-Werror=unused-const-variable=]
    3543 | static const struct intel_cdclk_funcs i830_cdclk_funcs = {
         |                                       ^~~~~~~~~~~~~~~~
>> drivers/gpu/drm/i915/display/intel_cdclk.c:3538:39: error: 'i845g_cdclk_funcs' defined but not used [-Werror=unused-const-variable=]
    3538 | static const struct intel_cdclk_funcs i845g_cdclk_funcs = {
         |                                       ^~~~~~~~~~~~~~~~~
>> drivers/gpu/drm/i915/display/intel_cdclk.c:3533:39: error: 'i85x_cdclk_funcs' defined but not used [-Werror=unused-const-variable=]
    3533 | static const struct intel_cdclk_funcs i85x_cdclk_funcs = {
         |                                       ^~~~~~~~~~~~~~~~
>> drivers/gpu/drm/i915/display/intel_cdclk.c:3528:39: error: 'i865g_cdclk_funcs' defined but not used [-Werror=unused-const-variable=]
    3528 | static const struct intel_cdclk_funcs i865g_cdclk_funcs = {
         |                                       ^~~~~~~~~~~~~~~~~
>> drivers/gpu/drm/i915/display/intel_cdclk.c:3523:39: error: 'i915g_cdclk_funcs' defined but not used [-Werror=unused-const-variable=]
    3523 | static const struct intel_cdclk_funcs i915g_cdclk_funcs = {
         |                                       ^~~~~~~~~~~~~~~~~
>> drivers/gpu/drm/i915/display/intel_cdclk.c:3518:39: error: 'i915gm_cdclk_funcs' defined but not used [-Werror=unused-const-variable=]
    3518 | static const struct intel_cdclk_funcs i915gm_cdclk_funcs = {
         |                                       ^~~~~~~~~~~~~~~~~~
>> drivers/gpu/drm/i915/display/intel_cdclk.c:3511:39: error: 'i945gm_cdclk_funcs' defined but not used [-Werror=unused-const-variable=]
    3511 | static const struct intel_cdclk_funcs i945gm_cdclk_funcs = {
         |                                       ^~~~~~~~~~~~~~~~~~
>> drivers/gpu/drm/i915/display/intel_cdclk.c:3506:39: error: 'g33_cdclk_funcs' defined but not used [-Werror=unused-const-variable=]
    3506 | static const struct intel_cdclk_funcs g33_cdclk_funcs = {
         |                                       ^~~~~~~~~~~~~~~
>> drivers/gpu/drm/i915/display/intel_cdclk.c:3501:39: error: 'pnv_cdclk_funcs' defined but not used [-Werror=unused-const-variable=]
    3501 | static const struct intel_cdclk_funcs pnv_cdclk_funcs = {
         |                                       ^~~~~~~~~~~~~~~
>> drivers/gpu/drm/i915/display/intel_cdclk.c:3494:39: error: 'i965gm_cdclk_funcs' defined but not used [-Werror=unused-const-variable=]
    3494 | static const struct intel_cdclk_funcs i965gm_cdclk_funcs = {
         |                                       ^~~~~~~~~~~~~~~~~~
>> drivers/gpu/drm/i915/display/intel_cdclk.c:3487:39: error: 'gm45_cdclk_funcs' defined but not used [-Werror=unused-const-variable=]
    3487 | static const struct intel_cdclk_funcs gm45_cdclk_funcs = {
         |                                       ^~~~~~~~~~~~~~~~
>> drivers/gpu/drm/i915/display/intel_cdclk.c:3482:39: error: 'ilk_cdclk_funcs' defined but not used [-Werror=unused-const-variable=]
    3482 | static const struct intel_cdclk_funcs ilk_cdclk_funcs = {
         |                                       ^~~~~~~~~~~~~~~
>> drivers/gpu/drm/i915/display/intel_cdclk.c:3477:39: error: 'fixed_400mhz_cdclk_funcs' defined but not used [-Werror=unused-const-variable=]
    3477 | static const struct intel_cdclk_funcs fixed_400mhz_cdclk_funcs = {
         |                                       ^~~~~~~~~~~~~~~~~~~~~~~~
>> drivers/gpu/drm/i915/display/intel_cdclk.c:3471:39: error: 'hsw_cdclk_funcs' defined but not used [-Werror=unused-const-variable=]
    3471 | static const struct intel_cdclk_funcs hsw_cdclk_funcs = {
         |                                       ^~~~~~~~~~~~~~~
>> drivers/gpu/drm/i915/display/intel_cdclk.c:3465:39: error: 'vlv_cdclk_funcs' defined but not used [-Werror=unused-const-variable=]
    3465 | static const struct intel_cdclk_funcs vlv_cdclk_funcs = {
         |                                       ^~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/display/intel_cdclk.c:3459:39: error: 'chv_cdclk_funcs' defined but not used [-Werror=unused-const-variable=]
    3459 | static const struct intel_cdclk_funcs chv_cdclk_funcs = {
         |                                       ^~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/display/intel_cdclk.c:3453:39: error: 'bdw_cdclk_funcs' defined but not used [-Werror=unused-const-variable=]
    3453 | static const struct intel_cdclk_funcs bdw_cdclk_funcs = {
         |                                       ^~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/display/intel_cdclk.c:3447:39: error: 'skl_cdclk_funcs' defined but not used [-Werror=unused-const-variable=]
    3447 | static const struct intel_cdclk_funcs skl_cdclk_funcs = {
         |                                       ^~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/display/intel_cdclk.c:3440:39: error: 'bxt_cdclk_funcs' defined but not used [-Werror=unused-const-variable=]
    3440 | static const struct intel_cdclk_funcs bxt_cdclk_funcs = {
         |                                       ^~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/display/intel_cdclk.c:3433:39: error: 'icl_cdclk_funcs' defined but not used [-Werror=unused-const-variable=]
    3433 | static const struct intel_cdclk_funcs icl_cdclk_funcs = {
         |                                       ^~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/display/intel_cdclk.c:3426:39: error: 'ehl_cdclk_funcs' defined but not used [-Werror=unused-const-variable=]
    3426 | static const struct intel_cdclk_funcs ehl_cdclk_funcs = {
         |                                       ^~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/display/intel_cdclk.c:1272:38: error: 'rkl_cdclk_table' defined but not used [-Werror=unused-const-variable=]
    1272 | static const struct intel_cdclk_vals rkl_cdclk_table[] = {
         |                                      ^~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/display/intel_cdclk.c:1248:38: error: 'icl_cdclk_table' defined but not used [-Werror=unused-const-variable=]
    1248 | static const struct intel_cdclk_vals icl_cdclk_table[] = {
         |                                      ^~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/display/intel_cdclk.c:1241:38: error: 'glk_cdclk_table' defined but not used [-Werror=unused-const-variable=]
    1241 | static const struct intel_cdclk_vals glk_cdclk_table[] = {
         |                                      ^~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/display/intel_cdclk.c:1232:38: error: 'bxt_cdclk_table' defined but not used [-Werror=unused-const-variable=]
    1232 | static const struct intel_cdclk_vals bxt_cdclk_table[] = {
         |                                      ^~~~~~~~~~~~~~~
   cc1: all warnings being treated as errors


vim +/if +3562 drivers/gpu/drm/i915/display/intel_cdclk.c

  3425	
> 3426	static const struct intel_cdclk_funcs ehl_cdclk_funcs = {
  3427		.get_cdclk = bxt_get_cdclk,
  3428		.set_cdclk = bxt_set_cdclk,
  3429		.modeset_calc_cdclk = bxt_modeset_calc_cdclk,
  3430		.calc_voltage_level = ehl_calc_voltage_level,
  3431	};
  3432	
> 3433	static const struct intel_cdclk_funcs icl_cdclk_funcs = {
  3434		.get_cdclk = bxt_get_cdclk,
  3435		.set_cdclk = bxt_set_cdclk,
  3436		.modeset_calc_cdclk = bxt_modeset_calc_cdclk,
  3437		.calc_voltage_level = icl_calc_voltage_level,
  3438	};
  3439	
> 3440	static const struct intel_cdclk_funcs bxt_cdclk_funcs = {
  3441		.get_cdclk = bxt_get_cdclk,
  3442		.set_cdclk = bxt_set_cdclk,
  3443		.modeset_calc_cdclk = bxt_modeset_calc_cdclk,
  3444		.calc_voltage_level = bxt_calc_voltage_level,
  3445	};
  3446	
> 3447	static const struct intel_cdclk_funcs skl_cdclk_funcs = {
  3448		.get_cdclk = skl_get_cdclk,
  3449		.set_cdclk = skl_set_cdclk,
  3450		.modeset_calc_cdclk = skl_modeset_calc_cdclk,
  3451	};
  3452	
> 3453	static const struct intel_cdclk_funcs bdw_cdclk_funcs = {
  3454		.get_cdclk = bdw_get_cdclk,
  3455		.set_cdclk = bdw_set_cdclk,
  3456		.modeset_calc_cdclk = bdw_modeset_calc_cdclk,
  3457	};
  3458	
> 3459	static const struct intel_cdclk_funcs chv_cdclk_funcs = {
  3460		.get_cdclk = vlv_get_cdclk,
  3461		.set_cdclk = chv_set_cdclk,
  3462		.modeset_calc_cdclk = vlv_modeset_calc_cdclk,
  3463	};
  3464	
> 3465	static const struct intel_cdclk_funcs vlv_cdclk_funcs = {
  3466		.get_cdclk = vlv_get_cdclk,
  3467		.set_cdclk = vlv_set_cdclk,
  3468		.modeset_calc_cdclk = vlv_modeset_calc_cdclk,
  3469	};
  3470	
> 3471	static const struct intel_cdclk_funcs hsw_cdclk_funcs = {
  3472		.get_cdclk = hsw_get_cdclk,
  3473		.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
  3474	};
  3475	
  3476	/* SNB, IVB, 965G, 945G */
> 3477	static const struct intel_cdclk_funcs fixed_400mhz_cdclk_funcs = {
  3478		.get_cdclk = fixed_400mhz_get_cdclk,
  3479		.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
  3480	};
  3481	
> 3482	static const struct intel_cdclk_funcs ilk_cdclk_funcs = {
  3483		.get_cdclk = fixed_450mhz_get_cdclk,
  3484		.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
  3485	};
  3486	
> 3487	static const struct intel_cdclk_funcs gm45_cdclk_funcs = {
  3488		.get_cdclk = gm45_get_cdclk,
  3489		.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
  3490	};
  3491	
  3492	/* G45 uses G33 */
  3493	
> 3494	static const struct intel_cdclk_funcs i965gm_cdclk_funcs = {
  3495		.get_cdclk = i965gm_get_cdclk,
  3496		.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
  3497	};
  3498	
  3499	/* i965G uses fixed 400 */
  3500	
> 3501	static const struct intel_cdclk_funcs pnv_cdclk_funcs = {
  3502		.get_cdclk = pnv_get_cdclk,
  3503		.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
  3504	};
  3505	
> 3506	static const struct intel_cdclk_funcs g33_cdclk_funcs = {
  3507		.get_cdclk = g33_get_cdclk,
  3508		.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
  3509	};
  3510	
> 3511	static const struct intel_cdclk_funcs i945gm_cdclk_funcs = {
  3512		.get_cdclk = i945gm_get_cdclk,
  3513		.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
  3514	};
  3515	
  3516	/* i945G uses fixed 400 */
  3517	
> 3518	static const struct intel_cdclk_funcs i915gm_cdclk_funcs = {
  3519		.get_cdclk = i915gm_get_cdclk,
  3520		.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
  3521	};
  3522	
> 3523	static const struct intel_cdclk_funcs i915g_cdclk_funcs = {
  3524		.get_cdclk = fixed_333mhz_get_cdclk,
  3525		.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
  3526	};
  3527	
> 3528	static const struct intel_cdclk_funcs i865g_cdclk_funcs = {
  3529		.get_cdclk = fixed_266mhz_get_cdclk,
  3530		.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
  3531	};
  3532	
> 3533	static const struct intel_cdclk_funcs i85x_cdclk_funcs = {
  3534		.get_cdclk = i85x_get_cdclk,
  3535		.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
  3536	};
  3537	
> 3538	static const struct intel_cdclk_funcs i845g_cdclk_funcs = {
  3539		.get_cdclk = fixed_200mhz_get_cdclk,
  3540		.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
  3541	};
  3542	
> 3543	static const struct intel_cdclk_funcs i830_cdclk_funcs = {
  3544		.get_cdclk = fixed_133mhz_get_cdclk,
  3545		.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
  3546	};
  3547	
  3548	/**
  3549	 * intel_init_cdclk_hooks - Initialize CDCLK related modesetting hooks
  3550	 * @dev_priv: i915 device
  3551	 */
  3552	void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
  3553	{
  3554		if (IS_METEORLAKE(dev_priv)) {
  3555			dev_priv->display.funcs.cdclk = &mtl_cdclk_funcs;
  3556			dev_priv->display.cdclk.table = mtl_cdclk_table;
  3557		} else if (IS_DG2(dev_priv)) {
  3558			dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
  3559			dev_priv->display.cdclk.table = dg2_cdclk_table;
  3560		} else if (IS_ALDERLAKE_P(dev_priv)) {
  3561			/* Wa_22011320316:adl-p[a0] */
> 3562			if (IS_ALDERLAKE_P_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
  3563				dev_priv->display.cdclk.table = adlp_a_step_cdclk_table;
  3564				dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
  3565			} else if (IS_ADLP_RPLU(dev_priv)) {
  3566				dev_priv->display.cdclk.table = rplu_cdclk_table;
  3567				dev_priv->display.funcs.cdclk = &rplu_cdclk_funcs;
  3568			} else {
  3569				dev_priv->display.cdclk.table = adlp_cdclk_table;
  3570				dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
  3571			}
> 3572		} else if (IS_ROCKETLAKE(dev_priv)) {
  3573			dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
  3574			dev_priv->display.cdclk.table = rkl_cdclk_table;
  3575		} else if (DISPLAY_VER(dev_priv) >= 12) {
  3576			dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
  3577			dev_priv->display.cdclk.table = icl_cdclk_table;
  3578		} else if (IS_JASPERLAKE_EHL(dev_priv)) {
  3579			dev_priv->display.funcs.cdclk = &ehl_cdclk_funcs;
  3580			dev_priv->display.cdclk.table = icl_cdclk_table;
  3581		} else if (DISPLAY_VER(dev_priv) >= 11) {
  3582			dev_priv->display.funcs.cdclk = &icl_cdclk_funcs;
  3583			dev_priv->display.cdclk.table = icl_cdclk_table;
  3584		} else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
  3585			dev_priv->display.funcs.cdclk = &bxt_cdclk_funcs;
  3586			if (IS_GEMINILAKE(dev_priv))
  3587				dev_priv->display.cdclk.table = glk_cdclk_table;
  3588			else
  3589				dev_priv->display.cdclk.table = bxt_cdclk_table;
  3590		} else if (DISPLAY_VER(dev_priv) == 9) {
  3591			dev_priv->display.funcs.cdclk = &skl_cdclk_funcs;
  3592		} else if (IS_BROADWELL(dev_priv)) {
  3593			dev_priv->display.funcs.cdclk = &bdw_cdclk_funcs;
  3594		} else if (IS_HASWELL(dev_priv)) {
  3595			dev_priv->display.funcs.cdclk = &hsw_cdclk_funcs;
  3596		} else if (IS_CHERRYVIEW(dev_priv)) {
  3597			dev_priv->display.funcs.cdclk = &chv_cdclk_funcs;
  3598		} else if (IS_VALLEYVIEW(dev_priv)) {
  3599			dev_priv->display.funcs.cdclk = &vlv_cdclk_funcs;
  3600		} else if (IS_SANDYBRIDGE(dev_priv) || IS_IVYBRIDGE(dev_priv)) {
  3601			dev_priv->display.funcs.cdclk = &fixed_400mhz_cdclk_funcs;
  3602		} else if (IS_IRONLAKE(dev_priv)) {
  3603			dev_priv->display.funcs.cdclk = &ilk_cdclk_funcs;
  3604		} else if (IS_GM45(dev_priv)) {
  3605			dev_priv->display.funcs.cdclk = &gm45_cdclk_funcs;
  3606		} else if (IS_G45(dev_priv)) {
  3607			dev_priv->display.funcs.cdclk = &g33_cdclk_funcs;
  3608		} else if (IS_I965GM(dev_priv)) {
  3609			dev_priv->display.funcs.cdclk = &i965gm_cdclk_funcs;
  3610		} else if (IS_I965G(dev_priv)) {
  3611			dev_priv->display.funcs.cdclk = &fixed_400mhz_cdclk_funcs;
  3612		} else if (IS_PINEVIEW(dev_priv)) {
  3613			dev_priv->display.funcs.cdclk = &pnv_cdclk_funcs;
  3614		} else if (IS_G33(dev_priv)) {
  3615			dev_priv->display.funcs.cdclk = &g33_cdclk_funcs;
  3616		} else if (IS_I945GM(dev_priv)) {
  3617			dev_priv->display.funcs.cdclk = &i945gm_cdclk_funcs;
  3618		} else if (IS_I945G(dev_priv)) {
  3619			dev_priv->display.funcs.cdclk = &fixed_400mhz_cdclk_funcs;
  3620		} else if (IS_I915GM(dev_priv)) {
  3621			dev_priv->display.funcs.cdclk = &i915gm_cdclk_funcs;
  3622		} else if (IS_I915G(dev_priv)) {
  3623			dev_priv->display.funcs.cdclk = &i915g_cdclk_funcs;
  3624		} else if (IS_I865G(dev_priv)) {
  3625			dev_priv->display.funcs.cdclk = &i865g_cdclk_funcs;
  3626		} else if (IS_I85X(dev_priv)) {
  3627			dev_priv->display.funcs.cdclk = &i85x_cdclk_funcs;
  3628		} else if (IS_I845G(dev_priv)) {
  3629			dev_priv->display.funcs.cdclk = &i845g_cdclk_funcs;
  3630		} else if (IS_I830(dev_priv)) {
  3631			dev_priv->display.funcs.cdclk = &i830_cdclk_funcs;
  3632		}
  3633	
> 3634		if (drm_WARN(&dev_priv->drm, !dev_priv->display.funcs.cdclk,
  3635			     "Unknown platform. Assuming i830\n"))
  3636			dev_priv->display.funcs.cdclk = &i830_cdclk_funcs;
> 3637	}

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki

Re: [Intel-gfx] [PATCH 07/11] drm/i915/adlp: s/ADLP/ALDERLAKE_P for display and graphics step

[kernel test robot]

Hi Dnyaneshwar,

kernel test robot noticed the following build errors:

[auto build test ERROR on drm-tip/drm-tip]

url:    https://github.com/intel-lab-lkp/linux/commits/Dnyaneshwar-Bhadane/drm-i915-TGL-s-TGL-TIGERLAKE-for-platform-subplatform-defines/20230615-130242
base:   git://anongit.freedesktop.org/drm/drm-tip drm-tip
patch link:    https://lore.kernel.org/r/20230615050015.3105902-8-dnyaneshwar.bhadane%40intel.com
patch subject: [Intel-gfx] [PATCH 07/11] drm/i915/adlp: s/ADLP/ALDERLAKE_P for display and graphics step
config: x86_64-defconfig (https://download.01.org/0day-ci/archive/20230615/202306151523.wIGn4dME-lkp@intel.com/config)
compiler: gcc-12 (Debian 12.2.0-14) 12.2.0
reproduce (this is a W=1 build):
        git remote add drm-tip git://anongit.freedesktop.org/drm/drm-tip
        git fetch drm-tip drm-tip
        git checkout drm-tip/drm-tip
        b4 shazam https://lore.kernel.org/r/20230615050015.3105902-8-dnyaneshwar.bhadane@intel.com
        # save the config file
        mkdir build_dir && cp config build_dir/.config
        make W=1 O=build_dir ARCH=x86_64 olddefconfig
        make W=1 O=build_dir ARCH=x86_64 SHELL=/bin/bash drivers/gpu/drm/i915/

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202306151523.wIGn4dME-lkp@intel.com/

All errors (new ones prefixed by >>):

   drivers/gpu/drm/i915/display/intel_cdclk.c: In function 'intel_init_cdclk_hooks':
>> drivers/gpu/drm/i915/display/intel_cdclk.c:3562:17: error: this 'if' clause does not guard... [-Werror=misleading-indentation]
    3562 |                 if (IS_ALDERLAKE_P_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
         |                 ^~
   drivers/gpu/drm/i915/display/intel_cdclk.c:3564:25: note: ...this statement, but the latter is misleadingly indented as if it were guarded by the 'if'
    3564 |                         dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
         |                         ^~~~~~~~
   drivers/gpu/drm/i915/display/intel_cdclk.c: At top level:
>> drivers/gpu/drm/i915/display/intel_cdclk.c:3572:11: error: expected identifier or '(' before 'else'
    3572 |         } else if (IS_ROCKETLAKE(dev_priv)) {
         |           ^~~~
   drivers/gpu/drm/i915/display/intel_cdclk.c:3575:11: error: expected identifier or '(' before 'else'
    3575 |         } else if (DISPLAY_VER(dev_priv) >= 12) {
         |           ^~~~
   drivers/gpu/drm/i915/display/intel_cdclk.c:3578:11: error: expected identifier or '(' before 'else'
    3578 |         } else if (IS_JASPERLAKE_EHL(dev_priv)) {
         |           ^~~~
   drivers/gpu/drm/i915/display/intel_cdclk.c:3581:11: error: expected identifier or '(' before 'else'
    3581 |         } else if (DISPLAY_VER(dev_priv) >= 11) {
         |           ^~~~
   drivers/gpu/drm/i915/display/intel_cdclk.c:3584:11: error: expected identifier or '(' before 'else'
    3584 |         } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
         |           ^~~~
   drivers/gpu/drm/i915/display/intel_cdclk.c:3590:11: error: expected identifier or '(' before 'else'
    3590 |         } else if (DISPLAY_VER(dev_priv) == 9) {
         |           ^~~~
   drivers/gpu/drm/i915/display/intel_cdclk.c:3592:11: error: expected identifier or '(' before 'else'
    3592 |         } else if (IS_BROADWELL(dev_priv)) {
         |           ^~~~
   drivers/gpu/drm/i915/display/intel_cdclk.c:3594:11: error: expected identifier or '(' before 'else'
    3594 |         } else if (IS_HASWELL(dev_priv)) {
         |           ^~~~
   drivers/gpu/drm/i915/display/intel_cdclk.c:3596:11: error: expected identifier or '(' before 'else'
    3596 |         } else if (IS_CHERRYVIEW(dev_priv)) {
         |           ^~~~
   drivers/gpu/drm/i915/display/intel_cdclk.c:3598:11: error: expected identifier or '(' before 'else'
    3598 |         } else if (IS_VALLEYVIEW(dev_priv)) {
         |           ^~~~
   drivers/gpu/drm/i915/display/intel_cdclk.c:3600:11: error: expected identifier or '(' before 'else'
    3600 |         } else if (IS_SANDYBRIDGE(dev_priv) || IS_IVYBRIDGE(dev_priv)) {
         |           ^~~~
   drivers/gpu/drm/i915/display/intel_cdclk.c:3602:11: error: expected identifier or '(' before 'else'
    3602 |         } else if (IS_IRONLAKE(dev_priv)) {
         |           ^~~~
   drivers/gpu/drm/i915/display/intel_cdclk.c:3604:11: error: expected identifier or '(' before 'else'
    3604 |         } else if (IS_GM45(dev_priv)) {
         |           ^~~~
   drivers/gpu/drm/i915/display/intel_cdclk.c:3606:11: error: expected identifier or '(' before 'else'
    3606 |         } else if (IS_G45(dev_priv)) {
         |           ^~~~
   drivers/gpu/drm/i915/display/intel_cdclk.c:3608:11: error: expected identifier or '(' before 'else'
    3608 |         } else if (IS_I965GM(dev_priv)) {
         |           ^~~~
   drivers/gpu/drm/i915/display/intel_cdclk.c:3610:11: error: expected identifier or '(' before 'else'
    3610 |         } else if (IS_I965G(dev_priv)) {
         |           ^~~~
   drivers/gpu/drm/i915/display/intel_cdclk.c:3612:11: error: expected identifier or '(' before 'else'
    3612 |         } else if (IS_PINEVIEW(dev_priv)) {
         |           ^~~~
   drivers/gpu/drm/i915/display/intel_cdclk.c:3614:11: error: expected identifier or '(' before 'else'
    3614 |         } else if (IS_G33(dev_priv)) {
         |           ^~~~
   drivers/gpu/drm/i915/display/intel_cdclk.c:3616:11: error: expected identifier or '(' before 'else'
    3616 |         } else if (IS_I945GM(dev_priv)) {
         |           ^~~~
   drivers/gpu/drm/i915/display/intel_cdclk.c:3618:11: error: expected identifier or '(' before 'else'
    3618 |         } else if (IS_I945G(dev_priv)) {
         |           ^~~~
   drivers/gpu/drm/i915/display/intel_cdclk.c:3620:11: error: expected identifier or '(' before 'else'
    3620 |         } else if (IS_I915GM(dev_priv)) {
         |           ^~~~
   drivers/gpu/drm/i915/display/intel_cdclk.c:3622:11: error: expected identifier or '(' before 'else'
    3622 |         } else if (IS_I915G(dev_priv)) {
         |           ^~~~
   drivers/gpu/drm/i915/display/intel_cdclk.c:3624:11: error: expected identifier or '(' before 'else'
    3624 |         } else if (IS_I865G(dev_priv)) {
         |           ^~~~
   drivers/gpu/drm/i915/display/intel_cdclk.c:3626:11: error: expected identifier or '(' before 'else'
    3626 |         } else if (IS_I85X(dev_priv)) {
         |           ^~~~
   drivers/gpu/drm/i915/display/intel_cdclk.c:3628:11: error: expected identifier or '(' before 'else'
    3628 |         } else if (IS_I845G(dev_priv)) {
         |           ^~~~
   drivers/gpu/drm/i915/display/intel_cdclk.c:3630:11: error: expected identifier or '(' before 'else'
    3630 |         } else if (IS_I830(dev_priv)) {
         |           ^~~~
>> drivers/gpu/drm/i915/display/intel_cdclk.c:3634:9: error: expected identifier or '(' before 'if'
    3634 |         if (drm_WARN(&dev_priv->drm, !dev_priv->display.funcs.cdclk,
         |         ^~
   In file included from arch/x86/include/asm/bug.h:87,
                    from include/linux/bug.h:5,
                    from include/linux/cpumask.h:14,
                    from arch/x86/include/asm/cpumask.h:5,
                    from arch/x86/include/asm/msr.h:11,
                    from arch/x86/include/asm/processor.h:23,
                    from arch/x86/include/asm/timex.h:5,
                    from include/linux/timex.h:67,
                    from include/linux/time32.h:13,
                    from include/linux/time.h:60,
                    from drivers/gpu/drm/i915/display/intel_cdclk.c:24:
>> include/asm-generic/bug.h:135:2: error: expected identifier or '(' before ')' token
     135 | })
         |  ^
   include/drm/drm_print.h:620:9: note: in expansion of macro 'WARN'
     620 |         WARN(condition, "%s %s: " format,                               \
         |         ^~~~
   drivers/gpu/drm/i915/display/intel_cdclk.c:3634:13: note: in expansion of macro 'drm_WARN'
    3634 |         if (drm_WARN(&dev_priv->drm, !dev_priv->display.funcs.cdclk,
         |             ^~~~~~~~
>> drivers/gpu/drm/i915/display/intel_cdclk.c:3637:1: error: expected identifier or '(' before '}' token
    3637 | }
         | ^
>> drivers/gpu/drm/i915/display/intel_cdclk.c:3543:39: error: 'i830_cdclk_funcs' defined but not used [-Werror=unused-const-variable=]
    3543 | static const struct intel_cdclk_funcs i830_cdclk_funcs = {
         |                                       ^~~~~~~~~~~~~~~~
>> drivers/gpu/drm/i915/display/intel_cdclk.c:3538:39: error: 'i845g_cdclk_funcs' defined but not used [-Werror=unused-const-variable=]
    3538 | static const struct intel_cdclk_funcs i845g_cdclk_funcs = {
         |                                       ^~~~~~~~~~~~~~~~~
>> drivers/gpu/drm/i915/display/intel_cdclk.c:3533:39: error: 'i85x_cdclk_funcs' defined but not used [-Werror=unused-const-variable=]
    3533 | static const struct intel_cdclk_funcs i85x_cdclk_funcs = {
         |                                       ^~~~~~~~~~~~~~~~
>> drivers/gpu/drm/i915/display/intel_cdclk.c:3528:39: error: 'i865g_cdclk_funcs' defined but not used [-Werror=unused-const-variable=]
    3528 | static const struct intel_cdclk_funcs i865g_cdclk_funcs = {
         |                                       ^~~~~~~~~~~~~~~~~
>> drivers/gpu/drm/i915/display/intel_cdclk.c:3523:39: error: 'i915g_cdclk_funcs' defined but not used [-Werror=unused-const-variable=]
    3523 | static const struct intel_cdclk_funcs i915g_cdclk_funcs = {
         |                                       ^~~~~~~~~~~~~~~~~
>> drivers/gpu/drm/i915/display/intel_cdclk.c:3518:39: error: 'i915gm_cdclk_funcs' defined but not used [-Werror=unused-const-variable=]
    3518 | static const struct intel_cdclk_funcs i915gm_cdclk_funcs = {
         |                                       ^~~~~~~~~~~~~~~~~~
>> drivers/gpu/drm/i915/display/intel_cdclk.c:3511:39: error: 'i945gm_cdclk_funcs' defined but not used [-Werror=unused-const-variable=]
    3511 | static const struct intel_cdclk_funcs i945gm_cdclk_funcs = {
         |                                       ^~~~~~~~~~~~~~~~~~
>> drivers/gpu/drm/i915/display/intel_cdclk.c:3506:39: error: 'g33_cdclk_funcs' defined but not used [-Werror=unused-const-variable=]
    3506 | static const struct intel_cdclk_funcs g33_cdclk_funcs = {
         |                                       ^~~~~~~~~~~~~~~
>> drivers/gpu/drm/i915/display/intel_cdclk.c:3501:39: error: 'pnv_cdclk_funcs' defined but not used [-Werror=unused-const-variable=]
    3501 | static const struct intel_cdclk_funcs pnv_cdclk_funcs = {
         |                                       ^~~~~~~~~~~~~~~
>> drivers/gpu/drm/i915/display/intel_cdclk.c:3494:39: error: 'i965gm_cdclk_funcs' defined but not used [-Werror=unused-const-variable=]
    3494 | static const struct intel_cdclk_funcs i965gm_cdclk_funcs = {
         |                                       ^~~~~~~~~~~~~~~~~~
>> drivers/gpu/drm/i915/display/intel_cdclk.c:3487:39: error: 'gm45_cdclk_funcs' defined but not used [-Werror=unused-const-variable=]
    3487 | static const struct intel_cdclk_funcs gm45_cdclk_funcs = {
         |                                       ^~~~~~~~~~~~~~~~
>> drivers/gpu/drm/i915/display/intel_cdclk.c:3482:39: error: 'ilk_cdclk_funcs' defined but not used [-Werror=unused-const-variable=]
    3482 | static const struct intel_cdclk_funcs ilk_cdclk_funcs = {
         |                                       ^~~~~~~~~~~~~~~
>> drivers/gpu/drm/i915/display/intel_cdclk.c:3477:39: error: 'fixed_400mhz_cdclk_funcs' defined but not used [-Werror=unused-const-variable=]
    3477 | static const struct intel_cdclk_funcs fixed_400mhz_cdclk_funcs = {
         |                                       ^~~~~~~~~~~~~~~~~~~~~~~~
>> drivers/gpu/drm/i915/display/intel_cdclk.c:3471:39: error: 'hsw_cdclk_funcs' defined but not used [-Werror=unused-const-variable=]
    3471 | static const struct intel_cdclk_funcs hsw_cdclk_funcs = {
         |                                       ^~~~~~~~~~~~~~~
>> drivers/gpu/drm/i915/display/intel_cdclk.c:3465:39: error: 'vlv_cdclk_funcs' defined but not used [-Werror=unused-const-variable=]
    3465 | static const struct intel_cdclk_funcs vlv_cdclk_funcs = {
         |                                       ^~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/display/intel_cdclk.c:3459:39: error: 'chv_cdclk_funcs' defined but not used [-Werror=unused-const-variable=]
    3459 | static const struct intel_cdclk_funcs chv_cdclk_funcs = {
         |                                       ^~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/display/intel_cdclk.c:3453:39: error: 'bdw_cdclk_funcs' defined but not used [-Werror=unused-const-variable=]
    3453 | static const struct intel_cdclk_funcs bdw_cdclk_funcs = {
         |                                       ^~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/display/intel_cdclk.c:3447:39: error: 'skl_cdclk_funcs' defined but not used [-Werror=unused-const-variable=]
    3447 | static const struct intel_cdclk_funcs skl_cdclk_funcs = {
         |                                       ^~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/display/intel_cdclk.c:3440:39: error: 'bxt_cdclk_funcs' defined but not used [-Werror=unused-const-variable=]
    3440 | static const struct intel_cdclk_funcs bxt_cdclk_funcs = {
         |                                       ^~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/display/intel_cdclk.c:3433:39: error: 'icl_cdclk_funcs' defined but not used [-Werror=unused-const-variable=]
    3433 | static const struct intel_cdclk_funcs icl_cdclk_funcs = {
         |                                       ^~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/display/intel_cdclk.c:3426:39: error: 'ehl_cdclk_funcs' defined but not used [-Werror=unused-const-variable=]
    3426 | static const struct intel_cdclk_funcs ehl_cdclk_funcs = {
         |                                       ^~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/display/intel_cdclk.c:1272:38: error: 'rkl_cdclk_table' defined but not used [-Werror=unused-const-variable=]
    1272 | static const struct intel_cdclk_vals rkl_cdclk_table[] = {
         |                                      ^~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/display/intel_cdclk.c:1248:38: error: 'icl_cdclk_table' defined but not used [-Werror=unused-const-variable=]
    1248 | static const struct intel_cdclk_vals icl_cdclk_table[] = {
         |                                      ^~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/display/intel_cdclk.c:1241:38: error: 'glk_cdclk_table' defined but not used [-Werror=unused-const-variable=]
    1241 | static const struct intel_cdclk_vals glk_cdclk_table[] = {
         |                                      ^~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/display/intel_cdclk.c:1232:38: error: 'bxt_cdclk_table' defined but not used [-Werror=unused-const-variable=]
    1232 | static const struct intel_cdclk_vals bxt_cdclk_table[] = {
         |                                      ^~~~~~~~~~~~~~~
   cc1: all warnings being treated as errors


vim +/if +3562 drivers/gpu/drm/i915/display/intel_cdclk.c

  3425	
> 3426	static const struct intel_cdclk_funcs ehl_cdclk_funcs = {
  3427		.get_cdclk = bxt_get_cdclk,
  3428		.set_cdclk = bxt_set_cdclk,
  3429		.modeset_calc_cdclk = bxt_modeset_calc_cdclk,
  3430		.calc_voltage_level = ehl_calc_voltage_level,
  3431	};
  3432	
> 3433	static const struct intel_cdclk_funcs icl_cdclk_funcs = {
  3434		.get_cdclk = bxt_get_cdclk,
  3435		.set_cdclk = bxt_set_cdclk,
  3436		.modeset_calc_cdclk = bxt_modeset_calc_cdclk,
  3437		.calc_voltage_level = icl_calc_voltage_level,
  3438	};
  3439	
> 3440	static const struct intel_cdclk_funcs bxt_cdclk_funcs = {
  3441		.get_cdclk = bxt_get_cdclk,
  3442		.set_cdclk = bxt_set_cdclk,
  3443		.modeset_calc_cdclk = bxt_modeset_calc_cdclk,
  3444		.calc_voltage_level = bxt_calc_voltage_level,
  3445	};
  3446	
> 3447	static const struct intel_cdclk_funcs skl_cdclk_funcs = {
  3448		.get_cdclk = skl_get_cdclk,
  3449		.set_cdclk = skl_set_cdclk,
  3450		.modeset_calc_cdclk = skl_modeset_calc_cdclk,
  3451	};
  3452	
> 3453	static const struct intel_cdclk_funcs bdw_cdclk_funcs = {
  3454		.get_cdclk = bdw_get_cdclk,
  3455		.set_cdclk = bdw_set_cdclk,
  3456		.modeset_calc_cdclk = bdw_modeset_calc_cdclk,
  3457	};
  3458	
> 3459	static const struct intel_cdclk_funcs chv_cdclk_funcs = {
  3460		.get_cdclk = vlv_get_cdclk,
  3461		.set_cdclk = chv_set_cdclk,
  3462		.modeset_calc_cdclk = vlv_modeset_calc_cdclk,
  3463	};
  3464	
> 3465	static const struct intel_cdclk_funcs vlv_cdclk_funcs = {
  3466		.get_cdclk = vlv_get_cdclk,
  3467		.set_cdclk = vlv_set_cdclk,
  3468		.modeset_calc_cdclk = vlv_modeset_calc_cdclk,
  3469	};
  3470	
> 3471	static const struct intel_cdclk_funcs hsw_cdclk_funcs = {
  3472		.get_cdclk = hsw_get_cdclk,
  3473		.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
  3474	};
  3475	
  3476	/* SNB, IVB, 965G, 945G */
> 3477	static const struct intel_cdclk_funcs fixed_400mhz_cdclk_funcs = {
  3478		.get_cdclk = fixed_400mhz_get_cdclk,
  3479		.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
  3480	};
  3481	
> 3482	static const struct intel_cdclk_funcs ilk_cdclk_funcs = {
  3483		.get_cdclk = fixed_450mhz_get_cdclk,
  3484		.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
  3485	};
  3486	
> 3487	static const struct intel_cdclk_funcs gm45_cdclk_funcs = {
  3488		.get_cdclk = gm45_get_cdclk,
  3489		.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
  3490	};
  3491	
  3492	/* G45 uses G33 */
  3493	
> 3494	static const struct intel_cdclk_funcs i965gm_cdclk_funcs = {
  3495		.get_cdclk = i965gm_get_cdclk,
  3496		.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
  3497	};
  3498	
  3499	/* i965G uses fixed 400 */
  3500	
> 3501	static const struct intel_cdclk_funcs pnv_cdclk_funcs = {
  3502		.get_cdclk = pnv_get_cdclk,
  3503		.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
  3504	};
  3505	
> 3506	static const struct intel_cdclk_funcs g33_cdclk_funcs = {
  3507		.get_cdclk = g33_get_cdclk,
  3508		.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
  3509	};
  3510	
> 3511	static const struct intel_cdclk_funcs i945gm_cdclk_funcs = {
  3512		.get_cdclk = i945gm_get_cdclk,
  3513		.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
  3514	};
  3515	
  3516	/* i945G uses fixed 400 */
  3517	
> 3518	static const struct intel_cdclk_funcs i915gm_cdclk_funcs = {
  3519		.get_cdclk = i915gm_get_cdclk,
  3520		.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
  3521	};
  3522	
> 3523	static const struct intel_cdclk_funcs i915g_cdclk_funcs = {
  3524		.get_cdclk = fixed_333mhz_get_cdclk,
  3525		.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
  3526	};
  3527	
> 3528	static const struct intel_cdclk_funcs i865g_cdclk_funcs = {
  3529		.get_cdclk = fixed_266mhz_get_cdclk,
  3530		.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
  3531	};
  3532	
> 3533	static const struct intel_cdclk_funcs i85x_cdclk_funcs = {
  3534		.get_cdclk = i85x_get_cdclk,
  3535		.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
  3536	};
  3537	
> 3538	static const struct intel_cdclk_funcs i845g_cdclk_funcs = {
  3539		.get_cdclk = fixed_200mhz_get_cdclk,
  3540		.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
  3541	};
  3542	
> 3543	static const struct intel_cdclk_funcs i830_cdclk_funcs = {
  3544		.get_cdclk = fixed_133mhz_get_cdclk,
  3545		.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
  3546	};
  3547	
  3548	/**
  3549	 * intel_init_cdclk_hooks - Initialize CDCLK related modesetting hooks
  3550	 * @dev_priv: i915 device
  3551	 */
  3552	void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
  3553	{
  3554		if (IS_METEORLAKE(dev_priv)) {
  3555			dev_priv->display.funcs.cdclk = &mtl_cdclk_funcs;
  3556			dev_priv->display.cdclk.table = mtl_cdclk_table;
  3557		} else if (IS_DG2(dev_priv)) {
  3558			dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
  3559			dev_priv->display.cdclk.table = dg2_cdclk_table;
  3560		} else if (IS_ALDERLAKE_P(dev_priv)) {
  3561			/* Wa_22011320316:adl-p[a0] */
> 3562			if (IS_ALDERLAKE_P_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
  3563				dev_priv->display.cdclk.table = adlp_a_step_cdclk_table;
  3564				dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
  3565			} else if (IS_ADLP_RPLU(dev_priv)) {
  3566				dev_priv->display.cdclk.table = rplu_cdclk_table;
  3567				dev_priv->display.funcs.cdclk = &rplu_cdclk_funcs;
  3568			} else {
  3569				dev_priv->display.cdclk.table = adlp_cdclk_table;
  3570				dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
  3571			}
> 3572		} else if (IS_ROCKETLAKE(dev_priv)) {
  3573			dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
  3574			dev_priv->display.cdclk.table = rkl_cdclk_table;
  3575		} else if (DISPLAY_VER(dev_priv) >= 12) {
  3576			dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
  3577			dev_priv->display.cdclk.table = icl_cdclk_table;
  3578		} else if (IS_JASPERLAKE_EHL(dev_priv)) {
  3579			dev_priv->display.funcs.cdclk = &ehl_cdclk_funcs;
  3580			dev_priv->display.cdclk.table = icl_cdclk_table;
  3581		} else if (DISPLAY_VER(dev_priv) >= 11) {
  3582			dev_priv->display.funcs.cdclk = &icl_cdclk_funcs;
  3583			dev_priv->display.cdclk.table = icl_cdclk_table;
  3584		} else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
  3585			dev_priv->display.funcs.cdclk = &bxt_cdclk_funcs;
  3586			if (IS_GEMINILAKE(dev_priv))
  3587				dev_priv->display.cdclk.table = glk_cdclk_table;
  3588			else
  3589				dev_priv->display.cdclk.table = bxt_cdclk_table;
  3590		} else if (DISPLAY_VER(dev_priv) == 9) {
  3591			dev_priv->display.funcs.cdclk = &skl_cdclk_funcs;
  3592		} else if (IS_BROADWELL(dev_priv)) {
  3593			dev_priv->display.funcs.cdclk = &bdw_cdclk_funcs;
  3594		} else if (IS_HASWELL(dev_priv)) {
  3595			dev_priv->display.funcs.cdclk = &hsw_cdclk_funcs;
  3596		} else if (IS_CHERRYVIEW(dev_priv)) {
  3597			dev_priv->display.funcs.cdclk = &chv_cdclk_funcs;
  3598		} else if (IS_VALLEYVIEW(dev_priv)) {
  3599			dev_priv->display.funcs.cdclk = &vlv_cdclk_funcs;
  3600		} else if (IS_SANDYBRIDGE(dev_priv) || IS_IVYBRIDGE(dev_priv)) {
  3601			dev_priv->display.funcs.cdclk = &fixed_400mhz_cdclk_funcs;
  3602		} else if (IS_IRONLAKE(dev_priv)) {
  3603			dev_priv->display.funcs.cdclk = &ilk_cdclk_funcs;
  3604		} else if (IS_GM45(dev_priv)) {
  3605			dev_priv->display.funcs.cdclk = &gm45_cdclk_funcs;
  3606		} else if (IS_G45(dev_priv)) {
  3607			dev_priv->display.funcs.cdclk = &g33_cdclk_funcs;
  3608		} else if (IS_I965GM(dev_priv)) {
  3609			dev_priv->display.funcs.cdclk = &i965gm_cdclk_funcs;
  3610		} else if (IS_I965G(dev_priv)) {
  3611			dev_priv->display.funcs.cdclk = &fixed_400mhz_cdclk_funcs;
  3612		} else if (IS_PINEVIEW(dev_priv)) {
  3613			dev_priv->display.funcs.cdclk = &pnv_cdclk_funcs;
  3614		} else if (IS_G33(dev_priv)) {
  3615			dev_priv->display.funcs.cdclk = &g33_cdclk_funcs;
  3616		} else if (IS_I945GM(dev_priv)) {
  3617			dev_priv->display.funcs.cdclk = &i945gm_cdclk_funcs;
  3618		} else if (IS_I945G(dev_priv)) {
  3619			dev_priv->display.funcs.cdclk = &fixed_400mhz_cdclk_funcs;
  3620		} else if (IS_I915GM(dev_priv)) {
  3621			dev_priv->display.funcs.cdclk = &i915gm_cdclk_funcs;
  3622		} else if (IS_I915G(dev_priv)) {
  3623			dev_priv->display.funcs.cdclk = &i915g_cdclk_funcs;
  3624		} else if (IS_I865G(dev_priv)) {
  3625			dev_priv->display.funcs.cdclk = &i865g_cdclk_funcs;
  3626		} else if (IS_I85X(dev_priv)) {
  3627			dev_priv->display.funcs.cdclk = &i85x_cdclk_funcs;
  3628		} else if (IS_I845G(dev_priv)) {
  3629			dev_priv->display.funcs.cdclk = &i845g_cdclk_funcs;
  3630		} else if (IS_I830(dev_priv)) {
  3631			dev_priv->display.funcs.cdclk = &i830_cdclk_funcs;
  3632		}
  3633	
> 3634		if (drm_WARN(&dev_priv->drm, !dev_priv->display.funcs.cdclk,
  3635			     "Unknown platform. Assuming i830\n"))
  3636			dev_priv->display.funcs.cdclk = &i830_cdclk_funcs;
> 3637	}

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki

Re: [Intel-gfx] [PATCH 07/11] drm/i915/adlp: s/ADLP/ALDERLAKE_P for display and graphics step

[kernel test robot]

Hi Dnyaneshwar,

kernel test robot noticed the following build warnings:

[auto build test WARNING on drm-tip/drm-tip]

url:    https://github.com/intel-lab-lkp/linux/commits/Dnyaneshwar-Bhadane/drm-i915-TGL-s-TGL-TIGERLAKE-for-platform-subplatform-defines/20230615-130242
base:   git://anongit.freedesktop.org/drm/drm-tip drm-tip
patch link:    https://lore.kernel.org/r/20230615050015.3105902-8-dnyaneshwar.bhadane%40intel.com
patch subject: [Intel-gfx] [PATCH 07/11] drm/i915/adlp: s/ADLP/ALDERLAKE_P for display and graphics step
config: i386-debian-10.3 (https://download.01.org/0day-ci/archive/20230615/202306151502.QcAZXboK-lkp@intel.com/config)
compiler: gcc-12 (Debian 12.2.0-14) 12.2.0
reproduce (this is a W=1 build):
        git remote add drm-tip git://anongit.freedesktop.org/drm/drm-tip
        git fetch drm-tip drm-tip
        git checkout drm-tip/drm-tip
        b4 shazam https://lore.kernel.org/r/20230615050015.3105902-8-dnyaneshwar.bhadane@intel.com
        # save the config file
        mkdir build_dir && cp config build_dir/.config
        make W=1 O=build_dir ARCH=i386 olddefconfig
        make W=1 O=build_dir ARCH=i386 SHELL=/bin/bash drivers/gpu/drm/i915/

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202306151502.QcAZXboK-lkp@intel.com/

All warnings (new ones prefixed by >>):

   drivers/gpu/drm/i915/display/intel_cdclk.c: In function 'intel_init_cdclk_hooks':
>> drivers/gpu/drm/i915/display/intel_cdclk.c:3562:17: warning: this 'if' clause does not guard... [-Wmisleading-indentation]
    3562 |                 if (IS_ALDERLAKE_P_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
         |                 ^~
   drivers/gpu/drm/i915/display/intel_cdclk.c:3564:25: note: ...this statement, but the latter is misleadingly indented as if it were guarded by the 'if'
    3564 |                         dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
         |                         ^~~~~~~~
   drivers/gpu/drm/i915/display/intel_cdclk.c: At top level:
   drivers/gpu/drm/i915/display/intel_cdclk.c:3572:11: error: expected identifier or '(' before 'else'
    3572 |         } else if (IS_ROCKETLAKE(dev_priv)) {
         |           ^~~~
   drivers/gpu/drm/i915/display/intel_cdclk.c:3575:11: error: expected identifier or '(' before 'else'
    3575 |         } else if (DISPLAY_VER(dev_priv) >= 12) {
         |           ^~~~
   drivers/gpu/drm/i915/display/intel_cdclk.c:3578:11: error: expected identifier or '(' before 'else'
    3578 |         } else if (IS_JASPERLAKE_EHL(dev_priv)) {
         |           ^~~~
   drivers/gpu/drm/i915/display/intel_cdclk.c:3581:11: error: expected identifier or '(' before 'else'
    3581 |         } else if (DISPLAY_VER(dev_priv) >= 11) {
         |           ^~~~
   drivers/gpu/drm/i915/display/intel_cdclk.c:3584:11: error: expected identifier or '(' before 'else'
    3584 |         } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
         |           ^~~~
   drivers/gpu/drm/i915/display/intel_cdclk.c:3590:11: error: expected identifier or '(' before 'else'
    3590 |         } else if (DISPLAY_VER(dev_priv) == 9) {
         |           ^~~~
   drivers/gpu/drm/i915/display/intel_cdclk.c:3592:11: error: expected identifier or '(' before 'else'
    3592 |         } else if (IS_BROADWELL(dev_priv)) {
         |           ^~~~
   drivers/gpu/drm/i915/display/intel_cdclk.c:3594:11: error: expected identifier or '(' before 'else'
    3594 |         } else if (IS_HASWELL(dev_priv)) {
         |           ^~~~
   drivers/gpu/drm/i915/display/intel_cdclk.c:3596:11: error: expected identifier or '(' before 'else'
    3596 |         } else if (IS_CHERRYVIEW(dev_priv)) {
         |           ^~~~
   drivers/gpu/drm/i915/display/intel_cdclk.c:3598:11: error: expected identifier or '(' before 'else'
    3598 |         } else if (IS_VALLEYVIEW(dev_priv)) {
         |           ^~~~
   drivers/gpu/drm/i915/display/intel_cdclk.c:3600:11: error: expected identifier or '(' before 'else'
    3600 |         } else if (IS_SANDYBRIDGE(dev_priv) || IS_IVYBRIDGE(dev_priv)) {
         |           ^~~~
   drivers/gpu/drm/i915/display/intel_cdclk.c:3602:11: error: expected identifier or '(' before 'else'
    3602 |         } else if (IS_IRONLAKE(dev_priv)) {
         |           ^~~~
   drivers/gpu/drm/i915/display/intel_cdclk.c:3604:11: error: expected identifier or '(' before 'else'
    3604 |         } else if (IS_GM45(dev_priv)) {
         |           ^~~~
   drivers/gpu/drm/i915/display/intel_cdclk.c:3606:11: error: expected identifier or '(' before 'else'
    3606 |         } else if (IS_G45(dev_priv)) {
         |           ^~~~
   drivers/gpu/drm/i915/display/intel_cdclk.c:3608:11: error: expected identifier or '(' before 'else'
    3608 |         } else if (IS_I965GM(dev_priv)) {
         |           ^~~~
   drivers/gpu/drm/i915/display/intel_cdclk.c:3610:11: error: expected identifier or '(' before 'else'
    3610 |         } else if (IS_I965G(dev_priv)) {
         |           ^~~~
   drivers/gpu/drm/i915/display/intel_cdclk.c:3612:11: error: expected identifier or '(' before 'else'
    3612 |         } else if (IS_PINEVIEW(dev_priv)) {
         |           ^~~~
   drivers/gpu/drm/i915/display/intel_cdclk.c:3614:11: error: expected identifier or '(' before 'else'
    3614 |         } else if (IS_G33(dev_priv)) {
         |           ^~~~
   drivers/gpu/drm/i915/display/intel_cdclk.c:3616:11: error: expected identifier or '(' before 'else'
    3616 |         } else if (IS_I945GM(dev_priv)) {
         |           ^~~~
   drivers/gpu/drm/i915/display/intel_cdclk.c:3618:11: error: expected identifier or '(' before 'else'
    3618 |         } else if (IS_I945G(dev_priv)) {
         |           ^~~~
   drivers/gpu/drm/i915/display/intel_cdclk.c:3620:11: error: expected identifier or '(' before 'else'
    3620 |         } else if (IS_I915GM(dev_priv)) {
         |           ^~~~
   drivers/gpu/drm/i915/display/intel_cdclk.c:3622:11: error: expected identifier or '(' before 'else'
    3622 |         } else if (IS_I915G(dev_priv)) {
         |           ^~~~
   drivers/gpu/drm/i915/display/intel_cdclk.c:3624:11: error: expected identifier or '(' before 'else'
    3624 |         } else if (IS_I865G(dev_priv)) {
         |           ^~~~
   drivers/gpu/drm/i915/display/intel_cdclk.c:3626:11: error: expected identifier or '(' before 'else'
    3626 |         } else if (IS_I85X(dev_priv)) {
         |           ^~~~
   drivers/gpu/drm/i915/display/intel_cdclk.c:3628:11: error: expected identifier or '(' before 'else'
    3628 |         } else if (IS_I845G(dev_priv)) {
         |           ^~~~
   drivers/gpu/drm/i915/display/intel_cdclk.c:3630:11: error: expected identifier or '(' before 'else'
    3630 |         } else if (IS_I830(dev_priv)) {
         |           ^~~~
   drivers/gpu/drm/i915/display/intel_cdclk.c:3634:9: error: expected identifier or '(' before 'if'
    3634 |         if (drm_WARN(&dev_priv->drm, !dev_priv->display.funcs.cdclk,
         |         ^~
   In file included from arch/x86/include/asm/bug.h:87,
                    from include/linux/bug.h:5,
                    from include/linux/fortify-string.h:5,
                    from include/linux/string.h:254,
                    from arch/x86/include/asm/page_32.h:18,
                    from arch/x86/include/asm/page.h:14,
                    from arch/x86/include/asm/processor.h:20,
                    from arch/x86/include/asm/timex.h:5,
                    from include/linux/timex.h:67,
                    from include/linux/time32.h:13,
                    from include/linux/time.h:60,
                    from drivers/gpu/drm/i915/display/intel_cdclk.c:24:
   include/asm-generic/bug.h:135:2: error: expected identifier or '(' before ')' token
     135 | })
         |  ^
   include/drm/drm_print.h:620:9: note: in expansion of macro 'WARN'
     620 |         WARN(condition, "%s %s: " format,                               \
         |         ^~~~
   drivers/gpu/drm/i915/display/intel_cdclk.c:3634:13: note: in expansion of macro 'drm_WARN'
    3634 |         if (drm_WARN(&dev_priv->drm, !dev_priv->display.funcs.cdclk,
         |             ^~~~~~~~
   drivers/gpu/drm/i915/display/intel_cdclk.c:3637:1: error: expected identifier or '(' before '}' token
    3637 | }
         | ^
>> drivers/gpu/drm/i915/display/intel_cdclk.c:3543:39: warning: 'i830_cdclk_funcs' defined but not used [-Wunused-const-variable=]
    3543 | static const struct intel_cdclk_funcs i830_cdclk_funcs = {
         |                                       ^~~~~~~~~~~~~~~~
>> drivers/gpu/drm/i915/display/intel_cdclk.c:3538:39: warning: 'i845g_cdclk_funcs' defined but not used [-Wunused-const-variable=]
    3538 | static const struct intel_cdclk_funcs i845g_cdclk_funcs = {
         |                                       ^~~~~~~~~~~~~~~~~
>> drivers/gpu/drm/i915/display/intel_cdclk.c:3533:39: warning: 'i85x_cdclk_funcs' defined but not used [-Wunused-const-variable=]
    3533 | static const struct intel_cdclk_funcs i85x_cdclk_funcs = {
         |                                       ^~~~~~~~~~~~~~~~
>> drivers/gpu/drm/i915/display/intel_cdclk.c:3528:39: warning: 'i865g_cdclk_funcs' defined but not used [-Wunused-const-variable=]
    3528 | static const struct intel_cdclk_funcs i865g_cdclk_funcs = {
         |                                       ^~~~~~~~~~~~~~~~~
>> drivers/gpu/drm/i915/display/intel_cdclk.c:3523:39: warning: 'i915g_cdclk_funcs' defined but not used [-Wunused-const-variable=]
    3523 | static const struct intel_cdclk_funcs i915g_cdclk_funcs = {
         |                                       ^~~~~~~~~~~~~~~~~
>> drivers/gpu/drm/i915/display/intel_cdclk.c:3518:39: warning: 'i915gm_cdclk_funcs' defined but not used [-Wunused-const-variable=]
    3518 | static const struct intel_cdclk_funcs i915gm_cdclk_funcs = {
         |                                       ^~~~~~~~~~~~~~~~~~
>> drivers/gpu/drm/i915/display/intel_cdclk.c:3511:39: warning: 'i945gm_cdclk_funcs' defined but not used [-Wunused-const-variable=]
    3511 | static const struct intel_cdclk_funcs i945gm_cdclk_funcs = {
         |                                       ^~~~~~~~~~~~~~~~~~
>> drivers/gpu/drm/i915/display/intel_cdclk.c:3506:39: warning: 'g33_cdclk_funcs' defined but not used [-Wunused-const-variable=]
    3506 | static const struct intel_cdclk_funcs g33_cdclk_funcs = {
         |                                       ^~~~~~~~~~~~~~~
>> drivers/gpu/drm/i915/display/intel_cdclk.c:3501:39: warning: 'pnv_cdclk_funcs' defined but not used [-Wunused-const-variable=]
    3501 | static const struct intel_cdclk_funcs pnv_cdclk_funcs = {
         |                                       ^~~~~~~~~~~~~~~
>> drivers/gpu/drm/i915/display/intel_cdclk.c:3494:39: warning: 'i965gm_cdclk_funcs' defined but not used [-Wunused-const-variable=]
    3494 | static const struct intel_cdclk_funcs i965gm_cdclk_funcs = {
         |                                       ^~~~~~~~~~~~~~~~~~
>> drivers/gpu/drm/i915/display/intel_cdclk.c:3487:39: warning: 'gm45_cdclk_funcs' defined but not used [-Wunused-const-variable=]
    3487 | static const struct intel_cdclk_funcs gm45_cdclk_funcs = {
         |                                       ^~~~~~~~~~~~~~~~
>> drivers/gpu/drm/i915/display/intel_cdclk.c:3482:39: warning: 'ilk_cdclk_funcs' defined but not used [-Wunused-const-variable=]
    3482 | static const struct intel_cdclk_funcs ilk_cdclk_funcs = {
         |                                       ^~~~~~~~~~~~~~~
>> drivers/gpu/drm/i915/display/intel_cdclk.c:3477:39: warning: 'fixed_400mhz_cdclk_funcs' defined but not used [-Wunused-const-variable=]
    3477 | static const struct intel_cdclk_funcs fixed_400mhz_cdclk_funcs = {
         |                                       ^~~~~~~~~~~~~~~~~~~~~~~~
>> drivers/gpu/drm/i915/display/intel_cdclk.c:3471:39: warning: 'hsw_cdclk_funcs' defined but not used [-Wunused-const-variable=]
    3471 | static const struct intel_cdclk_funcs hsw_cdclk_funcs = {
         |                                       ^~~~~~~~~~~~~~~
>> drivers/gpu/drm/i915/display/intel_cdclk.c:3465:39: warning: 'vlv_cdclk_funcs' defined but not used [-Wunused-const-variable=]
    3465 | static const struct intel_cdclk_funcs vlv_cdclk_funcs = {
         |                                       ^~~~~~~~~~~~~~~
>> drivers/gpu/drm/i915/display/intel_cdclk.c:3459:39: warning: 'chv_cdclk_funcs' defined but not used [-Wunused-const-variable=]
    3459 | static const struct intel_cdclk_funcs chv_cdclk_funcs = {
         |                                       ^~~~~~~~~~~~~~~
>> drivers/gpu/drm/i915/display/intel_cdclk.c:3453:39: warning: 'bdw_cdclk_funcs' defined but not used [-Wunused-const-variable=]
    3453 | static const struct intel_cdclk_funcs bdw_cdclk_funcs = {
         |                                       ^~~~~~~~~~~~~~~
>> drivers/gpu/drm/i915/display/intel_cdclk.c:3447:39: warning: 'skl_cdclk_funcs' defined but not used [-Wunused-const-variable=]
    3447 | static const struct intel_cdclk_funcs skl_cdclk_funcs = {
         |                                       ^~~~~~~~~~~~~~~
>> drivers/gpu/drm/i915/display/intel_cdclk.c:3440:39: warning: 'bxt_cdclk_funcs' defined but not used [-Wunused-const-variable=]
    3440 | static const struct intel_cdclk_funcs bxt_cdclk_funcs = {
         |                                       ^~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/display/intel_cdclk.c:3433:39: warning: 'icl_cdclk_funcs' defined but not used [-Wunused-const-variable=]
    3433 | static const struct intel_cdclk_funcs icl_cdclk_funcs = {
         |                                       ^~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/display/intel_cdclk.c:3426:39: warning: 'ehl_cdclk_funcs' defined but not used [-Wunused-const-variable=]
    3426 | static const struct intel_cdclk_funcs ehl_cdclk_funcs = {
         |                                       ^~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/display/intel_cdclk.c:1272:38: warning: 'rkl_cdclk_table' defined but not used [-Wunused-const-variable=]
    1272 | static const struct intel_cdclk_vals rkl_cdclk_table[] = {
         |                                      ^~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/display/intel_cdclk.c:1248:38: warning: 'icl_cdclk_table' defined but not used [-Wunused-const-variable=]
    1248 | static const struct intel_cdclk_vals icl_cdclk_table[] = {
         |                                      ^~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/display/intel_cdclk.c:1241:38: warning: 'glk_cdclk_table' defined but not used [-Wunused-const-variable=]
    1241 | static const struct intel_cdclk_vals glk_cdclk_table[] = {
         |                                      ^~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/display/intel_cdclk.c:1232:38: warning: 'bxt_cdclk_table' defined but not used [-Wunused-const-variable=]
    1232 | static const struct intel_cdclk_vals bxt_cdclk_table[] = {
         |                                      ^~~~~~~~~~~~~~~


vim +/if +3562 drivers/gpu/drm/i915/display/intel_cdclk.c

  3425	
> 3426	static const struct intel_cdclk_funcs ehl_cdclk_funcs = {
  3427		.get_cdclk = bxt_get_cdclk,
  3428		.set_cdclk = bxt_set_cdclk,
  3429		.modeset_calc_cdclk = bxt_modeset_calc_cdclk,
  3430		.calc_voltage_level = ehl_calc_voltage_level,
  3431	};
  3432	
> 3433	static const struct intel_cdclk_funcs icl_cdclk_funcs = {
  3434		.get_cdclk = bxt_get_cdclk,
  3435		.set_cdclk = bxt_set_cdclk,
  3436		.modeset_calc_cdclk = bxt_modeset_calc_cdclk,
  3437		.calc_voltage_level = icl_calc_voltage_level,
  3438	};
  3439	
> 3440	static const struct intel_cdclk_funcs bxt_cdclk_funcs = {
  3441		.get_cdclk = bxt_get_cdclk,
  3442		.set_cdclk = bxt_set_cdclk,
  3443		.modeset_calc_cdclk = bxt_modeset_calc_cdclk,
  3444		.calc_voltage_level = bxt_calc_voltage_level,
  3445	};
  3446	
> 3447	static const struct intel_cdclk_funcs skl_cdclk_funcs = {
  3448		.get_cdclk = skl_get_cdclk,
  3449		.set_cdclk = skl_set_cdclk,
  3450		.modeset_calc_cdclk = skl_modeset_calc_cdclk,
  3451	};
  3452	
> 3453	static const struct intel_cdclk_funcs bdw_cdclk_funcs = {
  3454		.get_cdclk = bdw_get_cdclk,
  3455		.set_cdclk = bdw_set_cdclk,
  3456		.modeset_calc_cdclk = bdw_modeset_calc_cdclk,
  3457	};
  3458	
> 3459	static const struct intel_cdclk_funcs chv_cdclk_funcs = {
  3460		.get_cdclk = vlv_get_cdclk,
  3461		.set_cdclk = chv_set_cdclk,
  3462		.modeset_calc_cdclk = vlv_modeset_calc_cdclk,
  3463	};
  3464	
> 3465	static const struct intel_cdclk_funcs vlv_cdclk_funcs = {
  3466		.get_cdclk = vlv_get_cdclk,
  3467		.set_cdclk = vlv_set_cdclk,
  3468		.modeset_calc_cdclk = vlv_modeset_calc_cdclk,
  3469	};
  3470	
> 3471	static const struct intel_cdclk_funcs hsw_cdclk_funcs = {
  3472		.get_cdclk = hsw_get_cdclk,
  3473		.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
  3474	};
  3475	
  3476	/* SNB, IVB, 965G, 945G */
> 3477	static const struct intel_cdclk_funcs fixed_400mhz_cdclk_funcs = {
  3478		.get_cdclk = fixed_400mhz_get_cdclk,
  3479		.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
  3480	};
  3481	
> 3482	static const struct intel_cdclk_funcs ilk_cdclk_funcs = {
  3483		.get_cdclk = fixed_450mhz_get_cdclk,
  3484		.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
  3485	};
  3486	
> 3487	static const struct intel_cdclk_funcs gm45_cdclk_funcs = {
  3488		.get_cdclk = gm45_get_cdclk,
  3489		.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
  3490	};
  3491	
  3492	/* G45 uses G33 */
  3493	
> 3494	static const struct intel_cdclk_funcs i965gm_cdclk_funcs = {
  3495		.get_cdclk = i965gm_get_cdclk,
  3496		.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
  3497	};
  3498	
  3499	/* i965G uses fixed 400 */
  3500	
> 3501	static const struct intel_cdclk_funcs pnv_cdclk_funcs = {
  3502		.get_cdclk = pnv_get_cdclk,
  3503		.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
  3504	};
  3505	
> 3506	static const struct intel_cdclk_funcs g33_cdclk_funcs = {
  3507		.get_cdclk = g33_get_cdclk,
  3508		.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
  3509	};
  3510	
> 3511	static const struct intel_cdclk_funcs i945gm_cdclk_funcs = {
  3512		.get_cdclk = i945gm_get_cdclk,
  3513		.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
  3514	};
  3515	
  3516	/* i945G uses fixed 400 */
  3517	
> 3518	static const struct intel_cdclk_funcs i915gm_cdclk_funcs = {
  3519		.get_cdclk = i915gm_get_cdclk,
  3520		.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
  3521	};
  3522	
> 3523	static const struct intel_cdclk_funcs i915g_cdclk_funcs = {
  3524		.get_cdclk = fixed_333mhz_get_cdclk,
  3525		.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
  3526	};
  3527	
> 3528	static const struct intel_cdclk_funcs i865g_cdclk_funcs = {
  3529		.get_cdclk = fixed_266mhz_get_cdclk,
  3530		.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
  3531	};
  3532	
> 3533	static const struct intel_cdclk_funcs i85x_cdclk_funcs = {
  3534		.get_cdclk = i85x_get_cdclk,
  3535		.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
  3536	};
  3537	
> 3538	static const struct intel_cdclk_funcs i845g_cdclk_funcs = {
  3539		.get_cdclk = fixed_200mhz_get_cdclk,
  3540		.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
  3541	};
  3542	
> 3543	static const struct intel_cdclk_funcs i830_cdclk_funcs = {
  3544		.get_cdclk = fixed_133mhz_get_cdclk,
  3545		.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
  3546	};
  3547	
  3548	/**
  3549	 * intel_init_cdclk_hooks - Initialize CDCLK related modesetting hooks
  3550	 * @dev_priv: i915 device
  3551	 */
  3552	void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
  3553	{
  3554		if (IS_METEORLAKE(dev_priv)) {
  3555			dev_priv->display.funcs.cdclk = &mtl_cdclk_funcs;
  3556			dev_priv->display.cdclk.table = mtl_cdclk_table;
  3557		} else if (IS_DG2(dev_priv)) {
  3558			dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
  3559			dev_priv->display.cdclk.table = dg2_cdclk_table;
  3560		} else if (IS_ALDERLAKE_P(dev_priv)) {
  3561			/* Wa_22011320316:adl-p[a0] */
> 3562			if (IS_ALDERLAKE_P_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
  3563				dev_priv->display.cdclk.table = adlp_a_step_cdclk_table;
  3564				dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
  3565			} else if (IS_ADLP_RPLU(dev_priv)) {
  3566				dev_priv->display.cdclk.table = rplu_cdclk_table;
  3567				dev_priv->display.funcs.cdclk = &rplu_cdclk_funcs;
  3568			} else {
  3569				dev_priv->display.cdclk.table = adlp_cdclk_table;
  3570				dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
  3571			}
  3572		} else if (IS_ROCKETLAKE(dev_priv)) {
  3573			dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
  3574			dev_priv->display.cdclk.table = rkl_cdclk_table;
  3575		} else if (DISPLAY_VER(dev_priv) >= 12) {
  3576			dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
  3577			dev_priv->display.cdclk.table = icl_cdclk_table;
  3578		} else if (IS_JASPERLAKE_EHL(dev_priv)) {
  3579			dev_priv->display.funcs.cdclk = &ehl_cdclk_funcs;
  3580			dev_priv->display.cdclk.table = icl_cdclk_table;
  3581		} else if (DISPLAY_VER(dev_priv) >= 11) {
  3582			dev_priv->display.funcs.cdclk = &icl_cdclk_funcs;
  3583			dev_priv->display.cdclk.table = icl_cdclk_table;
  3584		} else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
  3585			dev_priv->display.funcs.cdclk = &bxt_cdclk_funcs;
  3586			if (IS_GEMINILAKE(dev_priv))
  3587				dev_priv->display.cdclk.table = glk_cdclk_table;
  3588			else
  3589				dev_priv->display.cdclk.table = bxt_cdclk_table;
  3590		} else if (DISPLAY_VER(dev_priv) == 9) {
  3591			dev_priv->display.funcs.cdclk = &skl_cdclk_funcs;
  3592		} else if (IS_BROADWELL(dev_priv)) {
  3593			dev_priv->display.funcs.cdclk = &bdw_cdclk_funcs;
  3594		} else if (IS_HASWELL(dev_priv)) {
  3595			dev_priv->display.funcs.cdclk = &hsw_cdclk_funcs;
  3596		} else if (IS_CHERRYVIEW(dev_priv)) {
  3597			dev_priv->display.funcs.cdclk = &chv_cdclk_funcs;
  3598		} else if (IS_VALLEYVIEW(dev_priv)) {
  3599			dev_priv->display.funcs.cdclk = &vlv_cdclk_funcs;
  3600		} else if (IS_SANDYBRIDGE(dev_priv) || IS_IVYBRIDGE(dev_priv)) {
  3601			dev_priv->display.funcs.cdclk = &fixed_400mhz_cdclk_funcs;
  3602		} else if (IS_IRONLAKE(dev_priv)) {
  3603			dev_priv->display.funcs.cdclk = &ilk_cdclk_funcs;
  3604		} else if (IS_GM45(dev_priv)) {
  3605			dev_priv->display.funcs.cdclk = &gm45_cdclk_funcs;
  3606		} else if (IS_G45(dev_priv)) {
  3607			dev_priv->display.funcs.cdclk = &g33_cdclk_funcs;
  3608		} else if (IS_I965GM(dev_priv)) {
  3609			dev_priv->display.funcs.cdclk = &i965gm_cdclk_funcs;
  3610		} else if (IS_I965G(dev_priv)) {
  3611			dev_priv->display.funcs.cdclk = &fixed_400mhz_cdclk_funcs;
  3612		} else if (IS_PINEVIEW(dev_priv)) {
  3613			dev_priv->display.funcs.cdclk = &pnv_cdclk_funcs;
  3614		} else if (IS_G33(dev_priv)) {
  3615			dev_priv->display.funcs.cdclk = &g33_cdclk_funcs;
  3616		} else if (IS_I945GM(dev_priv)) {
  3617			dev_priv->display.funcs.cdclk = &i945gm_cdclk_funcs;
  3618		} else if (IS_I945G(dev_priv)) {
  3619			dev_priv->display.funcs.cdclk = &fixed_400mhz_cdclk_funcs;
  3620		} else if (IS_I915GM(dev_priv)) {
  3621			dev_priv->display.funcs.cdclk = &i915gm_cdclk_funcs;
  3622		} else if (IS_I915G(dev_priv)) {
  3623			dev_priv->display.funcs.cdclk = &i915g_cdclk_funcs;
  3624		} else if (IS_I865G(dev_priv)) {
  3625			dev_priv->display.funcs.cdclk = &i865g_cdclk_funcs;
  3626		} else if (IS_I85X(dev_priv)) {
  3627			dev_priv->display.funcs.cdclk = &i85x_cdclk_funcs;
  3628		} else if (IS_I845G(dev_priv)) {
  3629			dev_priv->display.funcs.cdclk = &i845g_cdclk_funcs;
  3630		} else if (IS_I830(dev_priv)) {
  3631			dev_priv->display.funcs.cdclk = &i830_cdclk_funcs;
  3632		}
  3633	
> 3634		if (drm_WARN(&dev_priv->drm, !dev_priv->display.funcs.cdclk,
  3635			     "Unknown platform. Assuming i830\n"))
  3636			dev_priv->display.funcs.cdclk = &i830_cdclk_funcs;
> 3637	}

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki

[Intel-gfx] [PATCH 07/11] drm/i915/adlp: s/ADLP/ALDERLAKE_P for display and graphics step

[Dnyaneshwar Bhadane]

From: Anusha Srivatsa <anusha.srivatsa@intel.com>

Driver refers to the platfrom Alderlake P as ADLP in places
and ALDERLAKE_P in some. Making the consistent change
to avoid confusion of the right naming convention for
the platform.

Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c         | 2 +-
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c      | 2 +-
 drivers/gpu/drm/i915/display/intel_psr.c           | 8 ++++----
 drivers/gpu/drm/i915/display/skl_universal_plane.c | 4 ++--
 drivers/gpu/drm/i915/i915_drv.h                    | 4 ++--
 5 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 2acfa0435675..034454233d87 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -3559,7 +3559,7 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
 		dev_priv->display.cdclk.table = dg2_cdclk_table;
 	} else if (IS_ALDERLAKE_P(dev_priv)) {
 		/* Wa_22011320316:adl-p[a0] */
-		if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) {
+		if (IS_ALDERLAKE_P_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) {
 			dev_priv->display.cdclk.table = adlp_a_step_cdclk_table;
 			dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
 		} else if (IS_ADLP_RPLU(dev_priv)) {
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index c6d376d414b8..47fe8311067e 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -3781,7 +3781,7 @@ static void adlp_cmtg_clock_gating_wa(struct drm_i915_private *i915, struct inte
 {
 	u32 val;
 
-	if (!IS_ADLP_DISPLAY_STEP(i915, STEP_A0, STEP_B0) ||
+	if (!IS_ALDERLAKE_P_DISPLAY_STEP(i915, STEP_A0, STEP_B0) ||
 	    pll->info->id != DPLL_ID_ICL_DPLL0)
 		return;
 	/*
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index f61d39d2b0fc..00c98c2b4324 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -639,7 +639,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
 	}
 
 	/* Wa_22012278275:adl-p */
-	if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_E0)) {
+	if (IS_ALDERLAKE_P_DISPLAY_STEP(dev_priv, STEP_A0, STEP_E0)) {
 		static const u8 map[] = {
 			2, /* 5 lines */
 			1, /* 6 lines */
@@ -807,7 +807,7 @@ tgl_dc3co_exitline_compute_config(struct intel_dp *intel_dp,
 		return;
 
 	/* Wa_16011303918:adl-p */
-	if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
+	if (IS_ALDERLAKE_P_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
 		return;
 
 	/*
@@ -975,7 +975,7 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
 		return false;
 	}
 
-	if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) {
+	if (IS_ALDERLAKE_P_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) {
 		drm_dbg_kms(&dev_priv->drm, "PSR2 not completely functional in this stepping\n");
 		return false;
 	}
@@ -1033,7 +1033,7 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
 
 	/* Wa_16011303918:adl-p */
 	if (crtc_state->vrr.enable &&
-	    IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) {
+	    IS_ALDERLAKE_P_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) {
 		drm_dbg_kms(&dev_priv->drm,
 			    "PSR2 not enabled, not compatible with HW stepping + VRR\n");
 		return false;
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 25b06ced9ce7..2458a9ea25ba 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -2174,7 +2174,7 @@ static bool skl_plane_has_rc_ccs(struct drm_i915_private *i915,
 		return false;
 
 	/* Wa_22011186057 */
-	if (IS_ADLP_DISPLAY_STEP(i915, STEP_A0, STEP_B0))
+	if (IS_ALDERLAKE_P_DISPLAY_STEP(i915, STEP_A0, STEP_B0))
 		return false;
 
 	if (DISPLAY_VER(i915) >= 11)
@@ -2200,7 +2200,7 @@ static bool gen12_plane_has_mc_ccs(struct drm_i915_private *i915,
 		return false;
 
 	/* Wa_22011186057 */
-	if (IS_ADLP_DISPLAY_STEP(i915, STEP_A0, STEP_B0))
+	if (IS_ALDERLAKE_P_DISPLAY_STEP(i915, STEP_A0, STEP_B0))
 		return false;
 
 	/* Wa_14013215631 */
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 3c4a66f1a7ba..08e14cf225b5 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -677,11 +677,11 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 	(IS_ALDERLAKE_S(__i915) && \
 	 IS_GRAPHICS_STEP(__i915, since, until))
 
-#define IS_ADLP_DISPLAY_STEP(__i915, since, until) \
+#define IS_ALDERLAKE_P_DISPLAY_STEP(__i915, since, until) \
 	(IS_ALDERLAKE_P(__i915) && \
 	 IS_DISPLAY_STEP(__i915, since, until))
 
-#define IS_ADLP_GRAPHICS_STEP(__i915, since, until) \
+#define IS_ALDERLAKE_P_GRAPHICS_STEP(__i915, since, until) \
 	(IS_ALDERLAKE_P(__i915) && \
 	 IS_GRAPHICS_STEP(__i915, since, until))
 
-- 
2.34.1

Re: [Intel-gfx] [PATCH 01/11] drm/i915/TGL: s/TGL/TIGERLAKE for platform/subplatform defines

[Srivatsa, Anusha]

> -----Original Message-----
> From: Bhadane, Dnyaneshwar <dnyaneshwar.bhadane@intel.com>
> Sent: Wednesday, June 14, 2023 10:00 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Atwood, Matthew S <matthew.s.atwood@intel.com>; Srivatsa, Anusha
> <anusha.srivatsa@intel.com>; Bhadane, Dnyaneshwar
> <dnyaneshwar.bhadane@intel.com>
> Subject: [PATCH 01/11] drm/i915/TGL: s/TGL/TIGERLAKE for
> platform/subplatform defines
> 
> Follow consistent naming convention. Replace TGL with TIGERLAKE.
>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>

> Signed-off-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c | 2 +-
> drivers/gpu/drm/i915/display/skl_universal_plane.c | 2 +-
>  drivers/gpu/drm/i915/i915_drv.h                    | 4 ++--
>  drivers/gpu/drm/i915/intel_step.c                  | 2 +-
>  4 files changed, 5 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
> b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
> index b7d20485bde5..9e34cc103aeb 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
> @@ -1390,7 +1390,7 @@ tgl_get_combo_buf_trans_dp(struct intel_encoder
> *encoder,
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> 
>  	if (crtc_state->port_clock > 270000) {
> -		if (IS_TGL_UY(dev_priv)) {
> +		if (IS_TIGERLAKE_UY(dev_priv)) {
>  			return
> intel_get_buf_trans(&tgl_uy_combo_phy_trans_dp_hbr2,
>  						   n_entries);
>  		} else {
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> index 6b01a0b68b97..26def9cb86e4 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> @@ -2196,7 +2196,7 @@ static bool gen12_plane_has_mc_ccs(struct
> drm_i915_private *i915,
> 
>  	/* Wa_14010477008 */
>  	if (IS_DG1(i915) || IS_ROCKETLAKE(i915) ||
> -	    IS_TGL_DISPLAY_STEP(i915, STEP_A0, STEP_D0))
> +	    IS_TIGERLAKE_DISPLAY_STEP(i915, STEP_A0, STEP_D0))
>  		return false;
> 
>  	/* Wa_22011186057 */
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index b4cf6f0f636d..0f30dc890209 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -647,7 +647,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> #define IS_ICL_WITH_PORT_F(i915) \
>  	IS_SUBPLATFORM(i915, INTEL_ICELAKE, INTEL_SUBPLATFORM_PORTF)
> 
> -#define IS_TGL_UY(i915) \
> +#define IS_TIGERLAKE_UY(i915) \
>  	IS_SUBPLATFORM(i915, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_UY)
> 
>  #define IS_SKL_GRAPHICS_STEP(p, since, until) (IS_SKYLAKE(p) &&
> IS_GRAPHICS_STEP(p, since, until)) @@ -662,7 +662,7 @@
> IS_SUBPLATFORM(const struct drm_i915_private *i915,  #define
> IS_JSL_EHL_DISPLAY_STEP(p, since, until) \
>  	(IS_JSL_EHL(p) && IS_DISPLAY_STEP(p, since, until))
> 
> -#define IS_TGL_DISPLAY_STEP(__i915, since, until) \
> +#define IS_TIGERLAKE_DISPLAY_STEP(__i915, since, until) \
>  	(IS_TIGERLAKE(__i915) && \
>  	 IS_DISPLAY_STEP(__i915, since, until))
> 
> diff --git a/drivers/gpu/drm/i915/intel_step.c
> b/drivers/gpu/drm/i915/intel_step.c
> index 8a9ff6227e53..67054c87bb5f 100644
> --- a/drivers/gpu/drm/i915/intel_step.c
> +++ b/drivers/gpu/drm/i915/intel_step.c
> @@ -213,7 +213,7 @@ void intel_step_init(struct drm_i915_private *i915)
>  	} else if (IS_ROCKETLAKE(i915)) {
>  		revids = rkl_revids;
>  		size = ARRAY_SIZE(rkl_revids);
> -	} else if (IS_TGL_UY(i915)) {
> +	} else if (IS_TIGERLAKE_UY(i915)) {
>  		revids = tgl_uy_revids;
>  		size = ARRAY_SIZE(tgl_uy_revids);
>  	} else if (IS_TIGERLAKE(i915)) {
> --
> 2.34.1

Re: [Intel-gfx] [PATCH 02/11] drm/i915/MTL: s/MTL/METEORLAKE for platform/subplatform defines

[Srivatsa, Anusha]

Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>


> -----Original Message-----
> From: Bhadane, Dnyaneshwar <dnyaneshwar.bhadane@intel.com>
> Sent: Wednesday, June 14, 2023 10:00 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Atwood, Matthew S <matthew.s.atwood@intel.com>; Srivatsa, Anusha
> <anusha.srivatsa@intel.com>; Bhadane, Dnyaneshwar
> <dnyaneshwar.bhadane@intel.com>
> Subject: [PATCH 02/11] drm/i915/MTL: s/MTL/METEORLAKE for
> platform/subplatform defines
> 
> Follow consistent naming convention. Replace MTL with METEORLAKE
> 
> Signed-off-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_fbc.c      |  2 +-
>  drivers/gpu/drm/i915/display/intel_pmdemand.c |  2 +-
>  drivers/gpu/drm/i915/display/intel_psr.c      | 10 ++---
>  .../drm/i915/display/skl_universal_plane.c    |  4 +-
>  drivers/gpu/drm/i915/gt/gen8_engine_cs.c      |  8 ++--
>  drivers/gpu/drm/i915/gt/intel_engine_cs.c     |  2 +-
>  .../drm/i915/gt/intel_execlists_submission.c  |  2 +-
>  drivers/gpu/drm/i915/gt/intel_gt_mcr.c        |  4 +-
>  drivers/gpu/drm/i915/gt/intel_lrc.c           |  4 +-
>  drivers/gpu/drm/i915/gt/intel_rc6.c           |  2 +-
>  drivers/gpu/drm/i915/gt/intel_workarounds.c   | 44 +++++++++----------
>  drivers/gpu/drm/i915/gt/uc/intel_guc.c        |  4 +-
>  .../gpu/drm/i915/gt/uc/intel_guc_submission.c |  4 +-
>  drivers/gpu/drm/i915/i915_drv.h               |  6 +--
>  drivers/gpu/drm/i915/i915_perf.c              |  4 +-
>  15 files changed, 51 insertions(+), 51 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
> b/drivers/gpu/drm/i915/display/intel_fbc.c
> index 7f8b2d7713c7..6358a8b26172 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> @@ -1093,7 +1093,7 @@ static int intel_fbc_check_plane(struct
> intel_atomic_state *state,
> 
>  	/* Wa_14016291713 */
>  	if ((IS_DISPLAY_VER(i915, 12, 13) ||
> -	     IS_MTL_DISPLAY_STEP(i915, STEP_A0, STEP_C0)) &&
> +	     IS_METEORLAKE_DISPLAY_STEP(i915, STEP_A0, STEP_C0)) &&
>  	    crtc_state->has_psr) {
>  		plane_state->no_fbc_reason = "PSR1 enabled
> (Wa_14016291713)";
>  		return 0;
> diff --git a/drivers/gpu/drm/i915/display/intel_pmdemand.c
> b/drivers/gpu/drm/i915/display/intel_pmdemand.c
> index f7608d363634..8c3158b188ef 100644
> --- a/drivers/gpu/drm/i915/display/intel_pmdemand.c
> +++ b/drivers/gpu/drm/i915/display/intel_pmdemand.c
> @@ -92,7 +92,7 @@ int intel_pmdemand_init(struct drm_i915_private *i915)
>  				     &pmdemand_state->base,
>  				     &intel_pmdemand_funcs);
> 
> -	if (IS_MTL_DISPLAY_STEP(i915, STEP_A0, STEP_C0))
> +	if (IS_METEORLAKE_DISPLAY_STEP(i915, STEP_A0, STEP_C0))
>  		/* Wa_14016740474 */
>  		intel_de_rmw(i915, XELPD_CHICKEN_DCPR_3, 0,
> DMD_RSP_TIMEOUT_DISABLE);
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index d58ed9b62e67..06b464229efe 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -1247,7 +1247,7 @@ static void wm_optimization_wa(struct intel_dp
> *intel_dp,
>  	bool set_wa_bit = false;
> 
>  	/* Wa_14015648006 */
> -	if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
> +	if (IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
>  	    IS_DISPLAY_VER(dev_priv, 11, 13))
>  		set_wa_bit |= crtc_state->wm_level_disabled;
> 
> @@ -1320,7 +1320,7 @@ static void intel_psr_enable_source(struct intel_dp
> *intel_dp,
>  		 * All supported adlp panels have 1-based X granularity, this may
>  		 * cause issues if non-supported panels are used.
>  		 */
> -		if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
> +		if (IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0,
> STEP_B0))
>  			intel_de_rmw(dev_priv,
> MTL_CHICKEN_TRANS(cpu_transcoder), 0,
>  				     ADLP_1_BASED_X_GRANULARITY);
>  		else if (IS_ALDERLAKE_P(dev_priv))
> @@ -1328,7 +1328,7 @@ static void intel_psr_enable_source(struct intel_dp
> *intel_dp,
>  				     ADLP_1_BASED_X_GRANULARITY);
> 
>  		/* Wa_16012604467:adlp,mtl[a0,b0] */
> -		if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
> +		if (IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0,
> STEP_B0))
>  			intel_de_rmw(dev_priv,
>  				     MTL_CLKGATE_DIS_TRANS(cpu_transcoder),
> 0,
> 
> MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS);
> @@ -1489,7 +1489,7 @@ static void intel_psr_disable_locked(struct intel_dp
> *intel_dp)
> 
>  	if (intel_dp->psr.psr2_enabled) {
>  		/* Wa_16012604467:adlp,mtl[a0,b0] */
> -		if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
> +		if (IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0,
> STEP_B0))
>  			intel_de_rmw(dev_priv,
>  				     MTL_CLKGATE_DIS_TRANS(cpu_transcoder),
> 
> MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS, 0); @@ -1963,7 +1963,7 @@
> int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
>  		goto skip_sel_fetch_set_loop;
> 
>  	/* Wa_14014971492 */
> -	if ((IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
> +	if ((IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
>  	     IS_ALDERLAKE_P(dev_priv) || IS_TIGERLAKE(dev_priv)) &&
>  	    crtc_state->splitter.enable)
>  		pipe_clip.y1 = 0;
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> index 26def9cb86e4..25b06ced9ce7 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> @@ -2169,8 +2169,8 @@ static bool skl_plane_has_rc_ccs(struct
> drm_i915_private *i915,
>  				 enum pipe pipe, enum plane_id plane_id)  {
>  	/* Wa_14017240301 */
> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
> +	if (IS_METEORLAKE_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> +	    IS_METEORLAKE_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
>  		return false;
> 
>  	/* Wa_22011186057 */
> diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> index 23857cc08eca..eb72610a8588 100644
> --- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> @@ -180,8 +180,8 @@ u32 *gen12_emit_aux_table_inv(struct intel_gt *gt, u32
> *cs, const i915_reg_t inv  static int mtl_dummy_pipe_control(struct
> i915_request *rq)  {
>  	/* Wa_14016712196 */
> -	if (IS_MTL_GRAPHICS_STEP(rq->engine->i915, M, STEP_A0, STEP_B0) ||
> -	    IS_MTL_GRAPHICS_STEP(rq->engine->i915, P, STEP_A0, STEP_B0)) {
> +	if (IS_METEORLAKE_GRAPHICS_STEP(rq->engine->i915, M, STEP_A0,
> STEP_B0) ||
> +	    IS_METEORLAKE_GRAPHICS_STEP(rq->engine->i915, P, STEP_A0,
> +STEP_B0)) {
>  		u32 *cs;
> 
>  		/* dummy PIPE_CONTROL + depth flush */ @@ -765,8 +765,8
> @@ u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
>  		     PIPE_CONTROL_FLUSH_ENABLE);
> 
>  	/* Wa_14016712196 */
> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
> +	if (IS_METEORLAKE_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> +	    IS_METEORLAKE_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
>  		/* dummy PIPE_CONTROL + depth flush */
>  		cs = gen12_emit_pipe_control(cs, 0,
> 
> PIPE_CONTROL_DEPTH_CACHE_FLUSH, 0); diff --git
> a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> index 0aff5bb13c53..f9af6b1a7c01 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> @@ -1616,7 +1616,7 @@ static int __intel_engine_stop_cs(struct
> intel_engine_cs *engine,
>  	 * Wa_22011802037: Prior to doing a reset, ensure CS is
>  	 * stopped, set ring stop bit and prefetch disable bit to halt CS
>  	 */
> -	if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
> +	if (IS_METEORLAKE_GRAPHICS_STEP(engine->i915, M, STEP_A0,
> STEP_B0) ||
>  	    (GRAPHICS_VER(engine->i915) >= 11 &&
>  	    GRAPHICS_VER_FULL(engine->i915) < IP_VER(12, 70)))
>  		intel_uncore_write_fw(uncore, RING_MODE_GEN7(engine-
> >mmio_base),
> diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> index 2ebd937f3b4c..901ecd59afbc 100644
> --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> @@ -3001,7 +3001,7 @@ static void execlists_reset_prepare(struct
> intel_engine_cs *engine)
>  	 * Wa_22011802037: In addition to stopping the cs, we need
>  	 * to wait for any pending mi force wakeups
>  	 */
> -	if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
> +	if (IS_METEORLAKE_GRAPHICS_STEP(engine->i915, M, STEP_A0,
> STEP_B0) ||
>  	    (GRAPHICS_VER(engine->i915) >= 11 &&
>  	    GRAPHICS_VER_FULL(engine->i915) < IP_VER(12, 70)))
>  		intel_engine_wait_for_pending_mi_fw(engine);
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
> b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
> index 0b414eae1683..1dc7180eeb27 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
> @@ -166,8 +166,8 @@ void intel_gt_mcr_init(struct intel_gt *gt)
>  		gt->steering_table[OADDRM] =
> xelpmp_oaddrm_steering_table;
>  	} else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) {
>  		/* Wa_14016747170 */
> -		if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> -		    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
> +		if (IS_METEORLAKE_GRAPHICS_STEP(i915, M, STEP_A0,
> STEP_B0) ||
> +		    IS_METEORLAKE_GRAPHICS_STEP(i915, P, STEP_A0,
> STEP_B0))
>  			fuse = REG_FIELD_GET(MTL_GT_L3_EXC_MASK,
>  					     intel_uncore_read(gt->uncore,
> 
> MTL_GT_ACTIVITY_FACTOR)); diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
> b/drivers/gpu/drm/i915/gt/intel_lrc.c
> index a4ec20aaafe2..cd9a76f048f3 100644
> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> @@ -1370,8 +1370,8 @@ gen12_emit_indirect_ctx_rcs(const struct
> intel_context *ce, u32 *cs)
>  					      cs, GEN12_GFX_CCS_AUX_NV);
> 
>  	/* Wa_16014892111 */
> -	if (IS_MTL_GRAPHICS_STEP(ce->engine->i915, M, STEP_A0, STEP_B0) ||
> -	    IS_MTL_GRAPHICS_STEP(ce->engine->i915, P, STEP_A0, STEP_B0) ||
> +	if (IS_METEORLAKE_GRAPHICS_STEP(ce->engine->i915, M, STEP_A0,
> STEP_B0) ||
> +	    IS_METEORLAKE_GRAPHICS_STEP(ce->engine->i915, P, STEP_A0,
> STEP_B0)
> +||
>  	    IS_DG2(ce->engine->i915))
>  		cs = dg2_emit_draw_watermark_setting(cs);
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c
> b/drivers/gpu/drm/i915/gt/intel_rc6.c
> index 58bb1c55294c..cc8b09b8a7fa 100644
> --- a/drivers/gpu/drm/i915/gt/intel_rc6.c
> +++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
> @@ -526,7 +526,7 @@ static bool rc6_supported(struct intel_rc6 *rc6)
>  		return false;
>  	}
> 
> -	if (IS_MTL_MEDIA_STEP(gt->i915, STEP_A0, STEP_B0) &&
> +	if (IS_METEORLAKE_MEDIA_STEP(gt->i915, STEP_A0, STEP_B0) &&
>  	    gt->type == GT_MEDIA) {
>  		drm_notice(&i915->drm,
>  			   "Media RC6 disabled on A step\n"); diff --git
> a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 4d2dece96011..a109ecd54944 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -819,8 +819,8 @@ static void mtl_ctx_gt_tuning_init(struct intel_engine_cs
> *engine,
> 
>  	dg2_ctx_gt_tuning_init(engine, wal);
> 
> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_B0, STEP_FOREVER) ||
> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_B0, STEP_FOREVER))
> +	if (IS_METEORLAKE_GRAPHICS_STEP(i915, M, STEP_B0, STEP_FOREVER)
> ||
> +	    IS_METEORLAKE_GRAPHICS_STEP(i915, P, STEP_B0, STEP_FOREVER))
>  		wa_add(wal, DRAW_WATERMARK, VERT_WM_VAL, 0x3FF, 0,
> false);  }
> 
> @@ -831,8 +831,8 @@ static void mtl_ctx_workarounds_init(struct
> intel_engine_cs *engine,
> 
>  	mtl_ctx_gt_tuning_init(engine, wal);
> 
> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) {
> +	if (IS_METEORLAKE_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> +	    IS_METEORLAKE_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) {
>  		/* Wa_14014947963 */
>  		wa_masked_field_set(wal, VF_PREEMPTION,
>  				    PREEMPTION_VERTEX_COUNT, 0x4000);
> @@ -1716,8 +1716,8 @@ xelpg_gt_workarounds_init(struct intel_gt *gt, struct
> i915_wa_list *wal)
>  	/* Wa_22016670082 */
>  	wa_write_or(wal, GEN12_SQCNT1, GEN12_STRICT_RAR_ENABLE);
> 
> -	if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
> -	    IS_MTL_GRAPHICS_STEP(gt->i915, P, STEP_A0, STEP_B0)) {
> +	if (IS_METEORLAKE_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
> +	    IS_METEORLAKE_GRAPHICS_STEP(gt->i915, P, STEP_A0, STEP_B0)) {
>  		/* Wa_14014830051 */
>  		wa_mcr_write_clr(wal, SARB_CHICKEN1, COMP_CKN_IN);
> 
> @@ -2413,15 +2413,15 @@ rcs_engine_wa_init(struct intel_engine_cs *engine,
> struct i915_wa_list *wal)  {
>  	struct drm_i915_private *i915 = engine->i915;
> 
> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) {
> +	if (IS_METEORLAKE_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> +	    IS_METEORLAKE_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) {
>  		/* Wa_22014600077 */
>  		wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS,
>  				 ENABLE_EU_COUNT_FOR_TDL_FLUSH);
>  	}
> 
> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
> +	if (IS_METEORLAKE_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> +	    IS_METEORLAKE_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
>  	    IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
>  	    IS_DG2_G11(i915) || IS_DG2_G12(i915)) {
>  		/* Wa_1509727124 */
> @@ -2431,7 +2431,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine,
> struct i915_wa_list *wal)
> 
>  	if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
>  	    IS_DG2_G11(i915) || IS_DG2_G12(i915) ||
> -	    IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0)) {
> +	    IS_METEORLAKE_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0)) {
>  		/* Wa_22012856258 */
>  		wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2,
>  				 GEN12_DISABLE_READ_SUPPRESSION);
> @@ -3016,13 +3016,13 @@ general_render_compute_wa_init(struct
> intel_engine_cs *engine, struct i915_wa_li
> 
> GEN11_INDIRECT_STATE_BASE_ADDR_OVERRIDE);
>  	}
> 
> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_B0, STEP_FOREVER) ||
> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_B0, STEP_FOREVER))
> +	if (IS_METEORLAKE_GRAPHICS_STEP(i915, M, STEP_B0, STEP_FOREVER)
> ||
> +	    IS_METEORLAKE_GRAPHICS_STEP(i915, P, STEP_B0, STEP_FOREVER))
>  		/* Wa_14017856879 */
>  		wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN3,
> MTL_DISABLE_FIX_FOR_EOT_FLUSH);
> 
> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
> +	if (IS_METEORLAKE_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> +	    IS_METEORLAKE_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
>  		/*
>  		 * Wa_14017066071
>  		 * Wa_14017654203
> @@ -3030,13 +3030,13 @@ general_render_compute_wa_init(struct
> intel_engine_cs *engine, struct i915_wa_li
>  		wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE,
>  				 MTL_DISABLE_SAMPLER_SC_OOO);
> 
> -	if (IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
> +	if (IS_METEORLAKE_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
>  		/* Wa_22015279794 */
>  		wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS,
>  				 DISABLE_PREFETCH_INTO_IC);
> 
> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
> +	if (IS_METEORLAKE_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> +	    IS_METEORLAKE_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
>  	    IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
>  	    IS_DG2_G11(i915) || IS_DG2_G12(i915)) {
>  		/* Wa_22013037850 */
> @@ -3044,16 +3044,16 @@ general_render_compute_wa_init(struct
> intel_engine_cs *engine, struct i915_wa_li
>  				DISABLE_128B_EVICTION_COMMAND_UDW);
>  	}
> 
> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
> +	if (IS_METEORLAKE_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> +	    IS_METEORLAKE_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
>  	    IS_PONTEVECCHIO(i915) ||
>  	    IS_DG2(i915)) {
>  		/* Wa_22014226127 */
>  		wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0,
> DISABLE_D8_D16_COASLESCE);
>  	}
> 
> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
> +	if (IS_METEORLAKE_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> +	    IS_METEORLAKE_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
>  	    IS_DG2(i915)) {
>  		/* Wa_18017747507 */
>  		wa_masked_en(wal, VFG_PREEMPTION_CHICKEN,
> POLYGON_TRIFAN_LINELOOP_DISABLE); diff --git
> a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> index 2eb891b270ae..3af0fcd7dd57 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> @@ -277,7 +277,7 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc)
>  		flags |= GUC_WA_GAM_CREDITS;
> 
>  	/* Wa_14014475959 */
> -	if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
> +	if (IS_METEORLAKE_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
>  	    IS_DG2(gt->i915))
>  		flags |= GUC_WA_HOLD_CCS_SWITCHOUT;
> 
> @@ -292,7 +292,7 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc)
>  		flags |= GUC_WA_DUAL_QUEUE;
> 
>  	/* Wa_22011802037: graphics version 11/12 */
> -	if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
> +	if (IS_METEORLAKE_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
>  	    (GRAPHICS_VER(gt->i915) >= 11 &&
>  	    GRAPHICS_VER_FULL(gt->i915) < IP_VER(12, 70)))
>  		flags |= GUC_WA_PRE_PARSER;
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> index a0e3ef1c65d2..5914c7348aba 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> @@ -1658,7 +1658,7 @@ static void guc_engine_reset_prepare(struct
> intel_engine_cs *engine)
>  	 * Wa_22011802037: In addition to stopping the cs, we need
>  	 * to wait for any pending mi force wakeups
>  	 */
> -	if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
> +	if (IS_METEORLAKE_GRAPHICS_STEP(engine->i915, M, STEP_A0,
> STEP_B0) ||
>  	    (GRAPHICS_VER(engine->i915) >= 11 &&
>  	     GRAPHICS_VER_FULL(engine->i915) < IP_VER(12, 70))) {
>  		intel_engine_stop_cs(engine);
> @@ -4267,7 +4267,7 @@ static void guc_default_vfuncs(struct intel_engine_cs
> *engine)
> 
>  	/* Wa_14014475959:dg2 */
>  	if (engine->class == COMPUTE_CLASS)
> -		if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0,
> STEP_B0) ||
> +		if (IS_METEORLAKE_GRAPHICS_STEP(engine->i915, M,
> STEP_A0, STEP_B0) ||
>  		    IS_DG2(engine->i915))
>  			engine->flags |=
> I915_ENGINE_USES_WA_HOLD_CCS_SWITCHOUT;
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 0f30dc890209..472a36cf1a72 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -688,15 +688,15 @@ IS_SUBPLATFORM(const struct drm_i915_private
> *i915,  #define IS_XEHPSDV_GRAPHICS_STEP(__i915, since, until) \
>  	(IS_XEHPSDV(__i915) && IS_GRAPHICS_STEP(__i915, since, until))
> 
> -#define IS_MTL_GRAPHICS_STEP(__i915, variant, since, until) \
> +#define IS_METEORLAKE_GRAPHICS_STEP(__i915, variant, since, until) \
>  	(IS_SUBPLATFORM(__i915, INTEL_METEORLAKE,
> INTEL_SUBPLATFORM_##variant) && \
>  	 IS_GRAPHICS_STEP(__i915, since, until))
> 
> -#define IS_MTL_DISPLAY_STEP(__i915, since, until) \
> +#define IS_METEORLAKE_DISPLAY_STEP(__i915, since, until) \
>  	(IS_METEORLAKE(__i915) && \
>  	 IS_DISPLAY_STEP(__i915, since, until))
> 
> -#define IS_MTL_MEDIA_STEP(__i915, since, until) \
> +#define IS_METEORLAKE_MEDIA_STEP(__i915, since, until) \
>  	(IS_METEORLAKE(__i915) && \
>  	 IS_MEDIA_STEP(__i915, since, until))
> 
> diff --git a/drivers/gpu/drm/i915/i915_perf.c
> b/drivers/gpu/drm/i915/i915_perf.c
> index 0a111b281578..e943ffbaecbc 100644
> --- a/drivers/gpu/drm/i915/i915_perf.c
> +++ b/drivers/gpu/drm/i915/i915_perf.c
> @@ -4214,7 +4214,7 @@ static int read_properties_unlocked(struct i915_perf
> *perf,
>  	 * C6 disable in BIOS. Fail if Media C6 is enabled on steppings where
> OAM
>  	 * does not work as expected.
>  	 */
> -	if (IS_MTL_MEDIA_STEP(props->engine->i915, STEP_A0, STEP_C0) &&
> +	if (IS_METEORLAKE_MEDIA_STEP(props->engine->i915, STEP_A0,
> STEP_C0) &&
>  	    props->engine->oa_group->type == TYPE_OAM &&
>  	    intel_check_bios_c6_setup(&props->engine->gt->rc6)) {
>  		drm_dbg(&perf->i915->drm,
> @@ -5322,7 +5322,7 @@ int i915_perf_ioctl_version(struct drm_i915_private
> *i915)
>  	 * C6 disable in BIOS. If Media C6 is enabled in BIOS, return version 6
>  	 * to indicate that OA media is not supported.
>  	 */
> -	if (IS_MTL_MEDIA_STEP(i915, STEP_A0, STEP_C0)) {
> +	if (IS_METEORLAKE_MEDIA_STEP(i915, STEP_A0, STEP_C0)) {
>  		struct intel_gt *gt;
>  		int i;
> 
> --
> 2.34.1

Re: [Intel-gfx] [PATCH 03/11] drm/i915/TGL: s/RKL/ROCKETLAKE for platform/subplatform defines

[Srivatsa, Anusha]

Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>


> -----Original Message-----
> From: Bhadane, Dnyaneshwar <dnyaneshwar.bhadane@intel.com>
> Sent: Wednesday, June 14, 2023 10:00 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Atwood, Matthew S <matthew.s.atwood@intel.com>; Srivatsa, Anusha
> <anusha.srivatsa@intel.com>; Bhadane, Dnyaneshwar
> <dnyaneshwar.bhadane@intel.com>
> Subject: [PATCH 03/11] drm/i915/TGL: s/RKL/ROCKETLAKE for
> platform/subplatform defines
> 
> Follow consistent naming convention. Replace RKL with ROCKETLAKE.
> 
> Signed-off-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display_power.c | 2 +-
>  drivers/gpu/drm/i915/i915_drv.h                    | 2 +-
>  2 files changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> b/drivers/gpu/drm/i915/display/intel_display_power.c
> index db5437043904..c65505b82065 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -1586,7 +1586,7 @@ static void tgl_bw_buddy_init(struct
> drm_i915_private *dev_priv)
>  		return;
> 
>  	if (IS_ALDERLAKE_S(dev_priv) ||
> -	    IS_RKL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
> +	    IS_ROCKETLAKE_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
>  		/* Wa_1409767108 */
>  		table = wa_1409767108_buddy_page_masks;
>  	else
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 472a36cf1a72..3e9567f9ad15 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -666,7 +666,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>  	(IS_TIGERLAKE(__i915) && \
>  	 IS_DISPLAY_STEP(__i915, since, until))
> 
> -#define IS_RKL_DISPLAY_STEP(p, since, until) \
> +#define IS_ROCKETLAKE_DISPLAY_STEP(p, since, until) \
>  	(IS_ROCKETLAKE(p) && IS_DISPLAY_STEP(p, since, until))
> 
>  #define IS_ADLS_DISPLAY_STEP(__i915, since, until) \
> --
> 2.34.1

Re: [Intel-gfx] [PATCH 04/11] drm/i915/JSL: s/JSL/JASPERLAKE for platform/subplatform defines

[Srivatsa, Anusha]

Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>


> -----Original Message-----
> From: Bhadane, Dnyaneshwar <dnyaneshwar.bhadane@intel.com>
> Sent: Wednesday, June 14, 2023 10:00 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Atwood, Matthew S <matthew.s.atwood@intel.com>; Srivatsa, Anusha
> <anusha.srivatsa@intel.com>; Bhadane, Dnyaneshwar
> <dnyaneshwar.bhadane@intel.com>
> Subject: [PATCH 04/11] drm/i915/JSL: s/JSL/JASPERLAKE for
> platform/subplatform defines
> 
> Follow consistent naming convention. Replace JSL with JASPERLAKE.
> 
> Signed-off-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>
> ---
>  drivers/gpu/drm/i915/display/icl_dsi.c         |  4 ++--
>  drivers/gpu/drm/i915/display/intel_cdclk.c     |  4 ++--
>  drivers/gpu/drm/i915/display/intel_combo_phy.c |  6 +++---
>  drivers/gpu/drm/i915/display/intel_ddi.c       |  6 +++---
>  drivers/gpu/drm/i915/display/intel_display.c   |  6 +++---
>  drivers/gpu/drm/i915/display/intel_dp.c        |  2 +-
>  drivers/gpu/drm/i915/display/intel_dpll_mgr.c  | 18 +++++++++---------
>  drivers/gpu/drm/i915/display/intel_hdmi.c      |  2 +-
>  drivers/gpu/drm/i915/display/intel_psr.c       |  2 +-
>  drivers/gpu/drm/i915/gem/i915_gem_object.c     |  2 +-
>  drivers/gpu/drm/i915/gt/intel_sseu.c           |  2 +-
>  drivers/gpu/drm/i915/gt/intel_workarounds.c    |  2 +-
>  drivers/gpu/drm/i915/i915_drv.h                | 10 +++++-----
>  drivers/gpu/drm/i915/intel_step.c              |  2 +-
>  drivers/gpu/drm/i915/soc/intel_pch.c           |  6 +++---
>  15 files changed, 37 insertions(+), 37 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
> b/drivers/gpu/drm/i915/display/icl_dsi.c
> index 59a2a289d9be..70f045da3bac 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> @@ -444,7 +444,7 @@ static void
> gen11_dsi_config_phy_lanes_sequence(struct intel_encoder *encoder)
>  		intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), tmp);
> 
>  		/* For EHL, TGL, set latency optimization for PCS_DW1 lanes */
> -		if (IS_JSL_EHL(dev_priv) || (DISPLAY_VER(dev_priv) >= 12)) {
> +		if (IS_JASPERLAKE_EHL(dev_priv) || (DISPLAY_VER(dev_priv) >=
> 12)) {
>  			intel_de_rmw(dev_priv,
> ICL_PORT_PCS_DW1_AUX(phy),
>  				     LATENCY_OPTIM_MASK,
> LATENCY_OPTIM_VAL(0));
> 
> @@ -553,7 +553,7 @@ gen11_dsi_setup_dphy_timings(struct intel_encoder
> *encoder,
>  		}
>  	}
> 
> -	if (IS_JSL_EHL(dev_priv)) {
> +	if (IS_JASPERLAKE_EHL(dev_priv)) {
>  		for_each_dsi_phy(phy, intel_dsi->phys)
>  			intel_de_rmw(dev_priv, ICL_DPHY_CHKN(phy),
>  				     0, ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP);
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
> b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 4207863b7b2a..2acfa0435675 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -3147,7 +3147,7 @@ static int intel_compute_max_dotclk(struct
> drm_i915_private *dev_priv)
>   */
>  void intel_update_max_cdclk(struct drm_i915_private *dev_priv)  {
> -	if (IS_JSL_EHL(dev_priv)) {
> +	if (IS_JASPERLAKE_EHL(dev_priv)) {
>  		if (dev_priv->display.cdclk.hw.ref == 24000)
>  			dev_priv->display.cdclk.max_cdclk_freq = 552000;
>  		else
> @@ -3575,7 +3575,7 @@ void intel_init_cdclk_hooks(struct drm_i915_private
> *dev_priv)
>  	} else if (DISPLAY_VER(dev_priv) >= 12) {
>  		dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
>  		dev_priv->display.cdclk.table = icl_cdclk_table;
> -	} else if (IS_JSL_EHL(dev_priv)) {
> +	} else if (IS_JASPERLAKE_EHL(dev_priv)) {
>  		dev_priv->display.funcs.cdclk = &ehl_cdclk_funcs;
>  		dev_priv->display.cdclk.table = icl_cdclk_table;
>  	} else if (DISPLAY_VER(dev_priv) >= 11) { diff --git
> a/drivers/gpu/drm/i915/display/intel_combo_phy.c
> b/drivers/gpu/drm/i915/display/intel_combo_phy.c
> index 922a6d87b553..37bd6d31ced1 100644
> --- a/drivers/gpu/drm/i915/display/intel_combo_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c
> @@ -141,7 +141,7 @@ static bool has_phy_misc(struct drm_i915_private
> *i915, enum phy phy)
> 
>  	if (IS_ALDERLAKE_S(i915))
>  		return phy == PHY_A;
> -	else if (IS_JSL_EHL(i915) ||
> +	else if (IS_JASPERLAKE_EHL(i915) ||
>  		 IS_ROCKETLAKE(i915) ||
>  		 IS_DG1(i915))
>  		return phy < PHY_C;
> @@ -242,7 +242,7 @@ static bool icl_combo_phy_verify_state(struct
> drm_i915_private *dev_priv,
>  		ret &= check_phy_reg(dev_priv, phy,
> ICL_PORT_COMP_DW8(phy),
>  				     IREFGEN, IREFGEN);
> 
> -		if (IS_JSL_EHL(dev_priv)) {
> +		if (IS_JASPERLAKE_EHL(dev_priv)) {
>  			if (ehl_vbt_ddi_d_present(dev_priv))
>  				expected_val = ICL_PHY_MISC_MUX_DDID;
> 
> @@ -333,7 +333,7 @@ static void icl_combo_phys_init(struct drm_i915_private
> *dev_priv)
>  		 * "internal" child devices.
>  		 */
>  		val = intel_de_read(dev_priv, ICL_PHY_MISC(phy));
> -		if (IS_JSL_EHL(dev_priv) && phy == PHY_A) {
> +		if (IS_JASPERLAKE_EHL(dev_priv) && phy == PHY_A) {
>  			val &= ~ICL_PHY_MISC_MUX_DDID;
> 
>  			if (ehl_vbt_ddi_d_present(dev_priv)) diff --git
> a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 090f242e610c..106387ff3658 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -3582,7 +3582,7 @@ void intel_ddi_compute_min_voltage_level(struct
> drm_i915_private *dev_priv,  {
>  	if (DISPLAY_VER(dev_priv) >= 12 && crtc_state->port_clock > 594000)
>  		crtc_state->min_voltage_level = 2;
> -	else if (IS_JSL_EHL(dev_priv) && crtc_state->port_clock > 594000)
> +	else if (IS_JASPERLAKE_EHL(dev_priv) && crtc_state->port_clock >
> +594000)
>  		crtc_state->min_voltage_level = 3;
>  	else if (DISPLAY_VER(dev_priv) >= 11 && crtc_state->port_clock >
> 594000)
>  		crtc_state->min_voltage_level = 1;
> @@ -4801,7 +4801,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv,
> enum port port)
>  		encoder->disable_clock = dg1_ddi_disable_clock;
>  		encoder->is_clock_enabled = dg1_ddi_is_clock_enabled;
>  		encoder->get_config = dg1_ddi_get_config;
> -	} else if (IS_JSL_EHL(dev_priv)) {
> +	} else if (IS_JASPERLAKE_EHL(dev_priv)) {
>  		if (intel_ddi_is_tc(dev_priv, port)) {
>  			encoder->enable_clock = jsl_ddi_tc_enable_clock;
>  			encoder->disable_clock = jsl_ddi_tc_disable_clock; @@
> -4872,7 +4872,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv,
> enum port port)
>  		encoder->hpd_pin = rkl_hpd_pin(dev_priv, port);
>  	else if (DISPLAY_VER(dev_priv) >= 12)
>  		encoder->hpd_pin = tgl_hpd_pin(dev_priv, port);
> -	else if (IS_JSL_EHL(dev_priv))
> +	else if (IS_JASPERLAKE_EHL(dev_priv))
>  		encoder->hpd_pin = ehl_hpd_pin(dev_priv, port);
>  	else if (DISPLAY_VER(dev_priv) == 11)
>  		encoder->hpd_pin = icl_hpd_pin(dev_priv, port); diff --git
> a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index d8533603ad05..e659f8abaec8 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -1750,7 +1750,7 @@ bool intel_phy_is_combo(struct drm_i915_private
> *dev_priv, enum phy phy)
>  		return phy <= PHY_E;
>  	else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
>  		return phy <= PHY_D;
> -	else if (IS_JSL_EHL(dev_priv))
> +	else if (IS_JASPERLAKE_EHL(dev_priv))
>  		return phy <= PHY_C;
>  	else if (IS_ALDERLAKE_P(dev_priv) || IS_DISPLAY_VER(dev_priv, 11, 12))
>  		return phy <= PHY_B;
> @@ -1802,7 +1802,7 @@ enum phy intel_port_to_phy(struct drm_i915_private
> *i915, enum port port)
>  		return PHY_B + port - PORT_TC1;
>  	else if ((IS_DG1(i915) || IS_ROCKETLAKE(i915)) && port >= PORT_TC1)
>  		return PHY_C + port - PORT_TC1;
> -	else if (IS_JSL_EHL(i915) && port == PORT_D)
> +	else if (IS_JASPERLAKE_EHL(i915) && port == PORT_D)
>  		return PHY_A;
> 
>  	return PHY_A + port - PORT_A;
> @@ -7440,7 +7440,7 @@ void intel_setup_outputs(struct drm_i915_private
> *dev_priv)
>  		intel_ddi_init(dev_priv, PORT_TC5);
>  		intel_ddi_init(dev_priv, PORT_TC6);
>  		icl_dsi_init(dev_priv);
> -	} else if (IS_JSL_EHL(dev_priv)) {
> +	} else if (IS_JASPERLAKE_EHL(dev_priv)) {
>  		intel_ddi_init(dev_priv, PORT_A);
>  		intel_ddi_init(dev_priv, PORT_B);
>  		intel_ddi_init(dev_priv, PORT_C);
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 09dc6c88ad28..da9962b914f4 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -500,7 +500,7 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
>  		else if (IS_ALDERLAKE_P(dev_priv) || IS_ALDERLAKE_S(dev_priv)
> ||
>  			 IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
>  			max_rate = 810000;
> -		else if (IS_JSL_EHL(dev_priv))
> +		else if (IS_JASPERLAKE_EHL(dev_priv))
>  			max_rate = ehl_max_source_rate(intel_dp);
>  		else
>  			max_rate = icl_max_source_rate(intel_dp); diff --git
> a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index 6b2d8a1e2aa9..c6d376d414b8 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -191,7 +191,7 @@ intel_combo_pll_enable_reg(struct drm_i915_private
> *i915,  {
>  	if (IS_DG1(i915))
>  		return DG1_DPLL_ENABLE(pll->info->id);
> -	else if (IS_JSL_EHL(i915) && (pll->info->id == DPLL_ID_EHL_DPLL4))
> +	else if (IS_JASPERLAKE_EHL(i915) && (pll->info->id ==
> +DPLL_ID_EHL_DPLL4))
>  		return MG_PLL_ENABLE(0);
> 
>  	return ICL_DPLL_ENABLE(pll->info->id); @@ -2461,7 +2461,7 @@ static
> bool  ehl_combo_pll_div_frac_wa_needed(struct drm_i915_private *i915)  {
>  	return ((IS_PLATFORM(i915, INTEL_ELKHARTLAKE) &&
> -		 IS_JSL_EHL_DISPLAY_STEP(i915, STEP_B0, STEP_FOREVER)) ||
> +		 IS_JASPERLAKE_EHL_DISPLAY_STEP(i915, STEP_B0,
> STEP_FOREVER)) ||
>  		 IS_TIGERLAKE(i915) || IS_ALDERLAKE_S(i915) ||
> IS_ALDERLAKE_P(i915)) &&
>  		 i915->display.dpll.ref_clks.nssc == 38400;  } @@ -3226,7
> +3226,7 @@ static int icl_get_combo_phy_dpll(struct intel_atomic_state
> *state,
>  			BIT(DPLL_ID_EHL_DPLL4) |
>  			BIT(DPLL_ID_ICL_DPLL1) |
>  			BIT(DPLL_ID_ICL_DPLL0);
> -	} else if (IS_JSL_EHL(dev_priv) && port != PORT_A) {
> +	} else if (IS_JASPERLAKE_EHL(dev_priv) && port != PORT_A) {
>  		dpll_mask =
>  			BIT(DPLL_ID_EHL_DPLL4) |
>  			BIT(DPLL_ID_ICL_DPLL1) |
> @@ -3567,7 +3567,7 @@ static bool icl_pll_get_hw_state(struct
> drm_i915_private *dev_priv,
>  			hw_state->div0 &=
> TGL_DPLL0_DIV0_AFC_STARTUP_MASK;
>  		}
>  	} else {
> -		if (IS_JSL_EHL(dev_priv) && id == DPLL_ID_EHL_DPLL4) {
> +		if (IS_JASPERLAKE_EHL(dev_priv) && id == DPLL_ID_EHL_DPLL4)
> {
>  			hw_state->cfgcr0 = intel_de_read(dev_priv,
>  							 ICL_DPLL_CFGCR0(4));
>  			hw_state->cfgcr1 = intel_de_read(dev_priv, @@ -
> 3623,7 +3623,7 @@ static void icl_dpll_write(struct drm_i915_private
> *dev_priv,
>  		cfgcr1_reg = TGL_DPLL_CFGCR1(id);
>  		div0_reg = TGL_DPLL0_DIV0(id);
>  	} else {
> -		if (IS_JSL_EHL(dev_priv) && id == DPLL_ID_EHL_DPLL4) {
> +		if (IS_JASPERLAKE_EHL(dev_priv) && id == DPLL_ID_EHL_DPLL4)
> {
>  			cfgcr0_reg = ICL_DPLL_CFGCR0(4);
>  			cfgcr1_reg = ICL_DPLL_CFGCR1(4);
>  		} else {
> @@ -3806,7 +3806,7 @@ static void combo_pll_enable(struct
> drm_i915_private *dev_priv,  {
>  	i915_reg_t enable_reg = intel_combo_pll_enable_reg(dev_priv, pll);
> 
> -	if (IS_JSL_EHL(dev_priv) &&
> +	if (IS_JASPERLAKE_EHL(dev_priv) &&
>  	    pll->info->id == DPLL_ID_EHL_DPLL4) {
> 
>  		/*
> @@ -3914,7 +3914,7 @@ static void combo_pll_disable(struct
> drm_i915_private *dev_priv,
> 
>  	icl_pll_disable(dev_priv, pll, enable_reg);
> 
> -	if (IS_JSL_EHL(dev_priv) &&
> +	if (IS_JASPERLAKE_EHL(dev_priv) &&
>  	    pll->info->id == DPLL_ID_EHL_DPLL4)
>  		intel_display_power_put(dev_priv, POWER_DOMAIN_DC_OFF,
>  					pll->wakeref);
> @@ -4150,7 +4150,7 @@ void intel_shared_dpll_init(struct drm_i915_private
> *dev_priv)
>  		dpll_mgr = &rkl_pll_mgr;
>  	else if (DISPLAY_VER(dev_priv) >= 12)
>  		dpll_mgr = &tgl_pll_mgr;
> -	else if (IS_JSL_EHL(dev_priv))
> +	else if (IS_JASPERLAKE_EHL(dev_priv))
>  		dpll_mgr = &ehl_pll_mgr;
>  	else if (DISPLAY_VER(dev_priv) >= 11)
>  		dpll_mgr = &icl_pll_mgr;
> @@ -4335,7 +4335,7 @@ static void readout_dpll_hw_state(struct
> drm_i915_private *i915,
> 
>  	pll->on = intel_dpll_get_hw_state(i915, pll, &pll->state.hw_state);
> 
> -	if (IS_JSL_EHL(i915) && pll->on &&
> +	if (IS_JASPERLAKE_EHL(i915) && pll->on &&
>  	    pll->info->id == DPLL_ID_EHL_DPLL4) {
>  		pll->wakeref = intel_display_power_get(i915,
> 
> POWER_DOMAIN_DC_OFF);
> diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
> b/drivers/gpu/drm/i915/display/intel_hdmi.c
> index 7ac5e6c5e00d..4e557594ba62 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> @@ -2903,7 +2903,7 @@ static u8 intel_hdmi_ddc_pin(struct intel_encoder
> *encoder)
>  		ddc_pin = rkl_port_to_ddc_pin(dev_priv, port);
>  	else if (DISPLAY_VER(dev_priv) == 9 && HAS_PCH_TGP(dev_priv))
>  		ddc_pin = gen9bc_tgp_port_to_ddc_pin(dev_priv, port);
> -	else if (IS_JSL_EHL(dev_priv) && HAS_PCH_TGP(dev_priv))
> +	else if (IS_JASPERLAKE_EHL(dev_priv) && HAS_PCH_TGP(dev_priv))
>  		ddc_pin = mcc_port_to_ddc_pin(dev_priv, port);
>  	else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
>  		ddc_pin = icl_port_to_ddc_pin(dev_priv, port); diff --git
> a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 06b464229efe..f61d39d2b0fc 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -963,7 +963,7 @@ static bool intel_psr2_config_valid(struct intel_dp
> *intel_dp,
>  		return false;
> 
>  	/* JSL and EHL only supports eDP 1.3 */
> -	if (IS_JSL_EHL(dev_priv)) {
> +	if (IS_JASPERLAKE_EHL(dev_priv)) {
>  		drm_dbg_kms(&dev_priv->drm, "PSR2 not supported by
> phy\n");
>  		return false;
>  	}
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.c
> b/drivers/gpu/drm/i915/gem/i915_gem_object.c
> index 97ac6fb37958..0b34518d051c 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_object.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_object.c
> @@ -226,7 +226,7 @@ bool i915_gem_object_can_bypass_llc(struct
> drm_i915_gem_object *obj)
>  	 * it, but since i915 takes the stance of always zeroing memory before
>  	 * handing it to userspace, we need to prevent this.
>  	 */
> -	return IS_JSL_EHL(i915);
> +	return IS_JASPERLAKE_EHL(i915);
>  }
> 
>  static void i915_gem_close_object(struct drm_gem_object *gem, struct
> drm_file *file) diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c
> b/drivers/gpu/drm/i915/gt/intel_sseu.c
> index 1141f875f5bd..6945a0bc9778 100644
> --- a/drivers/gpu/drm/i915/gt/intel_sseu.c
> +++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
> @@ -302,7 +302,7 @@ static void gen11_sseu_info_init(struct intel_gt *gt)
>  	u8 eu_en;
>  	u8 s_en;
> 
> -	if (IS_JSL_EHL(gt->i915))
> +	if (IS_JASPERLAKE_EHL(gt->i915))
>  		intel_sseu_set_info(sseu, 1, 4, 8);
>  	else
>  		intel_sseu_set_info(sseu, 1, 8, 8);
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index a109ecd54944..a62dcbc2f901 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -1441,7 +1441,7 @@ icl_gt_workarounds_init(struct intel_gt *gt, struct
> i915_wa_list *wal)
> 
>  	/* Wa_1607087056:icl,ehl,jsl */
>  	if (IS_ICELAKE(i915) ||
> -	    IS_JSL_EHL_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
> +	    IS_JASPERLAKE_EHL_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
>  		wa_write_or(wal,
>  			    GEN11_SLICE_UNIT_LEVEL_CLKGATE,
>  			    L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS); diff --git
> a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index
> 3e9567f9ad15..3981b890f053 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -563,7 +563,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>  #define IS_COFFEELAKE(i915)	IS_PLATFORM(i915, INTEL_COFFEELAKE)
>  #define IS_COMETLAKE(i915)	IS_PLATFORM(i915, INTEL_COMETLAKE)
>  #define IS_ICELAKE(i915)	IS_PLATFORM(i915, INTEL_ICELAKE)
> -#define IS_JSL_EHL(i915)	(IS_PLATFORM(i915, INTEL_JASPERLAKE) || \
> +#define IS_JASPERLAKE_EHL(i915)	(IS_PLATFORM(i915,
> INTEL_JASPERLAKE) || \
>  				IS_PLATFORM(i915, INTEL_ELKHARTLAKE))
>  #define IS_TIGERLAKE(i915)	IS_PLATFORM(i915, INTEL_TIGERLAKE)
>  #define IS_ROCKETLAKE(i915)	IS_PLATFORM(i915, INTEL_ROCKETLAKE)
> @@ -657,10 +657,10 @@ IS_SUBPLATFORM(const struct drm_i915_private
> *i915,  #define IS_KBL_DISPLAY_STEP(i915, since, until) \
>  	(IS_KABYLAKE(i915) && IS_DISPLAY_STEP(i915, since, until))
> 
> -#define IS_JSL_EHL_GRAPHICS_STEP(p, since, until) \
> -	(IS_JSL_EHL(p) && IS_GRAPHICS_STEP(p, since, until))
> -#define IS_JSL_EHL_DISPLAY_STEP(p, since, until) \
> -	(IS_JSL_EHL(p) && IS_DISPLAY_STEP(p, since, until))
> +#define IS_JASPERLAKE_EHL_GRAPHICS_STEP(p, since, until) \
> +	(IS_JASPERLAKE_EHL(p) && IS_GRAPHICS_STEP(p, since, until)) #define
> +IS_JASPERLAKE_EHL_DISPLAY_STEP(p, since, until) \
> +	(IS_JASPERLAKE_EHL(p) && IS_DISPLAY_STEP(p, since, until))
> 
>  #define IS_TIGERLAKE_DISPLAY_STEP(__i915, since, until) \
>  	(IS_TIGERLAKE(__i915) && \
> diff --git a/drivers/gpu/drm/i915/intel_step.c
> b/drivers/gpu/drm/i915/intel_step.c
> index 67054c87bb5f..847c7de50e1f 100644
> --- a/drivers/gpu/drm/i915/intel_step.c
> +++ b/drivers/gpu/drm/i915/intel_step.c
> @@ -219,7 +219,7 @@ void intel_step_init(struct drm_i915_private *i915)
>  	} else if (IS_TIGERLAKE(i915)) {
>  		revids = tgl_revids;
>  		size = ARRAY_SIZE(tgl_revids);
> -	} else if (IS_JSL_EHL(i915)) {
> +	} else if (IS_JASPERLAKE_EHL(i915)) {
>  		revids = jsl_ehl_revids;
>  		size = ARRAY_SIZE(jsl_ehl_revids);
>  	} else if (IS_ICELAKE(i915)) {
> diff --git a/drivers/gpu/drm/i915/soc/intel_pch.c
> b/drivers/gpu/drm/i915/soc/intel_pch.c
> index ba9843cb1b13..2e78b17843da 100644
> --- a/drivers/gpu/drm/i915/soc/intel_pch.c
> +++ b/drivers/gpu/drm/i915/soc/intel_pch.c
> @@ -115,7 +115,7 @@ intel_pch_type(const struct drm_i915_private
> *dev_priv, unsigned short id)
>  		return PCH_ICP;
>  	case INTEL_PCH_MCC_DEVICE_ID_TYPE:
>  		drm_dbg_kms(&dev_priv->drm, "Found Mule Creek Canyon
> PCH\n");
> -		drm_WARN_ON(&dev_priv->drm, !IS_JSL_EHL(dev_priv));
> +		drm_WARN_ON(&dev_priv->drm,
> !IS_JASPERLAKE_EHL(dev_priv));
>  		/* MCC is TGP compatible */
>  		return PCH_TGP;
>  	case INTEL_PCH_TGP_DEVICE_ID_TYPE:
> @@ -127,7 +127,7 @@ intel_pch_type(const struct drm_i915_private
> *dev_priv, unsigned short id)
>  		return PCH_TGP;
>  	case INTEL_PCH_JSP_DEVICE_ID_TYPE:
>  		drm_dbg_kms(&dev_priv->drm, "Found Jasper Lake PCH\n");
> -		drm_WARN_ON(&dev_priv->drm, !IS_JSL_EHL(dev_priv));
> +		drm_WARN_ON(&dev_priv->drm,
> !IS_JASPERLAKE_EHL(dev_priv));
>  		/* JSP is ICP compatible */
>  		return PCH_ICP;
>  	case INTEL_PCH_ADP_DEVICE_ID_TYPE:
> @@ -177,7 +177,7 @@ intel_virt_detect_pch(const struct drm_i915_private
> *dev_priv,
>  		id = INTEL_PCH_ADP_DEVICE_ID_TYPE;
>  	else if (IS_TIGERLAKE(dev_priv) || IS_ROCKETLAKE(dev_priv))
>  		id = INTEL_PCH_TGP_DEVICE_ID_TYPE;
> -	else if (IS_JSL_EHL(dev_priv))
> +	else if (IS_JASPERLAKE_EHL(dev_priv))
>  		id = INTEL_PCH_MCC_DEVICE_ID_TYPE;
>  	else if (IS_ICELAKE(dev_priv))
>  		id = INTEL_PCH_ICP_DEVICE_ID_TYPE;
> --
> 2.34.1

Re: [Intel-gfx] [PATCH 05/11] drm/i915/KBL: s/KBL/KABYLAKE for platform/subplatform defines

[Srivatsa, Anusha]

OK one thing that holds true for all patches in the series is the subject: drm/i915/PLATFORM:
The general convention is to have platform is lower cases I the subject prefix. So all occurrences of drm/i915/PLATFORM should be replaced with drm/i915/platform.
This is something I have missed mentioning in the previous patches that gave a r-b to.


Apart from the above mentioned platform prefix feedback,
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>

> -----Original Message-----
> From: Bhadane, Dnyaneshwar <dnyaneshwar.bhadane@intel.com>
> Sent: Wednesday, June 14, 2023 10:00 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Atwood, Matthew S <matthew.s.atwood@intel.com>; Srivatsa, Anusha
> <anusha.srivatsa@intel.com>; Bhadane, Dnyaneshwar
> <dnyaneshwar.bhadane@intel.com>
> Subject: [PATCH 05/11] drm/i915/KBL: s/KBL/KABYLAKE for
> platform/subplatform defines
> 
> Follow consistent naming convention. Replace KBL with KABYLAKE.
> 
> Signed-off-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c |  4 ++--
>  drivers/gpu/drm/i915/gt/gen8_engine_cs.c           |  2 +-
>  drivers/gpu/drm/i915/gt/intel_workarounds.c        |  6 +++---
>  drivers/gpu/drm/i915/i915_drv.h                    | 12 ++++++------
>  drivers/gpu/drm/i915/intel_clock_gating.c          |  4 ++--
>  5 files changed, 14 insertions(+), 14 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
> b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
> index 9e34cc103aeb..84b09d188d2a 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
> @@ -1718,9 +1718,9 @@ void intel_ddi_buf_trans_init(struct intel_encoder
> *encoder)
>  			encoder->get_buf_trans = icl_get_mg_buf_trans;
>  	} else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) {
>  		encoder->get_buf_trans = bxt_get_buf_trans;
> -	} else if (IS_CML_ULX(i915) || IS_CFL_ULX(i915) || IS_KBL_ULX(i915)) {
> +	} else if (IS_CML_ULX(i915) || IS_CFL_ULX(i915) ||
> +IS_KABYLAKE_ULX(i915)) {
>  		encoder->get_buf_trans = kbl_y_get_buf_trans;
> -	} else if (IS_CML_ULT(i915) || IS_CFL_ULT(i915) || IS_KBL_ULT(i915)) {
> +	} else if (IS_CML_ULT(i915) || IS_CFL_ULT(i915) ||
> +IS_KABYLAKE_ULT(i915)) {
>  		encoder->get_buf_trans = kbl_u_get_buf_trans;
>  	} else if (IS_COMETLAKE(i915) || IS_COFFEELAKE(i915) ||
> IS_KABYLAKE(i915)) {
>  		encoder->get_buf_trans = kbl_get_buf_trans; diff --git
> a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> index eb72610a8588..ec0771dc662a 100644
> --- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> @@ -43,7 +43,7 @@ int gen8_emit_flush_rcs(struct i915_request *rq, u32
> mode)
>  			vf_flush_wa = true;
> 
>  		/* WaForGAMHang:kbl */
> -		if (IS_KBL_GRAPHICS_STEP(rq->engine->i915, 0, STEP_C0))
> +		if (IS_KABYLAKE_GRAPHICS_STEP(rq->engine->i915, 0,
> STEP_C0))
>  			dc_flush_wa = true;
>  	}
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index a62dcbc2f901..b632fb5592a8 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -584,7 +584,7 @@ static void kbl_ctx_workarounds_init(struct
> intel_engine_cs *engine,
>  	gen9_ctx_workarounds_init(engine, wal);
> 
>  	/* WaToEnableHwFixForPushConstHWBug:kbl */
> -	if (IS_KBL_GRAPHICS_STEP(i915, STEP_C0, STEP_FOREVER))
> +	if (IS_KABYLAKE_GRAPHICS_STEP(i915, STEP_C0, STEP_FOREVER))
>  		wa_masked_en(wal, COMMON_SLICE_CHICKEN2,
>  			     GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
> 
> @@ -1185,7 +1185,7 @@ kbl_gt_workarounds_init(struct intel_gt *gt, struct
> i915_wa_list *wal)
>  	gen9_gt_workarounds_init(gt, wal);
> 
>  	/* WaDisableDynamicCreditSharing:kbl */
> -	if (IS_KBL_GRAPHICS_STEP(gt->i915, 0, STEP_C0))
> +	if (IS_KABYLAKE_GRAPHICS_STEP(gt->i915, 0, STEP_C0))
>  		wa_write_or(wal,
>  			    GAMT_CHKN_BIT_REG,
> 
> GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING);
> @@ -2933,7 +2933,7 @@ xcs_engine_wa_init(struct intel_engine_cs *engine,
> struct i915_wa_list *wal)
>  	struct drm_i915_private *i915 = engine->i915;
> 
>  	/* WaKBLVECSSemaphoreWaitPoll:kbl */
> -	if (IS_KBL_GRAPHICS_STEP(i915, STEP_A0, STEP_F0)) {
> +	if (IS_KABYLAKE_GRAPHICS_STEP(i915, STEP_A0, STEP_F0)) {
>  		wa_write(wal,
>  			 RING_SEMA_WAIT_POLL(engine->mmio_base),
>  			 1);
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 3981b890f053..f19915115cff 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -614,9 +614,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>  	IS_SUBPLATFORM(i915, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULT)
> #define IS_SKL_ULX(i915) \
>  	IS_SUBPLATFORM(i915, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULX) -
> #define IS_KBL_ULT(i915) \
> +#define IS_KABYLAKE_ULT(i915) \
>  	IS_SUBPLATFORM(i915, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT)
> -#define IS_KBL_ULX(i915) \
> +#define IS_KABYLAKE_ULX(i915) \
>  	IS_SUBPLATFORM(i915, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX)
>  #define IS_SKL_GT2(i915)	(IS_SKYLAKE(i915) && \
>  				 INTEL_INFO(i915)->gt == 2)
> @@ -624,9 +624,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>  				 INTEL_INFO(i915)->gt == 3)
>  #define IS_SKL_GT4(i915)	(IS_SKYLAKE(i915) && \
>  				 INTEL_INFO(i915)->gt == 4)
> -#define IS_KBL_GT2(i915)	(IS_KABYLAKE(i915) && \
> +#define IS_KABYLAKE_GT2(i915)	(IS_KABYLAKE(i915) && \
>  				 INTEL_INFO(i915)->gt == 2)
> -#define IS_KBL_GT3(i915)	(IS_KABYLAKE(i915) && \
> +#define IS_KABYLAKE_GT3(i915)	(IS_KABYLAKE(i915) && \
>  				 INTEL_INFO(i915)->gt == 3)
>  #define IS_CFL_ULT(i915) \
>  	IS_SUBPLATFORM(i915, INTEL_COFFEELAKE,
> INTEL_SUBPLATFORM_ULT) @@ -652,9 +652,9 @@ IS_SUBPLATFORM(const
> struct drm_i915_private *i915,
> 
>  #define IS_SKL_GRAPHICS_STEP(p, since, until) (IS_SKYLAKE(p) &&
> IS_GRAPHICS_STEP(p, since, until))
> 
> -#define IS_KBL_GRAPHICS_STEP(i915, since, until) \
> +#define IS_KABYLAKE_GRAPHICS_STEP(i915, since, until) \
>  	(IS_KABYLAKE(i915) && IS_GRAPHICS_STEP(i915, since, until)) -#define
> IS_KBL_DISPLAY_STEP(i915, since, until) \
> +#define IS_KABYLAKE_DISPLAY_STEP(i915, since, until) \
>  	(IS_KABYLAKE(i915) && IS_DISPLAY_STEP(i915, since, until))
> 
>  #define IS_JASPERLAKE_EHL_GRAPHICS_STEP(p, since, until) \ diff --git
> a/drivers/gpu/drm/i915/intel_clock_gating.c
> b/drivers/gpu/drm/i915/intel_clock_gating.c
> index a27600bc5976..bb349043522c 100644
> --- a/drivers/gpu/drm/i915/intel_clock_gating.c
> +++ b/drivers/gpu/drm/i915/intel_clock_gating.c
> @@ -456,12 +456,12 @@ static void kbl_init_clock_gating(struct
> drm_i915_private *i915)
>  	intel_uncore_rmw(&i915->uncore, FBC_LLC_READ_CTRL, 0,
> FBC_LLC_FULLY_OPEN);
> 
>  	/* WaDisableSDEUnitClockGating:kbl */
> -	if (IS_KBL_GRAPHICS_STEP(i915, 0, STEP_C0))
> +	if (IS_KABYLAKE_GRAPHICS_STEP(i915, 0, STEP_C0))
>  		intel_uncore_rmw(&i915->uncore, GEN8_UCGCTL6,
>  				 0, GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
> 
>  	/* WaDisableGamClockGating:kbl */
> -	if (IS_KBL_GRAPHICS_STEP(i915, 0, STEP_C0))
> +	if (IS_KABYLAKE_GRAPHICS_STEP(i915, 0, STEP_C0))
>  		intel_uncore_rmw(&i915->uncore, GEN6_UCGCTL1,
>  				 0, GEN6_GAMUNIT_CLOCK_GATE_DISABLE);
> 
> --
> 2.34.1

Re: [Intel-gfx] [PATCH 06/11] drm/i915/SKL: s/SKL/SKYLAKE for platform/subplatform defines

[Srivatsa, Anusha]

Apart from the platform subject prefix,

Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>


> -----Original Message-----
> From: Bhadane, Dnyaneshwar <dnyaneshwar.bhadane@intel.com>
> Sent: Wednesday, June 14, 2023 10:00 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Atwood, Matthew S <matthew.s.atwood@intel.com>; Srivatsa, Anusha
> <anusha.srivatsa@intel.com>; Bhadane, Dnyaneshwar
> <dnyaneshwar.bhadane@intel.com>
> Subject: [PATCH 06/11] drm/i915/SKL: s/SKL/SKYLAKE for platform/subplatform
> defines
> 
> Follow consistent naming convention. Replace SKL with SKYLAKE.
> 
> Signed-off-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c |  4 ++--
>  drivers/gpu/drm/i915/gt/intel_workarounds.c        |  2 +-
>  drivers/gpu/drm/i915/i915_drv.h                    | 14 +++++++-------
>  3 files changed, 10 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
> b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
> index 84b09d188d2a..ab84d003232c 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
> @@ -1724,9 +1724,9 @@ void intel_ddi_buf_trans_init(struct intel_encoder
> *encoder)
>  		encoder->get_buf_trans = kbl_u_get_buf_trans;
>  	} else if (IS_COMETLAKE(i915) || IS_COFFEELAKE(i915) ||
> IS_KABYLAKE(i915)) {
>  		encoder->get_buf_trans = kbl_get_buf_trans;
> -	} else if (IS_SKL_ULX(i915)) {
> +	} else if (IS_SKYLAKE_ULX(i915)) {
>  		encoder->get_buf_trans = skl_y_get_buf_trans;
> -	} else if (IS_SKL_ULT(i915)) {
> +	} else if (IS_SKYLAKE_ULT(i915)) {
>  		encoder->get_buf_trans = skl_u_get_buf_trans;
>  	} else if (IS_SKYLAKE(i915)) {
>  		encoder->get_buf_trans = skl_get_buf_trans; diff --git
> a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index b632fb5592a8..10a4e0fc23ec 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -1173,7 +1173,7 @@ skl_gt_workarounds_init(struct intel_gt *gt, struct
> i915_wa_list *wal)
>  		    GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE);
> 
>  	/* WaInPlaceDecompressionHang:skl */
> -	if (IS_SKL_GRAPHICS_STEP(gt->i915, STEP_A0, STEP_H0))
> +	if (IS_SKYLAKE_GRAPHICS_STEP(gt->i915, STEP_A0, STEP_H0))
>  		wa_write_or(wal,
>  			    GEN9_GAMT_ECO_REG_RW_IA,
>  			    GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index f19915115cff..3c4a66f1a7ba 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -610,19 +610,19 @@ IS_SUBPLATFORM(const struct drm_i915_private
> *i915,
>  /* ULX machines are also considered ULT. */  #define IS_HSW_ULX(i915) \
>  	IS_SUBPLATFORM(i915, INTEL_HASWELL, INTEL_SUBPLATFORM_ULX) -
> #define IS_SKL_ULT(i915) \
> +#define IS_SKYLAKE_ULT(i915) \
>  	IS_SUBPLATFORM(i915, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULT) -
> #define IS_SKL_ULX(i915) \
> +#define IS_SKYLAKE_ULX(i915) \
>  	IS_SUBPLATFORM(i915, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULX)
> #define IS_KABYLAKE_ULT(i915) \
>  	IS_SUBPLATFORM(i915, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT)
> #define IS_KABYLAKE_ULX(i915) \
>  	IS_SUBPLATFORM(i915, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX)
> -#define IS_SKL_GT2(i915)	(IS_SKYLAKE(i915) && \
> +#define IS_SKYLAKE_GT2(i915)	(IS_SKYLAKE(i915) && \
>  				 INTEL_INFO(i915)->gt == 2)
> -#define IS_SKL_GT3(i915)	(IS_SKYLAKE(i915) && \
> +#define IS_SKYLAKE_GT3(i915)	(IS_SKYLAKE(i915) && \
>  				 INTEL_INFO(i915)->gt == 3)
> -#define IS_SKL_GT4(i915)	(IS_SKYLAKE(i915) && \
> +#define IS_SKYLAKE_GT4(i915)	(IS_SKYLAKE(i915) && \
>  				 INTEL_INFO(i915)->gt == 4)
>  #define IS_KABYLAKE_GT2(i915)	(IS_KABYLAKE(i915) && \
>  				 INTEL_INFO(i915)->gt == 2)
> @@ -650,7 +650,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> #define IS_TIGERLAKE_UY(i915) \
>  	IS_SUBPLATFORM(i915, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_UY)
> 
> -#define IS_SKL_GRAPHICS_STEP(p, since, until) (IS_SKYLAKE(p) &&
> IS_GRAPHICS_STEP(p, since, until))
> +#define IS_SKYLAKE_GRAPHICS_STEP(p, since, until) (IS_SKYLAKE(p) &&
> +IS_GRAPHICS_STEP(p, since, until))
> 
>  #define IS_KABYLAKE_GRAPHICS_STEP(i915, since, until) \
>  	(IS_KABYLAKE(i915) && IS_GRAPHICS_STEP(i915, since, until)) @@ -
> 801,7 +801,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> 
>  /* WaRsDisableCoarsePowerGating:skl,cnl */
>  #define NEEDS_WaRsDisableCoarsePowerGating(i915)			\
> -	(IS_SKL_GT3(i915) || IS_SKL_GT4(i915))
> +	(IS_SKYLAKE_GT3(i915) || IS_SKYLAKE_GT4(i915))
> 
>  /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
>   * rows, which changed the alignment requirements and fence programming.
> --
> 2.34.1

Re: [Intel-gfx] [PATCH 07/11] drm/i915/adlp: s/ADLP/ALDERLAKE_P for display and graphics step

[Srivatsa, Anusha]

> -----Original Message-----
> From: Bhadane, Dnyaneshwar <dnyaneshwar.bhadane@intel.com>
> Sent: Wednesday, June 14, 2023 10:00 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Atwood, Matthew S <matthew.s.atwood@intel.com>; Srivatsa, Anusha
> <anusha.srivatsa@intel.com>; Bhadane, Dnyaneshwar
> <dnyaneshwar.bhadane@intel.com>
> Subject: [PATCH 07/11] drm/i915/adlp: s/ADLP/ALDERLAKE_P for display and
> graphics step
> 
> From: Anusha Srivatsa <anusha.srivatsa@intel.com>
> 
> Driver refers to the platfrom Alderlake P as ADLP in places and ALDERLAKE_P in
			^^^ noyiced I have made a typo	😝 @Bhadane, Dnyaneshwar You can fix the typo and add you S-O-B too with mine in the next spin.

Anusha
> some. Making the consistent change to avoid confusion of the right naming
> convention for the platform.
> 
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cdclk.c         | 2 +-
>  drivers/gpu/drm/i915/display/intel_dpll_mgr.c      | 2 +-
>  drivers/gpu/drm/i915/display/intel_psr.c           | 8 ++++----
>  drivers/gpu/drm/i915/display/skl_universal_plane.c | 4 ++--
>  drivers/gpu/drm/i915/i915_drv.h                    | 4 ++--
>  5 files changed, 10 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
> b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 2acfa0435675..831d1258ea3f 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -3559,7 +3559,7 @@ void intel_init_cdclk_hooks(struct drm_i915_private
> *dev_priv)
>  		dev_priv->display.cdclk.table = dg2_cdclk_table;
>  	} else if (IS_ALDERLAKE_P(dev_priv)) {
>  		/* Wa_22011320316:adl-p[a0] */
> -		if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) {
> +		if (IS_ALDERLAKE_P_DISPLAY_STEP(dev_priv, STEP_A0,
> STEP_B0))
>  			dev_priv->display.cdclk.table =
> adlp_a_step_cdclk_table;
>  			dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
>  		} else if (IS_ADLP_RPLU(dev_priv)) {
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index c6d376d414b8..47fe8311067e 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -3781,7 +3781,7 @@ static void adlp_cmtg_clock_gating_wa(struct
> drm_i915_private *i915, struct inte  {
>  	u32 val;
> 
> -	if (!IS_ADLP_DISPLAY_STEP(i915, STEP_A0, STEP_B0) ||
> +	if (!IS_ALDERLAKE_P_DISPLAY_STEP(i915, STEP_A0, STEP_B0) ||
>  	    pll->info->id != DPLL_ID_ICL_DPLL0)
>  		return;
>  	/*
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index f61d39d2b0fc..00c98c2b4324 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -639,7 +639,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
>  	}
> 
>  	/* Wa_22012278275:adl-p */
> -	if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_E0)) {
> +	if (IS_ALDERLAKE_P_DISPLAY_STEP(dev_priv, STEP_A0, STEP_E0)) {
>  		static const u8 map[] = {
>  			2, /* 5 lines */
>  			1, /* 6 lines */
> @@ -807,7 +807,7 @@ tgl_dc3co_exitline_compute_config(struct intel_dp
> *intel_dp,
>  		return;
> 
>  	/* Wa_16011303918:adl-p */
> -	if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
> +	if (IS_ALDERLAKE_P_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
>  		return;
> 
>  	/*
> @@ -975,7 +975,7 @@ static bool intel_psr2_config_valid(struct intel_dp
> *intel_dp,
>  		return false;
>  	}
> 
> -	if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) {
> +	if (IS_ALDERLAKE_P_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) {
>  		drm_dbg_kms(&dev_priv->drm, "PSR2 not completely
> functional in this stepping\n");
>  		return false;
>  	}
> @@ -1033,7 +1033,7 @@ static bool intel_psr2_config_valid(struct intel_dp
> *intel_dp,
> 
>  	/* Wa_16011303918:adl-p */
>  	if (crtc_state->vrr.enable &&
> -	    IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) {
> +	    IS_ALDERLAKE_P_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) {
>  		drm_dbg_kms(&dev_priv->drm,
>  			    "PSR2 not enabled, not compatible with HW stepping
> + VRR\n");
>  		return false;
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> index 25b06ced9ce7..2458a9ea25ba 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> @@ -2174,7 +2174,7 @@ static bool skl_plane_has_rc_ccs(struct
> drm_i915_private *i915,
>  		return false;
> 
>  	/* Wa_22011186057 */
> -	if (IS_ADLP_DISPLAY_STEP(i915, STEP_A0, STEP_B0))
> +	if (IS_ALDERLAKE_P_DISPLAY_STEP(i915, STEP_A0, STEP_B0))
>  		return false;
> 
>  	if (DISPLAY_VER(i915) >= 11)
> @@ -2200,7 +2200,7 @@ static bool gen12_plane_has_mc_ccs(struct
> drm_i915_private *i915,
>  		return false;
> 
>  	/* Wa_22011186057 */
> -	if (IS_ADLP_DISPLAY_STEP(i915, STEP_A0, STEP_B0))
> +	if (IS_ALDERLAKE_P_DISPLAY_STEP(i915, STEP_A0, STEP_B0))
>  		return false;
> 
>  	/* Wa_14013215631 */
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 3c4a66f1a7ba..08e14cf225b5 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -677,11 +677,11 @@ IS_SUBPLATFORM(const struct drm_i915_private
> *i915,
>  	(IS_ALDERLAKE_S(__i915) && \
>  	 IS_GRAPHICS_STEP(__i915, since, until))
> 
> -#define IS_ADLP_DISPLAY_STEP(__i915, since, until) \
> +#define IS_ALDERLAKE_P_DISPLAY_STEP(__i915, since, until) \
>  	(IS_ALDERLAKE_P(__i915) && \
>  	 IS_DISPLAY_STEP(__i915, since, until))
> 
> -#define IS_ADLP_GRAPHICS_STEP(__i915, since, until) \
> +#define IS_ALDERLAKE_P_GRAPHICS_STEP(__i915, since, until) \
>  	(IS_ALDERLAKE_P(__i915) && \
>  	 IS_GRAPHICS_STEP(__i915, since, until))
> 
> --
> 2.34.1

Re: [Intel-gfx] [PATCH 00/11] Replace acronym with full platform name in defines.

[Srivatsa, Anusha]

> -----Original Message-----
> From: Bhadane, Dnyaneshwar <dnyaneshwar.bhadane@intel.com>
> Sent: Wednesday, June 14, 2023 10:00 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Atwood, Matthew S <matthew.s.atwood@intel.com>; Srivatsa, Anusha
> <anusha.srivatsa@intel.com>; Bhadane, Dnyaneshwar
> <dnyaneshwar.bhadane@intel.com>
> Subject: [PATCH 00/11] Replace acronym with full platform name in defines.
> 
> Replace all occurences of ADL with ALDERLAKE, TGL with TIGERLAKE, MTL with
> METEORLAKE, RKL with ROCKETLAKE, JSL with JASPERLAKE, KBL with KABYLAKE
> and SKL with SKYLAKE in platform and subplatform defines. This way there is a
> consistent pattern to how platforms are referred. While the change is minor and
> could be combined to have lesser patches, splitting to per subpaltform for easier
> cherrypicks, if needed.

Thanks for taking this forward. I have reviewed the patches with the only feedback being use of lower case in the subject prefix. But the series also needs platform reordering. It should start from oldest to newest platform. SO
Patch 1:SKL
Patch 2:KBL
Patch 3:RKL
And so on. Order being:
SLK->KBL->RKL->JSL->TGL->ADLPS and its various flavours->ADLS->MTL

Anusha 
> 
> Anusha Srivatsa (5):
>   drm/i915/adlp: s/ADLP/ALDERLAKE_P for display and graphics step
>   drm/i915/rplp: s/ADLP/ALDERLAKE_P for RPLP defines
>   drm/i915/adln: s/ADLP/ALDERLAKE_P in ADLN defines
>   drm/i915/adls: s/ADLS/ALDERLAKE_S in platform and subplatform defines
>   drm/i915/rplu: s/ADLP/ALDERLAKE_P in RPLU defines
> 
> Dnyaneshwar Bhadane (6):
>   drm/i915/TGL: s/TGL/TIGERLAKE for platform/subplatform defines
>   drm/i915/MTL: s/MTL/METEORLAKE for platform/subplatform defines
>   drm/i915/TGL: s/RKL/ROCKETLAKE for platform/subplatform defines
>   drm/i915/JSL: s/JSL/JASPERLAKE for platform/subplatform defines
>   drm/i915/KBL: s/KBL/KABYLAKE for platform/subplatform defines
>   drm/i915/SKL: s/SKL/SKYLAKE for platform/subplatform defines
> 
>  drivers/gpu/drm/i915/display/icl_dsi.c        |  4 +-
>  drivers/gpu/drm/i915/display/intel_cdclk.c    |  8 +--
>  .../gpu/drm/i915/display/intel_combo_phy.c    |  6 +-
>  drivers/gpu/drm/i915/display/intel_ddi.c      |  6 +-
>  .../drm/i915/display/intel_ddi_buf_trans.c    | 10 +--
>  drivers/gpu/drm/i915/display/intel_display.c  |  6 +-
>  .../drm/i915/display/intel_display_device.c   |  2 +-
>  .../drm/i915/display/intel_display_power.c    |  2 +-
>  drivers/gpu/drm/i915/display/intel_dp.c       |  2 +-
>  drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 20 +++---
>  drivers/gpu/drm/i915/display/intel_fbc.c      |  2 +-
>  drivers/gpu/drm/i915/display/intel_hdmi.c     |  2 +-
>  drivers/gpu/drm/i915/display/intel_pmdemand.c |  2 +-
>  drivers/gpu/drm/i915/display/intel_psr.c      | 20 +++---
>  .../drm/i915/display/skl_universal_plane.c    | 10 +--
>  drivers/gpu/drm/i915/gem/i915_gem_object.c    |  2 +-
>  drivers/gpu/drm/i915/gt/gen8_engine_cs.c      | 10 +--
>  drivers/gpu/drm/i915/gt/intel_engine_cs.c     |  2 +-
>  .../drm/i915/gt/intel_execlists_submission.c  |  2 +-
>  drivers/gpu/drm/i915/gt/intel_gt_mcr.c        |  4 +-
>  drivers/gpu/drm/i915/gt/intel_lrc.c           |  4 +-
>  drivers/gpu/drm/i915/gt/intel_rc6.c           |  2 +-
>  drivers/gpu/drm/i915/gt/intel_sseu.c          |  2 +-
>  drivers/gpu/drm/i915/gt/intel_workarounds.c   | 54 ++++++++--------
>  drivers/gpu/drm/i915/gt/uc/intel_guc.c        |  4 +-
>  .../gpu/drm/i915/gt/uc/intel_guc_hwconfig.c   |  2 +-
>  .../gpu/drm/i915/gt/uc/intel_guc_submission.c |  4 +-
>  drivers/gpu/drm/i915/gt/uc/intel_uc.c         |  2 +-
>  drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c      |  2 +-
>  drivers/gpu/drm/i915/i915_drv.h               | 64 +++++++++----------
>  drivers/gpu/drm/i915/i915_perf.c              |  4 +-
>  drivers/gpu/drm/i915/intel_clock_gating.c     |  4 +-
>  drivers/gpu/drm/i915/intel_step.c             | 10 +--
>  drivers/gpu/drm/i915/soc/intel_pch.c          |  6 +-
>  34 files changed, 143 insertions(+), 143 deletions(-)
> 
> --
> 2.34.1