From: Zhanjun Dong <zhanjun.dong@intel.com>
To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH] drm/i915/gt: Remove incorrect hard coded cache coherrency setting
Date: Fri, 16 Jun 2023 15:11:10 -0700 [thread overview]
Message-ID: <20230616221110.1045918-1-zhanjun.dong@intel.com> (raw)
The previouse i915_gem_object_create_internal already set it with proper
value before function return. This hard coded setting is incorrect for
platforms like MTL, thus need to be removed.
Signed-off-by: Zhanjun Dong <zhanjun.dong@intel.com>
---
drivers/gpu/drm/i915/gt/intel_timeline.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_timeline.c b/drivers/gpu/drm/i915/gt/intel_timeline.c
index b9640212d659..693d18e14b00 100644
--- a/drivers/gpu/drm/i915/gt/intel_timeline.c
+++ b/drivers/gpu/drm/i915/gt/intel_timeline.c
@@ -26,8 +26,6 @@ static struct i915_vma *hwsp_alloc(struct intel_gt *gt)
if (IS_ERR(obj))
return ERR_CAST(obj);
- i915_gem_object_set_cache_coherency(obj, I915_CACHE_LLC);
-
vma = i915_vma_instance(obj, >->ggtt->vm, NULL);
if (IS_ERR(vma))
i915_gem_object_put(obj);
--
2.34.1
next reply other threads:[~2023-06-16 22:11 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-16 22:11 Zhanjun Dong [this message]
2023-06-22 12:27 ` [Intel-gfx] [PATCH] drm/i915/gt: Remove incorrect hard coded cache coherrency setting Nirmoy Das
-- strict thread matches above, loose matches on Subject: below --
2023-06-22 15:26 Zhanjun Dong
2023-06-22 15:29 ` Dong, Zhanjun
2023-06-22 22:20 ` Yang, Fei
2023-06-23 18:02 ` Dong, Zhanjun
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