From: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH v3 1/2] drm/i915/color: Upscale degamma values for MTL
Date: Tue, 25 Jul 2023 14:00:01 +0530 [thread overview]
Message-ID: <20230725083002.3779717-2-chaitanya.kumar.borah@intel.com> (raw)
In-Reply-To: <20230725083002.3779717-1-chaitanya.kumar.borah@intel.com>
MTL onwards Degamma LUT/PRE-CSC LUT precision has been increased from
16 bits to 24 bits. Currently, drm framework only supports LUTs up to 16
bit precision. Until a new uapi comes along to support higher bitdepth,
upscale the values sent from userland to 24 bit before writing into the
HW to continue supporting degamma on MTL.
Add helper function to upscale or downscale lut values. Parameters
'to' and 'from' needs to be less than 32. This should be sufficient
as currently there are no lut values exceeding 32 bit.
v2: (Jani)
- Reuse glk_load_degamma_lut()
- Create a helper function for upscaling values
v3: Fix multi line comment style (Uma)
Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/display/intel_color.c | 20 +++++++++++++++++++-
1 file changed, 19 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 8966e6560516..32182cdff928 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -1453,6 +1453,17 @@ static int glk_degamma_lut_size(struct drm_i915_private *i915)
return 35;
}
+/*
+ * change_lut_val_precision: helper function to upscale or downscale lut values.
+ * Parameters 'to' and 'from' needs to be less than 32. This should be sufficient
+ * as currently there are no lut values exceeding 32 bit.
+ */
+
+static u32 change_lut_val_precision(u32 lut_val, int to, int from)
+{
+ return mul_u32_u32(lut_val, (1 << to)) / (1 << from);
+}
+
static void glk_load_degamma_lut(const struct intel_crtc_state *crtc_state,
const struct drm_property_blob *blob)
{
@@ -1487,8 +1498,15 @@ static void glk_load_degamma_lut(const struct intel_crtc_state *crtc_state,
* ToDo: Extend to max 7.0. Enable 32 bit input value
* as compared to just 16 to achieve this.
*/
+ u32 lut_val;
+
+ if (DISPLAY_VER(i915) >= 14)
+ lut_val = change_lut_val_precision(lut[i].green, 24, 16);
+ else
+ lut_val = lut[i].green;
+
ilk_lut_write(crtc_state, PRE_CSC_GAMC_DATA(pipe),
- lut[i].green);
+ lut_val);
}
/* Clamp values > 1.0. */
--
2.25.1
next prev parent reply other threads:[~2023-07-25 8:31 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-25 8:30 [Intel-gfx] [PATCH 0/2] MTL Degamma implementation Chaitanya Kumar Borah
2023-07-25 8:30 ` Chaitanya Kumar Borah [this message]
2023-07-27 12:00 ` [Intel-gfx] [PATCH v3 1/2] drm/i915/color: Upscale degamma values for MTL Nautiyal, Ankit K
2023-07-27 12:33 ` [Intel-gfx] [PATCH v4 " Chaitanya Kumar Borah
2023-07-25 8:30 ` [Intel-gfx] [PATCH v2 2/2] drm/i915/color: Downscale degamma lut values read from hardware Chaitanya Kumar Borah
2023-07-25 9:57 ` [Intel-gfx] ✓ Fi.CI.BAT: success for MTL Degamma implementation (rev3) Patchwork
2023-07-25 15:11 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2023-07-26 6:16 ` Patchwork
2023-07-26 6:31 ` [Intel-gfx] ✓ Fi.CI.IGT: success " Patchwork
2023-07-27 11:57 ` [Intel-gfx] [PATCH 0/2] MTL Degamma implementation Nautiyal, Ankit K
2023-07-27 13:06 ` Nautiyal, Ankit K
2023-07-27 18:07 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for MTL Degamma implementation (rev4) Patchwork
2023-07-27 18:17 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-07-27 22:15 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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