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From: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH v2 2/2] drm/i915/color: Downscale degamma lut values read from hardware
Date: Tue, 25 Jul 2023 14:00:02 +0530	[thread overview]
Message-ID: <20230725083002.3779717-3-chaitanya.kumar.borah@intel.com> (raw)
In-Reply-To: <20230725083002.3779717-1-chaitanya.kumar.borah@intel.com>

For MTL and beyond, convert back the 24 bit lut values
read from HW to 16 bit values to maintain parity with
userspace values. This way we avoid pipe config mismatch
for pre-csc lut values.

v2: Add helper function to downscale values (Jani)

Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
---
 drivers/gpu/drm/i915/display/intel_color.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 32182cdff928..d78e2715d419 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -3457,6 +3457,14 @@ static struct drm_property_blob *glk_read_degamma_lut(struct intel_crtc *crtc)
 	for (i = 0; i < lut_size; i++) {
 		u32 val = intel_de_read_fw(dev_priv, PRE_CSC_GAMC_DATA(pipe));
 
+		/*
+		 * For MTL and beyond, convert back the 24 bit lut values
+		 * read from HW to 16 bit values to maintain parity with
+		 * userspace values
+		 */
+		if (DISPLAY_VER(dev_priv) >= 14)
+			val = change_lut_val_precision(val, 16, 24);
+
 		lut[i].red = val;
 		lut[i].green = val;
 		lut[i].blue = val;
-- 
2.25.1


  parent reply	other threads:[~2023-07-25  8:31 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-07-25  8:30 [Intel-gfx] [PATCH 0/2] MTL Degamma implementation Chaitanya Kumar Borah
2023-07-25  8:30 ` [Intel-gfx] [PATCH v3 1/2] drm/i915/color: Upscale degamma values for MTL Chaitanya Kumar Borah
2023-07-27 12:00   ` Nautiyal, Ankit K
2023-07-27 12:33   ` [Intel-gfx] [PATCH v4 " Chaitanya Kumar Borah
2023-07-25  8:30 ` Chaitanya Kumar Borah [this message]
2023-07-25  9:57 ` [Intel-gfx] ✓ Fi.CI.BAT: success for MTL Degamma implementation (rev3) Patchwork
2023-07-25 15:11 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2023-07-26  6:16 ` Patchwork
2023-07-26  6:31 ` [Intel-gfx] ✓ Fi.CI.IGT: success " Patchwork
2023-07-27 11:57 ` [Intel-gfx] [PATCH 0/2] MTL Degamma implementation Nautiyal, Ankit K
2023-07-27 13:06   ` Nautiyal, Ankit K
2023-07-27 18:07 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for MTL Degamma implementation (rev4) Patchwork
2023-07-27 18:17 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-07-27 22:15 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
  -- strict thread matches above, loose matches on Subject: below --
2023-07-10 13:43 [Intel-gfx] [PATCH 0/2] MTL Degamma implementation Chaitanya Kumar Borah
2023-07-10 13:43 ` [Intel-gfx] [PATCH v2 2/2] drm/i915/color: Downscale degamma lut values read from hardware Chaitanya Kumar Borah
2023-07-20 12:00   ` Shankar, Uma

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