From: Imre Deak <imre.deak@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH 05/17] drm/i915/dp: Limit the output link bpp in DSC mode
Date: Thu, 17 Aug 2023 19:14:44 +0300 [thread overview]
Message-ID: <20230817161456.3857111-6-imre.deak@intel.com> (raw)
In-Reply-To: <20230817161456.3857111-1-imre.deak@intel.com>
Limit the output link bpp in DSC mode to the link_config_limits
link.min_bpp .. max_bpp range the same way it's done in non-DSC mode.
Atm, this doesn't make a difference, the link bpp range being
0 .. max pipe bpp, but a follow-up patch will need a way to reduce max
link bpp below its current value.
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 12 +++++++++++-
drivers/gpu/drm/i915/display/intel_dp_mst.c | 3 +++
2 files changed, 14 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index c4016fd0dc980..b5d38765dde54 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1703,9 +1703,16 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
pipe_config->lane_count = limits->max_lane_count;
if (intel_dp_is_edp(intel_dp)) {
+ u16 dsc_max_output_bpp;
+
+ dsc_max_output_bpp =
+ min_t(u16, drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd),
+ limits->link.max_bpp);
+
pipe_config->dsc.compressed_bpp =
- min_t(u16, drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4,
+ min_t(u16, dsc_max_output_bpp >> 4,
pipe_config->pipe_bpp);
+
pipe_config->dsc.slice_count =
drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
true);
@@ -1761,6 +1768,9 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
* calculation procedure is bit different for MST case.
*/
if (compute_pipe_bpp) {
+ dsc_max_output_bpp = min_t(u16, dsc_max_output_bpp,
+ limits->link.max_bpp);
+
pipe_config->dsc.compressed_bpp = min_t(u16,
dsc_max_output_bpp >> 4,
pipe_config->pipe_bpp);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 48c247ddef53a..0dcb9a203dfe7 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -230,6 +230,9 @@ static int intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder,
if (max_bpp > sink_max_bpp)
max_bpp = sink_max_bpp;
+ min_bpp = max(min_bpp, (limits->link.min_bpp + 0xf) >> 4);
+ max_bpp = min(max_bpp, limits->link.max_bpp >> 4);
+
slots = intel_dp_mst_find_vcpi_slots_for_bpp(encoder, crtc_state, max_bpp,
min_bpp, limits,
conn_state, 2 * 3, true);
--
2.37.2
next prev parent reply other threads:[~2023-08-17 16:16 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-08-17 16:14 [Intel-gfx] [PATCH 00/17] drm/i915: Improve BW management on shared display links Imre Deak
2023-08-17 16:14 ` [Intel-gfx] [PATCH 01/17] drm/i915/dp: Factor out helpers to compute the link limits Imre Deak
2023-08-17 16:14 ` [Intel-gfx] [PATCH 02/17] drm/i915/dp: Track the pipe and link bpp limits separately Imre Deak
2023-08-17 16:27 ` Jani Nikula
2023-08-18 8:24 ` Kandpal, Suraj
2023-08-18 14:06 ` Imre Deak
2023-08-18 13:26 ` Imre Deak
2023-08-17 16:14 ` [Intel-gfx] [PATCH 03/17] drm/i915/dp: Skip computing a non-DSC link config if DSC is needed Imre Deak
2023-08-17 16:14 ` [Intel-gfx] [PATCH 04/17] drm/i915/dp: Update the link bpp limits for DSC mode Imre Deak
2023-08-17 16:14 ` Imre Deak [this message]
2023-08-17 16:14 ` [Intel-gfx] [PATCH 06/17] drm/i915: Add helper to modeset a set of pipes Imre Deak
2023-08-17 16:14 ` [Intel-gfx] [PATCH 07/17] drm/i915: Factor out a helper to check/compute all the CRTC states Imre Deak
2023-08-17 16:14 ` [Intel-gfx] [PATCH 08/17] drm/i915/fdi: Improve FDI BW sharing between pipe B and C Imre Deak
2023-08-17 16:14 ` [Intel-gfx] [PATCH 09/17] drm/dp_mst: Fix fractional bpp scaling in drm_dp_calc_pbn_mode() Imre Deak
2023-08-17 16:14 ` [Intel-gfx] [PATCH 10/17] drm/dp_mst: Add a way to calculate PBN values with FEC overhead Imre Deak
2023-08-17 16:14 ` [Intel-gfx] [PATCH 11/17] drm/dp_mst: Add helper to determine if an MST port is downstream of another port Imre Deak
2023-08-17 16:14 ` [Intel-gfx] [PATCH 12/17] drm/dp_mst: Factor out a helper to check the atomic state of a topology manager Imre Deak
2023-08-17 16:14 ` [Intel-gfx] [PATCH 13/17] drm/dp_mst: Swap the order of checking root vs. non-root port BW limitations Imre Deak
2023-08-17 16:14 ` [Intel-gfx] [PATCH 14/17] drm/i915/dp_mst: Fix PBN calculation with FEC overhead Imre Deak
2023-08-17 16:14 ` [Intel-gfx] [PATCH 15/17] drm/i915/dp_mst: Add atomic state for all streams on pre-tgl platforms Imre Deak
2023-08-17 16:14 ` [Intel-gfx] [PATCH 16/17] drm/i915/dp_mst: Improve BW sharing between MST streams Imre Deak
2023-08-17 16:14 ` [Intel-gfx] [PATCH 17/17] drm/i915/dp_mst: Check BW limitations only when all streams are computed Imre Deak
2023-08-18 1:33 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Improve BW management on shared display links Patchwork
2023-08-18 1:33 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-08-18 1:49 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-08-19 2:20 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
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