From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH 03/12] drm/i915: Extract intel_crtc_vblank_evade_scanlines()
Date: Fri, 1 Sep 2023 16:04:31 +0300 [thread overview]
Message-ID: <20230901130440.2085-4-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <20230901130440.2085-1-ville.syrjala@linux.intel.com>
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Pull the vblank evasion scanline calculations into their own helper
to declutter intel_pipe_update_start() a bit.
Reviewed-by: Manasi Navare <navaremanasi@chromium.org>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_crtc.c | 53 +++++++++++++----------
1 file changed, 31 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c
index 461949b48411..e46a15d59d79 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc.c
@@ -468,6 +468,36 @@ static int intel_mode_vblank_start(const struct drm_display_mode *mode)
return vblank_start;
}
+static void intel_crtc_vblank_evade_scanlines(struct intel_atomic_state *state,
+ struct intel_crtc *crtc,
+ int *min, int *max, int *vblank_start)
+{
+ const struct intel_crtc_state *new_crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
+ const struct drm_display_mode *adjusted_mode = &new_crtc_state->hw.adjusted_mode;
+
+ if (new_crtc_state->vrr.enable) {
+ if (intel_vrr_is_push_sent(new_crtc_state))
+ *vblank_start = intel_vrr_vmin_vblank_start(new_crtc_state);
+ else
+ *vblank_start = intel_vrr_vmax_vblank_start(new_crtc_state);
+ } else {
+ *vblank_start = intel_mode_vblank_start(adjusted_mode);
+ }
+
+ /* FIXME needs to be calibrated sensibly */
+ *min = *vblank_start - intel_usecs_to_scanlines(adjusted_mode,
+ VBLANK_EVASION_TIME_US);
+ *max = *vblank_start - 1;
+
+ /*
+ * M/N is double buffered on the transcoder's undelayed vblank,
+ * so with seamless M/N we must evade both vblanks.
+ */
+ if (new_crtc_state->seamless_m_n && intel_crtc_needs_fastset(new_crtc_state))
+ *min -= adjusted_mode->crtc_vblank_start - adjusted_mode->crtc_vdisplay;
+}
+
/**
* intel_pipe_update_start() - start update of a set of display registers
* @state: the atomic state
@@ -487,7 +517,6 @@ void intel_pipe_update_start(struct intel_atomic_state *state,
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
struct intel_crtc_state *new_crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
- const struct drm_display_mode *adjusted_mode = &new_crtc_state->hw.adjusted_mode;
long timeout = msecs_to_jiffies_timeout(1);
int scanline, min, max, vblank_start;
wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(&crtc->base);
@@ -503,27 +532,7 @@ void intel_pipe_update_start(struct intel_atomic_state *state,
if (intel_crtc_needs_vblank_work(new_crtc_state))
intel_crtc_vblank_work_init(new_crtc_state);
- if (new_crtc_state->vrr.enable) {
- if (intel_vrr_is_push_sent(new_crtc_state))
- vblank_start = intel_vrr_vmin_vblank_start(new_crtc_state);
- else
- vblank_start = intel_vrr_vmax_vblank_start(new_crtc_state);
- } else {
- vblank_start = intel_mode_vblank_start(adjusted_mode);
- }
-
- /* FIXME needs to be calibrated sensibly */
- min = vblank_start - intel_usecs_to_scanlines(adjusted_mode,
- VBLANK_EVASION_TIME_US);
- max = vblank_start - 1;
-
- /*
- * M/N is double buffered on the transcoder's undelayed vblank,
- * so with seamless M/N we must evade both vblanks.
- */
- if (new_crtc_state->seamless_m_n && intel_crtc_needs_fastset(new_crtc_state))
- min -= adjusted_mode->crtc_vblank_start - adjusted_mode->crtc_vdisplay;
-
+ intel_crtc_vblank_evade_scanlines(state, crtc, &min, &max, &vblank_start);
if (min <= 0 || max <= 0)
goto irq_disable;
--
2.41.0
next prev parent reply other threads:[~2023-09-01 13:05 UTC|newest]
Thread overview: 52+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-01 13:04 [Intel-gfx] [PATCH 00/12] drm/i915: VRR, LRR, and M/N stuff Ville Syrjala
2023-09-01 13:04 ` [Intel-gfx] [PATCH 01/12] drm/i915: Move psr unlock out from the pipe update critical section Ville Syrjala
2023-09-07 18:34 ` Manasi Navare
2023-09-11 17:42 ` Golani, Mitulkumar Ajitkumar
2023-09-01 13:04 ` [Intel-gfx] [PATCH 02/12] drm/i915: Change intel_pipe_update_{start, end}() calling convention Ville Syrjala
2023-09-07 18:36 ` Manasi Navare
2023-09-11 17:53 ` Golani, Mitulkumar Ajitkumar
2023-09-01 13:04 ` Ville Syrjala [this message]
2023-09-11 18:18 ` [Intel-gfx] [PATCH 03/12] drm/i915: Extract intel_crtc_vblank_evade_scanlines() Golani, Mitulkumar Ajitkumar
2023-09-01 13:04 ` [Intel-gfx] [PATCH 04/12] drm/i915: Enable VRR later during fastsets Ville Syrjala
2023-09-07 18:38 ` Manasi Navare
2023-09-11 18:24 ` Golani, Mitulkumar Ajitkumar
2023-09-01 13:04 ` [Intel-gfx] [PATCH 05/12] drm/i915: Adjust seamless_m_n flag behaviour Ville Syrjala
2023-09-07 18:39 ` Manasi Navare
2023-09-01 13:04 ` [Intel-gfx] [PATCH 06/12] drm/i915: Optimize out redundant M/N updates Ville Syrjala
2023-09-07 18:40 ` Manasi Navare
2023-09-01 13:04 ` [Intel-gfx] [PATCH 07/12] drm/i915: Relocate is_in_vrr_range() Ville Syrjala
2023-09-07 18:43 ` Manasi Navare
2023-09-15 5:38 ` Golani, Mitulkumar Ajitkumar
2023-09-01 13:04 ` [Intel-gfx] [PATCH 08/12] drm/i915: Validate that the timings are within the VRR range Ville Syrjala
2023-09-07 18:44 ` Manasi Navare
2023-09-15 5:39 ` Golani, Mitulkumar Ajitkumar
2023-09-01 13:04 ` [Intel-gfx] [PATCH 09/12] drm/i915: Disable VRR during seamless M/N changes Ville Syrjala
2023-09-07 18:49 ` Manasi Navare
2023-09-08 5:53 ` Ville Syrjälä
2023-09-08 23:29 ` Manasi Navare
2023-09-11 17:46 ` Golani, Mitulkumar Ajitkumar
2023-09-01 13:04 ` [Intel-gfx] [PATCH 10/12] drm/i915: Update VRR parameters in fastset Ville Syrjala
2023-09-14 17:05 ` Sean Paul
2023-09-01 13:04 ` [Intel-gfx] [PATCH 11/12] drm/i915: Assert that VRR is off during vblank evasion if necessary Ville Syrjala
2023-09-07 18:49 ` Manasi Navare
2023-09-15 8:34 ` Golani, Mitulkumar Ajitkumar
2023-09-01 13:04 ` [Intel-gfx] [PATCH 12/12] drm/i915: Implement transcoder LRR for TGL+ Ville Syrjala
2023-09-14 23:21 ` Manasi Navare
2023-09-15 10:23 ` Ville Syrjälä
2023-09-15 10:38 ` [Intel-gfx] [PATCH v2 " Ville Syrjala
2023-09-18 23:16 ` Manasi Navare
2023-09-20 18:47 ` Manasi Navare
2023-09-20 19:40 ` Ville Syrjälä
2023-09-20 20:40 ` Manasi Navare
2023-09-01 16:00 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: VRR, LRR, and M/N stuff Patchwork
2023-09-01 16:00 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-09-01 16:16 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2023-09-01 18:38 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: VRR, LRR, and M/N stuff (rev2) Patchwork
2023-09-01 18:38 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-09-01 18:58 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-09-02 4:49 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2023-09-15 11:18 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: VRR, LRR, and M/N stuff (rev3) Patchwork
2023-09-15 11:18 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-09-15 11:34 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2023-09-20 18:54 ` [Intel-gfx] [PATCH 00/12] drm/i915: VRR, LRR, and M/N stuff Manasi Navare
2023-09-20 20:56 ` Ville Syrjälä
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