* [Intel-gfx] [PATCH v8 0/3] Apply Wa_16018031267 / Wa_16018063123
@ 2023-09-08 0:29 Jonathan Cavitt
2023-09-08 0:29 ` [Intel-gfx] [PATCH v8 1/3] drm/i915: Reserve some kernel space per vm Jonathan Cavitt
` (5 more replies)
0 siblings, 6 replies; 7+ messages in thread
From: Jonathan Cavitt @ 2023-09-08 0:29 UTC (permalink / raw)
To: intel-gfx
Cc: andi.shyti, chris.p.wilson, tomasz.mistat, jonathan.cavitt,
rodrigo.vivi, gregory.f.germano, matthew.d.roper, nirmoy.das
Apply Wa_16018031267 / Wa_16018063123. This necessitates submitting a
fastcolor blit as WABB and setting the copy engine arbitration to
round-robin mode.
v2:
- Rename old platform check in second patch to match
declaration in first patch.
- Refactor second patch name to match first patch.
v3:
- Move NEEDS_FASTCOLOR_BLT_WABB to intel_gt.h.
- Refactor NEEDS_FASTCOLOR_BLT_WABB to make it more
streamlined to use.
- Stop dividing PAGE_SIZE by sizeof(u32) when computing
ctx_bb_ggtt_addr for lrc_setup_bb_per_ctx.
- Reduce comment complexity.
- Fix several checkpatch warnings.
v4:
- Actually stop dividing PAGE_SIZE by sizeof(u32) when
computing ctx_bb_ggtt_addr for lrc_setup_bb_per_ctx.
v5:
- Stop dividing PAGE_SIZE by sizeof(u32) in
check_ring_start during lrc live selftest.
v6:
- Append MI_BATCH_BUFFER_END to end of all PER_CTX_BB
command streams.
- No longer skip on empty, as command stream will never
be empty (always contains at least MI_BATCH_BUFFER_END).
- No longer append MI_NOOP until cachline aligned (was a
fragment from INDIRECT_CTX setup).
v7:
- Use 0x6b instead of 0 for color to maintain functionality.
v8:
- Revert v7.
- Add some reserved kernel space per vm to run the
workaround on.
Signed-off-by: Nirmoy Das <nirmoy.das@intel.com>
Signed-off-by: Jonathan Cavitt <jonathan.cavitt@intel.com>
CC: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
CC: Rodrigo Vivi <rodrigo.vivi@intel.com>
CC: Tomasz Mistat <tomasz.mistat@intel.com>
CC: Gregory F Germano <gregory.f.germano@intel.com>
CC: Matt Roper <matthew.d.roper@intel.com>
CC: James Ausmus <james.ausmus@intel.com>
CC: Chris Wilson <chris.p.wilson@linux.intel.com>
CC: Andi Shyti <andi.shyti@intel.com>
Jonathan Cavitt (3):
drm/i915: Reserve some kernel space per vm
drm/i915: Add WABB blit for Wa_16018031267 / Wa_16018063123
drm/i915: Set copy engine arbitration for Wa_16018031267 /
Wa_16018063123
drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 7 ++
drivers/gpu/drm/i915/gt/intel_engine_regs.h | 6 ++
drivers/gpu/drm/i915/gt/intel_gt.h | 4 +
drivers/gpu/drm/i915/gt/intel_gt_types.h | 2 +
drivers/gpu/drm/i915/gt/intel_gtt.h | 1 +
drivers/gpu/drm/i915/gt/intel_lrc.c | 101 +++++++++++++++++++-
drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +
drivers/gpu/drm/i915/gt/selftest_lrc.c | 65 +++++++++----
8 files changed, 170 insertions(+), 21 deletions(-)
--
2.25.1
^ permalink raw reply [flat|nested] 7+ messages in thread* [Intel-gfx] [PATCH v8 1/3] drm/i915: Reserve some kernel space per vm 2023-09-08 0:29 [Intel-gfx] [PATCH v8 0/3] Apply Wa_16018031267 / Wa_16018063123 Jonathan Cavitt @ 2023-09-08 0:29 ` Jonathan Cavitt 2023-09-08 0:29 ` [Intel-gfx] [PATCH v8 2/3] drm/i915: Add WABB blit for Wa_16018031267 / Wa_16018063123 Jonathan Cavitt ` (4 subsequent siblings) 5 siblings, 0 replies; 7+ messages in thread From: Jonathan Cavitt @ 2023-09-08 0:29 UTC (permalink / raw) To: intel-gfx Cc: andi.shyti, chris.p.wilson, tomasz.mistat, jonathan.cavitt, rodrigo.vivi, gregory.f.germano, matthew.d.roper, nirmoy.das Reserve a page in each vm for kernel space to use for things such as workarounds. Signed-off-by: Jonathan Cavitt <jonathan.cavitt@intel.com> Suggested-by: Chris Wilson <chris.p.wilson@linux.intel.com> --- drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 7 +++++++ drivers/gpu/drm/i915/gt/intel_gtt.h | 1 + 2 files changed, 8 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c index c8568e5d11479..6680fefcf8858 100644 --- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c +++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c @@ -230,6 +230,7 @@ static void gen8_ppgtt_cleanup(struct i915_address_space *vm) gen8_pd_top_count(vm), vm->top); free_scratch(vm); + drm_mm_remove_node(&vm->rsvd); } static u64 __gen8_ppgtt_clear(struct i915_address_space * const vm, @@ -1011,6 +1012,12 @@ struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt, ppgtt->vm.foreach = gen8_ppgtt_foreach; ppgtt->vm.cleanup = gen8_ppgtt_cleanup; + + ppgtt->vm.rsvd.start = ppgtt->vm.total - SZ_4K; + ppgtt->vm.rsvd.size = SZ_4K; + ppgtt->vm.rsvd.color = I915_COLOR_UNEVICTABLE; + GEM_BUG_ON(drm_mm_reserve_node(&ppgtt->vm.mm, &ppgtt->vm.rsvd)); + err = gen8_init_scratch(&ppgtt->vm); if (err) goto err_put; diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h b/drivers/gpu/drm/i915/gt/intel_gtt.h index 4d6296cdbcfdd..368d8ed98d0e9 100644 --- a/drivers/gpu/drm/i915/gt/intel_gtt.h +++ b/drivers/gpu/drm/i915/gt/intel_gtt.h @@ -246,6 +246,7 @@ struct i915_address_space { struct work_struct release_work; struct drm_mm mm; + struct drm_mm_node rsvd; struct intel_gt *gt; struct drm_i915_private *i915; struct device *dma; -- 2.25.1 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* [Intel-gfx] [PATCH v8 2/3] drm/i915: Add WABB blit for Wa_16018031267 / Wa_16018063123 2023-09-08 0:29 [Intel-gfx] [PATCH v8 0/3] Apply Wa_16018031267 / Wa_16018063123 Jonathan Cavitt 2023-09-08 0:29 ` [Intel-gfx] [PATCH v8 1/3] drm/i915: Reserve some kernel space per vm Jonathan Cavitt @ 2023-09-08 0:29 ` Jonathan Cavitt 2023-09-08 0:29 ` [Intel-gfx] [PATCH v8 3/3] drm/i915: Set copy engine arbitration " Jonathan Cavitt ` (3 subsequent siblings) 5 siblings, 0 replies; 7+ messages in thread From: Jonathan Cavitt @ 2023-09-08 0:29 UTC (permalink / raw) To: intel-gfx Cc: andi.shyti, chris.p.wilson, tomasz.mistat, jonathan.cavitt, rodrigo.vivi, gregory.f.germano, matthew.d.roper, nirmoy.das Apply WABB blit for Wa_16018031267 / Wa_16018063123. Additionally, update the lrc selftest to exercise the new WABB changes. Co-developed-by: Nirmoy Das <nirmoy.das@intel.com> Signed-off-by: Jonathan Cavitt <jonathan.cavitt@intel.com> --- drivers/gpu/drm/i915/gt/intel_engine_regs.h | 3 + drivers/gpu/drm/i915/gt/intel_gt.h | 4 + drivers/gpu/drm/i915/gt/intel_gt_types.h | 2 + drivers/gpu/drm/i915/gt/intel_lrc.c | 101 +++++++++++++++++++- drivers/gpu/drm/i915/gt/selftest_lrc.c | 65 +++++++++---- 5 files changed, 154 insertions(+), 21 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_engine_regs.h b/drivers/gpu/drm/i915/gt/intel_engine_regs.h index 6b9d9f8376692..2e06bea73297a 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_regs.h +++ b/drivers/gpu/drm/i915/gt/intel_engine_regs.h @@ -118,6 +118,9 @@ #define CCID_EXTENDED_STATE_RESTORE BIT(2) #define CCID_EXTENDED_STATE_SAVE BIT(3) #define RING_BB_PER_CTX_PTR(base) _MMIO((base) + 0x1c0) /* gen8+ */ +#define PER_CTX_BB_FORCE BIT(2) +#define PER_CTX_BB_VALID BIT(0) + #define RING_INDIRECT_CTX(base) _MMIO((base) + 0x1c4) /* gen8+ */ #define RING_INDIRECT_CTX_OFFSET(base) _MMIO((base) + 0x1c8) /* gen8+ */ #define ECOSKPD(base) _MMIO((base) + 0x1d0) diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h b/drivers/gpu/drm/i915/gt/intel_gt.h index 239848bcb2a42..40cc0005dd735 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt.h +++ b/drivers/gpu/drm/i915/gt/intel_gt.h @@ -83,6 +83,10 @@ struct drm_printer; ##__VA_ARGS__); \ } while (0) +#define NEEDS_FASTCOLOR_BLT_WABB(engine) ( \ + IS_GFX_GT_IP_RANGE(engine->gt, IP_VER(12, 55), IP_VER(12, 71)) && \ + engine->class == COPY_ENGINE_CLASS) + static inline bool gt_is_root(struct intel_gt *gt) { return !gt->info.id; diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h index def7dd0eb6f19..4917633f299dd 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_types.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h @@ -307,6 +307,8 @@ enum intel_gt_scratch_field { /* 8 bytes */ INTEL_GT_SCRATCH_FIELD_COHERENTL3_WA = 256, + + INTEL_GT_SCRATCH_FIELD_DUMMY_BLIT = 384, }; #define intel_gt_support_legacy_fencing(gt) ((gt)->ggtt->num_fences > 0) diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index 967fe4d77a874..01154174f4ac0 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -828,6 +828,18 @@ lrc_ring_indirect_offset_default(const struct intel_engine_cs *engine) return 0; } +static void +lrc_setup_bb_per_ctx(u32 *regs, + const struct intel_engine_cs *engine, + u32 ctx_bb_ggtt_addr) +{ + GEM_BUG_ON(lrc_ring_wa_bb_per_ctx(engine) == -1); + regs[lrc_ring_wa_bb_per_ctx(engine) + 1] = + ctx_bb_ggtt_addr | + PER_CTX_BB_FORCE | + PER_CTX_BB_VALID; +} + static void lrc_setup_indirect_ctx(u32 *regs, const struct intel_engine_cs *engine, @@ -997,7 +1009,13 @@ static u32 context_wa_bb_offset(const struct intel_context *ce) return PAGE_SIZE * ce->wa_bb_page; } -static u32 *context_indirect_bb(const struct intel_context *ce) +/* + * per_ctx below determines which WABB section is used. + * When true, the function returns the location of the + * PER_CTX_BB. When false, the function returns the + * location of the INDIRECT_CTX. + */ +static u32 *context_wabb(const struct intel_context *ce, bool per_ctx) { void *ptr; @@ -1006,6 +1024,7 @@ static u32 *context_indirect_bb(const struct intel_context *ce) ptr = ce->lrc_reg_state; ptr -= LRC_STATE_OFFSET; /* back to start of context image */ ptr += context_wa_bb_offset(ce); + ptr += per_ctx ? PAGE_SIZE : 0; return ptr; } @@ -1082,7 +1101,8 @@ __lrc_alloc_state(struct intel_context *ce, struct intel_engine_cs *engine) if (GRAPHICS_VER(engine->i915) >= 12) { ce->wa_bb_page = context_size / PAGE_SIZE; - context_size += PAGE_SIZE; + /* INDIRECT_CTX and PER_CTX_BB need separate pages. */ + context_size += PAGE_SIZE * 2; } if (intel_context_is_parent(ce) && intel_engine_uses_guc(engine)) { @@ -1370,12 +1390,86 @@ gen12_emit_indirect_ctx_xcs(const struct intel_context *ce, u32 *cs) return gen12_emit_aux_table_inv(ce->engine, cs); } +static u32 *xehp_emit_fastcolor_blt_wabb(const struct intel_context *ce, u32 *cs) +{ + struct intel_gt *gt = ce->engine->gt; + int mocs = gt->mocs.uc_index << 1; + + /** + * Wa_16018031267 / Wa_16018063123 requires that SW forces the + * main copy engine arbitration into round robin mode. We + * additionally need to submit the following WABB blt command + * to produce 4 subblits with each subblit generating 0 byte + * write requests as WABB: + * + * XY_FASTCOLOR_BLT + * BG0 -> 5100000E + * BG1 -> 0000003F (Dest pitch) + * BG2 -> 00000000 (X1, Y1) = (0, 0) + * BG3 -> 00040001 (X2, Y2) = (1, 4) + * BG4 -> scratch + * BG5 -> scratch + * BG6-12 -> 00000000 + * BG13 -> 20004004 (Surf. Width= 2,Surf. Height = 5 ) + * BG14 -> 00000010 (Qpitch = 4) + * BG15 -> 00000000 + */ + *cs++ = XY_FAST_COLOR_BLT_CMD | (16 - 2); + *cs++ = FIELD_PREP(XY_FAST_COLOR_BLT_MOCS_MASK, mocs) | 0x3f; + *cs++ = 0; + *cs++ = 4 << 16 | 1; + *cs++ = lower_32_bits(ce->vm->rsvd.start); + *cs++ = upper_32_bits(ce->vm->rsvd.start); + *cs++ = 0; + /* Use 0x6b instead of 0 for color to maintain functionality */ + *cs++ = 0x6b; + *cs++ = 0; + *cs++ = 0; + *cs++ = 0; + *cs++ = 0; + *cs++ = 0; + *cs++ = 0x20004004; + *cs++ = 0x10; + *cs++ = 0; + + return cs; +} + +static u32 * +xehp_emit_per_ctx_bb(const struct intel_context *ce, u32 *cs) +{ + /* Wa_16018031267, Wa_16018063123 */ + if (NEEDS_FASTCOLOR_BLT_WABB(ce->engine)) + cs = xehp_emit_fastcolor_blt_wabb(ce, cs); + + return cs; +} + +static void +setup_per_ctx_bb(const struct intel_context *ce, + const struct intel_engine_cs *engine, + u32 *(*emit)(const struct intel_context *, u32 *)) +{ + /* Place PER_CTX_BB on next page after INDIRECT_CTX */ + u32 * const start = context_wabb(ce, true); + u32 *cs; + + cs = emit(ce, start); + + /* PER_CTX_BB must manually terminate */ + *cs++ = MI_BATCH_BUFFER_END; + + GEM_BUG_ON(cs - start > I915_GTT_PAGE_SIZE / sizeof(*cs)); + lrc_setup_bb_per_ctx(ce->lrc_reg_state, engine, + lrc_indirect_bb(ce) + PAGE_SIZE); +} + static void setup_indirect_ctx_bb(const struct intel_context *ce, const struct intel_engine_cs *engine, u32 *(*emit)(const struct intel_context *, u32 *)) { - u32 * const start = context_indirect_bb(ce); + u32 * const start = context_wabb(ce, false); u32 *cs; cs = emit(ce, start); @@ -1474,6 +1568,7 @@ u32 lrc_update_regs(const struct intel_context *ce, /* Mutually exclusive wrt to global indirect bb */ GEM_BUG_ON(engine->wa_ctx.indirect_ctx.size); setup_indirect_ctx_bb(ce, engine, fn); + setup_per_ctx_bb(ce, engine, xehp_emit_per_ctx_bb); } return lrc_descriptor(ce) | CTX_DESC_FORCE_RESTORE; diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c index 5f826b6dcf5d6..e17b8777d21dc 100644 --- a/drivers/gpu/drm/i915/gt/selftest_lrc.c +++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c @@ -1555,7 +1555,7 @@ static int live_lrc_isolation(void *arg) return err; } -static int indirect_ctx_submit_req(struct intel_context *ce) +static int wabb_ctx_submit_req(struct intel_context *ce) { struct i915_request *rq; int err = 0; @@ -1579,7 +1579,8 @@ static int indirect_ctx_submit_req(struct intel_context *ce) #define CTX_BB_CANARY_INDEX (CTX_BB_CANARY_OFFSET / sizeof(u32)) static u32 * -emit_indirect_ctx_bb_canary(const struct intel_context *ce, u32 *cs) +emit_wabb_ctx_canary(const struct intel_context *ce, + u32 *cs, bool per_ctx) { *cs++ = MI_STORE_REGISTER_MEM_GEN8 | MI_SRM_LRM_GLOBAL_GTT | @@ -1587,26 +1588,43 @@ emit_indirect_ctx_bb_canary(const struct intel_context *ce, u32 *cs) *cs++ = i915_mmio_reg_offset(RING_START(0)); *cs++ = i915_ggtt_offset(ce->state) + context_wa_bb_offset(ce) + - CTX_BB_CANARY_OFFSET; + CTX_BB_CANARY_OFFSET + + (per_ctx ? PAGE_SIZE : 0); *cs++ = 0; return cs; } +static u32 * +emit_indirect_ctx_bb_canary(const struct intel_context *ce, u32 *cs) +{ + return emit_wabb_ctx_canary(ce, cs, false); +} + +static u32 * +emit_per_ctx_bb_canary(const struct intel_context *ce, u32 *cs) +{ + return emit_wabb_ctx_canary(ce, cs, true); +} + static void -indirect_ctx_bb_setup(struct intel_context *ce) +wabb_ctx_setup(struct intel_context *ce, bool per_ctx) { - u32 *cs = context_indirect_bb(ce); + u32 *cs = context_wabb(ce, per_ctx); cs[CTX_BB_CANARY_INDEX] = 0xdeadf00d; - setup_indirect_ctx_bb(ce, ce->engine, emit_indirect_ctx_bb_canary); + if (per_ctx) + setup_per_ctx_bb(ce, ce->engine, emit_per_ctx_bb_canary); + else + setup_indirect_ctx_bb(ce, ce->engine, emit_indirect_ctx_bb_canary); } -static bool check_ring_start(struct intel_context *ce) +static bool check_ring_start(struct intel_context *ce, bool per_ctx) { const u32 * const ctx_bb = (void *)(ce->lrc_reg_state) - - LRC_STATE_OFFSET + context_wa_bb_offset(ce); + LRC_STATE_OFFSET + context_wa_bb_offset(ce) + + (per_ctx ? PAGE_SIZE : 0); if (ctx_bb[CTX_BB_CANARY_INDEX] == ce->lrc_reg_state[CTX_RING_START]) return true; @@ -1618,21 +1636,21 @@ static bool check_ring_start(struct intel_context *ce) return false; } -static int indirect_ctx_bb_check(struct intel_context *ce) +static int wabb_ctx_check(struct intel_context *ce, bool per_ctx) { int err; - err = indirect_ctx_submit_req(ce); + err = wabb_ctx_submit_req(ce); if (err) return err; - if (!check_ring_start(ce)) + if (!check_ring_start(ce, per_ctx)) return -EINVAL; return 0; } -static int __live_lrc_indirect_ctx_bb(struct intel_engine_cs *engine) +static int __lrc_wabb_ctx(struct intel_engine_cs *engine, bool per_ctx) { struct intel_context *a, *b; int err; @@ -1667,14 +1685,14 @@ static int __live_lrc_indirect_ctx_bb(struct intel_engine_cs *engine) * As ring start is restored apriori of starting the indirect ctx bb and * as it will be different for each context, it fits to this purpose. */ - indirect_ctx_bb_setup(a); - indirect_ctx_bb_setup(b); + wabb_ctx_setup(a, per_ctx); + wabb_ctx_setup(b, per_ctx); - err = indirect_ctx_bb_check(a); + err = wabb_ctx_check(a, per_ctx); if (err) goto unpin_b; - err = indirect_ctx_bb_check(b); + err = wabb_ctx_check(b, per_ctx); unpin_b: intel_context_unpin(b); @@ -1688,7 +1706,7 @@ static int __live_lrc_indirect_ctx_bb(struct intel_engine_cs *engine) return err; } -static int live_lrc_indirect_ctx_bb(void *arg) +static int lrc_wabb_ctx(void *arg, bool per_ctx) { struct intel_gt *gt = arg; struct intel_engine_cs *engine; @@ -1697,7 +1715,7 @@ static int live_lrc_indirect_ctx_bb(void *arg) for_each_engine(engine, gt, id) { intel_engine_pm_get(engine); - err = __live_lrc_indirect_ctx_bb(engine); + err = __lrc_wabb_ctx(engine, per_ctx); intel_engine_pm_put(engine); if (igt_flush_test(gt->i915)) @@ -1710,6 +1728,16 @@ static int live_lrc_indirect_ctx_bb(void *arg) return err; } +static int live_lrc_indirect_ctx_bb(void *arg) +{ + return lrc_wabb_ctx(arg, false); +} + +static int live_lrc_per_ctx_bb(void *arg) +{ + return lrc_wabb_ctx(arg, true); +} + static void garbage_reset(struct intel_engine_cs *engine, struct i915_request *rq) { @@ -1947,6 +1975,7 @@ int intel_lrc_live_selftests(struct drm_i915_private *i915) SUBTEST(live_lrc_garbage), SUBTEST(live_pphwsp_runtime), SUBTEST(live_lrc_indirect_ctx_bb), + SUBTEST(live_lrc_per_ctx_bb), }; if (!HAS_LOGICAL_RING_CONTEXTS(i915)) -- 2.25.1 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* [Intel-gfx] [PATCH v8 3/3] drm/i915: Set copy engine arbitration for Wa_16018031267 / Wa_16018063123 2023-09-08 0:29 [Intel-gfx] [PATCH v8 0/3] Apply Wa_16018031267 / Wa_16018063123 Jonathan Cavitt 2023-09-08 0:29 ` [Intel-gfx] [PATCH v8 1/3] drm/i915: Reserve some kernel space per vm Jonathan Cavitt 2023-09-08 0:29 ` [Intel-gfx] [PATCH v8 2/3] drm/i915: Add WABB blit for Wa_16018031267 / Wa_16018063123 Jonathan Cavitt @ 2023-09-08 0:29 ` Jonathan Cavitt 2023-09-08 2:37 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Apply " Patchwork ` (2 subsequent siblings) 5 siblings, 0 replies; 7+ messages in thread From: Jonathan Cavitt @ 2023-09-08 0:29 UTC (permalink / raw) To: intel-gfx Cc: andi.shyti, chris.p.wilson, tomasz.mistat, jonathan.cavitt, rodrigo.vivi, gregory.f.germano, matthew.d.roper, nirmoy.das Set copy engine arbitration into round robin mode for part of Wa_16018031267 / Wa_16018063123 mitigation. Signed-off-by: Nirmoy Das <nirmoy.das@intel.com> Signed-off-by: Jonathan Cavitt <jonathan.cavitt@intel.com> --- drivers/gpu/drm/i915/gt/intel_engine_regs.h | 3 +++ drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +++++ 2 files changed, 8 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_engine_regs.h b/drivers/gpu/drm/i915/gt/intel_engine_regs.h index 2e06bea73297a..823c6c40213f5 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_regs.h +++ b/drivers/gpu/drm/i915/gt/intel_engine_regs.h @@ -124,6 +124,9 @@ #define RING_INDIRECT_CTX(base) _MMIO((base) + 0x1c4) /* gen8+ */ #define RING_INDIRECT_CTX_OFFSET(base) _MMIO((base) + 0x1c8) /* gen8+ */ #define ECOSKPD(base) _MMIO((base) + 0x1d0) +#define XEHP_BLITTER_SCHEDULING_MODE_MASK REG_GENMASK(12, 11) +#define XEHP_BLITTER_ROUND_ROBIN_MODE \ + REG_FIELD_PREP(XEHP_BLITTER_SCHEDULING_MODE_MASK, 1) #define ECO_CONSTANT_BUFFER_SR_DISABLE REG_BIT(4) #define ECO_GATING_CX_ONLY REG_BIT(3) #define GEN6_BLITTER_FBC_NOTIFY REG_BIT(3) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 70071ead0659c..3f8177bf5de70 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -2777,6 +2777,11 @@ xcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) RING_SEMA_WAIT_POLL(engine->mmio_base), 1); } + /* Wa_16018031267, Wa_16018063123 */ + if (NEEDS_FASTCOLOR_BLT_WABB(engine)) + wa_masked_field_set(wal, ECOSKPD(engine->mmio_base), + XEHP_BLITTER_SCHEDULING_MODE_MASK, + XEHP_BLITTER_ROUND_ROBIN_MODE); } static void -- 2.25.1 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Apply Wa_16018031267 / Wa_16018063123 2023-09-08 0:29 [Intel-gfx] [PATCH v8 0/3] Apply Wa_16018031267 / Wa_16018063123 Jonathan Cavitt ` (2 preceding siblings ...) 2023-09-08 0:29 ` [Intel-gfx] [PATCH v8 3/3] drm/i915: Set copy engine arbitration " Jonathan Cavitt @ 2023-09-08 2:37 ` Patchwork 2023-09-08 2:37 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork 2023-09-08 2:57 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork 5 siblings, 0 replies; 7+ messages in thread From: Patchwork @ 2023-09-08 2:37 UTC (permalink / raw) To: Jonathan Cavitt; +Cc: intel-gfx == Series Details == Series: Apply Wa_16018031267 / Wa_16018063123 URL : https://patchwork.freedesktop.org/series/123407/ State : warning == Summary == Error: dim checkpatch failed 3eeb4a8cbf6a drm/i915: Reserve some kernel space per vm -:28: CHECK:LINE_SPACING: Please don't use multiple blank lines #28: FILE: drivers/gpu/drm/i915/gt/gen8_ppgtt.c:1015: + -:32: WARNING:AVOID_BUG: Do not crash the kernel unless it is absolutely unavoidable--use WARN_ON_ONCE() plus recovery code (if feasible) instead of BUG() or variants #32: FILE: drivers/gpu/drm/i915/gt/gen8_ppgtt.c:1019: + GEM_BUG_ON(drm_mm_reserve_node(&ppgtt->vm.mm, &ppgtt->vm.rsvd)); total: 0 errors, 1 warnings, 1 checks, 26 lines checked ffd37bba386c drm/i915: Add WABB blit for Wa_16018031267 / Wa_16018063123 -:10: WARNING:BAD_SIGN_OFF: Co-developed-by and Signed-off-by: name/email do not match #10: Co-developed-by: Nirmoy Das <nirmoy.das@intel.com> Signed-off-by: Jonathan Cavitt <jonathan.cavitt@intel.com> -:35: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'engine' - possible side-effects? #35: FILE: drivers/gpu/drm/i915/gt/intel_gt.h:86: +#define NEEDS_FASTCOLOR_BLT_WABB(engine) ( \ + IS_GFX_GT_IP_RANGE(engine->gt, IP_VER(12, 55), IP_VER(12, 71)) && \ + engine->class == COPY_ENGINE_CLASS) -:35: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'engine' may be better as '(engine)' to avoid precedence issues #35: FILE: drivers/gpu/drm/i915/gt/intel_gt.h:86: +#define NEEDS_FASTCOLOR_BLT_WABB(engine) ( \ + IS_GFX_GT_IP_RANGE(engine->gt, IP_VER(12, 55), IP_VER(12, 71)) && \ + engine->class == COPY_ENGINE_CLASS) -:68: WARNING:AVOID_BUG: Do not crash the kernel unless it is absolutely unavoidable--use WARN_ON_ONCE() plus recovery code (if feasible) instead of BUG() or variants #68: FILE: drivers/gpu/drm/i915/gt/intel_lrc.c:836: + GEM_BUG_ON(lrc_ring_wa_bb_per_ctx(engine) == -1); -:184: WARNING:AVOID_BUG: Do not crash the kernel unless it is absolutely unavoidable--use WARN_ON_ONCE() plus recovery code (if feasible) instead of BUG() or variants #184: FILE: drivers/gpu/drm/i915/gt/intel_lrc.c:1462: + GEM_BUG_ON(cs - start > I915_GTT_PAGE_SIZE / sizeof(*cs)); total: 0 errors, 3 warnings, 2 checks, 317 lines checked c7052a9d7020 drm/i915: Set copy engine arbitration for Wa_16018031267 / Wa_16018063123 ^ permalink raw reply [flat|nested] 7+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Apply Wa_16018031267 / Wa_16018063123 2023-09-08 0:29 [Intel-gfx] [PATCH v8 0/3] Apply Wa_16018031267 / Wa_16018063123 Jonathan Cavitt ` (3 preceding siblings ...) 2023-09-08 2:37 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Apply " Patchwork @ 2023-09-08 2:37 ` Patchwork 2023-09-08 2:57 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork 5 siblings, 0 replies; 7+ messages in thread From: Patchwork @ 2023-09-08 2:37 UTC (permalink / raw) To: Jonathan Cavitt; +Cc: intel-gfx == Series Details == Series: Apply Wa_16018031267 / Wa_16018063123 URL : https://patchwork.freedesktop.org/series/123407/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. ^ permalink raw reply [flat|nested] 7+ messages in thread
* [Intel-gfx] ✗ Fi.CI.BAT: failure for Apply Wa_16018031267 / Wa_16018063123 2023-09-08 0:29 [Intel-gfx] [PATCH v8 0/3] Apply Wa_16018031267 / Wa_16018063123 Jonathan Cavitt ` (4 preceding siblings ...) 2023-09-08 2:37 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork @ 2023-09-08 2:57 ` Patchwork 5 siblings, 0 replies; 7+ messages in thread From: Patchwork @ 2023-09-08 2:57 UTC (permalink / raw) To: Jonathan Cavitt; +Cc: intel-gfx [-- Attachment #1: Type: text/plain, Size: 18012 bytes --] == Series Details == Series: Apply Wa_16018031267 / Wa_16018063123 URL : https://patchwork.freedesktop.org/series/123407/ State : failure == Summary == CI Bug Log - changes from CI_DRM_13612 -> Patchwork_123407v1 ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_123407v1 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_123407v1, please notify your bug team (lgci.bug.filing@intel.com) to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123407v1/index.html Participating hosts (38 -> 38) ------------------------------ Additional (3): fi-kbl-soraka bat-dg2-9 fi-apl-guc Missing (3): fi-skl-guc bat-dg2-8 fi-snb-2520m Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_123407v1: ### IGT changes ### #### Possible regressions #### * igt@i915_selftest@live@gtt: - fi-cfl-guc: [PASS][1] -> [DMESG-FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13612/fi-cfl-guc/igt@i915_selftest@live@gtt.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123407v1/fi-cfl-guc/igt@i915_selftest@live@gtt.html - bat-jsl-3: [PASS][3] -> [DMESG-FAIL][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13612/bat-jsl-3/igt@i915_selftest@live@gtt.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123407v1/bat-jsl-3/igt@i915_selftest@live@gtt.html - fi-kbl-x1275: [PASS][5] -> [DMESG-FAIL][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13612/fi-kbl-x1275/igt@i915_selftest@live@gtt.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123407v1/fi-kbl-x1275/igt@i915_selftest@live@gtt.html - fi-cfl-8109u: [PASS][7] -> [DMESG-FAIL][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13612/fi-cfl-8109u/igt@i915_selftest@live@gtt.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123407v1/fi-cfl-8109u/igt@i915_selftest@live@gtt.html - fi-kbl-8809g: [PASS][9] -> [DMESG-FAIL][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13612/fi-kbl-8809g/igt@i915_selftest@live@gtt.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123407v1/fi-kbl-8809g/igt@i915_selftest@live@gtt.html - bat-mtlp-8: [PASS][11] -> [DMESG-FAIL][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13612/bat-mtlp-8/igt@i915_selftest@live@gtt.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123407v1/bat-mtlp-8/igt@i915_selftest@live@gtt.html - fi-kbl-guc: [PASS][13] -> [DMESG-FAIL][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13612/fi-kbl-guc/igt@i915_selftest@live@gtt.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123407v1/fi-kbl-guc/igt@i915_selftest@live@gtt.html - bat-jsl-1: [PASS][15] -> [DMESG-FAIL][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13612/bat-jsl-1/igt@i915_selftest@live@gtt.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123407v1/bat-jsl-1/igt@i915_selftest@live@gtt.html - fi-tgl-1115g4: [PASS][17] -> [DMESG-FAIL][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13612/fi-tgl-1115g4/igt@i915_selftest@live@gtt.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123407v1/fi-tgl-1115g4/igt@i915_selftest@live@gtt.html - bat-rpls-1: [PASS][19] -> [DMESG-FAIL][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13612/bat-rpls-1/igt@i915_selftest@live@gtt.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123407v1/bat-rpls-1/igt@i915_selftest@live@gtt.html - bat-mtlp-6: [PASS][21] -> [DMESG-FAIL][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13612/bat-mtlp-6/igt@i915_selftest@live@gtt.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123407v1/bat-mtlp-6/igt@i915_selftest@live@gtt.html - fi-skl-6600u: [PASS][23] -> [DMESG-FAIL][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13612/fi-skl-6600u/igt@i915_selftest@live@gtt.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123407v1/fi-skl-6600u/igt@i915_selftest@live@gtt.html - fi-apl-guc: NOTRUN -> [DMESG-FAIL][25] [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123407v1/fi-apl-guc/igt@i915_selftest@live@gtt.html - bat-dg1-5: [PASS][26] -> [DMESG-FAIL][27] [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13612/bat-dg1-5/igt@i915_selftest@live@gtt.html [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123407v1/bat-dg1-5/igt@i915_selftest@live@gtt.html - fi-glk-j4005: [PASS][28] -> [DMESG-FAIL][29] [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13612/fi-glk-j4005/igt@i915_selftest@live@gtt.html [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123407v1/fi-glk-j4005/igt@i915_selftest@live@gtt.html - fi-cfl-8700k: [PASS][30] -> [DMESG-FAIL][31] [30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13612/fi-cfl-8700k/igt@i915_selftest@live@gtt.html [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123407v1/fi-cfl-8700k/igt@i915_selftest@live@gtt.html - bat-kbl-2: [PASS][32] -> [DMESG-FAIL][33] [32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13612/bat-kbl-2/igt@i915_selftest@live@gtt.html [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123407v1/bat-kbl-2/igt@i915_selftest@live@gtt.html - fi-rkl-11600: [PASS][34] -> [DMESG-FAIL][35] [34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13612/fi-rkl-11600/igt@i915_selftest@live@gtt.html [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123407v1/fi-rkl-11600/igt@i915_selftest@live@gtt.html Known issues ------------ Here are the changes found in Patchwork_123407v1 that come from known issues: ### CI changes ### #### Issues hit #### * boot: - fi-hsw-4770: [PASS][36] -> [FAIL][37] ([i915#8293]) [36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13612/fi-hsw-4770/boot.html [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123407v1/fi-hsw-4770/boot.html ### IGT changes ### #### Issues hit #### * igt@gem_huc_copy@huc-copy: - fi-kbl-soraka: NOTRUN -> [SKIP][38] ([fdo#109271] / [i915#2190]) [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123407v1/fi-kbl-soraka/igt@gem_huc_copy@huc-copy.html * igt@gem_lmem_swapping@basic: - fi-apl-guc: NOTRUN -> [SKIP][39] ([fdo#109271] / [i915#4613]) +3 other tests skip [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123407v1/fi-apl-guc/igt@gem_lmem_swapping@basic.html - fi-kbl-soraka: NOTRUN -> [SKIP][40] ([fdo#109271] / [i915#4613]) +3 other tests skip [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123407v1/fi-kbl-soraka/igt@gem_lmem_swapping@basic.html * igt@gem_mmap@basic: - bat-dg2-9: NOTRUN -> [SKIP][41] ([i915#4083]) [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123407v1/bat-dg2-9/igt@gem_mmap@basic.html * igt@gem_mmap_gtt@basic: - bat-dg2-9: NOTRUN -> [SKIP][42] ([i915#4077]) +2 other tests skip [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123407v1/bat-dg2-9/igt@gem_mmap_gtt@basic.html * igt@gem_render_tiled_blits@basic: - bat-dg2-9: NOTRUN -> [SKIP][43] ([i915#4079]) +1 other test skip [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123407v1/bat-dg2-9/igt@gem_render_tiled_blits@basic.html * igt@i915_pm_backlight@basic-brightness: - bat-dg2-9: NOTRUN -> [SKIP][44] ([i915#5354] / [i915#7561]) [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123407v1/bat-dg2-9/igt@i915_pm_backlight@basic-brightness.html * igt@i915_pm_rps@basic-api: - bat-dg2-9: NOTRUN -> [SKIP][45] ([i915#6621]) [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123407v1/bat-dg2-9/igt@i915_pm_rps@basic-api.html * igt@i915_selftest@live@gt_heartbeat: - fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][46] ([i915#5334] / [i915#7872]) [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123407v1/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html - fi-glk-j4005: [PASS][47] -> [DMESG-FAIL][48] ([i915#5334]) [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13612/fi-glk-j4005/igt@i915_selftest@live@gt_heartbeat.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123407v1/fi-glk-j4005/igt@i915_selftest@live@gt_heartbeat.html * igt@i915_selftest@live@gt_pm: - fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][49] ([i915#1886] / [i915#7913]) [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123407v1/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html * igt@i915_selftest@live@gtt: - bat-atsm-1: [PASS][50] -> [DMESG-FAIL][51] ([i915#7913]) [50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13612/bat-atsm-1/igt@i915_selftest@live@gtt.html [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123407v1/bat-atsm-1/igt@i915_selftest@live@gtt.html - bat-dg2-9: NOTRUN -> [DMESG-FAIL][52] ([i915#7913]) [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123407v1/bat-dg2-9/igt@i915_selftest@live@gtt.html - fi-bsw-n3050: [PASS][53] -> [DMESG-FAIL][54] ([i915#7913]) [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13612/fi-bsw-n3050/igt@i915_selftest@live@gtt.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123407v1/fi-bsw-n3050/igt@i915_selftest@live@gtt.html - bat-adlp-9: [PASS][55] -> [DMESG-FAIL][56] ([i915#7913]) [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13612/bat-adlp-9/igt@i915_selftest@live@gtt.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123407v1/bat-adlp-9/igt@i915_selftest@live@gtt.html - bat-dg2-11: [PASS][57] -> [DMESG-FAIL][58] ([i915#7913]) [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13612/bat-dg2-11/igt@i915_selftest@live@gtt.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123407v1/bat-dg2-11/igt@i915_selftest@live@gtt.html - fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][59] ([i915#7913]) [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123407v1/fi-kbl-soraka/igt@i915_selftest@live@gtt.html - fi-bsw-nick: [PASS][60] -> [DMESG-FAIL][61] ([i915#7913]) [60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13612/fi-bsw-nick/igt@i915_selftest@live@gtt.html [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123407v1/fi-bsw-nick/igt@i915_selftest@live@gtt.html - bat-adls-5: [PASS][62] -> [DMESG-FAIL][63] ([i915#7913]) [62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13612/bat-adls-5/igt@i915_selftest@live@gtt.html [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123407v1/bat-adls-5/igt@i915_selftest@live@gtt.html * igt@i915_selftest@live@hugepages: - bat-mtlp-8: [PASS][64] -> [DMESG-WARN][65] ([i915#9121]) [64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13612/bat-mtlp-8/igt@i915_selftest@live@hugepages.html [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123407v1/bat-mtlp-8/igt@i915_selftest@live@hugepages.html * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy: - bat-dg2-9: NOTRUN -> [SKIP][66] ([i915#5190]) [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123407v1/bat-dg2-9/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html * igt@kms_addfb_basic@basic-y-tiled-legacy: - bat-dg2-9: NOTRUN -> [SKIP][67] ([i915#4215] / [i915#5190]) [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123407v1/bat-dg2-9/igt@kms_addfb_basic@basic-y-tiled-legacy.html * igt@kms_addfb_basic@framebuffer-vs-set-tiling: - bat-dg2-9: NOTRUN -> [SKIP][68] ([i915#4212]) +7 other tests skip [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123407v1/bat-dg2-9/igt@kms_addfb_basic@framebuffer-vs-set-tiling.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-kbl-soraka: NOTRUN -> [SKIP][69] ([fdo#109271]) +8 other tests skip [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123407v1/fi-kbl-soraka/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: - bat-dg2-9: NOTRUN -> [SKIP][70] ([i915#4103] / [i915#4213]) +1 other test skip [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123407v1/bat-dg2-9/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html * igt@kms_force_connector_basic@force-load-detect: - bat-dg2-9: NOTRUN -> [SKIP][71] ([fdo#109285]) [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123407v1/bat-dg2-9/igt@kms_force_connector_basic@force-load-detect.html * igt@kms_force_connector_basic@prune-stale-modes: - bat-dg2-9: NOTRUN -> [SKIP][72] ([i915#5274]) [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123407v1/bat-dg2-9/igt@kms_force_connector_basic@prune-stale-modes.html * igt@kms_frontbuffer_tracking@basic: - fi-bsw-nick: [PASS][73] -> [FAIL][74] ([i915#9276]) [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13612/fi-bsw-nick/igt@kms_frontbuffer_tracking@basic.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123407v1/fi-bsw-nick/igt@kms_frontbuffer_tracking@basic.html * igt@kms_hdmi_inject@inject-audio: - fi-apl-guc: NOTRUN -> [SKIP][75] ([fdo#109271]) +16 other tests skip [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123407v1/fi-apl-guc/igt@kms_hdmi_inject@inject-audio.html * igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence: - bat-dg2-11: NOTRUN -> [SKIP][76] ([i915#1845]) +3 other tests skip [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123407v1/bat-dg2-11/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence.html * igt@kms_psr@sprite_plane_onoff: - bat-dg2-9: NOTRUN -> [SKIP][77] ([i915#1072]) +3 other tests skip [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123407v1/bat-dg2-9/igt@kms_psr@sprite_plane_onoff.html * igt@kms_setmode@basic-clone-single-crtc: - bat-dg2-9: NOTRUN -> [SKIP][78] ([i915#3555]) [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123407v1/bat-dg2-9/igt@kms_setmode@basic-clone-single-crtc.html * igt@prime_vgem@basic-fence-flip: - bat-dg2-9: NOTRUN -> [SKIP][79] ([i915#3708]) [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123407v1/bat-dg2-9/igt@prime_vgem@basic-fence-flip.html * igt@prime_vgem@basic-fence-mmap: - bat-dg2-9: NOTRUN -> [SKIP][80] ([i915#3708] / [i915#4077]) +1 other test skip [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123407v1/bat-dg2-9/igt@prime_vgem@basic-fence-mmap.html * igt@prime_vgem@basic-write: - bat-dg2-9: NOTRUN -> [SKIP][81] ([i915#3291] / [i915#3708]) +2 other tests skip [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123407v1/bat-dg2-9/igt@prime_vgem@basic-write.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285 [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072 [i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845 [i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886 [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190 [i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291 [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555 [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708 [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077 [i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079 [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083 [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103 [i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212 [i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213 [i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215 [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613 [i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190 [i915#5274]: https://gitlab.freedesktop.org/drm/intel/issues/5274 [i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334 [i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354 [i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621 [i915#7561]: https://gitlab.freedesktop.org/drm/intel/issues/7561 [i915#7872]: https://gitlab.freedesktop.org/drm/intel/issues/7872 [i915#7913]: https://gitlab.freedesktop.org/drm/intel/issues/7913 [i915#8293]: https://gitlab.freedesktop.org/drm/intel/issues/8293 [i915#9121]: https://gitlab.freedesktop.org/drm/intel/issues/9121 [i915#9276]: https://gitlab.freedesktop.org/drm/intel/issues/9276 Build changes ------------- * Linux: CI_DRM_13612 -> Patchwork_123407v1 CI-20190529: 20190529 CI_DRM_13612: 96fa6997c7d6fc80d5137c02f3e4e6fc69534d9f @ git://anongit.freedesktop.org/gfx-ci/linux IGT_7474: 9d91cf2c6e7bb64d60c2030d1535e40ca0ad53ee @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_123407v1: 96fa6997c7d6fc80d5137c02f3e4e6fc69534d9f @ git://anongit.freedesktop.org/gfx-ci/linux ### Linux commits 669f654aa709 drm/i915: Set copy engine arbitration for Wa_16018031267 / Wa_16018063123 669cc576f7df drm/i915: Add WABB blit for Wa_16018031267 / Wa_16018063123 7ba4987a3626 drm/i915: Reserve some kernel space per vm == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123407v1/index.html [-- Attachment #2: Type: text/html, Size: 20902 bytes --] ^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2023-09-08 2:57 UTC | newest] Thread overview: 7+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2023-09-08 0:29 [Intel-gfx] [PATCH v8 0/3] Apply Wa_16018031267 / Wa_16018063123 Jonathan Cavitt 2023-09-08 0:29 ` [Intel-gfx] [PATCH v8 1/3] drm/i915: Reserve some kernel space per vm Jonathan Cavitt 2023-09-08 0:29 ` [Intel-gfx] [PATCH v8 2/3] drm/i915: Add WABB blit for Wa_16018031267 / Wa_16018063123 Jonathan Cavitt 2023-09-08 0:29 ` [Intel-gfx] [PATCH v8 3/3] drm/i915: Set copy engine arbitration " Jonathan Cavitt 2023-09-08 2:37 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Apply " Patchwork 2023-09-08 2:37 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork 2023-09-08 2:57 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
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