From: Alexander Usyskin <alexander.usyskin@intel.com>
To: Miquel Raynal <miquel.raynal@bootlin.com>,
Richard Weinberger <richard@nod.at>,
Vignesh Raghavendra <vigneshr@ti.com>,
Jani Nikula <jani.nikula@linux.intel.com>,
Joonas Lahtinen <joonas.lahtinen@linux.intel.com>,
Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Alexander Usyskin <alexander.usyskin@intel.com>,
intel-gfx@lists.freedesktop.org,
Lucas De Marchi <lucas.demarchi@intel.com>,
linux-mtd@lists.infradead.org,
Tomas Winkler <tomas.winkler@intel.com>,
Vitaly Lubart <vitaly.lubart@intel.com>
Subject: [Intel-gfx] [PATCH 07/10] drm/i915/spi: mtd: implement access handlers
Date: Sun, 10 Sep 2023 15:39:46 +0300 [thread overview]
Message-ID: <20230910123949.1251964-8-alexander.usyskin@intel.com> (raw)
In-Reply-To: <20230910123949.1251964-1-alexander.usyskin@intel.com>
From: Tomas Winkler <tomas.winkler@intel.com>
Implement mtd read, erase, and write handlers.
For erase operation address and size should be 4K aligned.
For write operation address and size has to be 4bytes aligned.
CC: Rodrigo Vivi <rodrigo.vivi@intel.com>
CC: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
Signed-off-by: Vitaly Lubart <vitaly.lubart@intel.com>
Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
---
drivers/gpu/drm/i915/spi/intel_spi_drv.c | 152 +++++++++++++++++++++--
1 file changed, 144 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/spi/intel_spi_drv.c b/drivers/gpu/drm/i915/spi/intel_spi_drv.c
index 355f9ad71602..39369a0c64a0 100644
--- a/drivers/gpu/drm/i915/spi/intel_spi_drv.c
+++ b/drivers/gpu/drm/i915/spi/intel_spi_drv.c
@@ -175,7 +175,6 @@ static int i915_spi_is_valid(struct i915_spi *spi)
return 0;
}
-__maybe_unused
static unsigned int spi_get_region(const struct i915_spi *spi, loff_t from)
{
unsigned int i;
@@ -207,7 +206,6 @@ static ssize_t spi_rewrite_partial(struct i915_spi *spi, loff_t to,
return len;
}
-__maybe_unused
static ssize_t spi_write(struct i915_spi *spi, u8 region,
loff_t to, size_t len, const unsigned char *buf)
{
@@ -266,7 +264,6 @@ static ssize_t spi_write(struct i915_spi *spi, u8 region,
return len;
}
-__maybe_unused
static ssize_t spi_read(struct i915_spi *spi, u8 region,
loff_t from, size_t len, unsigned char *buf)
{
@@ -325,7 +322,6 @@ static ssize_t spi_read(struct i915_spi *spi, u8 region,
return len;
}
-__maybe_unused
static ssize_t
spi_erase(struct i915_spi *spi, u8 region, loff_t from, u64 len, u64 *fail_addr)
{
@@ -414,24 +410,164 @@ static int i915_spi_init(struct i915_spi *spi, struct device *device)
static int i915_spi_erase(struct mtd_info *mtd, struct erase_info *info)
{
- dev_err(&mtd->dev, "erasing %lld %lld\n", info->addr, info->len);
+ struct i915_spi *spi;
+ unsigned int idx;
+ u8 region;
+ u64 addr;
+ ssize_t bytes;
+ loff_t from;
+ size_t len;
+ size_t total_len;
+ int ret = 0;
+
+ if (!mtd || !info)
+ return -EINVAL;
- return 0;
+ spi = mtd->priv;
+ if (WARN_ON(!spi))
+ return -EINVAL;
+
+ if (!IS_ALIGNED(info->addr, SZ_4K) || !IS_ALIGNED(info->len, SZ_4K)) {
+ dev_err(&mtd->dev, "unaligned erase %llx %llx\n",
+ info->addr, info->len);
+ info->fail_addr = MTD_FAIL_ADDR_UNKNOWN;
+ return -EINVAL;
+ }
+
+ total_len = info->len;
+ addr = info->addr;
+
+ mutex_lock(&spi->lock);
+
+ while (total_len > 0) {
+ if (!IS_ALIGNED(addr, SZ_4K) || !IS_ALIGNED(total_len, SZ_4K)) {
+ dev_err(&mtd->dev, "unaligned erase %llx %zx\n", addr, total_len);
+ info->fail_addr = addr;
+ ret = -ERANGE;
+ goto out;
+ }
+
+ idx = spi_get_region(spi, addr);
+ if (idx >= spi->nregions) {
+ dev_err(&mtd->dev, "out of range");
+ info->fail_addr = MTD_FAIL_ADDR_UNKNOWN;
+ ret = -ERANGE;
+ goto out;
+ }
+
+ from = addr - spi->regions[idx].offset;
+ region = spi->regions[idx].id;
+ len = total_len;
+ if (len > spi->regions[idx].size - from)
+ len = spi->regions[idx].size - from;
+
+ dev_dbg(&mtd->dev, "erasing region[%d] %s from %llx len %zx\n",
+ region, spi->regions[idx].name, from, len);
+
+ bytes = spi_erase(spi, region, from, len, &info->fail_addr);
+ if (bytes < 0) {
+ dev_dbg(&mtd->dev, "erase failed with %zd\n", bytes);
+ info->fail_addr += spi->regions[idx].offset;
+ ret = bytes;
+ goto out;
+ }
+
+ addr += len;
+ total_len -= len;
+ }
+
+out:
+ mutex_unlock(&spi->lock);
+ return ret;
}
static int i915_spi_read(struct mtd_info *mtd, loff_t from, size_t len,
size_t *retlen, u_char *buf)
{
- dev_err(&mtd->dev, "read %lld %zd\n", from, len);
+ struct i915_spi *spi;
+ ssize_t ret;
+ unsigned int idx;
+ u8 region;
+
+ if (!mtd)
+ return -EINVAL;
+
+ spi = mtd->priv;
+ if (WARN_ON(!spi))
+ return -EINVAL;
+
+ idx = spi_get_region(spi, from);
+ dev_dbg(&mtd->dev, "reading region[%d] %s from %lld len %zd\n",
+ spi->regions[idx].id, spi->regions[idx].name, from, len);
+
+ if (idx >= spi->nregions) {
+ dev_err(&mtd->dev, "out of ragnge");
+ return -ERANGE;
+ }
+
+ from -= spi->regions[idx].offset;
+ region = spi->regions[idx].id;
+ if (len > spi->regions[idx].size - from)
+ len = spi->regions[idx].size - from;
+
+ mutex_lock(&spi->lock);
+
+ ret = spi_read(spi, region, from, len, buf);
+ if (ret < 0) {
+ dev_dbg(&mtd->dev, "read failed with %zd\n", ret);
+ mutex_unlock(&spi->lock);
+ return ret;
+ }
+
+ *retlen = ret;
+
+ mutex_unlock(&spi->lock);
return 0;
}
static int i915_spi_write(struct mtd_info *mtd, loff_t to, size_t len,
size_t *retlen, const u_char *buf)
{
- dev_err(&mtd->dev, "writing %lld %zd\n", to, len);
+ struct i915_spi *spi;
+ ssize_t ret;
+ unsigned int idx;
+ u8 region;
+
+ if (!mtd)
+ return -EINVAL;
+
+ spi = mtd->priv;
+ if (WARN_ON(!spi))
+ return -EINVAL;
+
+ idx = spi_get_region(spi, to);
+
+ dev_dbg(&mtd->dev, "writing region[%d] %s to %lld len %zd\n",
+ spi->regions[idx].id, spi->regions[idx].name, to, len);
+
+ if (idx >= spi->nregions) {
+ dev_err(&mtd->dev, "out of range");
+ return -ERANGE;
+ }
+
+ to -= spi->regions[idx].offset;
+ region = spi->regions[idx].id;
+ if (len > spi->regions[idx].size - to)
+ len = spi->regions[idx].size - to;
+
+ mutex_lock(&spi->lock);
+
+ ret = spi_write(spi, region, to, len, buf);
+ if (ret < 0) {
+ dev_dbg(&mtd->dev, "write failed with %zd\n", ret);
+ mutex_unlock(&spi->lock);
+ return ret;
+ }
+
+ *retlen = ret;
+ mutex_unlock(&spi->lock);
return 0;
}
--
2.34.1
next prev parent reply other threads:[~2023-09-10 12:44 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-10 12:39 [Intel-gfx] [PATCH 00/10] drm/i915/spi: spi access for discrete graphics Alexander Usyskin
2023-09-10 12:39 ` [Intel-gfx] [PATCH 01/10] drm/i915/spi: add spi device " Alexander Usyskin
2023-09-11 15:41 ` Jani Nikula
2023-09-12 10:47 ` Usyskin, Alexander
2023-09-10 12:39 ` [Intel-gfx] [PATCH 02/10] drm/i915/spi: add intel_spi_region map Alexander Usyskin
2023-09-10 12:39 ` [Intel-gfx] [PATCH 03/10] drm/i915/spi: add driver for on-die spi device Alexander Usyskin
2023-09-10 12:39 ` [Intel-gfx] [PATCH 04/10] drm/i915/spi: implement region enumeration Alexander Usyskin
2023-09-10 12:39 ` [Intel-gfx] [PATCH 05/10] drm/i915/spi: implement spi access functions Alexander Usyskin
2023-09-10 12:39 ` [Intel-gfx] [PATCH 06/10] drm/i915/spi: spi register with mtd Alexander Usyskin
2023-10-16 8:39 ` Miquel Raynal
2023-10-17 11:54 ` Usyskin, Alexander
2023-10-17 13:55 ` Miquel Raynal
2023-10-17 14:20 ` Usyskin, Alexander
2023-10-17 14:46 ` Miquel Raynal
2023-11-14 8:47 ` Usyskin, Alexander
2023-11-14 9:13 ` Miquel Raynal
2024-02-14 12:16 ` Usyskin, Alexander
2024-02-19 9:09 ` Miquel Raynal
2023-09-10 12:39 ` Alexander Usyskin [this message]
2023-09-10 12:39 ` [Intel-gfx] [PATCH 08/10] drm/i915/spi: align 64bit read and write Alexander Usyskin
2023-09-10 12:39 ` [Intel-gfx] [PATCH 09/10] drm/i915/spi: wake card on operations Alexander Usyskin
2023-09-10 12:39 ` [Intel-gfx] [PATCH 10/10] drm/i915/spi: add support for access mode Alexander Usyskin
2023-09-10 13:11 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/spi: spi access for discrete graphics Patchwork
2023-09-10 13:11 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-09-11 7:42 ` [Intel-gfx] [PATCH 00/10] " Miquel Raynal
2023-09-12 10:50 ` Usyskin, Alexander
2023-09-12 12:14 ` Mark Brown
2023-09-12 13:15 ` Usyskin, Alexander
2023-09-12 13:21 ` Miquel Raynal
2023-09-12 13:36 ` Mark Brown
2023-09-20 13:52 ` Usyskin, Alexander
2023-09-20 15:54 ` Mark Brown
2023-09-20 21:00 ` Winkler, Tomas
2023-09-21 11:29 ` Mark Brown
2023-09-27 14:11 ` Usyskin, Alexander
2023-09-27 14:37 ` Mark Brown
2023-09-27 14:54 ` Miquel Raynal
2023-09-28 6:33 ` Usyskin, Alexander
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