From: kernel test robot <lkp@intel.com>
To: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>,
dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org
Cc: suijingfeng@loongson.cn, jani.nikula@intel.com,
mripard@kernel.org, oe-kbuild-all@lists.linux.dev
Subject: Re: [Intel-gfx] [PATCH 2/8] drm/i915/display: Store compressed bpp in U6.4 format
Date: Sat, 30 Sep 2023 13:41:40 +0800 [thread overview]
Message-ID: <202309301303.ujZmUWZH-lkp@intel.com> (raw)
In-Reply-To: <20230929071322.945521-3-mitulkumar.ajitkumar.golani@intel.com>
Hi Mitul,
kernel test robot noticed the following build errors:
[auto build test ERROR on drm-tip/drm-tip]
url: https://github.com/intel-lab-lkp/linux/commits/Mitul-Golani/drm-display-dp-Add-helper-function-to-get-DSC-bpp-precision/20230929-162949
base: git://anongit.freedesktop.org/drm/drm-tip drm-tip
patch link: https://lore.kernel.org/r/20230929071322.945521-3-mitulkumar.ajitkumar.golani%40intel.com
patch subject: [PATCH 2/8] drm/i915/display: Store compressed bpp in U6.4 format
config: x86_64-rhel-8.3-kselftests (https://download.01.org/0day-ci/archive/20230930/202309301303.ujZmUWZH-lkp@intel.com/config)
compiler: gcc-12 (Debian 12.2.0-14) 12.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20230930/202309301303.ujZmUWZH-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202309301303.ujZmUWZH-lkp@intel.com/
All errors (new ones prefixed by >>):
drivers/gpu/drm/i915/display/intel_link_bw.c: In function 'intel_link_bw_reduce_bpp':
>> drivers/gpu/drm/i915/display/intel_link_bw.c:71:52: error: 'struct <anonymous>' has no member named 'compressed_bpp'; did you mean 'compressed_bpp_x16'?
71 | link_bpp = crtc_state->dsc.compressed_bpp;
| ^~~~~~~~~~~~~~
| compressed_bpp_x16
vim +71 drivers/gpu/drm/i915/display/intel_link_bw.c
8ca0b875c08258 Imre Deak 2023-09-21 28
8ca0b875c08258 Imre Deak 2023-09-21 29 /**
8ca0b875c08258 Imre Deak 2023-09-21 30 * intel_link_bw_reduce_bpp - reduce maximum link bpp for a selected pipe
8ca0b875c08258 Imre Deak 2023-09-21 31 * @state: atomic state
8ca0b875c08258 Imre Deak 2023-09-21 32 * @limits: link BW limits
8ca0b875c08258 Imre Deak 2023-09-21 33 * @pipe_mask: mask of pipes to select from
8ca0b875c08258 Imre Deak 2023-09-21 34 * @reason: explanation of why bpp reduction is needed
8ca0b875c08258 Imre Deak 2023-09-21 35 *
8ca0b875c08258 Imre Deak 2023-09-21 36 * Select the pipe from @pipe_mask with the biggest link bpp value and set the
8ca0b875c08258 Imre Deak 2023-09-21 37 * maximum of link bpp in @limits below this value. Modeset the selected pipe,
8ca0b875c08258 Imre Deak 2023-09-21 38 * so that its state will get recomputed.
8ca0b875c08258 Imre Deak 2023-09-21 39 *
8ca0b875c08258 Imre Deak 2023-09-21 40 * This function can be called to resolve a link's BW overallocation by reducing
8ca0b875c08258 Imre Deak 2023-09-21 41 * the link bpp of one pipe on the link and hence reducing the total link BW.
8ca0b875c08258 Imre Deak 2023-09-21 42 *
8ca0b875c08258 Imre Deak 2023-09-21 43 * Returns
8ca0b875c08258 Imre Deak 2023-09-21 44 * - 0 in case of success
8ca0b875c08258 Imre Deak 2023-09-21 45 * - %-ENOSPC if no pipe can further reduce its link bpp
8ca0b875c08258 Imre Deak 2023-09-21 46 * - Other negative error, if modesetting the selected pipe failed
8ca0b875c08258 Imre Deak 2023-09-21 47 */
8ca0b875c08258 Imre Deak 2023-09-21 48 int intel_link_bw_reduce_bpp(struct intel_atomic_state *state,
8ca0b875c08258 Imre Deak 2023-09-21 49 struct intel_link_bw_limits *limits,
8ca0b875c08258 Imre Deak 2023-09-21 50 u8 pipe_mask,
8ca0b875c08258 Imre Deak 2023-09-21 51 const char *reason)
8ca0b875c08258 Imre Deak 2023-09-21 52 {
8ca0b875c08258 Imre Deak 2023-09-21 53 struct drm_i915_private *i915 = to_i915(state->base.dev);
8ca0b875c08258 Imre Deak 2023-09-21 54 enum pipe max_bpp_pipe = INVALID_PIPE;
8ca0b875c08258 Imre Deak 2023-09-21 55 struct intel_crtc *crtc;
8ca0b875c08258 Imre Deak 2023-09-21 56 int max_bpp = 0;
8ca0b875c08258 Imre Deak 2023-09-21 57
8ca0b875c08258 Imre Deak 2023-09-21 58 for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, pipe_mask) {
8ca0b875c08258 Imre Deak 2023-09-21 59 struct intel_crtc_state *crtc_state;
8ca0b875c08258 Imre Deak 2023-09-21 60 int link_bpp;
8ca0b875c08258 Imre Deak 2023-09-21 61
8ca0b875c08258 Imre Deak 2023-09-21 62 if (limits->bpp_limit_reached_pipes & BIT(crtc->pipe))
8ca0b875c08258 Imre Deak 2023-09-21 63 continue;
8ca0b875c08258 Imre Deak 2023-09-21 64
8ca0b875c08258 Imre Deak 2023-09-21 65 crtc_state = intel_atomic_get_crtc_state(&state->base,
8ca0b875c08258 Imre Deak 2023-09-21 66 crtc);
8ca0b875c08258 Imre Deak 2023-09-21 67 if (IS_ERR(crtc_state))
8ca0b875c08258 Imre Deak 2023-09-21 68 return PTR_ERR(crtc_state);
8ca0b875c08258 Imre Deak 2023-09-21 69
8ca0b875c08258 Imre Deak 2023-09-21 70 if (crtc_state->dsc.compression_enable)
8ca0b875c08258 Imre Deak 2023-09-21 @71 link_bpp = crtc_state->dsc.compressed_bpp;
8ca0b875c08258 Imre Deak 2023-09-21 72 else
8ca0b875c08258 Imre Deak 2023-09-21 73 /*
8ca0b875c08258 Imre Deak 2023-09-21 74 * TODO: for YUV420 the actual link bpp is only half
8ca0b875c08258 Imre Deak 2023-09-21 75 * of the pipe bpp value. The MST encoder's BW allocation
8ca0b875c08258 Imre Deak 2023-09-21 76 * is based on the pipe bpp value, set the actual link bpp
8ca0b875c08258 Imre Deak 2023-09-21 77 * limit here once the MST BW allocation is fixed.
8ca0b875c08258 Imre Deak 2023-09-21 78 */
8ca0b875c08258 Imre Deak 2023-09-21 79 link_bpp = crtc_state->pipe_bpp;
8ca0b875c08258 Imre Deak 2023-09-21 80
8ca0b875c08258 Imre Deak 2023-09-21 81 if (link_bpp > max_bpp) {
8ca0b875c08258 Imre Deak 2023-09-21 82 max_bpp = link_bpp;
8ca0b875c08258 Imre Deak 2023-09-21 83 max_bpp_pipe = crtc->pipe;
8ca0b875c08258 Imre Deak 2023-09-21 84 }
8ca0b875c08258 Imre Deak 2023-09-21 85 }
8ca0b875c08258 Imre Deak 2023-09-21 86
8ca0b875c08258 Imre Deak 2023-09-21 87 if (max_bpp_pipe == INVALID_PIPE)
8ca0b875c08258 Imre Deak 2023-09-21 88 return -ENOSPC;
8ca0b875c08258 Imre Deak 2023-09-21 89
8ca0b875c08258 Imre Deak 2023-09-21 90 limits->max_bpp_x16[max_bpp_pipe] = to_bpp_x16(max_bpp) - 1;
8ca0b875c08258 Imre Deak 2023-09-21 91
8ca0b875c08258 Imre Deak 2023-09-21 92 return intel_modeset_pipes_in_mask_early(state, reason,
8ca0b875c08258 Imre Deak 2023-09-21 93 BIT(max_bpp_pipe));
8ca0b875c08258 Imre Deak 2023-09-21 94 }
8ca0b875c08258 Imre Deak 2023-09-21 95
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
next prev parent reply other threads:[~2023-09-30 5:43 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-29 7:13 [Intel-gfx] [PATCH 0/8] Add DSC fractional bpp support Mitul Golani
2023-09-29 7:13 ` [Intel-gfx] [PATCH 1/8] drm/display/dp: Add helper function to get DSC bpp precision Mitul Golani
2023-09-29 7:13 ` [Intel-gfx] [PATCH 2/8] drm/i915/display: Store compressed bpp in U6.4 format Mitul Golani
2023-09-30 5:41 ` kernel test robot [this message]
2023-09-29 7:13 ` [Intel-gfx] [PATCH 3/8] drm/i915/display: Consider fractional vdsc bpp while computing m_n values Mitul Golani
2023-09-29 7:13 ` [Intel-gfx] [PATCH 4/8] drm/i915/audio : Consider fractional vdsc bpp while computing tu_data Mitul Golani
2023-09-29 7:13 ` [Intel-gfx] [PATCH 5/8] drm/i915/dsc/mtl: Add support for fractional bpp Mitul Golani
2023-09-29 7:13 ` [Intel-gfx] [PATCH 6/8] drm/i915/dp: Iterate over output bpp with fractional step size Mitul Golani
2023-09-29 7:13 ` [Intel-gfx] [PATCH 7/8] drm/i915/dsc: Add debugfs entry to validate DSC fractional bpp Mitul Golani
2023-09-29 7:13 ` [Intel-gfx] [PATCH 8/8] drm/i915/dsc: Allow DSC only with fractional bpp when forced from debugfs Mitul Golani
2023-09-29 14:38 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for Add DSC fractional bpp support (rev9) Patchwork
-- strict thread matches above, loose matches on Subject: below --
2023-09-26 8:23 [Intel-gfx] [PATCH 0/8] Add DSC fractional bpp support Mitul Golani
2023-09-26 8:23 ` [Intel-gfx] [PATCH 2/8] drm/i915/display: Store compressed bpp in U6.4 format Mitul Golani
2023-09-13 6:05 [Intel-gfx] [PATCH 0/8] Add DSC fractional bpp support Mitul Golani
2023-09-13 6:06 ` [Intel-gfx] [PATCH 2/8] drm/i915/display: Store compressed bpp in U6.4 format Mitul Golani
2023-09-12 16:37 [Intel-gfx] [PATCH 0/8] Add DSC fractional bpp support Mitul Golani
2023-09-12 16:37 ` [Intel-gfx] [PATCH 2/8] drm/i915/display: Store compressed bpp in U6.4 format Mitul Golani
2023-09-13 4:42 ` Kandpal, Suraj
2023-09-11 5:05 [Intel-gfx] [PATCH 0/8] Add DSC fractional bpp support Mitul Golani
2023-09-11 5:05 ` [Intel-gfx] [PATCH 2/8] drm/i915/display: Store compressed bpp in U6.4 format Mitul Golani
2023-09-11 9:13 ` Kandpal, Suraj
2023-09-11 9:17 ` Kandpal, Suraj
2023-09-11 11:36 ` Jani Nikula
2023-09-11 12:03 ` Golani, Mitulkumar Ajitkumar
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