From: Jonathan Cavitt <jonathan.cavitt@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: janusz.krzysztofik@intel.com, andi.shyti@intel.com,
matthew.d.roper@intel.com, jonathan.cavitt@intel.com,
chris.p.wilson@linux.intel.com, nirmoy.das@intel.com
Subject: [Intel-gfx] [PATCH dii-client v6 0/5] Subject: [PATCH dii-client v6 0/4] drm/i915: Define and use GuC and CTB TLB invalidation routines
Date: Thu, 5 Oct 2023 12:35:30 -0700 [thread overview]
Message-ID: <20231005193536.1463159-1-jonathan.cavitt@intel.com> (raw)
The GuC firmware had defined the interface for Translation Look-Aside
Buffer (TLB) invalidation. We should use this interface when
invalidating the engine and GuC TLBs.
Add additional functionality to intel_gt_invalidate_tlb, invalidating
the GuC TLBs and falling back to GT invalidation when the GuC is
disabled.
The invalidation is done by sending a request directly to the GuC
tlb_lookup that invalidates the table. The invalidation is submitted as
a wait request and is performed in the CT event handler. This means we
cannot perform this TLB invalidation path if the CT is not enabled.
If the request isn't fulfilled in two seconds, this would constitute
an error in the invalidation as that would constitute either a lost
request or a severe GuC overload.
The tlb_lookup table is allocated as an xarray because the set of
pending TLB invalidations may have no upper bound. The consequence of
this is that all actions interfacting with this table need to use the
xarray functions, such as xa_alloc_cyclic_irq for array insertion.
With this new invalidation routine, we can perform GuC-based GGTT
invalidations. GuC-based GGTT invalidation is incompatible with
MMIO invalidation so we should not perform MMIO invalidation when
GuC-based GGTT invalidation is expected.
v2:
- Add missing supporting patches.
v3:
- Split suspend/resume changes and multi-gt support into separate
patches.
- Only perform GuC TLB invalidation functions when supported.
- Move intel_guc_is_enabled check function to usage location.
- Address comments.
v4:
- Change conditions for GuC-based tlb invalidation support
to a pci tag that's only active for MTL.
- Address some FIXMEs and formatting issues.
- Move suspend/resume changes to helper functions in intel_gt.h
- Improve comment for ct_handle_event change.
- Use cleaner if-else conditions.
- Address comments.
v5:
- Reintroduce missing change to selftest msleep duration
- Move suspend/resume loops from intel_gt.h to intel_tlb.c,
making them no longer static inlines.
- Remove superfluous blocking and error checks.
- Move ct_handle_event exception to general case in
ct_process_request.
- Explain usage of xa_alloc_cyclic_irq.
- Modify explanation of purpose of
OUTSTANDING_GUC_TIMEOUT_PERIOD macro.
- Explain purpose of performing tlb invalidation twice in
intel_gt_tlb_resume_all.
v6:
- Add this cover letter.
- Fix explanation of purpose of
OUTSTANDING_GUC_TIMEOUT_PERIOD macro again.
- s/pci tags/pci flags
- Enable GuC TLB Invalidations separately from adding the
flags to do so.
Signed-off-by: Jonathan Cavitt <jonathan.cavitt@intel.com>
CC: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
CC: Bruce Chang <yu.bruce.chang@intel.com>
CC: Chris Wilson <chris.p.wilson@intel.com>
CC: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
CC: Aravind Iddamsetty <aravind.iddamsetty@intel.com>
CC: Fei Yang <fei.yang@intel.com>
CC: Andi Shyti <andi.shyti@linux.intel.com>
CC: John Harrison <john.c.harrison@intel.com>
CC: Nirmoy Das <nirmoy.das@intel.com>
CC: Janusz Krzysztofik <janusz.krzysztofik@intel.com>
CC: Matt Roper <matthew.d.roper@intel.com>
CC: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Jonathan Cavitt (4):
drm/i915: Add GuC TLB Invalidation pci flags
drm/i915: No TLB invalidation on wedged or suspended GT
drm/i915/gt: Increase sleep in gt_tlb selftest sanitycheck
drm/i915: Enable GuC TLB invalidations for MTL
Prathap Kumar Valsan (1):
drm/i915: Define and use GuC and CTB TLB invalidation routines
drivers/gpu/drm/i915/gt/intel_ggtt.c | 42 +++-
drivers/gpu/drm/i915/gt/intel_gt.h | 1 +
drivers/gpu/drm/i915/gt/intel_tlb.c | 39 ++-
drivers/gpu/drm/i915/gt/intel_tlb.h | 3 +
drivers/gpu/drm/i915/gt/selftest_tlb.c | 2 +-
.../gpu/drm/i915/gt/uc/abi/guc_actions_abi.h | 33 +++
drivers/gpu/drm/i915/gt/uc/intel_guc.h | 23 ++
drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 6 +
drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 1 +
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 236 +++++++++++++++++-
drivers/gpu/drm/i915/i915_driver.c | 6 +
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_pci.c | 1 +
drivers/gpu/drm/i915/intel_device_info.h | 3 +-
14 files changed, 379 insertions(+), 18 deletions(-)
--
2.25.1
next reply other threads:[~2023-10-05 19:46 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-05 19:35 Jonathan Cavitt [this message]
2023-10-05 19:35 ` [Intel-gfx] [PATCH v7 0/5] drm/i915: Define and use GuC and CTB TLB invalidation routines Jonathan Cavitt
2023-10-05 19:35 ` [Intel-gfx] [PATCH v7 1/5] drm/i915: Add GuC TLB Invalidation device info flags Jonathan Cavitt
2023-10-06 2:24 ` John Harrison
2023-10-06 10:22 ` Nirmoy Das
2023-10-05 19:35 ` [Intel-gfx] [PATCH v7 2/5] drm/i915: Define and use GuC and CTB TLB invalidation routines Jonathan Cavitt
2023-10-06 2:19 ` John Harrison
2023-10-06 11:57 ` Andi Shyti
2023-10-06 10:11 ` Tvrtko Ursulin
2023-10-06 10:20 ` Nirmoy Das
2023-10-06 16:18 ` John Harrison
2023-10-06 16:44 ` John Harrison
2023-10-06 13:04 ` Tvrtko Ursulin
2023-10-06 18:38 ` Cavitt, Jonathan
2023-10-05 19:35 ` [Intel-gfx] [PATCH v7 3/5] drm/i915: No TLB invalidation on wedged or suspended GT Jonathan Cavitt
2023-10-06 10:23 ` Tvrtko Ursulin
2023-10-06 17:30 ` John Harrison
2023-10-05 19:35 ` [Intel-gfx] [PATCH v7 4/5] drm/i915/gt: Increase sleep in gt_tlb selftest sanitycheck Jonathan Cavitt
2023-10-06 17:57 ` John Harrison
2023-10-05 19:35 ` [Intel-gfx] [PATCH v7 5/5] drm/i915: Enable GuC TLB invalidations for MTL Jonathan Cavitt
2023-10-06 1:20 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Subject: [PATCH dii-client v6 0/4] drm/i915: Define and use GuC and CTB TLB invalidation routines (rev2) Patchwork
2023-10-06 1:20 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-10-06 1:39 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2023-10-06 10:15 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Subject: [PATCH dii-client v6 0/4] drm/i915: Define and use GuC and CTB TLB invalidation routines (rev3) Patchwork
2023-10-06 10:15 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-10-06 10:26 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-10-06 22:08 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
-- strict thread matches above, loose matches on Subject: below --
2023-10-04 22:07 [Intel-gfx] [PATCH dii-client v6 0/5] Subject: [PATCH dii-client v6 0/4] drm/i915: Define and use GuC and CTB TLB invalidation routines Jonathan Cavitt
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20231005193536.1463159-1-jonathan.cavitt@intel.com \
--to=jonathan.cavitt@intel.com \
--cc=andi.shyti@intel.com \
--cc=chris.p.wilson@linux.intel.com \
--cc=intel-gfx@lists.freedesktop.org \
--cc=janusz.krzysztofik@intel.com \
--cc=matthew.d.roper@intel.com \
--cc=nirmoy.das@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox