From: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: dri-devel@lists.freedesktop.org, ankit.k.nautiyal@intel.com,
jani.nikula@intel.com
Subject: [PATCH v10 3/8] drm/i915: Update trans_vrr_ctl flag when cmrr is computed
Date: Thu, 30 May 2024 11:34:03 +0530 [thread overview]
Message-ID: <20240530060408.67027-4-mitulkumar.ajitkumar.golani@intel.com> (raw)
In-Reply-To: <20240530060408.67027-1-mitulkumar.ajitkumar.golani@intel.com>
Add/update trans_vrr_ctl flag when crtc_state->cmrr.enable
is set, With this commit setting the stage for subsequent
CMRR enablement.
--v2:
- Check pipe active state in cmrr enabling. [Jani]
- Remove usage of bitwise OR on booleans. [Jani]
- Revert unrelated changes. [Jani]
- Update intel_vrr_enable, vrr and cmrr enable conditions. [Jani]
- Simplify whole if-ladder in intel_vrr_enable. [Jani]
- Revert patch restructuring mistakes in intel_vrr_get_config. [Jani]
--v3:
- Check pipe active state in cmrr disabling.[Jani]
- Correct messed up condition in intel_vrr_enable. [Jani]
--v4:
- Removing RFC tag.
--v5:
- CMRR handling in co-existatnce of LRR and DRRS.
--v7:
- Rebase on top of AS SDP merge.
--v8:
- Remove cmrr_enabling/disabling and update commit message. (Ankit)
--v9:
- Revert removed line(Ankit).
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
---
drivers/gpu/drm/i915/display/intel_vrr.c | 10 ++++++++--
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 1f363e34495e..c2b5424f53db 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -284,8 +284,14 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state)
VRR_VSYNC_END(crtc_state->vrr.vsync_end) |
VRR_VSYNC_START(crtc_state->vrr.vsync_start));
- intel_de_write(dev_priv, TRANS_VRR_CTL(dev_priv, cpu_transcoder),
- VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state));
+ if (crtc_state->cmrr.enable) {
+ intel_de_write(dev_priv, TRANS_VRR_CTL(dev_priv, cpu_transcoder),
+ VRR_CTL_VRR_ENABLE | VRR_CTL_CMRR_ENABLE |
+ trans_vrr_ctl(crtc_state));
+ } else {
+ intel_de_write(dev_priv, TRANS_VRR_CTL(dev_priv, cpu_transcoder),
+ VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state));
+ }
}
void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state)
--
2.25.1
next prev parent reply other threads:[~2024-05-30 6:14 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-30 6:04 [PATCH v10 0/8] Implement CMRR Support Mitul Golani
2024-05-30 6:04 ` [PATCH v10 1/8] drm/i915: Separate VRR related register definitions Mitul Golani
2024-05-30 13:48 ` Jani Nikula
2024-05-31 11:49 ` Golani, Mitulkumar Ajitkumar
2024-05-31 12:01 ` Jani Nikula
2024-06-03 6:05 ` Golani, Mitulkumar Ajitkumar
2024-05-30 6:04 ` [PATCH v10 2/8] drm/i915: Define and compute Transcoder CMRR registers Mitul Golani
2024-05-31 6:06 ` Nautiyal, Ankit K
2024-05-30 6:04 ` Mitul Golani [this message]
2024-05-31 5:31 ` [PATCH v10 3/8] drm/i915: Update trans_vrr_ctl flag when cmrr is computed Nautiyal, Ankit K
2024-05-30 6:04 ` [PATCH v10 4/8] drm/i915: Compute CMRR and calculate vtotal Mitul Golani
2024-05-31 5:42 ` Nautiyal, Ankit K
2024-05-30 6:04 ` [PATCH v10 5/8] drm/dp: Add refresh rate divider to struct representing AS SDP Mitul Golani
2024-05-30 6:04 ` [PATCH v10 6/8] drm/i915/display: Add support for pack and unpack Mitul Golani
2024-05-31 5:44 ` Nautiyal, Ankit K
2024-05-30 6:04 ` [PATCH v10 7/8] drm/i915/display: Compute Adaptive sync SDP params Mitul Golani
2024-05-31 5:48 ` Nautiyal, Ankit K
2024-05-30 6:04 ` [PATCH v10 8/8] drm/i915/display: Compute vrr vsync params Mitul Golani
2024-05-31 5:52 ` Nautiyal, Ankit K
2024-05-30 6:49 ` ✗ Fi.CI.CHECKPATCH: warning for Implement CMRR Support (rev10) Patchwork
2024-05-30 6:49 ` ✗ Fi.CI.SPARSE: " Patchwork
2024-05-30 6:58 ` ✗ Fi.CI.BAT: failure " Patchwork
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