Intel-GFX Archive on lore.kernel.org
 help / color / mirror / Atom feed
From: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: dri-devel@lists.freedesktop.org, ankit.k.nautiyal@intel.com,
	jani.nikula@intel.com
Subject: [PATCH v11 3/8] drm/i915: Update trans_vrr_ctl flag when cmrr is computed
Date: Mon,  3 Jun 2024 11:18:59 +0530	[thread overview]
Message-ID: <20240603054904.222589-4-mitulkumar.ajitkumar.golani@intel.com> (raw)
In-Reply-To: <20240603054904.222589-1-mitulkumar.ajitkumar.golani@intel.com>

Add/update trans_vrr_ctl flag when crtc_state->cmrr.enable
is set, With this commit setting the stage for subsequent
CMRR enablement.

--v2:
- Check pipe active state in cmrr enabling. [Jani]
- Remove usage of bitwise OR on booleans. [Jani]
- Revert unrelated changes. [Jani]
- Update intel_vrr_enable, vrr and cmrr enable conditions. [Jani]
- Simplify whole if-ladder in intel_vrr_enable. [Jani]
- Revert patch restructuring mistakes in intel_vrr_get_config. [Jani]

--v3:
- Check pipe active state in cmrr disabling.[Jani]
- Correct messed up condition in intel_vrr_enable. [Jani]

--v4:
- Removing RFC tag.

--v5:
- CMRR handling in co-existatnce of LRR and DRRS.

--v7:
- Rebase on top of AS SDP merge.

--v8:
- Remove cmrr_enabling/disabling and update commit message. (Ankit)

--v9:
- Revert removed line(Ankit).

Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vrr.c      | 10 ++++++++--
 drivers/gpu/drm/i915/display/intel_vrr_regs.h |  2 ++
 2 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index d2f854d9d18b..19b364074de0 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -282,8 +282,14 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state)
 			       VRR_VSYNC_END(crtc_state->vrr.vsync_end) |
 			       VRR_VSYNC_START(crtc_state->vrr.vsync_start));
 
-	intel_de_write(dev_priv, TRANS_VRR_CTL(dev_priv, cpu_transcoder),
-		       VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state));
+	if (crtc_state->cmrr.enable) {
+		intel_de_write(dev_priv, TRANS_VRR_CTL(dev_priv, cpu_transcoder),
+			       VRR_CTL_VRR_ENABLE | VRR_CTL_CMRR_ENABLE |
+			       trans_vrr_ctl(crtc_state));
+	} else {
+		intel_de_write(dev_priv, TRANS_VRR_CTL(dev_priv, cpu_transcoder),
+			       VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state));
+	}
 }
 
 void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state)
diff --git a/drivers/gpu/drm/i915/display/intel_vrr_regs.h b/drivers/gpu/drm/i915/display/intel_vrr_regs.h
index 532ca5040a2e..e565aed06c88 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_vrr_regs.h
@@ -123,5 +123,7 @@
 #define _TRANS_CMRR_N_HI_A			0x604FC
 #define TRANS_CMRR_N_HI(dev_priv, trans)        _MMIO_TRANS2(dev_priv, trans, _TRANS_CMRR_N_HI_A)
 
+#define VRR_CTL_CMRR_ENABLE			REG_BIT(27)
+
 #endif /* __INTEL_VRR_REGS__ */
 
-- 
2.25.1


  parent reply	other threads:[~2024-06-03  5:59 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-06-03  5:48 [PATCH v11 0/8] Implement CMRR Support Mitul Golani
2024-06-03  5:48 ` [PATCH v11 1/8] drm/i915: Separate VRR related register definitions Mitul Golani
2024-06-04  5:54   ` Nautiyal, Ankit K
2024-06-03  5:48 ` [PATCH v11 2/8] drm/i915: Define and compute Transcoder CMRR registers Mitul Golani
2024-06-04  6:28   ` Nautiyal, Ankit K
2024-06-03  5:48 ` Mitul Golani [this message]
2024-06-03  5:49 ` [PATCH v11 4/8] drm/dp: Add refresh rate divider to struct representing AS SDP Mitul Golani
2024-06-03  5:49 ` [PATCH v11 5/8] drm/i915/display: Add support for pack and unpack Mitul Golani
2024-06-03  5:49 ` [PATCH v11 6/8] drm/i915/display: Compute Adaptive sync SDP params Mitul Golani
2024-06-03 12:48   ` Nautiyal, Ankit K
2024-06-03  5:49 ` [PATCH v11 7/8] drm/i915/display: Compute vrr vsync params Mitul Golani
2024-06-03  5:49 ` [PATCH v11 8/8] drm/i915: Compute CMRR and calculate vtotal Mitul Golani
2024-06-03  6:38 ` ✗ Fi.CI.CHECKPATCH: warning for Implement CMRR Support (rev11) Patchwork
2024-06-03  6:38 ` ✗ Fi.CI.SPARSE: " Patchwork
2024-06-03  6:46 ` ✓ Fi.CI.BAT: success " Patchwork
2024-06-03  8:43 ` ✗ Fi.CI.IGT: failure " Patchwork

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20240603054904.222589-4-mitulkumar.ajitkumar.golani@intel.com \
    --to=mitulkumar.ajitkumar.golani@intel.com \
    --cc=ankit.k.nautiyal@intel.com \
    --cc=dri-devel@lists.freedesktop.org \
    --cc=intel-gfx@lists.freedesktop.org \
    --cc=jani.nikula@intel.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox